CN113113372A - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
CN113113372A
CN113113372A CN202010577648.0A CN202010577648A CN113113372A CN 113113372 A CN113113372 A CN 113113372A CN 202010577648 A CN202010577648 A CN 202010577648A CN 113113372 A CN113113372 A CN 113113372A
Authority
CN
China
Prior art keywords
layer
dielectric layer
recess
integrated circuit
top surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010577648.0A
Other languages
English (en)
Other versions
CN113113372B (zh
Inventor
施江林
丘世仰
张庆弘
吴佩甄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Publication of CN113113372A publication Critical patent/CN113113372A/zh
Application granted granted Critical
Publication of CN113113372B publication Critical patent/CN113113372B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05006—Dual damascene structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种半导体结构及其制造方法，半导体结构包括半导体集成电路装置与重分布层结构。半导体集成电路装置具有顶面与延伸至顶面的电极。重分布层结构形成于半导体集成电路装置的顶面上。重分布层结构包括氧化层、氮化层、介电层、凹槽与穿孔。氧化层形成于顶面上。氮化层形成于氧化层上。介电层形成于氮化层上，并且具有大于氧化层与氮化层合计厚度的厚度。凹槽形成在介电层的顶侧上且重叠于电极。穿孔形成于凹槽的底部。穿孔从凹槽的底部通过介电层、氮化层与氧化层垂直地延伸至电极的部分。导电材料填充满穿孔与凹槽。如此，半导体结构的RLC表现得以获得改善。

Description

半导体结构及其制造方法
技术领域
本发明有关于一种半导体装置及其制造方法。
背景技术
重分布层结构是用于重新分配半导体装置的电极分布，并且重新分布过后的电极可以具有较好的连接位置，而能够以较好的方式与其他装置连接。然而，在具有额外的重分布层结构的情况，相应的半导体装置的RLC表现也会受到影响。
举例而言，半导体装置的其中一种包含具有电阻与晶体管的随机存取存储器(DRAM)，重分布层结构用于重新分布电阻与晶体管暴露的接点，而使得对应到的RLC表现变成一个很重要的问题。
因此，如何以一个低成本的制造方式，改善重分布层的RLC表现，是业界人士所欲解决的问题。
发明内容
本发明的一方面是有关于RLC表现得以获得改善的半导体结构。
根据本发明的一实施方式，一种半导体结构包括半导体集成电路装置与重分布层结构。半导体集成电路装置具有顶面与延伸至顶面的电极。重分布层结构形成于半导体集成电路装置的顶面上。重分布层结构包括氧化层、氮化层、介电层、凹槽与穿孔。氧化层形成于顶面上。氮化层形成于氧化层上。介电层形成于氮化层上，并且具有大于氧化层与氮化层合计厚度的一厚度。凹槽形成在介电层的顶侧上且重叠于电极。穿孔形成于凹槽的底部。穿孔从凹槽的底部通过介电层、氮化层与氧化层垂直地延伸至电极的部分。导电材料填充满穿孔与凹槽。
在本发明的一或多个实施方式中，凹槽的深度是小于等于介电层厚度的25％。
在本发明的一或多个实施方式中，穿孔的宽度是小于等于凹槽宽度的三分之一。
在本发明的一或多个实施方式中，介电层厚度的范围是介于8μm至10μm之间。
在本发明的一或多个实施方式中，上述的半导体结构还包括绝缘层与金属层。绝缘层形成于介电层上。窗口形成于绝缘层内，以暴露介电层顶侧的凹槽。金属层形成于绝缘层上并填充窗口，以与导电材料接触。在一些实施方式中，半导体结构还包括形成于金属层上的导电凸块。在一些实施方式中，窗口的宽度是小于凹槽的宽度。
本发明的另一方面有关于一种重分布层结构的制造方法。
根据本发明的一实施方式，上述制造方法是用于制造半导体结构。半导体结构的制造方法包括以下流程。提供半导体集成电路装置。半导体集成电路装置具有顶面与延伸至顶面的电极。在顶面上依序形成氧化层与氮化层。在氮化层上形成介电层。介电层具有大于氧化层与氮化层合计厚的厚度。在介电层的顶侧上形成凹槽。凹槽重叠于半导体集成电路装置的电极。在凹槽的底部形成穿孔。穿孔从凹槽的底部通过介电层、氮化层与氧化层垂直地延伸至电极。在穿孔与凹槽内填满导电材料。
在本发明的一或多个实施方式中，上述制造方法进一步包括以下流程。平坦化介电层的顶侧。
在本发明的一或多个实施方式中，上述制造方法进一步包括以下流程。在介电层上形成绝缘层。在绝缘层内形成窗口以暴露凹槽。在绝缘层上及窗口内形成金属层，以接触导电材料。在一些实施方式中，上述制造方法进一步包括在金属层上形成导电凸块。
在本发明的一或多个实施方式中，在上述制造方法中，氧化层与介电层的材料包含氧化硅，氮化层的材料包含氮化硅，并且在形成穿孔于凹槽的底部的流程是通过硅穿孔工艺来执行。
综上所述，对于半导体结构，重分布层结构是形成于所提供的半导体集成电路装置上，重分布层结构能够通过凹槽与穿孔建构。举例来说，介电层、氧化层与硅化层可以是硅化物，而穿孔可以通过一个成熟的硅穿孔工艺加以形成，而这样成熟的硅工艺是低成本的。此外，介电层可以具有大的厚度，介电层的等效电容可以减少，并且半导体结构的RLC表现得以获得改善。
应理解到，以上的一般说明与以下的详细描述都是通过示例做进一步说明，旨在为本发明提供做进一步的解释。
附图说明
本发明的优点与附图，应由接下来列举的实施方式，并参考附图，以获得更好的理解。这些附图的说明仅仅是列举的实施方式，因此不该认为是限制了个别实施方式，或是限制了本发明权利要求的保护范围。
图1根据本发明的一实施方式绘示由重分布层结构与半导体集成电路装置所形成的半导体结构的剖面示意图；
图2是根据本发明的一实施方式的半导体结构制造方法的流程图，半导体结构包括重分布层结构与半导体集成电路装置；以及
图3至图11根据本发明的一实施方式分别绘示在半导体结构制造方法不同流程对应的剖面图。
主要附图标记说明：
100-半导体结构，105-重分布层结构，110-氧化层，120-氮化层，130-介电层，140-凹槽，150-穿孔，155-导电材料，160-绝缘层，165-窗口，170-金属层，180-导电凸块，200-半导体集成电路装置，210-电极，300-制造方法，310～350-流程，Ld-厚度，Li-厚度，Lg-深度，Wg-宽度，Wtv-宽度。
具体实施方式
下文列举实施例配合所附附图进行详细说明，但所提供的实施例并非用以限制本发明所涵盖的范围，而结构运作的描述非用以限制其执行的顺序，任何由元件重新组合的结构，所产生具有均等功效的装置，皆为本发明所涵盖的范围。另外，附图仅以说明为目的，并未依照原尺寸作图。为使便于理解，下述说明中相同元件或相似元件将以相同的符号标示来说明。
除非另有定义，本文所使用的所有词汇(包括技术和科学术语)具有其通常的意涵，其意涵是能够被熟悉此领域者所理解。更进一步的说，上述的词汇在普遍常用的字典中的定义，在本说明书的内容中应被解读为与本发明相关领域一致的意涵。除非有特别明确定义，这些词汇将不被解释为理想化的或过于正式的意涵。
关于本文中所使用的“第一”、“第二”、…等，并非特别指称次序或顺位的意思，亦非用以限定本发明，其仅仅是为了区别以相同技术用语描述的元件或操作而已。
其次，在本文中所使用的用词“包含”、“包括”、“具有”、“含有”等等，均为开放性的用语，即意指包含但不限于。
再者，于本文中，除非内文中对于冠词有所特别限定，否则“一”与“该”可泛指单一个或多个。将进一步理解的是，本文中所使用的“包含”、“包括”、“具有”及相似词汇，指明其所记载的特征、区域、整数、步骤、操作、元件与/或组件，但不排除其所述或额外的其一个或多个其它特征、区域、整数、步骤、操作、元件、组件，与/或其中的群组。
请参照图1。图1根据本发明的一实施方式绘示由重分布层结构105与半导体集成电路装置200所形成的半导体结构100的剖面示意图。重分布层结构105是形成于半导体集成电路装置200之上。
如图1所示，本发明的一实施方式提供半导体集成电路装置200，并且电极210是自半导体集成电路装置200的顶面上暴露。在一些实施方式中，半导体集成电路装置200是一个随机存取存储器(DRAM)结构，并且暴露的电极210是分别连接至随机存取存储器的晶体管或是电容。因此，对于半导体集成电路装置200，RLC问题是一个重要的议题。RLC问题是是电阻、电感与电容三者耦合所对应产生的延迟问题。在一些实施方式中，电极210例如是连接半导体集成电路装置200内部元件的金属垫。
重分布层结构105是形成于半导体集成电路装置200的顶面上。在本实施方式中，重分布层结构105包括氧化层110、氮化层120、介电层130、凹槽140与穿孔150。
氧化层110是形成于半导体集成电路装置200的顶面上。在一些实施方式中，氧化层110是用于作为一个薄的介电质来隔绝电极210。在本实施方式中，氧化层110是氧化硅。
氮化层120是形成于氧化层110之上。在一些实施方式中，氮化层120是用于增加重分布层结构105的结构强度。在本实施方式中，氮化层120是氮化硅，然而并不以此限制本发明。
介电层130是形成于氮化层120之上。如图1所示，介电层130具有厚度Ld，厚度Ld大于氧化层110与氮化层120合计厚度Li。在具有大的厚度Ld的情况下，介电层130所产生的总电容相应减少。介电层130包含底侧与顶侧。介电层130的底侧靠近氮化层120。介电层130的顶侧相对于底侧。在本实施方式中，介电层130是氧化硅，但并不以此限制本发明。
凹槽140是形成于介电层130的顶侧上，并部分形成于介电层130内。如图1所示，凹槽140具有深度Lg，并且凹槽140的深度Lg是小于介电层130的厚度Ld。凹槽140重叠于半导体集成电路装置200的其中一个电极210。在本实施方式中，凹槽140在半导体集成电路装置200的顶面上具有垂直投影，而凹槽140的此垂直投影覆盖该被重叠的电极210。在一些实施方式中，被覆盖的电极210是位在凹槽140垂直投影的中心。在一些实施方式中，凹槽140可以部分地重叠于半导体集成电路装置200。
穿孔150是形成于凹槽140的底部。如图1所示，穿孔150从凹槽140的底部垂直地延伸至电极210的部分。具体而言，穿孔150的延伸是穿过介电层130、氮化层120与氧化层110。
如图1所示，穿孔150与凹槽140为导电材料155所填满。在本实施方式中，导电材料155是铜，但并不以此限定本发明。因此，电极210能够通过在凹槽140与穿孔150内的导电材料155而延伸连接至介电层130的顶面。
在本实施方式中，介电层130可以具有一个大的厚度Ld。在一些实施方式中，介电层130的厚度Ld可以是在8μm至10μm的范围内。在一些实施方式中，介电层130甚至可以具有更大的厚度Ld。因为重分布层结构105的连接是通过穿孔150加以执行，较大的厚度Ld并不会造成较大的成本。此外，在本实施方式中，介电层130、氧化层110与氮化层120是硅化物，并且穿孔150可以由传统的硅穿孔工艺来形成。
回到图1。在本实施方式中，重分布层结构105包括绝缘层160、金属层170与导电凸块180。在本实施方式中，绝缘层160的材料是氧化硅，但并不以此限制本发明。
如图1所示，窗口165是形成于绝缘层160，以暴露自介电层130的顶侧暴露的导电材料155。换言之，窗口165暴露为导电材料155所填满的凹槽140。在本实施方式中，窗口165的宽度是小于凹槽140的宽度Wg，以避免与导电材料155非预期的接触。
金属层170是形成于绝缘层160上且形成于窗口165内，以接处导电材料155。是故，电极210是通过为导电材料155填满的穿孔150连接至金属层170。也就是说，电极210可以通过金属层170来连接。举例而言，在本实施方式中，金属层170的材料是铝，但并不以此限制本发明。
在本实施方式中，导电凸块180是形成于窗口165内，并且导电凸块180可以进一步连接至其他的导线。在一些实施方式中，导电凸块180可以形成在窗口165的外。举例来说，导电凸块180可以形成于金属层170顶面的一部分上，此金属层170顶面的一部分是位于绝缘层160之上，并且导电凸块180不重叠于凹槽140。
凹槽140是形成以大致对准电极210，并且穿孔1500能够进一步延伸至电极210内。因此，凹槽140的深度Lg可以是非常地浅。在一些实施方式中，凹槽140的深度Lg是小于等于介电层130厚度Ld的25％。在一些实施方式中，介电层130的厚度Ld是介于8μm至10μm的范围之间，并且凹槽140的深度Lg是在1μm至2μm的范围之间。
在凹槽140形成后，半导体集成电路装置200顶面的电极210是被对齐的，并且穿孔150可以精确地延伸至电极210。在一些实施方式中，在介电层130顶侧的凹槽140的形状，是矩形或是八边形。如图1所示，穿孔150的宽度Wtv是小于凹槽140的宽度Wg，以避免在制造过程中由于某些失误使得穿孔150所在的位置不在凹槽140内，具体请见后述。在一些实施方式中，穿孔150的宽度Wtv是小于等于凹槽140的宽度Wg的三分之一。在一些实施方式中，穿孔150的宽度Wtv是3μm，并且凹槽140的宽度Wg是约为10μm或是更大一些。在一些实施方式中，穿孔150的宽度Wtv是5μm，并且凹槽140的宽度是15μm或是更大一些。在一些实施方式中，穿孔150的宽度Wtv是7μm，而凹槽140的宽度约为25μm或是更大一些。
在本实施方式中，穿孔150的深度约为10μm，因此穿孔150也被称作是一个小穿孔结构。在一些实施方式中，凹槽140的中心可以对准电极210。
请参照图2，同时也参照图3至图11。图2是根据本发明的一实施方式的半导体结构100的制造方法300的流程图，半导体结构100包括重分布层结构105与半导体集成电路装置200。图3至图11根据本发明的一实施方式分别绘示在半导体结构100的制造方法300的不同流程对应的剖面图。
在图3中，提供具有裸露电极210作为电性接点的半导体集成电路装置200。在流程310中，同时也参照图4，氧化层110与氮化层120是形成于半导体集成电路装置200的顶面上。
在流程315中，介电层130是形成于氮化层120之上。如图5所示，介电层130具有大于氧化层110与氮化层120合计的厚度。
接续流程315，如图6所示，在流程320，凹槽140是形成在介电层130的顶侧上。凹槽140自介电层130的顶侧凹陷，并且重叠于半导体集成电路装置200的其中一个电极210。因此，此一电极210与凹槽140在空间上是对准的。
在流程325，穿孔150是形成在凹槽140的底面上。如图7所示，穿孔150从凹槽140的底部垂直地延伸至电极210。穿孔150通过介电层130、氮化层120与氧化层110来延伸。在本实施方式中，氧化层110与介电层130是氧化硅，氮化层120是氮化硅，而在凹槽底部形成穿孔的步骤可以由传统的硅穿孔工艺来执行。
接续流程325，在流程330，穿孔150与凹槽140为导电材料155所填充，如图8所示。进一步地，如图8所示，介电层130的顶侧被平坦化。在一些实施方式中，平坦化是通过化学机械平面化(chemical mechanical planarization,CMP)工艺来执行。
流程320、流程325与流程330一起合称为一个双镶嵌工艺(dual damasceneprocess)。双镶嵌工艺是指在形成凹槽140以及于凹槽140内形成穿孔150后，再填充导电材料155。
如图9所示，在流程335，绝缘层160形成与介电层130之上。绝缘层160覆盖凹槽140与自凹槽140暴露的导电材料155。
在流程340中，窗口165是形成于绝缘层160内以暴露自凹槽140暴露的导电材料，如图10所示。在本实施方式中，窗口165的宽度是小于凹槽140的宽度。
图11绘示流程345与流程350对应的剖面图，如图11所示，对应流程345，金属层170形成于绝缘层160上且形成于窗口165内，并且在流程350中，导电凸块180形成于金属层170上。因此，通过使用穿孔150内的导电材料155作为连接，导电凸块180与半导体集成电路装置200的顶面上的电极210连接。在一些实施方式中，导电凸块180可以由其他的导电结构替代，例如是导线或者是其他的重分布结构。
因为主要的连接功能是通过硅穿孔工艺来获得而可以加以实现，即使是介电层130具有大的厚度，穿孔150仍可以形成并延伸至半导体集成电路装置200顶面上的电极210。在一些实施方式中，介电层130的厚度是在8μm至10μm的范围内。在一些实施方式中，介电层130的厚度可以大于10μm。介电层130的大厚度使得整体电容相应减少。因此，重分布层结构105所产生的RLC表现获得改善。
此外，在本实施方式中，导电材料155是铜，金属层170的材料是铝，金属层170的材料不同于导电材料155。导电材料155具有更好的导电性质，并且电极210与金属层170之间的总电阻能够减少，使得重分布层结构105的RLC表现被进一步改善。
综上所述，半导体结构包括半导体集成电路装置与重分布层结构，并且本发明的重分布层结构可以由凹槽与穿孔加以建构。所使用的介电层、氧化层与氮化层可以是硅化物，并且穿孔的形成可以使用传统的硅穿孔工艺，传统的硅穿孔工艺对应到低的成本。因为重分布层结构是通过穿孔加以实现，重分布层结构内的介电层厚度可以很大，并且重分布层结构的总电容值能够减少。因此。半导体结构的RLC表现能够被改善。
虽然本发明已以实施例公开如上，然其并不用以限定本发明，任何所属领域的技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视后权利要求所界定的为准。
对于本领域技术人员将显而易见的是，在不脱离本公开的范围或精神的情况下，可以对本发明实施例的结构进行各种修改和变化。鉴于前述内容，本发明旨在覆盖各种的修改与变形，只要它们落入权利要求的范围内。

Claims (12)

1.一种半导体结构，其特征在于，包括：
半导体集成电路装置，其中所述半导体集成电路装置具有顶面与延伸至所述顶面的电极；以及
重分布层结构，形成于所述半导体集成电路装置的所述顶面上，其中所述重分布层结构包括：
氧化层，形成于所述顶面上；
氮化层，形成于所述氧化层上；
介电层，形成于所述氮化层上且具有大于所述氧化层与所述氮化层合计厚度的厚度；
凹槽，形成在所述介电层的顶侧上且重叠于所述电极；以及
穿孔，形成于所述凹槽的底部，其中所述穿孔从所述凹槽的所述底部通过所述介电层、所述氮化层与所述氧化层垂直地延伸至所述电极的一部分，导电材料填充满所述穿孔与所述凹槽。
2.如权利要求1所述的半导体结构，其特征在于，所述凹槽的深度小于等于所述介电层的厚度的25％。
3.如权利要求1所述的半导体结构，其特征在于，所述穿孔的宽度是小于等于所述凹槽的宽度的三分之一。
4.如权利要求1所述的半导体结构，其特征在于，所述介电层的厚度的范围是介于8μm至10μm之间。
5.如权利要求1所述的半导体结构，其特征在于，进一步包括：
绝缘层，形成于所述介电层上，其中窗口形成于所述绝缘层内，以暴露所述介电层的所述顶侧的所述凹槽；以及
金属层，形成于所述绝缘层上并填充所述窗口，以与所述导电材料接触。
6.如权利要求5所述的半导体结构，其特征在于，进一步包括导电凸块，所述导电凸块形成于所述金属层上。
7.如权利要求5所述的半导体结构，其特征在于，所述窗口的宽度是小于所述凹槽的宽度。
8.一种半导体结构的制造方法，其特征在于，包括：
提供半导体集成电路装置，其中所述半导体集成电路装置具有顶面与延伸至所述顶面的电极；
在所述顶面上依序形成氧化层与氮化层；
在所述氮化层上形成介电层，其中所述介电层具有大于所述氧化层与所述氮化层合计厚度的厚度；
在所述介电层的顶侧上形成凹槽，其中所述凹槽重叠于所述半导体集成电路装置的所述电极；
在所述凹槽的底部形成穿孔，其中所述穿孔从所述凹槽的所述底部通过所述介电层、所述氮化层与所述氧化层垂直地延伸至所述电极；以及
在所述穿孔与所述凹槽内填满导电材料。
9.如权利要求8所述的制造方法，其特征在于，进一步包括：
平坦化所述介电层的所述顶侧。
10.如权利要求8所述的制造方法，其特征在于，进一步包括：
在所述介电层上形成绝缘层；
在所述绝缘层内形成窗口以暴露所述凹槽；以及
在所述绝缘层上及所述窗口内形成金属层，以接触所述导电材料。
11.如权利要求10所述的制造方法，其特征在于，进一步包括：
在所述金属层上形成导电凸块。
12.如权利要求8所述的制造方法，其特征在于，所述氧化层与所述介电层的材料包含氧化硅，所述氮化层的材料包含氮化硅，并且所述形成所述穿孔于所述凹槽的所述底部的流程是通过硅穿孔工艺来执行。
CN202010577648.0A 2020-01-09 2020-06-23 半导体结构及其制造方法 Active CN113113372B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/739,106 2020-01-09
US16/739,106 US11205607B2 (en) 2020-01-09 2020-01-09 Semiconductor structure and method of manufacturing thereof

Publications (2)

Publication Number Publication Date
CN113113372A true CN113113372A (zh) 2021-07-13
CN113113372B CN113113372B (zh) 2024-07-30

Family

ID=76036175

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010577648.0A Active CN113113372B (zh) 2020-01-09 2020-06-23 半导体结构及其制造方法

Country Status (3)

Country Link
US (2) US11205607B2 (zh)
CN (1) CN113113372B (zh)
TW (1) TWI722882B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12040592B2 (en) * 2021-05-28 2024-07-16 Lumentum Operations Llc Packaging substrate with low thermal resistance and low parasitic inductance
US20230187400A1 (en) * 2021-12-13 2023-06-15 Amkor Technology Singapore Holding Pte. Ltd. Electronic devices and methods of manufacturing electronic devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101510548A (zh) * 2008-02-14 2009-08-19 株式会社瑞萨科技 半导体器件及其制造方法
US20150194345A1 (en) * 2014-01-03 2015-07-09 International Busines Machines Corporation Semiconductor chip with a dual damascene wire and through-substrate via (tsv) structure
CN105977202A (zh) * 2015-03-12 2016-09-28 新加坡商格罗方德半导体私人有限公司 具有低k互连的逻辑装置的整合式磁性随机存取记忆体
US20180019199A1 (en) * 2016-07-14 2018-01-18 Chengdu Monolithic Power Systems Co., Ltd. Semiconductor device having redistribution layer with copper migration stopping
US20180138202A1 (en) * 2016-11-15 2018-05-17 Vanguard International Semiconductor Corporation Semiconductor structures and method for fabricating the same
CN110416184A (zh) * 2018-04-27 2019-11-05 台湾积体电路制造股份有限公司 半导体结构及其形成方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926723B1 (en) * 1997-11-26 2007-01-17 STMicroelectronics S.r.l. Process for forming front-back through contacts in micro-integrated electronic devices
US7138717B2 (en) * 2004-12-01 2006-11-21 International Business Machines Corporation HDP-based ILD capping layer
US7309653B2 (en) * 2005-02-24 2007-12-18 International Business Machines Corporation Method of forming damascene filament wires and the structure so formed
JP5656341B2 (ja) * 2007-10-29 2015-01-21 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置およびその製造方法
JP2009147218A (ja) * 2007-12-17 2009-07-02 Toshiba Corp 半導体装置とその製造方法
KR101458958B1 (ko) * 2008-06-10 2014-11-13 삼성전자주식회사 반도체 칩, 반도체 패키지 및 반도체 칩의 제조 방법
US8399987B2 (en) * 2009-12-04 2013-03-19 Samsung Electronics Co., Ltd. Microelectronic devices including conductive vias, conductive caps and variable thickness insulating layers
US8772942B2 (en) * 2010-01-26 2014-07-08 International Business Machines Corporation Interconnect structure employing a Mn-group VIIIB alloy liner
US8581418B2 (en) * 2010-07-21 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die stacking using bumps with different sizes
KR20120020553A (ko) * 2010-08-30 2012-03-08 삼성전자주식회사 반도체 칩 및 반도체 칩의 형성 방법
FR2970119B1 (fr) * 2010-12-30 2013-12-13 St Microelectronics Crolles 2 Sas Puce de circuits integres et procede de fabrication.
KR101867961B1 (ko) * 2012-02-13 2018-06-15 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
KR102111474B1 (ko) * 2013-11-20 2020-06-08 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US9837278B2 (en) * 2014-02-27 2017-12-05 Taiwan Semiconductor Manufacturing Company Ltd. Wafer level chip scale package and method of manufacturing the same
KR102411064B1 (ko) * 2015-03-10 2022-06-21 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그의 제조방법
US10038026B2 (en) * 2015-06-25 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure for bonding improvement
KR102379165B1 (ko) * 2015-08-17 2022-03-25 삼성전자주식회사 Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법
US10049953B2 (en) * 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US10871466B2 (en) * 2015-11-04 2020-12-22 Massachusetts Institute Of Technology Sensor systems and related fabrication techniques
KR102406573B1 (ko) * 2017-04-28 2022-06-09 삼성전자주식회사 반도체 소자 및 그 제조 방법
US10541228B2 (en) * 2017-06-15 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages formed using RDL-last process
US10347543B2 (en) * 2017-11-13 2019-07-09 Globalfoundries Inc. FDSOI semiconductor device with contact enhancement layer and method of manufacturing
US10460959B2 (en) * 2018-03-15 2019-10-29 Powertech Technology Inc. Package structure and manufacturing method thereof
US11004733B2 (en) * 2018-06-29 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Protection structures for bonded wafers
KR102493464B1 (ko) * 2018-07-19 2023-01-30 삼성전자 주식회사 집적회로 장치 및 이의 제조 방법
KR102530319B1 (ko) * 2018-12-07 2023-05-09 삼성전자주식회사 전도성 필라를 갖는 반도체 패키지 및 그 제조 방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101510548A (zh) * 2008-02-14 2009-08-19 株式会社瑞萨科技 半导体器件及其制造方法
US20150194345A1 (en) * 2014-01-03 2015-07-09 International Busines Machines Corporation Semiconductor chip with a dual damascene wire and through-substrate via (tsv) structure
CN105977202A (zh) * 2015-03-12 2016-09-28 新加坡商格罗方德半导体私人有限公司 具有低k互连的逻辑装置的整合式磁性随机存取记忆体
US20180019199A1 (en) * 2016-07-14 2018-01-18 Chengdu Monolithic Power Systems Co., Ltd. Semiconductor device having redistribution layer with copper migration stopping
US20180138202A1 (en) * 2016-11-15 2018-05-17 Vanguard International Semiconductor Corporation Semiconductor structures and method for fabricating the same
CN110416184A (zh) * 2018-04-27 2019-11-05 台湾积体电路制造股份有限公司 半导体结构及其形成方法

Also Published As

Publication number Publication date
US20210217684A1 (en) 2021-07-15
TW202127622A (zh) 2021-07-16
TWI722882B (zh) 2021-03-21
US11205607B2 (en) 2021-12-21
US20220059435A1 (en) 2022-02-24
CN113113372B (zh) 2024-07-30

Similar Documents

Publication Publication Date Title
JP6548377B2 (ja) 集積回路素子及びその製造方法
US6734489B2 (en) Semiconductor element and MIM-type capacitor formed in different layers of a semiconductor device
TWI292204B (en) Semiconductor device and method for manufacturing the same
JP6310217B2 (ja) Ｔｓｖ構造を備える集積回路素子及びその製造方法
JP4577687B2 (ja) 半導体装置
JP3396137B2 (ja) コンデンサおよびその作製方法
US9437491B2 (en) Method of forming chip with through silicon via electrode
CN109801896B (zh) 高密度金属-绝缘体-金属的电容器
TWI700837B (zh) 半導體結構及其製造方法
JP5388768B2 (ja) ローカルインターコネクトを備えた半導体装置
US11735498B2 (en) Through via electrode and device isolation structure including oxide layer pattern and nitride layer pattern sequentially stacked on inner surface of trench
US8907410B2 (en) TSV structure with a built-in U-shaped FET transistor for improved characterization
CN102113115A (zh) 晶片通孔及其制造方法
US20070152258A1 (en) Semiconductor device with a capacitor
CN113113372B (zh) 半导体结构及其制造方法
KR20210047043A (ko) 인터포저 구조체, 그를 포함하는 반도체 패키지 및 그 제조 방법
JP3685722B2 (ja) 半導体装置及びその製造方法
CN110085574B (zh) 用于动态随机存取存储器的电阻器
US8492812B2 (en) Semiconductor device having dummy pattern and method of fabricating a semiconductor device comprising dummy pattern
KR100881488B1 (ko) Ｍｉｍ 캐패시터를 갖는 반도체 소자 및 그의 제조방법
CN115884594A (zh) 半导体结构及半导体结构的制备方法
CN114725059A (zh) 具有超通孔的半导体结构以及其制作方法
US7694262B2 (en) Deep trench capacitor and method of making same
US7084057B2 (en) Bit line contact structure and fabrication method thereof
CN117766522A (zh) 硅电容结构及其制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant