WO2023035324A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2023035324A1
WO2023035324A1 PCT/CN2021/119797 CN2021119797W WO2023035324A1 WO 2023035324 A1 WO2023035324 A1 WO 2023035324A1 CN 2021119797 W CN2021119797 W CN 2021119797W WO 2023035324 A1 WO2023035324 A1 WO 2023035324A1
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Prior art keywords
layer
protrusion
metal
channel region
drain
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PCT/CN2021/119797
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English (en)
French (fr)
Inventor
刘净
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Tcl华星光电技术有限公司
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Priority to US17/607,876 priority Critical patent/US20240030229A1/en
Publication of WO2023035324A1 publication Critical patent/WO2023035324A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display panel.
  • the manufacturing process of the corresponding array substrate is also developing rapidly.
  • the current array substrate is mainly prepared by using 4 photomasks (4Mask) to achieve the purpose of cost saving.
  • the protruding length of the active layer relative to the upper source and drain will inevitably appear big phenomenon.
  • the protruding part of the active layer compared to the source and drain is called an amorphous silicon tail (Amorphous Silion Tail, AS Tail).
  • AS Tail amorphous Silion Tail
  • Embodiments of the present application provide an array substrate, a manufacturing method thereof, and a display panel, so as to reduce the length of the AS Tail.
  • An embodiment of the present application provides an array substrate, which includes:
  • an active layer disposed on the substrate, the active layer having a channel region
  • the drain is arranged on the active layer, the source and the drain are located on opposite sides of the channel region, and both the source and the drain are arranged in turn on the active layer. a metal barrier layer and a conductive metal layer on the layer;
  • the metal barrier layer includes a first protrusion, and the first protrusion extends from the end of the conductive metal layer to extending in a direction away from the channel region.
  • the length of the first protrusion in a direction in which the channel region faces the source and/or the drain, is 0.05 ⁇ m-1.5 ⁇ m.
  • the length of the first protrusion is 1.0 ⁇ m-1.5 ⁇ m.
  • the active layer includes a second protrusion extending from the end of the first protrusion in a direction away from the channel region .
  • the active layer includes an amorphous silicon layer and an ohmic contact layer, and the ohmic contact layer is located on a side of the amorphous silicon layer close to the metal barrier layer,
  • the second protrusion includes a first sub-protrusion and a second sub-protrusion, the first sub-protrusion is located in the amorphous silicon layer, and the second sub-protrusion is located in the ohmic contact layer;
  • both the first sub-protrusion and the second sub-protrusion are away from the end of the first protrusion extending in the direction of the channel region.
  • the active layer includes an amorphous silicon layer and an ohmic contact layer, and the ohmic contact layer is located on a side of the amorphous silicon layer close to the metal barrier layer, the second protrusion is located in the amorphous silicon layer;
  • a side surface of the ohmic contact layer is flush with a side surface of the first protrusion.
  • the length of the second protrusion in the direction of the channel region towards the source and/or the drain, is in the range of 0 ⁇ m to 2 ⁇ m .
  • the material of the metal barrier layer includes at least one of molybdenum or a molybdenum alloy, and the material of the conductive metal layer includes copper.
  • An embodiment of the present application provides a display panel, the display panel includes an array substrate, and the array substrate includes:
  • an active layer disposed on the substrate, the active layer having a channel region
  • the drain is arranged on the active layer, the source and the drain are located on opposite sides of the channel region, and both the source and the drain are arranged in turn on the active layer. a metal barrier layer and a conductive metal layer on the layer;
  • the metal barrier layer includes a first protrusion, and the first protrusion extends from the end of the conductive metal layer to extending in a direction away from the channel region.
  • the length of the first protrusion in a direction in which the channel region faces the source and/or the drain, is 0.05 ⁇ m-1.5 ⁇ m.
  • the length of the first protrusion is 1.0 ⁇ m-1.5 ⁇ m.
  • the active layer includes a second protrusion extending from the end of the first protrusion in a direction away from the channel region .
  • the active layer includes an amorphous silicon layer and an ohmic contact layer, and the ohmic contact layer is located on a side of the amorphous silicon layer close to the metal barrier layer,
  • the second protrusion includes a first sub-protrusion and a second sub-protrusion, the first sub-protrusion is located in the amorphous silicon layer, and the second sub-protrusion is located in the ohmic contact layer;
  • both the first sub-protrusion and the second sub-protrusion are away from the end of the first protrusion extending in the direction of the channel region.
  • the active layer includes an amorphous silicon layer and an ohmic contact layer, and the ohmic contact layer is located on a side of the amorphous silicon layer close to the metal barrier layer, the second protrusion is located in the amorphous silicon layer;
  • a side surface of the ohmic contact layer is flush with a side surface of the first protrusion.
  • the length of the second protrusion in the direction of the channel region towards the source and/or the drain, is in the range of 0 ⁇ m to 2 ⁇ m .
  • the material of the metal barrier layer includes at least one of molybdenum or a molybdenum alloy, and the material of the conductive metal layer includes copper.
  • An embodiment of the present application provides a method for preparing an array substrate, which includes the following steps:
  • the first metal layer and the second metal layer are etched with an etchant to form a metal barrier layer and a conductive metal layer respectively, the source and drain patterns are formed as source electrodes and drain electrodes, and the first metal layer
  • the etch rate of the layer in the etchant is less than the etch rate of the second metal layer in the etchant
  • the metal barrier layer includes a first protrusion, and the first protrusion is formed from the conductive metal layer. The end portion of the channel region extends away from the channel region.
  • the etching solution in the step of etching the first metal layer and the second metal layer with an etching solution, includes an acidic oxidant and a metal etchant,
  • the mass content of the acidic oxidant in the etching solution is 5%-6%
  • the mass content of the metal etchant in the etching solution is 0.01%-0.05%.
  • the active base layer includes an amorphous silicon base layer and an ohmic contact base layer formed sequentially
  • the active layer pattern includes an amorphous silicon layer and an ohmic contact layer pattern
  • the The step of etching the active layer pattern includes:
  • the material of the first metal layer includes at least one of molybdenum or a molybdenum alloy
  • the material of the conductive metal layer includes copper
  • the acidic oxidizer is hydrogen peroxide
  • the metal etchant is a molybdenum etchant.
  • both the source and the drain include a metal barrier layer and a conductive metal layer sequentially arranged on the active layer. /or the end of the drain away from the channel region, so that the metal barrier layer has a first protrusion, and the first protrusion extends from the end of the conductive metal layer to the end far away from the channel region.
  • the arrangement of the first protrusion can cover part of the active layer, thereby reducing the protruding length of the active layer compared to the metal barrier layer, that is, reducing The protruding length of the active layer compared to the source electrode and/or the drain electrode can be reduced, so that the stability of the driving signal in the array substrate can be improved.
  • FIG. 1 is a schematic flowchart of a method for manufacturing an array substrate provided in a first embodiment of the present application.
  • FIGS. 2A to 2H are structural diagrams obtained sequentially at various stages in the method for manufacturing the array substrate shown in FIG. 1 .
  • FIG. 3 is a schematic flowchart of a method for manufacturing an array substrate provided in a second embodiment of the present application.
  • FIG. 4A to FIG. 4H are structural diagrams obtained sequentially at various stages in the manufacturing method of the array substrate shown in FIG. 3 .
  • FIG. 5 is a schematic structural diagram of the array substrate provided by the first embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of the array substrate provided by the second embodiment of the present application.
  • Embodiments of the present application provide an array substrate, a manufacturing method thereof, and a display panel. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • the first embodiment of the present application provides a method for preparing an array substrate, which includes the following steps:
  • B12 sequentially forming an active base layer, a first metal base layer and a second metal base layer on the substrate;
  • B15 Etching the first metal layer and the second metal layer with an etchant to form a metal barrier layer and a conductive metal layer respectively, the source and drain patterns are formed as source and drain, and the first The etching rate of a metal layer in the etching solution is lower than the etching rate of the second metal layer in the etching solution;
  • the metal barrier layer includes a second A protrusion, the first protrusion extends from the end of the conductive metal layer in a direction away from the channel region.
  • the etching rate of the first metal layer in the etching solution is lower than that of the second metal layer.
  • the etching rate of the metal layer in the etching solution further makes the metal barrier layer formed after the first metal layer is etched have a first protrusion protruding outward compared with the conductive metal layer. Since the first protrusion is located above the active layer, the formation of the first protrusion can reduce the protruding length of the active layer compared to the metal barrier layer, that is, reduce the length of the active layer compared to the source layer.
  • the protruding length of the electrode and/or the drain can reduce the difference in the parasitic capacitance formed by the gate and the source/drain under light and non-light conditions, which is conducive to improving the stability of the driving signal in the array substrate.
  • the array substrate in this embodiment includes thin film transistors, and the thin film transistors may have a top-gate structure or a bottom-gate structure, and this embodiment only uses a bottom-gate structure thin film transistor as an example. description, but not limited thereto.
  • the method for preparing the array substrate 100 provided in the first embodiment of the present application includes the following steps:
  • the substrate 10 is provided.
  • the substrate 10 may be a rigid substrate, such as a glass substrate; or, the substrate 10 may also be a flexible substrate, such as a polyimide substrate, and the material of the substrate 10 is not specifically limited in this application.
  • step B11 further include: sequentially forming a gate 11 and a gate insulating layer 12 on the substrate 10 .
  • the materials and formation process of the gate 11 and the gate insulating layer 12 can refer to the prior art, and will not be repeated here.
  • B12 sequentially forming an active base layer 13a, a first metal base layer 14a and a second metal base layer 15a on the substrate 10 to form a structure as shown in FIG. 2A.
  • B12 specifically includes the following steps:
  • B121 sequentially forming an amorphous silicon base layer 131a and an ohmic contact base layer 132a on the substrate 10, the amorphous silicon base layer 131a and the ohmic contact base layer 132a constitute the active base layer 13a;
  • the material of the amorphous silicon base layer 131a may be amorphous silicon.
  • the material of the ohmic contact base layer 132a may be doped amorphous silicon, such as N-type or P-type doped amorphous silicon. In this embodiment, the material of the ohmic contact base layer 132a is N-type doped amorphous silicon.
  • the amorphous silicon base layer 131 a and the ohmic contact base layer 132 a may be sequentially formed by chemical vapor deposition.
  • the material of the first metal base layer 14a may be selected from at least one of molybdenum or molybdenum alloys.
  • the molybdenum alloy can be a binary alloy of molybdenum, and the binary alloy can include one of titanium, chromium, nickel or aluminum other than molybdenum; or, the molybdenum alloy can also be a triad of molybdenum.
  • the ternary alloys may include any two of titanium, chromium, nickel and aluminum other than molybdenum.
  • the first metal base layer 14a can be formed by sputtering, thermal evaporation, electroplating and other film forming methods.
  • the material of the second metal base layer 15a may include copper. In some embodiments, the material of the second metal base layer 15a may also include one or more of molybdenum, titanium, aluminum, chromium or nickel.
  • the second metal base layer 15a may be formed by sputtering, thermal evaporation, electroplating and other film forming methods.
  • step B12 further include the steps of:
  • the photoresist layer 16 is exposed and developed by using a halftone mask or a grayscale tone mask to form a first photoresist pattern 161.
  • the thickness of the two sides of the first photoresist pattern 161 is greater than the thickness of the middle part, as shown in the figure 2C.
  • the first wet etching using the first photoresist pattern 161 as a mask, the first metal base layer 14 a and the second metal base layer 15 a are etched by a wet etching process.
  • the parts of the first metal base layer 14 a and the second metal base layer 15 a not covered by the first photoresist pattern 161 are etched away by using an etching solution. Since wet etching etches materials isotropically, the first metal layer 141 a and the second metal layer 151 a formed after etching have overcut regions (not marked in the figure) under the first photoresist pattern 161 .
  • the first dry etching the first photoresist pattern 161 and the active base layer 13 a are etched by a dry etching process.
  • the dry etching process may be performed in an oxygen atmosphere.
  • the first photoresist pattern 161 is subjected to ashing treatment to reduce the thickness of the first photoresist pattern 161 and remove a part of the middle area of the first photoresist pattern 161 to form the second photoresist pattern 162 .
  • the active base layer 13a is etched to form an active layer pattern 13A.
  • the active layer pattern 13A includes an amorphous silicon layer 131 and an ohmic contact layer pattern 132b, the amorphous silicon layer 131 is formed by etching the amorphous silicon base layer 131a, and the ohmic contact layer pattern 132b is formed by etching the ohmic contact base layer 132a.
  • B15 Utilize etchant to etch the first metal layer 141a and the second metal layer 151a to form the metal barrier layer 141 and the conductive metal layer 151 respectively, and the source-drain pattern 14A is formed as the source electrode 14 and the drain electrode 15, as shown in FIG. 2F, wherein the etching rate of the first metal layer 141a in the etching solution is lower than the etching rate of the second metal layer 151a in the etching solution.
  • the second wet etching using the second photoresist pattern 162 as a mask, the first metal layer 141 a and the second metal layer 151 a are etched by a wet etching process.
  • the parts of the first metal layer 141 a and the second metal layer 151 a not covered by the second photoresist pattern 162 are etched away by using an etching solution. Since the etching of materials by wet etching is isotropic, there will be an overcut region (not marked in the figure) under the second photoresist pattern 162 in the metal barrier layer 141 and the conductive metal layer 151 .
  • the etching solution used in the etching process of the first metal layer 141a and the second metal layer 151a includes an acidic oxidant and a metal etchant, and the metal etchant is used to control the etching rate of the second metal layer 151a.
  • the acidic oxidizing agent may be hydrogen peroxide.
  • the metal etchant may be a molybdenum etchant.
  • the mass content of the acidic oxidant in the etching solution is set to 5%-6 %
  • the mass content of the metal etchant in the etching solution is set at 0.01%-0.05%.
  • the mass content of the acidic oxidizing agent in the etching solution can be 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9% or 6%.
  • the mass content of the metal etchant in the etching solution may be 0.01%, 0.015%, 0.02%, 0.025%, 0.03%, 0.035%, 0.04%, 0.045% or 0.05%.
  • the part of the metal barrier layer 141 protruding from the conductive metal layer 151 is a first protrusion 1411 .
  • the first protrusion 1411 extends from the drain 15 toward the source 14
  • the first protrusion 1411 extends from the source 14 toward the drain 15 . It should be noted that only the first convex portion 1411 in the source electrode 14 is marked in the drawings corresponding to this embodiment, but it should not be understood as a limitation of the present application.
  • the length n of the first protrusion 1411 obtained by the preparation method of this embodiment can reach 0.05 ⁇ m-1.0 ⁇ m.
  • the length n of the first protrusion 1411 may be 0.05 ⁇ m, 0.08 ⁇ m, 0.1 ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 0.8 ⁇ m or 1.0 ⁇ m.
  • the etching solution used for the second wet etching can also include components such as an acid stabilizer, a pH regulator, an etching inhibitor, a metal ion stabilizer and a regulator, and the etching solution
  • components such as an acid stabilizer, a pH regulator, an etching inhibitor, a metal ion stabilizer and a regulator, and the etching solution
  • the specific components can be selected according to actual application requirements, which is not limited in this application.
  • the barrier metal layer 141 includes a first protrusion 1411 extending from the end of the conductive metal layer 151 in a direction away from the channel region 17 , as shown in FIG. 2G .
  • the second dry etching using the second photoresist pattern 162 as a mask, the active layer pattern 13A is etched by a dry etching process.
  • the ohmic contact layer pattern 132b in the active layer pattern 13A is etched to form the ohmic contact layer 132, and the ohmic contact layer 132 and the amorphous silicon layer 131 constitute the active layer.
  • layer 13 and the ohmic contact layer 132 is respectively in contact with the corresponding source 14/drain 15.
  • the amorphous silicon layer 131 has a first sub-protrusion 1311 .
  • the ohmic contact layer 132 has a second sub-protrusion 1321 .
  • the first sub-protrusion 1311 and the second sub-protrusion 1321 are both from the end of the first protrusion 1411 to the direction away from the channel.
  • the direction of zone 17 extends.
  • the first sub-protrusion 1311 and the second sub-protrusion 1321 constitute the second protrusion 13B of the active layer 13 .
  • the present embodiment since the first protrusion 1411 is formed in the metal barrier layer 141, compared with the situation in the prior art that the metal barrier layer is not formed with a protruding part, the present embodiment The length of the second convex portion 13B obtained after the second dry etching can be reduced. That is to say, in this embodiment, by making the metal barrier layer 141 protrude compared to the conductive metal layer 151, the protruding length of the active layer 13 compared to the source electrode 14 and the drain electrode 15 is reduced, thereby reducing the size of the gate electrode 11. The difference between the parasitic capacitance formed with the source 14 and the drain 15 under the illumination and non-illumination conditions is beneficial to improve the stability of the driving signal in the array substrate 100 .
  • the length m of the second protrusion 13B is in the range of 0 ⁇ m to 2 ⁇ m in the direction from the channel region 17 to the source 14 . That is, in this embodiment, by providing the first protrusion 1411 in the metal barrier layer 141 , the length m of the second protrusion 13B can be reduced to 2 ⁇ m or less. In some specific embodiments, the length m of the second protrusion 13B may be 0.05 ⁇ m, 0.1 ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 0.6 ⁇ m, 0.8 ⁇ m, 1.0 ⁇ m, 1.2 ⁇ m, 1.5 ⁇ m, 1.8 ⁇ m or 2 ⁇ m.
  • step B16 it further includes: stripping the second photoresist pattern 162 to form the structure shown in FIG. 2H .
  • the preparation method of the array substrate 100 in this embodiment further includes forming a passivation layer on the conductive metal layer 151, forming an exposed source electrode 14/
  • a passivation layer on the conductive metal layer 151
  • the second embodiment of the present application provides a method for preparing an array substrate, which includes the following steps:
  • B22 sequentially forming an active base layer, a first metal base layer and a second metal base layer on the substrate;
  • B23 Etching the first metal base layer and the second metal base layer to form a first metal layer and a second metal layer respectively, the first metal layer and the second metal layer forming a source and drain pattern;
  • B26 Etching the first metal layer and the active layer pattern to form a metal barrier layer and an active layer respectively, and the source and drain patterns are formed as the source and the drain; wherein, in the The source and/or the drain are away from one end of the channel region of the active layer, the metal barrier layer includes a first protrusion, and the first protrusion extends from the end of the conductive metal layer to extending in a direction away from the channel region.
  • the first metal layer is not etched in the step of etching the second metal layer, and after the second metal layer is etched to form a conductive metal layer, simultaneously
  • the first metal layer and the active layer pattern are etched to form the metal barrier layer and the active layer respectively, so that the finally formed metal barrier layer has a first protrusion protruding outward compared with the conductive metal layer. Since the first protrusion is located above the active layer, the formation of the first protrusion can reduce the protruding length of the active layer compared to the metal barrier layer, that is, reduce the length of the active layer compared to the source layer.
  • the protruding length of the electrode and/or the drain can reduce the difference in the parasitic capacitance formed by the gate and the source/drain under light and non-light conditions, which is conducive to improving the stability of the driving signal in the array substrate.
  • the array substrate in this embodiment includes thin film transistors, and the thin film transistors may have a top-gate structure or a bottom-gate structure, and this embodiment only uses a bottom-gate structure thin film transistor as an example. description, but not limited thereto.
  • the method for preparing the array substrate 100 provided in the second embodiment of the present application includes the following steps:
  • B24 Etching the active base layer 13a to form an active layer pattern 13A.
  • steps B21 - B24 for the specific process flow of steps B21 - B24 , reference may be made to the description of steps B11 - B14 in the foregoing embodiments, and details are not repeated here.
  • B25 Etching the second metal layer 151 a with an etchant to form a conductive metal layer 151 , as shown in FIG. 4F .
  • the second wet etching using the second photoresist pattern 162 as a mask, the second metal layer 151 a is etched by a wet etching process.
  • the portion of the second metal layer 151 a not covered by the second photoresist pattern 162 is etched away by using an etching solution. Since the etching of materials by wet etching is isotropic, there will be an overcut area (not marked in the figure) in the conductive metal layer 151 under the second photoresist pattern 162 .
  • the difference between the etching solution used in step B25 and the etching solution used in step B15 of the previous embodiment is that the etching solution in this embodiment does not use a molybdenum etchant, so as to ensure that the first metal layer 141a is wet-etched for the second time. Not etched away during etching.
  • the barrier metal layer 141 includes a first protrusion 1411, the first protrusion 1411 extends from the end of the conductive metal layer 151 in a direction away from the channel region 17 , as shown in FIG. 4G .
  • the second dry etching using the second photoresist pattern 162 as a mask, the first metal layer 141 a and the active layer pattern 13A are etched by a dry etching process.
  • the first metal layer 141a and the ohmic contact layer pattern 132b in the active layer pattern 13A are etched to form the metal barrier layer 141 and the ohmic contact layer 132 respectively.
  • the contact layer 132 and the amorphous silicon layer 131 constitute the active layer 13 , and the ohmic contact layer 132 is in contact with the corresponding source 14 and drain 15 respectively.
  • the metal barrier layer 141 forms a first protrusion 1411 compared with the conductive metal layer 151.
  • the first protrusion The portion 1411 extends from the drain 15 toward the source 14 , and in the drain 15 , the first convex portion 1411 extends from the source 14 toward the drain 15 . It should be noted that only the first convex portion 1411 in the source electrode 14 is marked in the drawings corresponding to this embodiment, but it should not be understood as a limitation of the present application.
  • the side surface of the ohmic contact layer 132 is flush with the side surface of the first protrusion 1411 .
  • the second protrusion 13B is formed in the amorphous silicon layer 131 . The second protrusion 13B extends from the end of the first protrusion 1411 in a direction away from the channel region 17 .
  • this embodiment does not etch the first metal layer 141a in the second wet etching, but simultaneously etches the first metal layer 141a and the active layer pattern 13A in the second dry etching, the above etching method can further The length n of the first protrusion 1411 in the barrier metal layer 141 is increased.
  • the ohmic contact layer 132 since the first protrusion 1411 and the ohmic contact layer 132 are formed at the same time, and the side surfaces of the ohmic contact layer 132 are flush with the side surfaces of the first protrusion 1411, the ohmic contact layer 132 does not block the lower amorphous silicon layer 131, Therefore, the length of the outer protrusion of the amorphous silicon layer 131 compared with the first protrusion 1411 can be further reduced, that is, the length of the second protrusion 13B in the active layer 13 can be further reduced.
  • the metal barrier layer 141 protrude compared to the conductive metal layer 151, the protruding length of the active layer 13 compared to the source electrode 14 and the drain electrode 15 can be further reduced, thereby reducing the size of the gate electrode 11.
  • the difference between the parasitic capacitance formed with the source 14 and the drain 15 under the illumination and non-illumination conditions is beneficial to improve the stability of the driving signal in the array substrate 100 .
  • the length n of the first protrusion 1411 obtained by the preparation method of this embodiment can reach 0.05 ⁇ m-1.5 ⁇ m.
  • the length n of the first protrusion 1411 can be 0.05 ⁇ m, 0.08 ⁇ m, 0.1 ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 0.8 ⁇ m, 1.0 ⁇ m, 1.1 ⁇ m, 1.2 ⁇ m, 1.3 ⁇ m, 1.4 ⁇ m or 1.5 ⁇ m.
  • the length m of the second protrusion 13B is in the range of 0 ⁇ m to 2 ⁇ m. That is, in this embodiment, by providing the first protrusion 1411 in the metal barrier layer 141 , the length m of the second protrusion 13B can be reduced to 2 ⁇ m or less. In some specific embodiments, the length m of the second protrusion 13B may be 0.05 ⁇ m, 0.1 ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 0.6 ⁇ m, 0.8 ⁇ m, 1.0 ⁇ m, 1.2 ⁇ m, 1.5 ⁇ m, 1.8 ⁇ m or 2 ⁇ m.
  • step B26 further include: stripping the second photoresist pattern 162 to form the structure shown in FIG. 4H .
  • the preparation method of the array substrate 100 in this embodiment further includes forming a passivation layer on the conductive metal layer 151, forming an exposed source electrode 14/
  • a passivation layer on the conductive metal layer 151
  • the first embodiment of the present application provides an array substrate 100 .
  • the array substrate 100 includes a substrate 10 , an active layer 13 , a source 14 and a drain 15 .
  • Active layer 13 is provided on substrate 10 .
  • the active layer 13 has a channel region 17 .
  • a source 14 and a drain 15 are provided on the active layer 13 .
  • the source 14 and the drain 15 are located on opposite sides of the channel region 17 .
  • Both the source electrode 14 and the drain electrode 15 include a metal barrier layer 141 and a conductive metal layer 151 sequentially disposed on the active layer 13 .
  • the barrier metal layer 141 includes a first protrusion 1411 .
  • the first protrusion 1411 extends from the end of the conductive metal layer 151 to a direction away from the channel region 17 .
  • the substrate 10 may be a hard substrate, such as a glass substrate; or, the substrate 10 may also be a flexible substrate, such as a polyimide substrate, and the material of the substrate 10 is not specifically limited in this application.
  • the array substrate 100 also includes a gate 11 and a gate insulating layer 12 sequentially disposed on the substrate 10 .
  • the gate insulating layer 12 is located on a side of the gate 11 close to the active layer 13 .
  • the active layer 13 , the gate 11 , the source 14 and the drain 15 form a thin film transistor (not marked in the figure).
  • the thin film transistors in this application may have a top-gate structure or a bottom-gate structure.
  • a thin-film transistor with a bottom-gate structure is used as an example for illustration, but it is not limited thereto.
  • the material of the conductive metal layer 151 includes copper. In some embodiments, the material of the conductive metal layer 151 may also include one or more of molybdenum, titanium, aluminum, chromium or nickel.
  • the material of the barrier metal layer 141 includes at least one of molybdenum or a molybdenum alloy.
  • the molybdenum alloy can be a binary alloy of molybdenum, and the binary alloy can include one of titanium, chromium, nickel or aluminum other than molybdenum; or, the molybdenum alloy can also be a triad of molybdenum.
  • the ternary alloys may include any two of titanium, chromium, nickel and aluminum other than molybdenum.
  • the metal barrier layer 141 may include a first protrusion 1411 .
  • the first protrusion 1411 may also be disposed at an end of any one of the source electrode 14 and the drain electrode 15 away from the channel, which will not be repeated here.
  • the length n of the first protrusion 1411 is 0.05 ⁇ m-1.0 ⁇ m. Specifically, the length n of the first protrusion 1411 may be 0.05 ⁇ m, 0.08 ⁇ m, 0.1 ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 0.8 ⁇ m or 1.0 ⁇ m.
  • the active layer 13 includes the second convex portion 13B.
  • the second protrusion 13B extends from the end of the first protrusion 1411 in a direction away from the channel region 17 . Since the first protruding portion 1411 is located above the active layer 13, compared with the prior art where no protruding portion is provided in the metal barrier layer, the setting of the first protruding portion 1411 in this embodiment can cover part of the The active layer 13 can further reduce the protruding length of the active layer 13 compared with the source electrode 14 /drain electrode 15 , that is, reduce the length of the second protruding portion 13B.
  • the length m of the second protrusion 13B is in the range of 0 ⁇ m to 2 ⁇ m. That is, in this embodiment, by providing the first protrusion 1411 in the barrier metal layer 141 , the length of the second protrusion 13B can be reduced to 2 ⁇ m or less. In some specific embodiments, the length m of the second protrusion 13B may be 0.05 ⁇ m, 0.1 ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 0.6 ⁇ m, 0.8 ⁇ m, 1.0 ⁇ m, 1.2 ⁇ m, 1.5 ⁇ m, 1.8 ⁇ m or 2 ⁇ m.
  • the active layer 13 includes an amorphous silicon layer 131 and an ohmic contact layer 132 .
  • the ohmic contact layer 132 is located on a side of the amorphous silicon layer 131 close to the barrier metal layer 141 .
  • the active layer 13 may also only include the amorphous silicon layer 131 , which will not be repeated here.
  • the second convex portion 13B includes a first sub-convex portion 1311 and a second sub-convex portion 1321 .
  • the first sub-protrusion 1311 is located in the amorphous silicon layer 131 .
  • the second sub-protrusion 1321 is located in the ohmic contact layer 132 .
  • the first sub-protrusion 1311 and the second sub-protrusion 1321 are both from the end of the first protrusion 1411 to the direction away from the channel.
  • the direction of zone 17 extends.
  • the length m of the second protruding portion 13B is the length of the first sub-protruding portion 1311 (not marked in the figure).
  • the parasitic capacitance will be generated among the gate 11 , the source 14 /drain 15 and the storage capacitor (not shown in the figure) in the array substrate 100 .
  • the length m of the second convex portion 13B is reduced, which is beneficial to improving the driving signal in the array substrate 100. stability.
  • the array substrate 100 in this embodiment can be prepared by using the method for preparing the array substrate 100 provided in the first embodiment above, and related preparation methods can refer to the description of the first embodiment above, and will not be repeated here.
  • the second embodiment of the present application provides an array substrate 100.
  • the difference between the array substrate 100 provided in the second embodiment of the present application and the first embodiment is that the second convex portion 13B is located on the amorphous silicon layer. 131 in.
  • the side surface of the ohmic contact layer 132 is flush with the side surface of the first protrusion 1411 .
  • the length n of the first protrusion 1411 is 0.05 ⁇ m-1.5 ⁇ m.
  • the side surfaces of the ohmic contact layer 132 are flush with the side surfaces of the first protrusion 1411 .
  • the side surface of the ohmic contact layer 132 can be arranged to be aligned with the first protrusion 1411 sides flush.
  • the length n of the first protrusion 1411 can be 0.05 ⁇ m, 0.08 ⁇ m, 0.1 ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 0.8 ⁇ m, 1.0 ⁇ m, 1.1 ⁇ m, 1.2 ⁇ m, 1.3 ⁇ m, 1.4 ⁇ m or 1.5 ⁇ m.
  • the length n of the first protrusion 1411 is set at 0.05 ⁇ m-1.5 ⁇ m, so that the first protrusion 1411 covers part of the amorphous silicon layer 131 , thereby reducing the size of the amorphous silicon layer 131 .
  • the side of the ohmic contact layer 132 is flush with the side of the first protrusion 1411, that is, the ohmic contact layer 132 will not cover the lower amorphous silicon layer 131 .
  • this embodiment can greatly reduce the protruding length of the amorphous silicon layer 131 compared with the metal barrier layer 141, thereby reducing the protruding length of the active layer 13 compared with the source electrode 14 and the drain electrode 15, and also That is, the length of the second convex portion 13B is reduced.
  • the length m of the second protrusion 13B is in the range of 0 ⁇ m to 2 ⁇ m. That is, in this embodiment, the length of the second protrusion 13B can be reduced by providing the first protrusion 1411 in the barrier metal layer 141 and making the side surfaces of the ohmic contact layer 132 flush with the side surfaces of the first protrusion 1411 To 2 ⁇ m and below.
  • the length m of the second protrusion 13B may be 0.05 ⁇ m, 0.1 ⁇ m, 0.2 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 0.6 ⁇ m, 0.8 ⁇ m, 1.0 ⁇ m, 1.2 ⁇ m, 1.5 ⁇ m, 1.8 ⁇ m or 2 ⁇ m.
  • the array substrate 100 in this embodiment can be prepared by using the preparation method of the array substrate 100 provided in the aforementioned second embodiment, and the relevant preparation method can refer to the description of the aforementioned second embodiment, which will not be repeated here.
  • the embodiment of the present application also provides a display panel, the display panel includes an array substrate 100, the array substrate 100 can be the array substrate 100 described in any of the foregoing embodiments, and the specific structure of the array substrate 100 can refer to the foregoing embodiments description and will not be repeated here.
  • the display panel is a liquid crystal display panel.
  • the display panel may also be an organic light emitting diode display panel, which will not be repeated here.
  • the array substrate 100 in the foregoing embodiments is applied to a display panel, during the driving process of the display panel, the difference in parasitic capacitance under positive and negative field conditions can be reduced, thereby reducing the probability of lateral crosstalk occurring in the display panel under an electric field, It is beneficial to improve the display taste of display products.

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Abstract

本申请公开了一种阵列基板及其制备方法、显示面板。阵列基板包括依次设置的衬底、有源层、源极以及漏极；有源层具有一沟道区；源极和漏极位于沟道区的相对两侧，源极和漏极均包括依次设置的金属阻挡层和导电金属层；在源极和/或漏极远离沟道区的一端，金属阻挡层包括第一凸部，第一凸部自导电金属层的端部向远离沟道区的方向延伸。

Description

阵列基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及其制备方法、显示面板。
 背景技术
随着液晶显示技术的快速发展，相应的阵列基板的制作工艺也在快速发展。相较于传统阵列基板的5道光罩制程，目前的阵列基板主要采用4道光罩（4Mask）制备得到，以达到节省成本的目的。
 技术问题
在4Mask工艺中，由于有源层和源漏极采用同一道光罩制得，因此，在制备得到的有源层中，不可避免地会出现有源层相对于上方的源漏极外凸长度较大的现象。其中，有源层相较于源漏极凸出的部分称为非晶硅尾纤（Amorphous Silion Tail, AS Tail），当AS Tail长度过大时，会影响阵列基板中驱动信号的稳定性。
 技术解决方案
本申请实施例提供一种阵列基板及其制备方法、显示面板，以减小AS Tail的长度。
本申请实施例提供一种阵列基板，其包括：
衬底；
有源层，设置在所述衬底上，所述有源层具有一沟道区；
源极，设置在所述有源层上；以及
漏极，设置在所述有源层上，所述源极和所述漏极位于所述沟道区的相对两侧，所述源极和所述漏极均包括依次设置在所述有源层上的金属阻挡层和导电金属层；
其中，在所述源极和/或所述漏极远离所述沟道区的一端，所述金属阻挡层包括第一凸部，所述第一凸部自所述导电金属层的端部向远离所述沟道区的方向延伸。
可选的，在本申请的一些实施例中，在所述沟道区朝向所述源极和/或所述漏极的方向上，所述第一凸部的长度为0.05μm-1.5μm。
可选的，在本申请的一些实施例中，所述第一凸部的长度为1.0μm-1.5μm。
可选的，在本申请的一些实施例中，所述有源层包括第二凸部，所述第二凸部自所述第一凸部的端部向远离所述沟道区的方向延伸。
可选的，在本申请的一些实施例中，所述有源层包括非晶硅层和欧姆接触层，所述欧姆接触层位于所述非晶硅层靠近所述金属阻挡层的一侧，所述第二凸部包括第一子凸部和第二子凸部，所述第一子凸部位于所述非晶硅层中，所述第二子凸部位于所述欧姆接触层中；
在所述源极和/或所述漏极远离所述沟道区的一端，所述第一子凸部和所述第二子凸部均自所述第一凸部的端部向远离所述沟道区的方向延伸。
可选的，在本申请的一些实施例中，所述有源层包括非晶硅层和欧姆接触层，所述欧姆接触层位于所述非晶硅层靠近所述金属阻挡层的一侧，所述第二凸部位于所述非晶硅层中；
在所述源极和/或所述漏极远离所述沟道区的一端，所述欧姆接触层的侧面与所述第一凸部的侧面齐平。
可选的，在本申请的一些实施例中，在所述沟道区朝向所述源极和/或所述漏极的方向上，所述第二凸部的长度处于0μm至2μm的范围内。
可选的，在本申请的一些实施例中，所述金属阻挡层的材料包括钼或钼合金中的至少一种，所述导电金属层的材料包括铜。
本申请实施例提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
衬底；
有源层，设置在所述衬底上，所述有源层具有一沟道区；
源极，设置在所述有源层上；以及
漏极，设置在所述有源层上，所述源极和所述漏极位于所述沟道区的相对两侧，所述源极和所述漏极均包括依次设置在所述有源层上的金属阻挡层和导电金属层；
其中，在所述源极和/或所述漏极远离所述沟道区的一端，所述金属阻挡层包括第一凸部，所述第一凸部自所述导电金属层的端部向远离所述沟道区的方向延伸。
可选的，在本申请的一些实施例中，在所述沟道区朝向所述源极和/或所述漏极的方向上，所述第一凸部的长度为0.05μm-1.5μm。
可选的，在本申请的一些实施例中，所述第一凸部的长度为1.0μm-1.5μm。
可选的，在本申请的一些实施例中，所述有源层包括第二凸部，所述第二凸部自所述第一凸部的端部向远离所述沟道区的方向延伸。
可选的，在本申请的一些实施例中，所述有源层包括非晶硅层和欧姆接触层，所述欧姆接触层位于所述非晶硅层靠近所述金属阻挡层的一侧，所述第二凸部包括第一子凸部和第二子凸部，所述第一子凸部位于所述非晶硅层中，所述第二子凸部位于所述欧姆接触层中；
在所述源极和/或所述漏极远离所述沟道区的一端，所述第一子凸部和所述第二子凸部均自所述第一凸部的端部向远离所述沟道区的方向延伸。
可选的，在本申请的一些实施例中，所述有源层包括非晶硅层和欧姆接触层，所述欧姆接触层位于所述非晶硅层靠近所述金属阻挡层的一侧，所述第二凸部位于所述非晶硅层中；
在所述源极和/或所述漏极远离所述沟道区的一端，所述欧姆接触层的侧面与所述第一凸部的侧面齐平。
可选的，在本申请的一些实施例中，在所述沟道区朝向所述源极和/或所述漏极的方向上，所述第二凸部的长度处于0μm至2μm的范围内。
可选的，在本申请的一些实施例中，所述金属阻挡层的材料包括钼或钼合金中的至少一种，所述导电金属层的材料包括铜。
本申请实施例提供一种阵列基板的制备方法，其包括以下步骤：
提供衬底；
在所述衬底上依次形成有源基层、第一金属基层和第二金属基层；
蚀刻所述第一金属基层和所述第二金属基层，以分别形成第一金属层和第二金属层，所述第一金属层和所述第二金属层构成源漏极图案；
蚀刻所述有源基层，以形成有源层图案；
利用蚀刻液对所述第一金属层和所述第二金属层进行蚀刻，以分别形成金属阻挡层和导电金属层，所述源漏极图案形成为源极和漏极，所述第一金属层在所述蚀刻液中的蚀刻速率小于所述第二金属层在所述蚀刻液中的蚀刻速率；
蚀刻所述有源层图案，以形成有源层；
其中，在所述源极和/或所述漏极远离所述有源层的沟道区的一端，所述金属阻挡层包括第一凸部，所述第一凸部自所述导电金属层的端部向远离所述沟道区的方向延伸。
可选的，在本申请的一些实施例中，所述利用蚀刻液对所述第一金属层和所述第二金属层进行蚀刻的步骤中，所述蚀刻液包括酸性氧化剂和金属蚀刻剂，所述酸性氧化剂在所述蚀刻液中的质量含量为5%-6%，所述金属蚀刻剂在所述蚀刻液中的质量含量为0.01%-0.05%。
可选的，在本申请的一些实施例中，所述有源基层包括依次形成的非晶硅基层和欧姆接触基层，所述有源层图案包括非晶硅层和欧姆接触层图案，所述蚀刻所述有源层图案的步骤，包括：
蚀刻所述欧姆接触层图案，以形成欧姆接触层，所述非晶硅层和所述欧姆接触层构成所述有源层；其中，所述非晶硅层具有第一子凸部，所述欧姆接触层具有第二子凸部，在所述源极和/或所述漏极远离所述沟道区的一端，所述第一子凸部和所述第二子凸部均自所述第一凸部的端部向远离所述沟道区的方向延伸。
可选的，在本申请的一些实施例中，所述第一金属层的材料包括钼或钼合金中的至少一种，所述导电金属层的材料包括铜，所述酸性氧化剂为过氧化氢，所述金属蚀刻剂为钼蚀刻剂。
 有益效果
相较于现有技术中的阵列基板，在本申请提供的阵列基板中，源极和漏极均包括依次设置在有源层上的金属阻挡层和导电金属层，本申请通过在源极和/或漏极远离沟道区的一端，使得金属阻挡层具有第一凸部，且第一凸部自导电金属层的端部向远离沟道区的端部延伸。由于第一凸部位于有源层的上方，因此，第一凸部的设置可以覆盖部分有源层，进而能够减小有源层相较于金属阻挡层的外凸长度，也即，减小了有源层相较于源极和/或漏极的外凸长度，从而能够提高阵列基板中驱动信号的稳定性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请第一实施例提供的阵列基板的制备方法的流程示意图。
图2A至图2H是图1所示的阵列基板的制备方法中各阶段依次得到的结构示意图。
图3是本申请第二实施例提供的阵列基板的制备方法的流程示意图。
图4A至图4H是图3所示的阵列基板的制备方法中各阶段依次得到的结构示意图。
图5是本申请第一实施例提供的阵列基板的结构示意图。
图6是本申请第二实施例提供的阵列基板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供一种阵列基板及其制备方法、显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参照图1，本申请第一实施例提供一种阵列基板的制备方法，其包括以下步骤：
B11：提供衬底；
B12：在所述衬底上依次形成有源基层、第一金属基层和第二金属基层；
B13：蚀刻所述第一金属基层和所述第二金属基层，以分别形成第一金属层和第二金属层，所述第一金属层和所述第二金属层构成源漏极图案；
B14：蚀刻所述有源基层，以形成有源层图案；
B15：利用蚀刻液对所述第一金属层和所述第二金属层进行蚀刻，以分别形成金属阻挡层和导电金属层，所述源漏极图案形成为源极和漏极，所述第一金属层在所述蚀刻液中的蚀刻速率小于所述第二金属层在所述蚀刻液中的蚀刻速率；
B16：蚀刻所述有源层图案，以形成有源层；其中，在所述源极和/或所述漏极远离所述有源层的沟道区的一端，所述金属阻挡层包括第一凸部，所述第一凸部自所述导电金属层的端部向远离所述沟道区的方向延伸。
由此，在本申请第一实施例提供的阵列基板的制备方法中，通过在第一金属层和第二金属层的蚀刻过程中，使第一金属层在蚀刻液中的蚀刻速率小于第二金属层在蚀刻液中的蚀刻速率，进而使得第一金属层蚀刻后形成的金属阻挡层中形成有相较于导电金属层外凸的第一凸部。由于第一凸部位于有源层的上方，因此，第一凸部的形成能够减小有源层相较于金属阻挡层的外凸长度，也即，减小了有源层相较于源极和/或漏极的外凸长度，进而能够降低栅极和源极/漏极形成的寄生电容在光照和非光照条件下的差异，有利于提高阵列基板中驱动信号的稳定性。
下面对本申请第一实施例提供的阵列基板制备方法进行详细的阐述。
需要说明的是，本实施例中的阵列基板包括薄膜晶体管，所述薄膜晶体管可以为顶栅型结构，也可以为底栅型结构，本实施例仅以底栅型结构的薄膜晶体管为例进行说明，但并不限于此。
请一并参照图1、图2A至图2H，本申请第一实施例提供的阵列基板100的制备方法包括以下步骤：
B11：提供衬底10。
衬底10可以为硬质基板，如可以为玻璃基板；或者，衬底10也可以为柔性基板，如可以为聚酰亚胺基板，本申请对衬底10的材质不作具体限定。
在步骤B11之后，还包括：在衬底10上依次形成栅极11和栅极绝缘层12。其中，栅极11和栅极绝缘层12的材料及形成工艺均可以参照现有技术，在此不再赘述。
B12：在衬底10上依次形成有源基层13a、第一金属基层14a和第二金属基层15a，形成如图2A所示的结构。
B12具体包括以下步骤：
B121：在衬底10上依次形成非晶硅基层131a和欧姆接触基层132a，非晶硅基层131a和欧姆接触基层132a构成有源基层13a；
非晶硅基层131a的材料可以为非晶硅。欧姆接触基层132a的材料可以为掺杂的非晶硅，如可以为N型或P型掺杂的非晶硅。本实施例中，欧姆接触基层132a的材料为N型掺杂的非晶硅。
其中，在形成栅极绝缘层12之后，可以采用化学气相沉积法依次形成非晶硅基层131a和欧姆接触基层132a。
B122：在欧姆接触基层132a上形成第一金属基层14a；
第一金属基层14a的材料可以选自钼或钼合金中的至少一种。其中，所述钼合金可以为钼的二元合金，所述二元合金可以包括除钼之外的钛、铬、镍或铝中的一者；或者，所述钼合金还可以为钼的三元合金，所述三元合金可以包括除钼之外的钛、铬、镍和铝中的任意两者。
其中，在形成有源基层13a之后，可以采用溅射、热蒸发、电镀等成膜方式形成第一金属基层14a。
B123：在第一金属基层14a上形成第二金属基层15a。
第二金属基层15a的材料可以包括铜。在一些实施例中，第二金属基层15a的材料还可以包括钼、钛、铝、铬或镍中的一种或多种。
其中，在形成第一金属基层14a之后，可以采用溅射、热蒸发、电镀等成膜方式形成第二金属基层15a。
在步骤B12之后，还包括步骤：
在第二金属基层15a上涂覆一层光阻层16，如图2B所示；
利用半色调掩膜板或灰阶色调掩膜板对光阻层16进行曝光显影，以形成第一光阻图案161，第一光阻图案161两侧部分的厚度大于中间部分的厚度，如图2C所示。
B13：蚀刻第一金属基层14a和第二金属基层15a，以分别形成第一金属层141a和第二金属层151a，第一金属层141a和第二金属层151a构成源漏极图案14A，如图2D所示。
第一次湿法蚀刻：以第一光阻图案161为掩膜，采用湿法蚀刻工艺对第一金属基层14a和第二金属基层15a进行蚀刻处理。
具体的，利用蚀刻液蚀刻掉第一金属基层14a和第二金属基层15a未被第一光阻图案161覆盖的部分。由于湿法蚀刻对材料的蚀刻为各向同性，因此，蚀刻后形成的第一金属层141a和第二金属层151a在第一光阻图案161下方存在过刻区（图中未标识）。
需要说明的是，第一次湿法蚀刻中所用蚀刻液的具体成分可以参照现有技术，在此不再赘述。
B14：蚀刻有源基层13a，以形成有源层图案13A，如图2E所示。
第一次干法蚀刻：采用干法蚀刻工艺对第一光阻图案161和有源基层13a进行蚀刻处理。
所述干法蚀刻工艺可以在氧气气氛中进行。具体的，通过对第一光阻图案161进行灰化处理，以减薄第一光阻图案161的厚度，并去除第一光阻图案161中间区域的部分，以形成第二光阻图案162。与此同时，有源基层13a蚀刻形成为有源层图案13A。有源层图案13A包括非晶硅层131和欧姆接触层图案132b，非晶硅层131由非晶硅基层131a蚀刻形成，欧姆接触层图案132b由欧姆接触基层132a蚀刻形成。
B15：利用蚀刻液对第一金属层141a和第二金属层151a进行蚀刻，以分别形成金属阻挡层141和导电金属层151，源漏极图案14A形成为源极14和漏极15，如图2F所示，其中，第一金属层141a在蚀刻液中的蚀刻速率小于第二金属层151a在蚀刻液中的蚀刻速率。
第二次湿法蚀刻：以第二光阻图案162为掩膜，采用湿法蚀刻工艺对第一金属层141a和第二金属层151a进行蚀刻处理。
具体的，采用蚀刻液蚀刻掉第一金属层141a和第二金属层151a未被第二光阻图案162覆盖的部分。由于湿法蚀刻对材料的蚀刻为各向同性，因此，金属阻挡层141和导电金属层151在第二光阻图案162下方会存在过刻区（图中未标识）。
进一步的，第一金属层141a和第二金属层151a蚀刻过程中所用的蚀刻液包括酸性氧化剂和金属蚀刻剂，金属蚀刻剂用于控制第二金属层151a的蚀刻速率。其中，所述酸性氧化剂可以为过氧化氢。所述金属蚀刻剂可以为钼蚀刻剂。
在本实施例中，为了确保第一金属层141a在蚀刻液中的蚀刻速率小于第二金属层151a在蚀刻液中的蚀刻速率，将酸性氧化剂在蚀刻液中的质量含量设为5%-6%，金属蚀刻剂在蚀刻液中的质量含量设为0.01%-0.05%。在上述范围内，可以大大降低第一金属层141a在蚀刻液中的蚀刻速率，从而使得蚀刻之后形成的金属阻挡层141相较于导电金属层151外凸。
在一些具体实施方式中，酸性氧化剂在蚀刻液中的质量含量可以为5%、5.1%、5.2%、5.3%、5.4%、5.5%、5.6%、5.7%、5.8%、5.9%或6%。在另一些具体实施方式中，金属蚀刻剂在蚀刻液中的质量含量可以为0.01%、0.015%、0.02%、0.025%、0.03%、0.035%、0.04%、0.045%或0.05%。
如图2F所示，在源极14远离漏极15的一端以及漏极15远离源极14的一端，金属阻挡层141相较于导电金属层151外凸的部分为第一凸部1411。在源极14中，第一凸部1411自漏极15朝向源极14的方向延伸，在漏极15中，第一凸部1411自源极14朝向漏极15的方向延伸。需要说明的是，本实施例对应附图中仅对源极14中的第一凸部1411进行了标识，但并不能理解为对本申请的限制。
其中，采用本实施例的制备方法得到的第一凸部1411的长度n可达0.05μm-1.0μm。在一些具体实施方式中，第一凸部1411的长度n可以为0.05μm、0.08μm、0.1μm、0.2μm、0.3μm、0.5μm、0.8μm或1.0μm。
需要说明的是，在一些实施例中，第二次湿法蚀刻所用的蚀刻液还可以包括酸性稳定剂、PH调节剂、蚀刻抑制剂、金属离子稳定剂以及调节剂等成分，所述蚀刻液的具体成分可以根据实际应用需求进行选择，本申请对此不作限定。
B16：蚀刻有源层图案13A，以形成有源层13，有源层13位于源极14和漏极15之间的区域为沟道区17；其中，在源极14和/或漏极15远离沟道区17的一端，金属阻挡层141包括第一凸部1411，第一凸部1411自导电金属层151的端部向远离沟道区17的方向延伸，如图2G所示。
第二次干法蚀刻：以第二光阻图案162为掩膜，采用干法蚀刻工艺对有源层图案13A进行蚀刻处理。
具体的，以第二光阻图案162为掩膜，对有源层图案13A中的欧姆接触层图案132b进行蚀刻，以形成欧姆接触层132，欧姆接触层132和非晶硅层131构成有源层13，且欧姆接触层132分别与对应的源极14/漏极15相接触。其中，非晶硅层131具有第一子凸部1311。欧姆接触层132具有第二子凸部1321。在源极14远离沟道区17的一端以及漏极15远离沟道区17的一端，第一子凸部1311和第二子凸部1321均自第一凸部1411的端部向远离沟道区17的方向延伸。第一子凸部1311和第二子凸部1321构成有源层13的第二凸部13B。
在本实施例的第二次湿法蚀刻工艺中，由于金属阻挡层141中形成了第一凸部1411，相较于现有技术中金属阻挡层未形成有外凸部分的情况，本实施例能够减小第二次干法蚀刻之后得到的第二凸部13B的长度。也即，本实施例通过使金属阻挡层141相较于导电金属层151外凸，减小了有源层13相较于源极14和漏极15的外凸长度，进而能够降低栅极11和源极14/漏极15形成的寄生电容在光照和非光照条件下的差异，有利于提高阵列基板100中驱动信号的稳定性。
在本实施例中，在沟道区17朝向源极14的方向上，第二凸部13B的长度m处于0μm至2μm的范围内。也即，本实施例通过在金属阻挡层141中设置第一凸部1411，能够将第二凸部13B的长度m减小至2μm及以下。在一些具体实施例中，第二凸部13B的长度m可以为0.05μm、0.1μm、0.2μm、0.3μm、0.5μm、0.6μm、0.8μm、1.0μm、1.2μm、1.5μm、1.8μm或2μm。
在步骤B16之后，还包括：剥离第二光阻图案162，以形成如图2H所示的结构。
需要说明的是，在剥离第二光阻图案162之后，本实施例的阵列基板100的制备方法还包括在导电金属层151上形成钝化层、在钝化层上形成裸露出源极14/漏极15的过孔、以及在钝化层上形成通过上述过孔电连接源极14/漏极15的像素电极等步骤，相关技术可以参照现有技术，在此不再赘述。
由此，便完成了本申请第一实施例提供的阵列基板100的制备方法。
请参照图3，本申请第二实施例提供一种阵列基板的制备方法，其包括以下步骤：
B21：提供衬底；
B22：在所述衬底上依次形成有源基层、第一金属基层和第二金属基层；
B23：蚀刻所述第一金属基层和所述第二金属基层，以分别形成第一金属层和第二金属层，所述第一金属层和所述第二金属层构成源漏极图案；
B24：蚀刻所述有源基层，以形成有源层图案；
B25：利用蚀刻液对所述第二金属层进行蚀刻，以形成导电金属层；
B26：蚀刻所述第一金属层和所述有源层图案，以分别形成金属阻挡层和有源层，所述源漏极图案形成为所述源极和所述漏极；其中，在所述源极和/或所述漏极远离所述有源层的沟道区的一端，所述金属阻挡层包括第一凸部，所述第一凸部自所述导电金属层的端部向远离所述沟道区的方向延伸。
由此，在本申请第二实施例提供的阵列基板的制备方法中，在蚀刻第二金属层的步骤中并未蚀刻第一金属层，在第二金属层蚀刻形成导电金属层之后，再同时对第一金属层和有源层图案进行蚀刻，以分别形成金属阻挡层和有源层，使得最终形成的金属阻挡层中形成有相较于导电金属层外凸的第一凸部。由于第一凸部位于有源层的上方，因此，第一凸部的形成能够减小有源层相较于金属阻挡层的外凸长度，也即，减小了有源层相较于源极和/或漏极的外凸长度，进而能够降低栅极和源极/漏极形成的寄生电容在光照和非光照条件下的差异，有利于提高阵列基板中驱动信号的稳定性。
下面对本申请第二实施例提供的阵列基板的制备方法进行详细的阐述。
需要说明的是，本实施例中的阵列基板包括薄膜晶体管，所述薄膜晶体管可以为顶栅型结构，也可以为底栅型结构，本实施例仅以底栅型结构的薄膜晶体管为例进行说明，但并不限于此。
请一并参照图3、图4A至图4H，本申请第二实施例提供的阵列基板100的制备方法包括以下步骤：
B21：提供衬底10。
B22：在衬底10上依次形成有源基层13a、第一金属基层14a和第二金属基层15a。
B23：蚀刻第一金属基层14a和第二金属基层15a，以分别形成第一金属层141a和第二金属层151a，第一金属层141a和第二金属层151a构成源漏极图案14A。
B24：蚀刻有源基层13a，以形成有源层图案13A。
结合图4A至图4E，步骤B21-B24的具体工艺流程可以参照前述实施例中对步骤B11-B14的描述，在此不再赘述。
B25：利用蚀刻液对第二金属层151a进行蚀刻，以形成导电金属层151，如图4F所示。
第二次湿法蚀刻：以第二光阻图案162为掩膜，采用湿法蚀刻工艺对第二金属层151a进行蚀刻处理。
具体的，采用蚀刻液蚀刻掉第二金属层151a未被第二光阻图案162覆盖的部分。由于湿法蚀刻对材料的蚀刻为各向同性，因此，导电金属层151在第二光阻图案162下方会存在过刻区（图中未标识）。
步骤B25中所用的蚀刻液与前述实施例的步骤B15中所用蚀刻液的不同之处在于：本实施例中的蚀刻液未使用钼蚀刻剂，以确保第一金属层141a在第二次湿刻蚀刻中不被蚀刻掉。
B26：蚀刻第一金属层141a和有源层图案13A，以分别形成金属阻挡层141和有源层13，源漏极图案14A形成为源极14和漏极15，有源层13位于源极14和漏极15之间的区域为沟道区17；其中，在源极14和/或漏极15远离沟道区17的一端，金属阻挡层141包括第一凸部1411，第一凸部1411自导电金属层151的端部向远离沟道区17的方向延伸，如图4G所示。
第二次干法蚀刻：以第二光阻图案162为掩膜，采用干法蚀刻工艺对第一金属层141a和有源层图案13A进行蚀刻处理。
具体的，以第二光阻图案162为掩膜，对第一金属层141a和有源层图案13A中的欧姆接触层图案132b进行蚀刻，以分别形成金属阻挡层141和欧姆接触层132，欧姆接触层132和非晶硅层131构成有源层13，且欧姆接触层132分别与对应的源极14和漏极15相接触。其中，在源极14远离漏极15的一端以及漏极15远离源极14的一端，金属阻挡层141相较于导电金属层151形成第一凸部1411，在源极14中，第一凸部1411自漏极15朝向源极14的方向延伸，在漏极15中，第一凸部1411自源极14朝向漏极15的方向延伸。需要说明的是，本实施例对应附图中仅对源极14中的第一凸部1411进行了标识，但并不能理解为对本申请的限制。
在本实施例中，在源极14远离沟道区17的一端以及漏极15远离沟道的一端，欧姆接触层132的侧面与第一凸部1411的侧面齐平。非晶硅层131中形成有第二凸部13B。第二凸部13B自第一凸部1411的端部向远离沟道区17的方向延伸。
由于本实施例在第二次湿法蚀刻中并未蚀刻第一金属层141a，而是在第二次干法蚀刻中同时蚀刻第一金属层141a和有源层图案13A，上述蚀刻方式能够进一步增大金属阻挡层141中第一凸部1411的长度n。另外，由于第一凸部1411与欧姆接触层132同时形成，欧姆接触层132的侧面与第一凸部1411的侧面齐平，因而欧姆接触层132并不会遮挡下方的非晶硅层131，从而能够进一步减小非晶硅层131相较于第一凸部1411的外凸长度，也即，进一步减小了有源层13中第二凸部13B的长度。故而，本实施例通过使金属阻挡层141相较于导电金属层151外凸，能够进一步减小有源层13相较于源极14和漏极15的外凸长度，进而能够降低栅极11和源极14/漏极15形成的寄生电容在光照和非光照条件下的差异，有利于提高阵列基板100中驱动信号的稳定性。
其中，采用本实施例的制备方法得到的第一凸部1411的长度n可达0.05μm-1.5μm。在一些具体实施方式中，第一凸部1411的长度n可以为0.05μm、0.08μm、0.1μm、0.2μm、0.3μm、0.5μm、0.8μm、1.0μm、1.1μm、1.2μm、1.3μm、1.4μm或1.5μm。
相应的，第二凸部13B的长度为m处于0μm至2μm的范围内。也即，本实施例通过在金属阻挡层141中设置第一凸部1411，能够将第二凸部13B的长度m减小至2μm及以下。在一些具体实施例中，第二凸部13B的长度m可以为0.05μm、0.1μm、0.2μm、0.3μm、0.5μm、0.6μm、0.8μm、1.0μm、1.2μm、1.5μm、1.8μm或2μm。
在步骤B26之后，还包括：剥离第二光阻图案162，以形成如图4H所示的结构。
需要说明的是，在剥离第二光阻图案162之后，本实施例的阵列基板100的制备方法还包括在导电金属层151上形成钝化层、在钝化层上形成裸露出源极14/漏极15的过孔、以及在钝化层上形成通过上述过孔电连接源极14/漏极15的像素电极等步骤，相关技术可以参照现有技术，在此不再赘述。
由此，便完成了本申请第二实施例提供的阵列基板100的制备方法。
请参照图5，本申请第一实施例提供一种阵列基板100。阵列基板100包括衬底10、有源层13、源极14以及漏极15。有源层13设置在衬底10上。有源层13具有一沟道区17。源极14和漏极15设置在有源层13上。源极14和漏极15位于沟道区17的相对两侧。源极14和漏极15均包括依次设置在有源层13上的金属阻挡层141和导电金属层151。在源极14和/或漏极15远离沟道区17的一端，金属阻挡层141包括第一凸部1411。第一凸部1411自导电金属层151的端部向远离沟道区17的方向延伸。
其中，衬底10可以为硬质基板，如可以为玻璃基板；或者，衬底10也可以为柔性基板，如可以为聚酰亚胺基板，本申请对衬底10的材质不作具体限定。
阵列基板100还包括依次设置在衬底10上的栅极11和栅极绝缘层12。栅极绝缘层12位于栅极11靠近有源层13的一侧。其中，有源层13、栅极11、源极14以及漏极15构成薄膜晶体管（图中未标识）。需要说明的是，本申请中的薄膜晶体管可以为顶栅型结构，也可以为底栅型结构，本实施例仅以底栅型结构的薄膜晶体管为例进行说明，但并不限于此。
在本实施例中，导电金属层151的材料包括铜。在一些实施例中，导电金属层151的材料还可以包括钼、钛、铝、铬或镍中的一种或多种。
金属阻挡层141的材料包括钼或钼合金中的至少一种。其中，所述钼合金可以为钼的二元合金，所述二元合金可以包括除钼之外的钛、铬、镍或铝中的一者；或者，所述钼合金还可以为钼的三元合金，所述三元合金可以包括除钼之外的钛、铬、镍和铝中的任意两者。
在本实施例中，在源极14和漏极15远离沟道的一端，金属阻挡层141均可以包括第一凸部1411。在一些实施例中，还可以将第一凸部1411设置在源极14和漏极15中任意一者远离沟道的一端，在此不再赘述。
其中，第一凸部1411的长度n为0.05μm-1.0μm。具体的，第一凸部1411的长度n可以为0.05μm、0.08μm、0.1μm、0.2μm、0.3μm、0.5μm、0.8μm或1.0μm。
需要说明的是，本实施例对应附图中仅对源极14中的第一凸部1411进行了标识，但并不限于此。
在本实施例中，有源层13包括第二凸部13B。第二凸部13B自第一凸部1411的端部向远离沟道区17的方向延伸。由于第一凸部1411位于有源层13的上方，因此，相较于现有技术中未在金属阻挡层中设置外凸部分的情况，本实施例中第一凸部1411的设置可以覆盖部分有源层13，进而能够减小有源层13相较于源极14/漏极15外凸的长度，也即，减小了第二凸部13B的长度。
在沟道区17朝向源极14的方向上，第二凸部13B的长度为m处于0μm至2μm的范围内。也即，本实施例通过在金属阻挡层141中设置第一凸部1411，能够将第二凸部13B的长度减小至2μm及以下。在一些具体实施例中，第二凸部13B的长度m可以为0.05μm、0.1μm、0.2μm、0.3μm、0.5μm、0.6μm、0.8μm、1.0μm、1.2μm、1.5μm、1.8μm或2μm。
在本实施例中，有源层13包括非晶硅层131和欧姆接触层132。欧姆接触层132位于非晶硅层131靠近金属阻挡层141的一侧。在一些实施例中，有源层13也可以仅包括非晶硅层131，在此不再赘述。
第二凸部13B包括第一子凸部1311和第二子凸部1321。第一子凸部1311位于非晶硅层131中。第二子凸部1321位于欧姆接触层132中。在源极14远离沟道区17的一端以及漏极15远离沟道区17的一端，第一子凸部1311和第二子凸部1321均自第一凸部1411的端部向远离沟道区17的方向延伸。其中，第二凸部13B的长度m即为第一子凸部1311的长度（图中未标识）。
由于阵列基板100中的栅极11、源极14/漏极15以及存储电容（图中未示出）之间会产生寄生电容。本实施例通过将第二凸部13B的长度m减小至2μm及以下，能够降低阵列基板100中的寄生电容在光照和非光照条件下的差异，从而有利于提高阵列基板100中驱动信号的稳定性。
需要说明的是，本实施例中的阵列基板100可以采用前述第一实施例提供的阵列基板100的制备方法制备得到，相关制备方法可以参照前述第一实施例的描述，在此不再赘述。
请参照图6，本申请第二实施例提供一种阵列基板100，本申请第二实施例提供的阵列基板100与第一实施例的不同之处在于：第二凸部13B位于非晶硅层131中。在源极14和/或漏极15远离沟道区17的一端，欧姆接触层132的侧面与第一凸部1411的侧面齐平。第一凸部1411的长度n为0.05μm-1.5μm。
在本实施例中，在源极14远离沟道区17的一端以及漏极15远离沟道区17的一端，欧姆接触层132的侧面均与第一凸部1411的侧面齐平。在一些实施例中，也可以在源极14远离沟道区17的一端和漏极15远离沟道区17的一端的一者中，将欧姆接触层132的侧面设置为与第一凸部1411的侧面齐平。
在一些具体实施方式中，第一凸部1411的长度n可以为0.05μm、0.08μm、0.1μm、0.2μm、0.3μm、0.5μm、0.8μm、1.0μm、1.1μm、1.2μm、1.3μm、1.4μm或1.5μm。
一方面，本实施例通过将第一凸部1411的长度n设置在0.05μm-1.5μm，使得第一凸部1411覆盖了部分非晶硅层131，进而能够减小非晶硅层131相较于金属阻挡层141外凸的长度；另一方面，由于欧姆接触层132的侧面与第一凸部1411的侧面齐平，也即，欧姆接触层132并不会覆盖下方的非晶硅层131。因此，本实施例可以大大减小非晶硅层131相较于金属阻挡层141的外凸长度，进而能够减小有源层13相较于源极14和漏极15外凸的长度，也即，减小了第二凸部13B的长度。
在沟道区17朝向源极14的方向上，第二凸部13B的长度为m处于0μm至2μm的范围内。也即，本实施例通过在金属阻挡层141中设置第一凸部1411，并使欧姆接触层132的侧面与第一凸部1411的侧面齐平，能够将第二凸部13B的长度减小至2μm及以下。在一些具体实施例中，第二凸部13B的长度m可以为0.05μm、0.1μm、0.2μm、0.3μm、0.5μm、0.6μm、0.8μm、1.0μm、1.2μm、1.5μm、1.8μm或2μm。
需要说明的是，本实施例中的阵列基板100可以采用前述第二实施例提供的阵列基板100的制备方法制备得到，相关制备方法可以参照前述第二实施例的描述，在此不再赘述。
本申请实施例还提供一种显示面板，所述显示面板包括阵列基板100，所述阵列基板100可以为前述任一实施例所述的阵列基板100，阵列基板100的具体结构可以参照前述实施例的描述，在此不再赘述。
其中，在本实施例中，所述显示面板为液晶显示面板。在一些实施例中，所述显示面板也可以为有机发光二极管显示面板，在此不再赘述。
当将前述实施例中的阵列基板100应用至显示面板中时，在显示面板的驱动过程中，能够降低正负半帧条件下寄生电容的差异，进而显示面板在电场下发生横向串扰的几率，有利于改善显示产品的显示品味。
以上对本申请实施例所提供的一种阵列基板及其制备方法、显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其包括：
    衬底；
    有源层，设置在所述衬底上，所述有源层具有一沟道区；
    源极，设置在所述有源层上；以及
    漏极，设置在所述有源层上，所述源极和所述漏极位于所述沟道区的相对两侧，所述源极和所述漏极均包括依次设置在所述有源层上的金属阻挡层和导电金属层；
    其中，在所述源极和/或所述漏极远离所述沟道区的一端，所述金属阻挡层包括第一凸部，所述第一凸部自所述导电金属层的端部向远离所述沟道区的方向延伸。
  2. 根据权利要求1所述的阵列基板，其中，在所述沟道区朝向所述源极和/或所述漏极的方向上，所述第一凸部的长度为0.05μm-1.5μm。
  3. 根据权利要求2所述的阵列基板，其中，所述第一凸部的长度为1.0μm-1.5μm。
  4. 根据权利要求1所述的阵列基板，其中，所述有源层包括第二凸部，所述第二凸部自所述第一凸部的端部向远离所述沟道区的方向延伸。
  5. 根据权利要求4所述的阵列基板，其中，所述有源层包括非晶硅层和欧姆接触层，所述欧姆接触层位于所述非晶硅层靠近所述金属阻挡层的一侧，所述第二凸部包括第一子凸部和第二子凸部，所述第一子凸部位于所述非晶硅层中，所述第二子凸部位于所述欧姆接触层中；
    在所述源极和/或所述漏极远离所述沟道区的一端，所述第一子凸部和所述第二子凸部均自所述第一凸部的端部向远离所述沟道区的方向延伸。
  6. 根据权利要求4所述的阵列基板，其中，所述有源层包括非晶硅层和欧姆接触层，所述欧姆接触层位于所述非晶硅层靠近所述金属阻挡层的一侧，所述第二凸部位于所述非晶硅层中；
    在所述源极和/或所述漏极远离所述沟道区的一端，所述欧姆接触层的侧面与所述第一凸部的侧面齐平。
  7. 根据权利要求5所述的阵列基板，其中，在所述沟道区朝向所述源极和/或所述漏极的方向上，所述第二凸部的长度处于0μm至2μm的范围内。
  8. 根据权利要求1所述的阵列基板，其中，所述金属阻挡层的材料包括钼或钼合金中的至少一种，所述导电金属层的材料包括铜。
  9. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括：
    衬底；
    有源层，设置在所述衬底上，所述有源层具有一沟道区；
    源极，设置在所述有源层上；以及
    漏极，设置在所述有源层上，所述源极和所述漏极位于所述沟道区的相对两侧，所述源极和所述漏极均包括依次设置在所述有源层上的金属阻挡层和导电金属层；
    其中，在所述源极和/或所述漏极远离所述沟道区的一端，所述金属阻挡层包括第一凸部，所述第一凸部自所述导电金属层的端部向远离所述沟道区的方向延伸。
  10. 根据权利要求9所述的显示面板，其中，在所述沟道区朝向所述源极和/或所述漏极的方向上，所述第一凸部的长度为0.05μm-1.5μm。
  11. 根据权利要求10所述的显示面板，其中，所述第一凸部的长度为1.0μm-1.5μm。
  12. 根据权利要求9所述的显示面板，其中，所述有源层包括第二凸部，所述第二凸部自所述第一凸部的端部向远离所述沟道区的方向延伸。
  13. 根据权利要求12所述的显示面板，其中，所述有源层包括非晶硅层和欧姆接触层，所述欧姆接触层位于所述非晶硅层靠近所述金属阻挡层的一侧，所述第二凸部包括第一子凸部和第二子凸部，所述第一子凸部位于所述非晶硅层中，所述第二子凸部位于所述欧姆接触层中；
    在所述源极和/或所述漏极远离所述沟道区的一端，所述第一子凸部和所述第二子凸部均自所述第一凸部的端部向远离所述沟道区的方向延伸。
  14. 根据权利要求12所述的显示面板，其中，所述有源层包括非晶硅层和欧姆接触层，所述欧姆接触层位于所述非晶硅层靠近所述金属阻挡层的一侧，所述第二凸部位于所述非晶硅层中；
    在所述源极和/或所述漏极远离所述沟道区的一端，所述欧姆接触层的侧面与所述第一凸部的侧面齐平。
  15. 根据权利要求13所述的显示面板，其中，在所述沟道区朝向所述源极和/或所述漏极的方向上，所述第二凸部的长度处于0μm至2μm的范围内。
  16. 根据权利要求9所述的显示面板，其中，所述金属阻挡层的材料包括钼或钼合金中的至少一种，所述导电金属层的材料包括铜。
  17. 一种阵列基板的制备方法，其包括以下步骤：
    提供衬底；
    在所述衬底上依次形成有源基层、第一金属基层和第二金属基层；
    蚀刻所述第一金属基层和所述第二金属基层，以分别形成第一金属层和第二金属层，所述第一金属层和所述第二金属层构成源漏极图案；
    蚀刻所述有源基层，以形成有源层图案；
    利用蚀刻液对所述第一金属层和所述第二金属层进行蚀刻，以分别形成金属阻挡层和导电金属层，所述源漏极图案形成为源极和漏极，所述第一金属层在所述蚀刻液中的蚀刻速率小于所述第二金属层在所述蚀刻液中的蚀刻速率；
    蚀刻所述有源层图案，以形成有源层；
    其中，在所述源极和/或所述漏极远离所述有源层的沟道区的一端，所述金属阻挡层包括第一凸部，所述第一凸部自所述导电金属层的端部向远离所述沟道区的方向延伸。
  18. 根据权利要求17所述的阵列基板的制备方法，其中，所述利用蚀刻液对所述第一金属层和所述第二金属层进行蚀刻的步骤中，所述蚀刻液包括酸性氧化剂和金属蚀刻剂，所述酸性氧化剂在所述蚀刻液中的质量含量为5%-6%，所述金属蚀刻剂在所述蚀刻液中的质量含量为0.01%-0.05%。
  19. 根据权利要求17所述的阵列基板的制备方法，其中，所述有源基层包括依次形成的非晶硅基层和欧姆接触基层，所述有源层图案包括非晶硅层和欧姆接触层图案，所述蚀刻所述有源层图案的步骤，包括：
    蚀刻所述欧姆接触层图案，以形成欧姆接触层，所述非晶硅层和所述欧姆接触层构成所述有源层；其中，所述非晶硅层具有第一子凸部，所述欧姆接触层具有第二子凸部，在所述源极和/或所述漏极远离所述沟道区的一端，所述第一子凸部和所述第二子凸部均自所述第一凸部的端部向远离所述沟道区的方向延伸。
  20. 根据权利要求18所述的阵列基板的制备方法，其中，所述第一金属层的材料包括钼或钼合金中的至少一种，所述导电金属层的材料包括铜，所述酸性氧化剂为过氧化氢，所述金属蚀刻剂为钼蚀刻剂。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107154403A (zh) * 2016-03-02 2017-09-12 群创光电股份有限公司 晶体管阵列基板及应用的显示面板
CN107591415A (zh) * 2017-08-29 2018-01-16 惠科股份有限公司 一种阵列基板及其制造方法
US20190280016A1 (en) * 2018-03-09 2019-09-12 HKC Corporation Limited Manufacturing method of array substrate and array substrate
CN112071867A (zh) * 2020-09-17 2020-12-11 惠科股份有限公司 主动开关阵列基板、薄膜晶体管阵列基板的制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100415617B1 (ko) * 2001-12-06 2004-01-24 엘지.필립스 엘시디 주식회사 에천트와 이를 이용한 금속배선 제조방법 및박막트랜지스터의 제조방법
KR101345171B1 (ko) * 2007-11-14 2013-12-27 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
KR101593443B1 (ko) * 2009-02-19 2016-02-12 엘지디스플레이 주식회사 어레이 기판의 제조방법
KR101582946B1 (ko) * 2009-12-04 2016-01-08 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
KR101682078B1 (ko) * 2010-07-30 2016-12-05 삼성디스플레이 주식회사 박막 트랜지스터 표시판의 제조 방법
CN108417583B (zh) * 2018-03-09 2021-10-29 惠科股份有限公司 一种阵列基板的制造方法和阵列基板
US10727256B2 (en) * 2018-10-24 2020-07-28 HKC Corporation Limited Method for fabricating array substrate, array substrate and display

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107154403A (zh) * 2016-03-02 2017-09-12 群创光电股份有限公司 晶体管阵列基板及应用的显示面板
CN107591415A (zh) * 2017-08-29 2018-01-16 惠科股份有限公司 一种阵列基板及其制造方法
US20190280016A1 (en) * 2018-03-09 2019-09-12 HKC Corporation Limited Manufacturing method of array substrate and array substrate
CN112071867A (zh) * 2020-09-17 2020-12-11 惠科股份有限公司 主动开关阵列基板、薄膜晶体管阵列基板的制造方法

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