WO2023028814A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023028814A1
WO2023028814A1 PCT/CN2021/115556 CN2021115556W WO2023028814A1 WO 2023028814 A1 WO2023028814 A1 WO 2023028814A1 CN 2021115556 W CN2021115556 W CN 2021115556W WO 2023028814 A1 WO2023028814 A1 WO 2023028814A1
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WO
WIPO (PCT)
Prior art keywords
base substrate
layer
dielectric layer
display
pins
Prior art date
Application number
PCT/CN2021/115556
Other languages
English (en)
French (fr)
Inventor
周宏军
杜丽丽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/115556 priority Critical patent/WO2023028814A1/zh
Priority to EP21955387.2A priority patent/EP4273621A4/en
Priority to CN202180002360.3A priority patent/CN116097420A/zh
Priority to US17/791,956 priority patent/US20230127776A1/en
Publication of WO2023028814A1 publication Critical patent/WO2023028814A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/851—Division of substrate

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate and a display device.
  • the test is carried out by group lighting. Therefore, it is necessary to lead the signal lines used for testing each display panel from the display panel to the substrate. corresponding pins on the However, in this way, the signal line needs to cross the cutting line of the display panel, which is easily affected by the structure of the cutting line.
  • Embodiments of the present disclosure provide, including:
  • a base substrate including a display area and a peripheral area at least on one side of the display area;
  • a plurality of pins located in the peripheral region of the base substrate, configured to transmit electrical signals to the plurality of sub-pixels, the orthographic projections of the plurality of pins on the base substrate extend along a first direction and distributed at intervals along the second direction, the first direction intersects the second direction;
  • the plurality of leads are electrically connected to the plurality of sub-pixels through the plurality of leads;
  • a plurality of extension pads located on the side of the plurality of pins away from the display area, extending along the first direction and distributed at intervals along the second direction, the plurality of extension pads and the plurality of lead foot connection;
  • a plurality of partition structures, located between the plurality of extension pads and extending along the first direction, the orthographic projections of the plurality of partition structures on the base substrate are the same as those of the plurality of extension pads on the substrate
  • the orthographic projections on the base substrate do not overlap, and the plurality of isolation structures are configured to electrically insulate the plurality of elongated pads.
  • the plurality of partition structures and the plurality of extension pads are distributed alternately.
  • the plurality of partition structures and the plurality of extension pads are alternately distributed one by one.
  • the display substrate includes a first dielectric layer on the base substrate, the first dielectric layer has a plurality of first openings arranged along the second direction and extending along the first direction, the At least part of the extension pad is located in the first opening, and the first dielectric layer between adjacent first openings is the plurality of partition structures.
  • the display substrate includes a first dielectric layer located on the base substrate, and the first dielectric layer has a plurality of first openings arranged along the second direction and extending along the first direction, so The plurality of first openings are the plurality of partition structures, the extension pad is located on the side of the first dielectric layer between adjacent first openings away from the base substrate, and the plurality of The orthographic projection of the first opening on the base substrate does not overlap with the orthographic projection of the plurality of extension pads on the base substrate.
  • the display substrate further includes a second dielectric layer and a third dielectric layer located in the peripheral area, the second dielectric layer is located on the side of the first dielectric layer away from the base substrate, and the third dielectric layer layer is located on the side of the second dielectric layer away from the base substrate, the extension pad is located in the conductor layer between the first dielectric layer and the second dielectric layer, and the second dielectric layer has A second opening, the third dielectric layer has a third opening, the second opening and the third opening expose at least part of the extension pad.
  • the orthographic projections of the plurality of first openings on the base substrate are located within the orthographic projections of the second openings on the base substrate, and the second openings are on the base substrate
  • the orthographic projection of is located within the orthographic projection of the third opening on the base substrate.
  • each of the plurality of elongated pads has a first orthographic projection on the base substrate
  • each of the plurality of isolation structures has a second orthographic projection on the substrate substrate.
  • the distance between each first orthographic projection and the adjacent second orthographic projection in the first direction is in the range of 0um-20um.
  • the distance between the centerline of each first orthographic projection in the second direction and the centerlines of two second orthographic projections adjacent to the first orthographic projection in the second direction is equal.
  • the first direction is perpendicular to the second direction.
  • the orthographic projection of the isolation structure on the base substrate is a rectangle.
  • the first direction is not perpendicular to the second direction
  • the orthographic projection of the isolation structure on the base substrate is a parallelogram
  • the thickness of the first dielectric layer is in the range of 500nm-1000nm
  • the thickness of the extension pad in the direction perpendicular to the surface of the substrate is in the range of 200nm-900nm.
  • the size of the partition structure in the first direction is smaller than the size of the extension pad in the first direction.
  • the display substrate further includes: a test-related circuit, located in the peripheral area, arranged on the side of the plurality of pins facing the display area, and surrounding at least a part of the display area, the test-related The circuit is connected to a plurality of subpixels in the display area through a plurality of signal lines, and connected to a plurality of pins through a plurality of lead wires.
  • a test-related circuit located in the peripheral area, arranged on the side of the plurality of pins facing the display area, and surrounding at least a part of the display area, the test-related The circuit is connected to a plurality of subpixels in the display area through a plurality of signal lines, and connected to a plurality of pins through a plurality of lead wires.
  • the plurality of extension pads includes at least one first extension pad and at least one second extension pad, each first extension pad is connected to one of the plurality of pins, and each second extension pad is connected to one of the plurality of pins. At least two of the plurality of pins are connected, and the line width of the first extended pad is smaller than the line width of the second extended pad.
  • the test-related circuits include a unit test circuit
  • the plurality of signal lines include a plurality of data lines
  • the plurality of lead wires include a plurality of unit test control signal lines
  • the plurality of pins include a plurality of first lead wires. feet
  • the unit test circuit is connected to a plurality of sub-pixels in the display area through the plurality of data lines, and connected to the plurality of first pins through the unit test control signal line.
  • the test-related circuit further includes a driving circuit
  • the plurality of signal lines further includes a plurality of driving signal lines
  • the plurality of lead wires further includes a plurality of driving control signal lines and a plurality of driving test signal lines
  • the plurality of pins also includes a plurality of second pins
  • the driving circuit is connected to a plurality of sub-pixels in the display area through the plurality of driving signal lines, and is connected to the plurality of sub-pixels in the display area through the plurality of driving control signal lines and the plurality of driving test signal lines.
  • the second pin is connected.
  • test-related circuit further includes a multiplexing circuit
  • the plurality of leads further includes a plurality of multiplexing control signal lines
  • the plurality of pins further includes a plurality of third pins
  • the multiplexing circuit is connected to a plurality of sub-pixels in the display area through the plurality of data lines, and is connected to the plurality of third pins through the plurality of multiplexing control signal lines connect.
  • the test-related circuit further includes a power supply voltage line and a reference voltage line
  • the multiple signal lines also include a first power supply voltage wiring and a first reference voltage wiring
  • the plurality of lead wires also include a power supply voltage second wiring.
  • the plurality of pins further includes a plurality of fourth pins, and,
  • the power supply voltage line is connected to a plurality of sub-pixels in the display area through the first power supply voltage line
  • the reference voltage line is connected to a plurality of sub-pixels in the display area through the first reference voltage line.
  • a plurality of sub-pixels, the power supply voltage line is connected to at least one fourth pin of the plurality of fourth pins through the second power supply voltage line
  • the reference voltage line is connected to at least one fourth pin through the second reference voltage line
  • a wire is connected to at least another fourth pin of the plurality of fourth pins.
  • the display substrate further includes: a fourth dielectric layer, located in the peripheral region, arranged between the first dielectric layer and the base substrate, and has a fourth opening, the fourth opening is in the substrate
  • the orthographic projection on the base substrate is located within the orthographic projection of the second opening on the base substrate
  • the orthographic projection of the plurality of first openings on the base substrate is located within the orthographic projection of the fourth opening on the base substrate. within the orthographic projection on the substrate substrate.
  • the display substrate further includes: a fifth dielectric layer located in the peripheral area, arranged between the second dielectric layer and the third dielectric layer and having a fifth opening, the fifth opening is formed on the base substrate
  • the orthographic projection of the third opening on the base substrate is within the orthographic projection of the second opening on the base substrate, and the orthographic projection of the second opening on the base substrate is within the orthographic projection of the fifth opening on the base substrate In the orthographic projection on .
  • At least one of the plurality of sub-pixels includes a driving thin film transistor and a storage capacitor
  • the driving thin film transistor includes an active layer located on the base substrate, a gate located on a side of the active layer away from the base substrate, and a gate located between the active layer and the gate A first gate insulating layer, a second gate insulating layer located on a side of the gate away from the base substrate, an interlayer dielectric layer located on a side of the second gate insulating layer away from the base substrate, and a second gate insulating layer located on a side away from the base substrate, and The source and drain on the side of the interlayer dielectric layer away from the base substrate;
  • the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is located on the same layer as the gate, and the second capacitor electrode is located between the second gate insulating layer and the interlayer dielectric layer between;
  • the plurality of extension pads are arranged on the same layer as at least one of the source electrodes and the drain electrodes of the plurality of sub-pixels, and the first dielectric layer located in the peripheral area is arranged on the same layer as the interlayer dielectric layer.
  • At least one of the plurality of sub-pixels further includes:
  • an anode located on the side of the planar layer away from the base substrate and connected to the source or the drain through the planar layer;
  • a pixel defining layer located on a side of the planar layer away from the base substrate and partially covering the anode
  • the second dielectric layer located in the peripheral area is provided on the same layer as the planar layer, and the third dielectric layer located on the peripheral area is provided on the same layer as the pixel defining layer.
  • At least one of the plurality of sub-pixels further includes:
  • a via electrode located on a side of the first planar layer away from the base substrate, and connected to the source of the thin film transistor through a via hole provided in the first planar layer;
  • the second flat layer is located on the side of the transfer electrode away from the base substrate;
  • an anode located on a side of the second planar layer away from the base substrate and connected to the transfer electrode through a via hole in the second planar layer;
  • a pixel defining layer located on a side of the second planar layer away from the base substrate and at least partially covering the anode
  • the peripheral area of the base substrate further includes a fifth dielectric layer located between the second dielectric layer and the third dielectric layer, the second dielectric layer and the first flat layer are arranged in the same layer, and the The third medium layer is set on the same layer as the pixel defining layer, and the fifth medium layer is set on the same layer as the second flat layer.
  • At least one of the plurality of sub-pixels further includes a buffer layer located between the base substrate and the first gate insulating layer;
  • the peripheral region of the base substrate further includes a fourth dielectric layer located between the first dielectric layer and the base substrate, the fourth dielectric layer and the buffer layer, the first gate insulating layer and the At least one of the second gate insulating layers is disposed in the same layer.
  • a display device includes the above-mentioned display substrate.
  • FIG. 1 shows a schematic plan view of a substrate to be cut according to an embodiment of the present disclosure.
  • FIG. 2 shows a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic diagram of the display area in FIG. 2 .
  • FIG. 4 shows a schematic diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 5 shows a schematic diagram of a unit test circuit according to an embodiment of the disclosure.
  • FIG. 6 shows a schematic plan view of an intersection region of a display substrate before cutting according to an embodiment of the present disclosure.
  • Fig. 7 shows a sectional view along AA' of Fig. 6 .
  • Fig. 8 shows a sectional view of Fig. 6 along BB'.
  • FIG. 9A shows a layout diagram of an intersection area before cutting according to an embodiment of the present disclosure.
  • Fig. 9B shows the layout diagram of the intersection area after cutting according to an embodiment of the present disclosure
  • FIG. 10 shows a schematic plan view of an intersection area of a display substrate according to another embodiment of the present disclosure.
  • Fig. 11 shows a sectional view along AA' of Fig. 10 .
  • Fig. 12 shows a sectional view of Fig. 10 along BB'.
  • FIG. 13 shows a structural diagram of sub-pixels in a display area according to an embodiment of the present disclosure.
  • FIG. 14 shows a schematic plan view of an intersection area of a display substrate according to another embodiment of the present disclosure.
  • FIG. 15 shows a schematic plan view of an intersection area of a display substrate according to another embodiment of the present disclosure.
  • FIG. 16 shows a schematic plan view of an intersection area of a display substrate according to another embodiment of the present disclosure.
  • Fig. 17 shows a sectional view along AA' of Fig. 16 .
  • Fig. 18 shows a sectional view of Fig. 16 along BB'.
  • FIG. 19 shows a structural diagram of sub-pixels of a display area according to another embodiment of the present disclosure.
  • connection may refer to two components being directly connected, or may refer to two components being connected via one or more other components. Furthermore, these two components can be connected or coupled by wire or wirelessly.
  • the gate layer it can be the first gate layer or the second gate layer
  • Source and drain layer leads the organic layer and the inorganic layer need to be excavated at the position of the cutting line to facilitate cutting.
  • the signal line is routed on the gate layer, in order to avoid etching away the metal of the gate layer by the anode wet etching process, it is necessary to use an interlayer dielectric layer to protect the signal line of the gate layer.
  • the other design adopts the source-drain layer wiring, but because the dicing line digs out the organic layer, inorganic layer and other film layers, the channel is relatively deep, and it is easy to break in the source-drain layer etching process or the anode etching process. There is a metal residue at the scribe line position, and there is a risk of short circuit of the signal line.
  • FIG. 1 shows a schematic plan view of a substrate to be cut according to an embodiment of the present disclosure.
  • the substrate to be cut includes a plurality of display substrates 100 , and in FIG. 1 , the plurality of display substrates 100 are arranged in an array, such as a 2 ⁇ 4 array.
  • a plurality of display substrates 100 may be arranged in other forms as required, and the number of display substrates 100 may also be set as required.
  • Each display substrate 100 includes a base substrate 110 . Multiple display substrates 100 on the substrate to be cut may share one base substrate 110 .
  • the substrate substrate 110 may be a rigid substrate substrate, such as a glass substrate.
  • the substrate substrate 110 may be a flexible substrate substrate, such as a flexible substrate substrate made of polyimide material.
  • a plurality of display areas AA and a peripheral area PA located at least one side of the display areas are disposed on the base substrate 110 .
  • a plurality of sub-pixels are arranged in the display area AA.
  • the substrate to be cut is further provided with a plurality of cutting lines 120 respectively surrounding the plurality of display areas AA, for example, each display area AA is surrounded by a corresponding cutting line 120 .
  • the cutting lane is the definition of the area where cutting is performed, rather than a solid structure.
  • connection traces SS and multiple sets of contact pads 140 are also arranged on the substrate to be cut.
  • Multiple groups of contact pads 140 are located outside each display substrate 100 .
  • a plurality of sub-pixels in the display area AA of each display substrate 100 are connected to a group of contact pads in the plurality of groups of contact pads 140 through a group of connection wires in the plurality of groups of connection wires SS.
  • FIG. 1 only two connection wires SS and two contact pads 140 are shown for each display substrate 100 for the sake of simplicity, but this is only for illustration, and any number of connection wires SS and contact pads 140 can be set as required in practice.
  • Contact pad 140 is only two connection wires SS and two contact pads 140 are shown for each display substrate 100 for the sake of simplicity, but this is only for illustration, and any number of connection wires SS and contact pads 140 can be set as required in practice.
  • connection wire SS and the contact pad 140 can be used to perform a cell test (Cell Test) on the sub-pixels in the display area AA.
  • Cell Test Cell Test
  • the unit test of the sub-pixels in the display area AA of each display substrate 100 can be implemented by applying various test signals for unit test to the contact pads 140 .
  • the substrate to be cut can be cut, for example, cut along each cutting line 120 , such as but not limited to wheel cutting or laser cutting, so as to obtain a plurality of independent display substrates 100 .
  • the cutting area defined along each cutting line corresponds to an independent display substrate 100 , and the structure of the display substrate will be described in detail below with reference to FIGS. 2 to 5 .
  • FIG. 2 shows a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a display area AA and a peripheral area PA at least on one side of the display area.
  • FIG. 2 shows the structure of the display substrate on the substrate to be cut before it is cut, so the boundary of the display substrate is defined by the cutting line 120 surrounding the display area.
  • the projection of the display area AA on the base substrate has a circular outline
  • the projection of the cutting line 120 on the base substrate is a strip extending around the display area AA, and the pattern surrounded by the strip is generally circular.
  • the embodiments of the present disclosure are not limited thereto, and the projection shapes of the cutting line and the display area can be set as required.
  • the projection of the base substrate of the display area can be a rectangle, a rounded rectangle, an ellipse, a polygon, etc.
  • the cutting lines around the display area can be designed to have corresponding projection patterns, such as rectangles, rounded rectangles, circles, etc. shapes, ovals, polygons, and even irregular shapes.
  • a plurality of pins 160 for transmitting electrical signals to the plurality of sub-pixels are further arranged in the peripheral area PA on at least one side of the display area AA.
  • a plurality of pins 160 are located on one side of the display area AA (in FIG. 2, the side near the straight edge of the scribe line).
  • the orthographic projections of the plurality of pins 160 on the substrate can extend along the first direction and be distributed along the second direction at intervals, for example, they can be arranged in one row or more along one edge of the display area. line, which will be explained in more detail below.
  • the embodiments of the present disclosure are not limited thereto, and the positions of the test-related circuit 150 and the pin 160 can be set as required.
  • Test related circuitry 150 may include unit test circuitry 1501.
  • the test-related circuit may further include at least one of a driving circuit 1502 , a multiplexing circuit 1503 , a power supply voltage line 1504 and a reference signal line 1505 .
  • the test-related circuit 150 is arranged on a side of the plurality of pins 160 facing the display area AA, and surrounds at least a part of the display area AA.
  • the test-related circuit 150 may be connected to a plurality of sub-pixels in the display area AA through a plurality of signal lines, and connected to the plurality of pins 160 through a plurality of lead wires.
  • the unit test circuit 1501 may be disposed on one side of the display area AA, for example, in FIG. 2 around the edge of the side of the display area AA away from the plurality of pins 160 .
  • the cell test circuit 1501 can be connected to multiple sub-pixels in the display area AA, and is used to perform a cell test (Cell Test) on the multiple sub-pixels in the display area.
  • a plurality of unit test control signal lines connected to the unit test circuit 1501 can be led out to a plurality of pins 160 .
  • the driving circuit 1502 can be arranged around the display area AA, so that the unit test circuit 1501 is located between the driving circuit 1502 and the display area AA.
  • the driving circuit 1502 may include a gate driving circuit and a light-emitting driving circuit.
  • the gate driving circuit is used to turn on the sub-pixels in the display area AA, and the light-emitting driving circuit is used to control the turned-on sub-pixels to emit light.
  • a plurality of driving control signal lines and a plurality of driving test signal lines connected to the driving circuit 1502 can be led out to the pin 160 .
  • the multiplexing circuit 1503 may be located on the side of the display area AA away from the unit test circuit 1501 , for example, arranged around the edge of the side of the display area AA away from the unit test circuit 1501 .
  • the multiplexing circuit 1503 is used to multiplex the received input signal into a multiplexed signal and provide it to multiple sub-pixels in the display area AA.
  • Multiple multiplexing control signal lines connected to the multiplexing circuit 1503 can be drawn out to the pin 160 .
  • the power supply voltage line 1504 and the reference voltage line 1505 are used to supply power to various elements in the display substrate, for example, to supply power to sub-pixels in the display area AA.
  • the power supply voltage line 1504 and the reference voltage line 1505 can also be used to supply power to at least one of the above-mentioned unit test circuit 1501 , drive circuit 1502 and multiplexing circuit 1503 .
  • the power supply voltage line 1504 is in the form of a ring, surrounds the display area AA, and is located in the area between the display area AA and the unit test circuit 1501 and the multiplexing circuit 1503;
  • the reference voltage line 1505 is in the form of a ring, and surrounds
  • the driving circuit 1502 described above is provided.
  • the supply voltage line 1504 is connected to at least two pins 160 of the plurality of pins 160 through Y-shaped voltage lines
  • the reference voltage line 1505 is connected to the plurality of pins 160 through two strip-shaped extending voltage lines. at least two other pins in the
  • a plurality of pins 160 are respectively connected to a plurality of connection wires SS. It can be seen from FIG. 2 that the scribe line 120 intersects with a plurality of connection traces SS in the area indicated by the dotted line, and the intersecting area will be described in detail below.
  • FIG. 3 shows a schematic diagram of the display area in FIG. 2 .
  • a plurality of sub-pixels Px1 are arranged in the display area AA, and the plurality of sub-pixels Px1 are arranged in the form of an array.
  • a plurality of sub-pixels Px1 are arranged in N rows and M columns.
  • the arrays are arranged in a circle as a whole, so that the projection of the display area AA on the base substrate 110 has a circular outline.
  • the embodiments of the present disclosure are not limited thereto, and the plurality of sub-pixels Px1 may be arranged in arrays of other shapes, such as rectangles, rounded rectangles, polygons, etc., as required.
  • a plurality of gate lines G1, G2, . . . GN electrically connected to the plurality of sub-pixels Px1 are also arranged in the display area AA.
  • N rows of sub-pixels Px1 are connected to N gate lines G1, G2, ... GN in one-to-one correspondence
  • M columns of sub-pixels Px1 are connected to M data lines D1, D2, ... DM in one-to-one correspondence. That is to say, each row of sub-pixels is connected to a gate line, and each column of sub-pixels is connected to a data line.
  • the embodiments of the present disclosure are not limited thereto, and the number and connection mode of gate lines and data lines can be selected according to needs, for example, two gate lines can be connected to each row of sub-pixels, and the number of gate lines is the number of sub-pixel rows or twice the number of sub-pixels; or every two columns of sub-pixels are connected with a data line, the number of data lines is half of the number of sub-pixel columns, and so on.
  • the gate drive circuit applies a gate drive signal to the gate lines G1 to GN to turn on each row of sub-pixels Px1, and the source drive circuit applies a source drive signal to the data lines D1 to DM to make the turned-on sub-pixels Px1
  • the pixel Px1 performs display according to the applied source driving signal.
  • a plurality of light emission control lines connected to the plurality of sub-pixels may also be provided in the display area, and the light emission driving circuit provides light emission control signals to the plurality of sub-pixels through the plurality of light emission control lines.
  • FIG. 4 shows a schematic diagram of a display substrate according to another embodiment of the present disclosure.
  • the display substrate shown in FIG. 4 is a display substrate cut from a substrate to be cut.
  • the display substrate includes a base substrate 110 , a plurality of pins, a plurality of leads 71 , 74 , 75 , 78 and 79 and a plurality of extension pads 130 .
  • the multiple extension pads 130 are obtained by cutting the above multiple connecting wires.
  • the plurality of pins includes at least one of a plurality of first pins 1601 , a plurality of second pins 1602 , a plurality of third pins 1603 and a plurality of fourth pins 1604 .
  • a plurality of pins 1601 to 1604 are electrically connected to the plurality of sub-pixels through the plurality of lead wires 71 , 74 , 75 , 78 and 79 .
  • a plurality of extension pads 130 are located on a side of the plurality of pins 1601 to 1604 away from the display area AA, extend along the first direction and are distributed along the second direction at intervals, and the plurality of extension pads 130 and The plurality of pins 1601 to 1604 are electrically connected.
  • the test-related circuits on the display substrate may include at least one of a unit test circuit 65 , a drive circuit 61 , a multiplexing circuit 64 , a power supply voltage line 68 and a reference voltage line 69 .
  • the test-related circuits are connected to a plurality of sub-pixels in the display area AA through a plurality of signal lines, and connected to a plurality of pins 1601 to 1604 through a plurality of lead wires 71 , 74 , 75 , 78 and 79 .
  • the plurality of pins may include at least one of a plurality of first pins 1601 , a plurality of second pins 1602 , a plurality of third pins 1603 and a plurality of fourth pins 1604 .
  • the unit test circuit 65 can be connected to a plurality of sub-pixels in the display area AA through a plurality of data lines, and connected to a plurality of first pins 1601 through a plurality of lead wires 75 .
  • the plurality of leads 75 may include a unit test control signal line used by the unit test circuit to receive a unit test control signal, which includes but not limited to a switch trace SW, a first test data trace DR, a second test data trace DG, and a second test data trace DG. At least one of the three test data traces DB.
  • the switch wire SW may include a first switch wire SWR, a second switch wire SWG, and a third switch wire SWB.
  • the driving circuit 61 may be connected to a plurality of sub-pixels in the display area AA through a plurality of driving signal lines, and connected to a plurality of second pins 1602 through a plurality of lead wires 71 .
  • a plurality of driving signal lines may be the routing lines used by the driving circuit to provide driving signals, including but not limited to gate lines and light emission control lines.
  • the pixels provide gate driving signals, and the light-emitting driving circuit provides light-emitting driving signals to the sub-pixels in the display area AA through the light-emitting control lines, thereby controlling the sub-pixels to emit light.
  • the plurality of lead wires 71 may include a plurality of driving control signal lines and a plurality of driving test signal lines.
  • the plurality of drive control signal lines include a gate drive control signal line connected to the gate drive circuit and a light emission drive control signal line connected to the light emission drive circuit.
  • the gate drive control signal line is used to provide the gate drive circuit with the drive control signal required for gate drive, including but not limited to the first start signal line GSTV, the first clock signal line GCK, the second clock signal line GCB.
  • the light-emitting drive control signal lines are used to provide light-emitting control signals required for light-emitting driving to the light-emitting driving circuit, including but not limited to the second start signal line ESTV, the third clock signal line ECK, and the fourth clock signal line ECB.
  • the driving test signal lines include but not limited to the gate output signal wiring Gout connected to the output end of the gate driving circuit and the light output signal wiring Eout connected to the output end of the light emitting driving circuit.
  • the multiplexing circuit 64 is connected to a plurality of sub-pixels in the display area AA through a plurality of data lines, and is connected to the third group of pins 1603 through a plurality of leads 74 .
  • the plurality of leads 74 may include switch control signal lines for controlling the multiplexing circuit to generate multiple multiplexed signals, such as but not limited to a multiplexed signal line for multiplexing each input signal into 6 output signals.
  • the power supply voltage line 68 can be connected to various circuit elements in the display area through the first power supply voltage wiring, and connected to at least one of the fourth pins 1604 through the lead 78 (the second power supply voltage wiring).
  • the reference voltage line 69 can be connected to various circuit elements in the display area through the first reference voltage wiring, and connected to at least another one of the fourth pins 1604 through the lead 79 (the second reference voltage wiring).
  • the second wiring 78 of the power supply voltage may be, for example, a Y-shaped wiring as shown in FIG. 4 , and the two leading ends of the Y-shaped wiring are respectively connected to two fourth pins 1604 .
  • the second reference voltage wiring 79 can be, for example, two strip-shaped wirings extending substantially straight as shown in FIG.
  • the supply voltage line 68 may include at least one of the following: a first supply voltage line VDD, a second supply voltage line ELVDD, a third supply voltage line VGH, and an initial voltage line VINT.
  • the reference voltage line 69 may include at least one of the following: a first reference voltage line VSS, a second reference voltage line ELVSS, and a third reference voltage line VGL.
  • a plurality of pins 1601 , 1602 , 1603 , 1604 are respectively connected to a plurality of extension pads 130 , for example, can be connected in a one-to-one correspondence.
  • one or more pins may be set to be redundant (Dummy), that is, not electrically connected to other circuit structures.
  • multiple pins may be connected to one extension pad 130 , or one pin may be connected to multiple extension pads 130 , which is not limited in the present disclosure.
  • an initial voltage line 67 may also be provided in the peripheral area PA.
  • the initial voltage line 67 is connected to the sub-pixels in the display area through the first initial voltage line, and connected to the subpixels in the display area through the second initial voltage line 77.
  • a data driving line 73 may also be provided in the peripheral area PA, and the data driving line 73 may be connected to the multiplexing circuit for providing input data signals to the multiplexing circuit.
  • Each data driving line 73 can correspond to multiple data lines.
  • the data driving line 73 may be connected to the sixth pin.
  • the unit test circuit, the driver circuit, the multiplexing circuit, the power supply voltage line and the reference voltage line, and the signal lines and leads connected to these circuits are shown in specific positions and layouts in the above embodiments, this is only In order to illustrate their electrical connections, their actual positions and layouts are not limited.
  • FIG. 5 shows a schematic diagram of a unit test circuit according to an embodiment of the disclosure.
  • the unit test circuit can be applied to the display substrate of any of the above embodiments.
  • the unit test control signal line connected to the unit test circuit includes a first switch trace SWR, a second switch trace SWG and a third switch trace SWB, a first test data trace DR, a second test trace data traces DG and a third test data trace DB.
  • the unit test circuit CT may include a plurality of test sub-circuits, at least one of which includes a first transistor, a second transistor, and a third transistor. 5 only shows 4 transistors in the unit test circuit CT for the sake of simplicity, wherein the first test sub-circuit includes transistors T1 (first transistor), T2 (second transistor) and T3 (third transistor), and Transistor T1' belongs to another first test subcircuit (as its first transistor), and so on.
  • the gate of the transistor T1 is electrically connected to the first switch wire SWR
  • the gate of the transistor T2 is electrically connected to the second switch wire SWG
  • the gate of the transistor T3 is electrically connected to the third switch wire SWB.
  • the first pole of the transistor T1 is electrically connected to the first test data line DR
  • the first pole of the transistor T2 is electrically connected to the second test data line DG
  • the first pole of the transistor T3 is electrically connected to the third test data line DB .
  • the second pole of the transistor T1, the second pole of the transistor T2 and the second pole of the transistor T3 are respectively electrically connected to three data lines DATA1, DATA2 and DATA3.
  • transistors T1 , T2 and T3 may be connected to the same switch trace SW.
  • intersection region of the display substrate will be described below with reference to FIGS. 6 to 9B .
  • FIG. 6 shows a schematic plan view of an intersection region of a display substrate before cutting according to an embodiment of the present disclosure.
  • Fig. 7 shows a sectional view along AA' of Fig. 6 .
  • Fig. 8 shows a sectional view of Fig. 6 along BB'.
  • the intersecting area before cutting shown in FIGS. 6 to 8 may correspond to, for example, the area X1 shown by the dotted line box in FIG. 2 .
  • the peripheral region of the base substrate 110 includes a first dielectric layer 112A on the base substrate 110, and the first dielectric layer 112A has a plurality of rows along the second direction (BB').
  • a plurality of first openings 1201A extending along the first direction (AA'). At least a portion of the first dielectric layer 112A is removed to form a first opening 1201A.
  • At least part of the extension pad 130A is located in the first opening 1201A, and the first dielectric layer 112A between adjacent first openings 1201A forms a plurality of isolation structures. As shown in FIG. 6 to FIG.
  • the plurality of isolation structures formed by the first dielectric layer 112A between adjacent first openings 1201A are located between the plurality of extension pads 130 and extend along the second direction, the plurality of isolation structures
  • the orthographic projection on the base substrate 110 does not overlap with the orthographic projection of the plurality of extension pads 130A on the base substrate 110, and the plurality of partition structures can make electrical connections between the plurality of extension pads 130A insulation. Since the display substrate has not been cut from the substrate to be cut in the embodiments of FIGS. 6 to 8 , the plurality of extension pads 130A serve as connection traces for connecting with contact pads outside the display substrate.
  • the display substrate may further include a second dielectric layer 113 and a third dielectric layer 114 sequentially stacked on the first dielectric layer 112A.
  • a plurality of extension pads 130A are located between the first dielectric layer 112A and the second dielectric layer 113 .
  • At least a part of each of the second dielectric layer 113 and the third dielectric layer 114 is removed to form the second opening 1202 and the third opening 1203 , and the position of the scribe line may be defined by the second opening and/or the third opening.
  • the projection of the first opening 1201A on the base substrate 110 is located within the projection of the second opening 1202 on the base substrate 110, and the projection of the second opening 1202 on the base substrate 110 is located within the projection of the third opening 1203 on the base substrate 110. within the projection above.
  • the extension direction of the cutting line can be defined by the cutting line CL, the cutting line refers to the center line of the cutting line in its extending direction, which is a virtual line, the distance between the line and the two sides of the cutting line equal.
  • a plurality of first openings 1201A are disposed in the first dielectric layer 112A, so that the plurality of extension pads 130 are isolated from each other by the plurality of first openings 1201A.
  • a plurality of first openings 1201A separated from each other extend in a first direction (a direction indicated by a dotted line AA') and are arranged in a second direction (a direction indicated by a dotted line BB'), the first direction being the The extending direction of the plurality of extension pads 130A, the second direction is the extending direction of the cutting lines.
  • the dimension (also referred to as length) of the projection of the extension pad 130A along the AA' direction is larger than that of the first opening 1201A, and in the BB' direction
  • the upper dimension (also referred to as width) is less than or equal to the first opening 1201A, so that the projection of the extension pad 130A spans the projection of the first opening 1201A along the AA' direction and is completely within the projection of the first opening 1201A along the BB direction.
  • the centerline of each first projection 130A in the first direction coincides with the centerline of the corresponding second projection 1201A in the first direction, that is, the centerlines of the two in the length direction coincide .
  • the centerlines of the two may have a certain offset from each other.
  • the distance between each first projection 130A and the corresponding second projection 1201A in the second direction is within a range of 0 um-20 um. Taking a first projection 130A in FIG.
  • the distance between the left edge of the first projection 130A and the left edge of the second projection 1201A and the first The distance between the right edge of the projection 130A and the right edge of the second projection may both be in the range of 0 um-20 um, and they may be equal or unequal.
  • adjacent extension pads 130A can be isolated by the material of the first dielectric layer 112A, thereby avoiding the occurrence of metal residues between adjacent extension pads 130A during the etching process of extension pads 130A.
  • the extension pad 130A is shorted.
  • the first direction (AA') is perpendicular to the second direction (BB'), and the second projection 1201A is a rectangle.
  • embodiments of the present disclosure are not limited thereto.
  • the technical concept of the present disclosure is applicable to any other cross-extended signal lines and scribe lines, for example, the signal lines and scribe lines cross each other non-perpendicularly or the signal lines and scribe lines extend and intersect along two arcs or even irregular trajectories, This will be described in further detail below.
  • At least one of the plurality of first openings 1201A can also be set to be redundant, and the redundant first opening does not overlap with the extension pad 130A, for example, in FIG.
  • the two first openings on the left and the rightmost are redundant first openings.
  • the thickness of the first dielectric layer 112A in the direction perpendicular to the surface of the base substrate 110 may be in the range of 500nm-1000nm, and the thickness of the extension pad 130A in the direction perpendicular to the substrate The thickness in the surface direction of the substrate 110 is in the range of 200nm-900nm.
  • a fourth dielectric layer 111 located between the first dielectric layer 112A and the base substrate 110 may also be disposed in the peripheral area of the base substrate 110 .
  • a part of the fourth dielectric layer 111 is removed to form a fourth opening 1204 .
  • the projection of the fourth opening 1204 on the base substrate 110 is located within the projection of the second opening 1202 on the base substrate, and the projection of the first opening 1201A on the base substrate 110 is located within The fourth opening 1204 is within a projection on the base substrate.
  • FIG. 9A shows a layout diagram of an intersection area before cutting according to an embodiment of the present disclosure, for example, the intersection area may correspond to the area X1 in FIG. 2 .
  • a plurality of extension pads 130A extend perpendicular to the dicing line CL of the dicing street.
  • the first opening 1201A, the second opening 1202 and the third opening 1203 are located within the scribe line.
  • the plurality of extension pads 130A may include a plurality of extension pads with different widths, for example, at least one first extension pad 130A_1 having a first width and at least one second extension pad 130A_2 having a second width, wherein the first width is smaller than the second extension pad 130A_2. width.
  • the so-called first width and second width may refer to the dimension perpendicular to the extension direction of the extension pad, for example, the dimension in the horizontal direction in FIG. 9A .
  • each first extension pad 130A_1 is connected to one of the plurality of pins 160 , and its width may be approximately equal to that of one pin.
  • Each second extension pad 130A_2 is connected to at least two of the plurality of pins 160, and its width may be approximately equal to the total width of the area occupied by the connected pins, for example, the area occupied by the two pins width.
  • the plurality of extension pads 130A may also include extension pads having other widths, for example, a third extension pad having a third width, wherein the first width, the second width, and the third width are different from each other. same.
  • a plurality of extension pads 130A_1 and 130A_2 are respectively connected to a plurality of pins 160 so as to be connected to the above-mentioned traces SW, DR, DG, DB, GSTV, GCK, GCB, ESTV, ECK, ECB, Gout, for example.
  • FIG. 9A only shows some of the multiple pins of a display substrate and the extension pads connected to these pins.
  • FIG. 9B shows a layout diagram of the intersection area after cutting according to an embodiment of the present disclosure, for example, the intersection area may correspond to the area X2 in FIG. 4 .
  • each extension pad 130A_1 and 130A_2 is cut to obtain an independent display substrate.
  • the lengths of the extension pads 130A_1 and 130A_2 in the first direction are in the range of 0 ⁇ m-100 ⁇ m, for example, 70 ⁇ m-90 ⁇ m. within range.
  • the length of the extension pads 130A_1 and 130A_2 in the first direction is 80 ⁇ m.
  • the length of the so-called extended pad here may refer to the length extending from the pin 160, that is, the length from the edge of the pin 160 to the cutting line.
  • the length of the first opening 1201A in the first direction is within a range of 0 ⁇ m-90 ⁇ m, for example, within a range of 40 ⁇ m-60 ⁇ m. In some embodiments, the length of the first opening 1201A in the first direction is 50 ⁇ m.
  • intersection region of the display substrate according to another embodiment of the present disclosure will be described below with reference to FIGS. 10 to 12 .
  • FIG. 10 shows a schematic plan view of an intersection area of a display substrate according to another embodiment of the present disclosure.
  • Fig. 11 shows a sectional view along AA' of Fig. 10 .
  • Fig. 12 shows a sectional view of Fig. 10 along BB'.
  • the intersecting area may correspond to the intersecting area before cutting.
  • the peripheral area of the base substrate 110 includes a first dielectric layer 112B, a second dielectric layer 113 and a third dielectric layer 114 stacked on the base substrate 110 in sequence.
  • a plurality of extension pads 130B are located between the first dielectric layer 112B and the second dielectric layer 113 .
  • At least a part of each of the first dielectric layer 112B, the second dielectric layer 113 and the third dielectric layer 114 is removed to form the first opening 1201B, the second opening 1202 and the third opening 1203, and the position of the scribe line is determined by the second opening and the third opening 1203. /or the third opening is defined.
  • the projection of the first opening 1201B on the base substrate 110 is located within the projection of the second opening 1202 on the base substrate 110, and the projection of the second opening 1202 on the base substrate 110 is located within the projection of the third opening 1203 on the base substrate 110. within the projection above.
  • a plurality of first openings 1201B serve as a plurality of partition structures, and the extension pads 130B are located between the adjacent first openings 1201B away from the first dielectric layer 112B.
  • One side of the base substrate 110 , and the orthographic projections of the plurality of first openings 1201B on the base substrate 110 do not overlap with the orthographic projections of the plurality of extension pads 130B on the base substrate.
  • the plurality of elongated pads 130B are isolated from each other by the plurality of first openings 1201B in the intersection region where the dicing lanes intersect with the plurality of elongated pads 130B.
  • the plurality of first openings 1201B separated from each other extend along a first direction, which is the extending direction of the plurality of extension pads 130B (the direction indicated by the dotted line AA′), and are arranged along a second direction, so The second direction is the extending direction of the scribe line (the direction indicated by the dotted line BB').
  • each extension pad 130B has a first projection (also denoted by 130B) on the base substrate 110 , and each first opening 1201B has a first projection on the base substrate 110 .
  • each first projection 130B does not overlap with each second projection 1201B, and adjacent first projections 130B are separated by at least one second projection 1201B.
  • the first projections 130B and the second projections 1201B are arranged alternately, so that there is a second projection 1201B between every two adjacent first projections 130B.
  • the distance between the centerline of each first projection 130B in the first direction and the centerlines of two second projections 1201B adjacent to the first projection in a direction is equal.
  • embodiments of the present disclosure are not limited thereto, and the distance between each first projection 130B and two second projections 1201B adjacent to the first projection 130B in the first direction may be set as required.
  • the two edges of the second projection 1201B in the second direction can be made as close as possible to the edge of the first projection 130B adjacent to the second projection 1201B, for example, the distance between the two can be set to Set in the range of 0um-20um.
  • the extension pad 130B can be raised by the material of the first dielectric layer 112B (as shown in FIG. 11 ), thereby avoiding the metal remaining on the adjacent extension pad 130B during the etching process of the extension pad 130B.
  • the extension pad 130B is short-circuited.
  • the first direction (AA') is perpendicular to the second direction (BB'), and the second projection 1201B is a rectangle.
  • embodiments of the present disclosure are not limited thereto.
  • the technical concept of the present disclosure is applicable to the extended pads and the dicing lanes extending in any other way, for example, the extending pads and the dicing lanes are non-perpendicular to each other or the signal line and the dicing lanes extend and intersect along two arcs or even irregular trajectories, This will be described in further detail below.
  • the thickness of the first dielectric layer 112B in the direction perpendicular to the surface of the base substrate 110 may be in the range of 500nm-1000nm, and the thickness of the extension pad 130B in the direction perpendicular to the substrate The thickness in the surface direction of the substrate 110 is in the range of 200nm-900nm.
  • a fourth dielectric layer 111 located between the first dielectric layer 112B and the base substrate 110 may also be disposed in the peripheral region of the base substrate 110 .
  • the fourth dielectric layer 111 can adopt the same design as the fourth dielectric layer of the above-mentioned embodiment, so that each cutting line includes not only the first opening 1201B, the second opening 1202, and the third opening 1203, but also includes a fourth opening 1204 .
  • FIG. 13 shows a structural diagram of sub-pixels in a display area according to an embodiment of the present disclosure.
  • the driving thin film transistor includes an active layer P-Si located on the base substrate 110, a gate G located on the side of the active layer P-Si away from the base substrate 110, and a gate G located on the side of the active layer P-Si - the first gate insulating layer 202 between Si and the gate G, the second gate insulating layer 203 located on the side of the gate G away from the substrate 110 , located on the second gate insulating layer 203
  • the storage capacitor includes a first capacitor electrode ED1 and a second capacitor electrode ED2.
  • the first capacitor electrode ED1 is located at the same layer as the gate G
  • the second capacitor electrode ED2 is located between the second gate insulating layer 203 and the interlayer dielectric layer 204 .
  • the multiple signal lines in the above embodiment are arranged on the same layer as at least one of the source S and the drain D of the multiple sub-pixels, and the first dielectric layer in the above embodiment is on the same layer as the interlayer dielectric layer 204 set up.
  • At least one of the plurality of sub-pixels further includes a flat layer 206 , an anode 207 and a pixel defining layer 209 .
  • the flat layer 206 is located on a side of the interlayer dielectric layer 204 away from the base substrate 110 .
  • the anode 207 is located on the side of the planar layer 206 away from the base substrate 110 and is connected to the source S or the drain D through the planar layer 206 .
  • the pixel defining layer 209 is located on a side of the flat layer 206 away from the base substrate 110 and partially covers the anode 207 .
  • the second dielectric layer may be provided on the same layer as the planar layer 206
  • the third dielectric layer may be provided on the same layer as the pixel defining layer 209 .
  • the sub-pixel may further include a buffer layer 201, the buffer layer 201 is located between the base substrate 110 and the first gate insulating layer 202, and the active layer P-Si of the driving thin film transistor is located between the buffer layer 201 and the first gate insulating layer 202 .
  • the fourth dielectric layer in the above embodiments may be provided in the same layer as at least one of the buffer layer 201 , the first gate insulating layer 202 and the second gate insulating layer 203 .
  • the fourth dielectric layer may include a first sublayer, a second sublayer and a third sublayer sequentially stacked on the base substrate, wherein the first sublayer is set on the same layer as the buffer layer 201, and the second sublayer The sub-layer is provided in the same layer as the first gate insulating layer 202 , and the third sub-layer is provided in the same layer as the second gate insulating layer 203 .
  • the sub-pixel may further include a passivation layer 205 located between the planarization layer 206 and the interlayer dielectric layer 204 and covering the source S and the drain D of the driving thin film transistor.
  • the anode 207 is connected to the source S of the driving thin film transistor through the interlayer dielectric layer 206 and the passivation layer 205 .
  • the sub-pixel may further include a light emitting layer 211 and a cathode 212 .
  • the light emitting layer 211 is located on the side of the anode 210 away from the base substrate 110 and partially covers the anode 207 .
  • the cathode 212 is located on a side of the light emitting layer 211 away from the base substrate 110 .
  • the sub-pixel may further include an encapsulation layer 213 .
  • the encapsulation layer 213 is located on the side of the cathode 212 away from the base substrate 110 .
  • the encapsulation layer 213 may include a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer stacked in sequence.
  • FIG. 14 shows a schematic plan view of an intersection area according to another embodiment of the present disclosure.
  • the intersection structure of the display substrate in FIG. 14 is similar to the structure shown in FIGS. 6 to 8, the difference is at least the second direction (ie, the direction of the cutting line CL) and the first direction (ie, the extending direction of the extension pad 130C) in FIG. 14 )not vertical.
  • a first opening 1201C, a second opening 1202, and a third opening 1203 are respectively formed in the first dielectric layer, the second dielectric layer, and the third dielectric layer, and a plurality of extended The pads 130C extend across the scribe lines.
  • the plurality of first openings 1201C extend along a first direction and are arranged along a cutting line CL (second direction), the first direction intersects the second direction and is not perpendicular to each other.
  • the projection of each extension pad 130C on the base substrate overlaps with the projection of a corresponding first opening 1201C on the base substrate.
  • the overlapping manner is similar to that shown in FIG. 6 to FIG.
  • the projection of the first opening 1201C on the substrate is a parallelogram. Among the four sides of the parallelogram, two sides extend parallel to the first direction, and the other two sides extend parallel to the second direction.
  • FIG. 15 shows a schematic plan view of an intersection area of a display substrate according to another embodiment of the present disclosure.
  • the structure of the intersecting region of the display substrate in FIG. 15 is similar to the structure shown in FIGS. 10 to 12 , the difference is at least that the extending direction of the cutting line 120 in FIG. 15 (that is, the direction of the cutting line CL) is not perpendicular to the extending direction of the extension pad 130D.
  • a first opening 1201D, a second opening 1202 and a third opening 1203 are respectively formed in the first dielectric layer, the second dielectric layer and the third dielectric layer, and a plurality of extension pads 130D intersects the cutting lines 120 .
  • the plurality of first openings 1201D extend along an extending direction (first direction) of the extension pad 130D and are arranged along a cutting line CL (second direction) that intersects the second direction and is not perpendicular to each other.
  • the projection of each extension pad 130D on the base substrate overlaps with the projection of a corresponding first opening 1201D on the base substrate.
  • the overlapping manner is similar to that shown in FIGS.
  • the projection of the first opening 1201D on the substrate is a parallelogram. Among the four sides of the parallelogram, two sides extend parallel to the first direction, and the other two sides extend parallel to the second direction.
  • intersection region of the display substrate according to another embodiment of the present disclosure will be described below with reference to FIGS. 16 to 18 .
  • Fig. 16 shows a schematic plan view of an intersection area according to another embodiment of the present disclosure.
  • Fig. 17 shows a sectional view along AA' of Fig. 16 .
  • Fig. 18 shows a sectional view of Fig. 16 along BB'.
  • the structure of the intersecting region of the display substrate in FIGS. 16 to 18 is similar to that shown in FIGS. 6 to 8 , except that the peripheral region of the base substrate in FIGS. 16 to 18 also includes a fifth dielectric layer 115 .
  • the following will mainly describe the differences in detail.
  • the peripheral area of the display substrate includes a fourth dielectric layer 111, a first dielectric layer 112A, a plurality of extension pads 130A, a second dielectric layer 113, a fifth Dielectric layer 115 and third dielectric layer 114 .
  • the layout of the extension pad 130A and the first to fourth dielectric layers may be the same as that described above with reference to FIGS. 6 to 8 .
  • the fifth dielectric layer 115 is located between the second dielectric layer 113 and the third dielectric layer 114 . A part of the fifth dielectric layer 115 is removed to form a fifth opening 1205 .
  • the projection of the fifth opening 1205 on the base substrate 110 is located within the projection of the third opening 114 on the base substrate 110, and the projection of the second opening 113 on the base substrate 110 is located within the projection of the fifth opening 1205 on the substrate. within the projection on the substrate 110 .
  • FIG. 19 shows a structural diagram of sub-pixels of a display area according to another embodiment of the present disclosure.
  • the sub-pixel structure in FIG. 19 is similar to that in FIG. 13 , except that the interlayer dielectric layer of the sub-pixel in FIG. 19 includes a first planar layer 206 and a second planar layer 208 , and the sub-pixel further includes a via electrode 210 .
  • At least one sub-pixel among the plurality of sub-pixels includes a driving thin film transistor and a storage capacitor.
  • the driving thin film transistor includes an active layer P-Si located on the base substrate 110, a gate G located on the side of the active layer P-Si away from the base substrate 110, and a gate G located on the side of the active layer P-Si - the first gate insulating layer 202 between Si and the gate G, the second gate insulating layer 203 located on the side of the gate G away from the substrate 110 , located on the second gate insulating layer 203
  • the storage capacitor includes a first capacitor electrode ED1 and a second capacitor electrode ED2.
  • the first capacitor electrode ED1 is located at the same layer as the gate G
  • the second capacitor electrode ED2 is located between the second gate insulating layer 203 and the interlayer dielectric layer 204 .
  • the multiple signal lines are arranged in the same layer as at least one of the source S and the drain D of the multiple sub-pixels.
  • the first dielectric layer and the interlayer dielectric layer 204 in the above embodiment are arranged in the same layer.
  • At least one of the plurality of sub-pixels further includes a first planar layer 206 , a second planar layer 208 , a via electrode 210 , an anode 207 and a pixel defining layer 209 .
  • the first planar layer 206 is located on a side of the interlayer dielectric layer 204 away from the base substrate 110 .
  • the via electrode 210 is located on a side of the first planar layer 206 away from the base substrate 110 , and is connected to the source S of the TFT through a via hole provided in the first planar layer 206 .
  • the second flat layer 208 is located on a side of the via electrode 210 away from the base substrate 110 .
  • the anode 207 is located on a side of the second planar layer 208 away from the base substrate 110 and is connected to the transfer electrode 210 through a via hole in the second planar layer 208 .
  • the pixel defining layer 209 is located on a side of the second flat layer 208 away from the base substrate and at least partially covers the anode 207 . 16 to 18 above, the second dielectric layer can be set in the same layer as the first flat layer 206, the third dielectric layer can be set in the same layer as the pixel defining layer 209, and the fifth dielectric layer can be set in the same layer as the second The flat layer 208 is set on the same layer.
  • the sub-pixel may further include a buffer layer 201, the buffer layer 201 is located between the base substrate 110 and the first gate insulating layer 202, and the active layer P-Si of the driving thin film transistor is located between the buffer layer 201 and the first gate insulating layer 202 .
  • the fourth dielectric layer in the above embodiment may include a first sub-layer, a second sub-layer and a third sub-layer stacked on the base substrate in sequence, wherein the first sub-layer is provided on the same layer as the buffer layer 201, so The second sublayer is provided in the same layer as the first gate insulating layer 202 , and the third sublayer is provided in the same layer as the second gate insulating layer 203 .
  • the sub-pixel may further include a passivation layer 205 located between the planarization layer 206 and the interlayer dielectric layer 204 and covering the source S and the drain D of the driving thin film transistor.
  • the anode 207 is connected to the source S of the driving thin film transistor through the interlayer dielectric layer 206 and the passivation layer 205 .
  • the sub-pixel may further include a light emitting layer 211 and a cathode 212 .
  • the luminescent layer 211 is located on a side of the anode 210 away from the base substrate 110 and partially covers the anode 210 .
  • the cathode 212 is located on a side of the light emitting layer 211 away from the base substrate 110 .
  • the sub-pixel may further include an encapsulation layer 213 .
  • the encapsulation layer 213 is located on the side of the cathode 212 away from the base substrate 110 .
  • the encapsulation layer 213 may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence.

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Abstract

一种显示基板(100)和显示装置，显示基板(100)包括：衬底基板(110)，包括显示区(AA)和周边区(PA)；多个子像素(Pxl)；多个引脚(160)，多个引脚(160)在衬底基板(110)上的正投影沿第一方向（AA`）延伸且沿与第一方向(AA `)相交的第二方向(BB`)间隔分布；多个引线(71,74,75,78,79)，至少位于周边区(PA)内，多个引脚(160)通过多个引线(71,74,75,78,79)与多个子像素(Pxl)电连接；多个延长垫(130)，位于多个引脚(160)远离显示区(AA)的一侧，沿第一方向延伸且沿第二方向间隔分布，多个延长垫(130)与多个引脚(160)电连接；多个隔断结构，位于多个延长垫(130)之间且沿第一方向延伸，多个隔断结构在衬底基板(110)上的正投影与多个延长垫(130)在衬底基板(110)上的正投影不交叠，多个隔断结构被配置为使多个延长垫(130)之间电绝缘。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
在显示面板的设计中，为提升测试效率，在对基板上的各个显示面板进行切割前采用分组点灯的方式进行测试，因此需要将测试各个显示面板需要用到的信号线从显示面板引出到基板上的对应引脚。但是这样信号线就需要跨过显示面板的切割道，容易受到切割道结构的影响。
发明内容
本公开的实施例提供了，包括：
衬底基板，包括显示区和至少位于所述显示区一侧的周边区；
多个子像素，位于所述显示区；
多个引脚，位于所述衬底基板的周边区内，被配置为向所述多个子像素传输电信号，所述多个引脚在所述衬底基板上的正投影沿第一方向延伸且沿第二方向间隔分布，所述第一方向与所述第二方向相交；
多个引线，至少位于所述衬底基板的周边区内，所述多个引脚通过所述多个引线与所述多个子像素电连接；
多个延长垫，位于所述多个引脚远离所述显示区的一侧，沿所述第一方向延伸且沿所述第二方向间隔分布，所述多个延长垫与所述多个引脚电连接；
多个隔断结构，位于所述多个延长垫之间且沿所述第一方向延伸，所述多个隔断结构在所述衬底基板上的正投影与所述多个延长垫在所述衬底基板上的正投影不交叠，所述多个隔断结构被配置为使所述多个延长垫之间电绝缘。
例如，所述多个隔断结构与所述多个延长垫交替分布。
例如，所述多个隔断结构与所述多个延长垫一一交替分布。
例如，所述显示基板包括位于所述衬底基板上的第一介质层，所述第一介质层具有多个沿第二方向排布且沿第一方向延伸的多个第一开口，所述延长垫的至少部分位于所述第一开口中，相邻所述第一开口之间的所述第一介质层为所述多个隔断结构。
例如，所述显示基板包括位于所述衬底基板上的第一介质层，所述第一介质层中具 有多个沿第二方向排布且沿第一方向延伸的多个第一开口，所述多个第一开口为所述多个隔断结构，所述延长垫位于相邻所述第一开口之间的所述第一介质层远离所述衬底基板的一侧，且所述多个第一开口在所述衬底基板的正投影与所述多个延长垫在所述衬底基板的正投影不交叠。
例如，所述显示基板还包括位于所述周边区的第二介质层和第三介质层，所述第二介质层位于第一介质层远离所述衬底基板的一侧，所述第三介质层位于所述第二介质层远离所述衬底基板的一侧，所述延长垫位于所述第一介质层与所述第二介质层之间的导体层中，所述第二介质层具有第二开口，所述第三介质层具有第三开口，所述第二开口和所述第三开口暴露至少部分所述延长垫。
例如，所述多个第一开口在所述衬底基板上的正投影位于所述第二开口在所述衬底基板上的正投影之内，所述第二开口在所述衬底基板上的正投影位于所述第三开口在所述衬底基板上的正投影之内。
例如，所述多个延长垫中的每个延长垫在所述衬底基板上具有第一正投影，所述多个隔断结构中的每个隔断结构在所述衬底基板上具有第二正投影，每个第一正投影与相邻的第二正投影在第一方向上的间距在0um-20um范围内。
例如，每个第一正投影在所述第二方向上的中心线跟与该第一正投影相邻的两个第二正投影在所述第二方向的中心线之间的距离相等。
例如，所述第一方向与所述第二方向垂直。
例如，所述隔断结构在所述衬底基板上的正投影为矩形。
例如，所述第一方向与所述第二方向不垂直，所述隔断结构在所述衬底基板上的正投影为平行四边形。
例如，所述第一介质层的厚度在500nm-1000nm范围内，所述延长垫在垂直于衬底基板表面方向上的厚度在200nm-900nm范围内。
例如，所述隔断结构在所述第一方向上的尺寸小于所述延长垫在所述第一方向上的尺寸。
例如，所述显示基板还包括：测试相关电路，位于所述周边区，布置在所述多个引脚面向所述显示区的一侧，并且包围所述显示区的至少一部分，所述测试相关电路通过多个信号线与所述显示区内的多个子像素连接，并且通过所述多个引线与所述多个引脚连接。
例如，所述多个延长垫包括至少一个第一延长垫和至少一个第二延长垫，每个第一 延长垫与所述多个引脚中的一个引脚连接，每个第二延长垫与所述多个引脚中的至少两个引脚连接，所述第一延长垫的线宽小于第二延长垫的线宽。
例如，所述测试相关电路包括单元测试电路，所述多个信号线包括多条数据线，所述多个引线包括多个单元测试控制信号线，所述多个引脚包括多个第一引脚，并且
其中，所述单元测试电路通过所述多条数据线与所述显示区内的多个子像素连接，并通过所述单元测试控制信号线与所述多个第一引脚连接。
例如，所述测试相关电路还包括驱动电路，所述多个信号线还包括多个驱动信号线，所述多个引线还包括多个驱动控制信号线和多条驱动测试信号线，所述多个引脚还包括多个第二引脚，并且
其中，所述驱动电路通过所述多条驱动信号线与所述显示区内的多个子像素连接，并且通过所述多条驱动控制信号线和所述多条驱动测试信号线与所述多个第二引脚连接。
例如，所述测试相关电路还包括多路复用电路，所述多个引线还包括多个多路复用控制信号线，所述多个引脚还包括多个第三引脚，并且，
其中，所述多路复用电路通过所述多条数据线与所述显示区内的多个子像素连接，并且通过所述多条多路复用控制信号线与所述多个第三引脚连接。
例如，所述测试相关电路还包括电源电压线和参考电压线，所述多个信号线还包括电源电压第一走线和参考电压第一走线，所述多个引线还包括电源电压第二走线和参考电压第二走线，所述多个引脚还包括多个第四引脚，并且，
其中，所述电源电压线通过所述电源电压第一走线连接至所述显示区内的多个子像素，所述参考电压线通过所述参考电压第一走线连接至所述显示区内的多个子像素，所述电源电压线通过所述电源电压第二走线连接至所述多个第四引脚中的至少一个第四引脚，所述参考电压线通过所述参考电压第二走线连接至所述多第四引脚中的至少另一个第四引脚。
例如，所述显示基板还包括：第四介质层，位于所述周边区，布置在第一介质层与所述衬底基板之间，且具有第四开口，所述第四开口在所述衬底基板上的正投影位于所述第二开口在所述衬底基板上的正投影内，并且所述多个第一开口在所述衬底基板上的正投影位于所述第四开口在所述衬底基板上的正投影内。
例如，所述显示基板还包括：第五介质层，位于所述周边区，布置在第二介质层与第三介质层之间且具有第五开口，所述第五开口在所述衬底基板上的正投影位于所述第 三开口在所述衬底基板上的正投影内，并且所述第二开口在所述衬底基板上的正投影位于所述第五开口在所述衬底基板上的正投影内。
例如，所述多个子像素中的至少一个包括驱动薄膜晶体管和存储电容；
所述驱动薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，位于所述有源层与所述栅极之间的第一栅绝缘层，位于所述栅极远离所述衬底基板一侧的第二栅绝缘层，位于所述第二栅绝缘层远离所述衬底基板一侧的层间介质层，以及位于所述层间介质层远离所述衬底基板一侧的源极和漏极；
所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极与所述栅极位于同一层，所述第二电容电极位于所述第二栅绝缘层和层间介质层之间；
所述多条延长垫与所述多个子像素的源极和漏极中的至少之一同层设置，位于周边区的第一介质层与所述层间介质层同层设置。
例如，所述多个子像素中的至少一个还包括：
平坦层，位于所述层间介质层远离所述衬底基板的一侧；
阳极，位于所述平坦层远离所述衬底基板的一侧并且穿过所述平坦层与所述源极或所述漏极连接；
像素界定层，位于所述平坦层远离所述衬底基板的一侧并且部分地覆盖所述阳极，
其中，位于周边区的第二介质层与所述平坦层同层设置，位于周边区的第三介质层与所述像素界定层同层设置。
例如，所述多个子像素中的至少一个还包括：
第一平坦层，位于所述层间介质层远离所述衬底基板的一侧；
转接电极，位于所述第一平坦层远离所述衬底基板的一侧，并且通过设置在所述第一平坦层中的过孔与所述薄膜晶体管的源极连接；
第二平坦层，位于所述转接电极远离所述衬底基板的一侧；
阳极，位于所述第二平坦层远离所述衬底基板的一侧并且通过所述第二平坦层中的过孔与所述转接电极连接；
像素界定层，位于所述第二平坦层远离衬底基板的一侧并且至少部分地覆盖所述阳极，
其中，所述衬底基板的周边区中还包括位于第二介质层与第三介质层之间的第五介质层，所述第二介质层与所述第一平坦层同层设置，所述第三介质层与所述像素界定层同层设置，所述第五介质层与所述第二平坦层同层设置。
例如，所述多个子像素中的至少一个还包括缓冲层，所述缓冲层位于所述衬底基板与所述第一栅绝缘层之间；并且
所述衬底基板的周边区中还包括位于第一介质层与所述衬底基板之间的第四介质层，所述第四介质层与所述缓冲层、所述第一栅绝缘层和所述第二栅绝缘层中的至少之一同层设置。
一种显示装置，包括如上所述的显示基板。
附图说明
图1示出了根据本公开实施例的待切割基板的平面示意图。
图2示出了根据本公开实施例的显示基板的示意图。
图3示出了图2中的显示区的示意图。
图4示出了根据本公开另一实施例的显示基板的示意图。
图5示出了根据本公开实施例的单元测试电路的原理图。
图6示出了根据本公开一实施例的显示基板的交叉区域在切割前的平面示意图。
图7示出了图6沿AA’的截面图。
图8示出了图6沿BB’的截面图。
图9A示出了根据本公开一实施例的交叉区域在切割前的布局图。
图9B示出了根据本公开一实施例的交叉区域在切割后的布局图
图10示出了根据本公开另一实施例的显示基板的交叉区域的平面示意图。
图11示出了图10沿AA’的截面图。
图12示出了图10沿BB’的截面图。
图13示出了根据本公开一实施例的显示区的子像素的结构图。
图14示出了根据本公开另一实施例的显示基板的交叉区域的平面示意图。
图15示出了根据本公开另一实施例的显示基板的交叉区域的平面示意图。
图16示出了根据本公开另一实施例的显示基板的交叉区域的平面示意图。
图17示出了图16沿AA’的截面图。
图18示出了图16沿BB’的截面图。
图19示出了根据本公开另一实施例的显示区的子像素的结构图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或配置。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“相连”或“连接至”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连。此外，这两个组件可以通过有线或无线方式相连或相耦合。
针对信号线需要跨过切割道的设计，一般情况下，可采用两类设计方式，一种是采用栅极层(可以是第一栅极层或第二栅极层)引线，另一种采用源漏层引线。通常在切割道位置处需要将有机层、无机层挖去，以利于切割。信号线采用栅极层走线时，为避免阳极湿刻工艺将栅极层的金属刻蚀掉，需要采用层间介质层保护栅极层的信号线。但是这需要在信号线的走线位置保留大量层间介质膜层，存在无机层断裂(Crack)风险。另一种采用源漏层走线的设计，但因切割道挖去了有机层、无机层等膜层，沟道较深，在源漏层的刻蚀工艺或阳极的刻蚀工艺中容易在切割道位置产生金属残留，存在信号线短路的风险。
图1示出了根据本公开实施例的待切割基板的平面示意图。
如图1所示，待切割基板包括多个显示基板100，在图1中，多个显示基板100布置成阵列的形式，例如2x4阵列的形式。然而本公开的实施例不限于此，多个显示基板100可以根据需要布置成其他形式，显示基板100的数量也可以根据需要来设置。每个显示基板100包括衬底基板110。在待切割基板上的多个显示基板100可以共用一个衬底基板110。衬底基板110可以是刚性衬底基板，例如玻璃基板。在一些实施例中，衬底基板110可以是柔性衬底基板，例如聚酰亚胺材料制成的柔性衬底基板。衬底基板110上设置有多个显示区AA以及至少位于所述显示区一侧的周边区PA。显示区AA 内设置有多个子像素。待切割基板上还设置有包括分别包围所述多个显示区AA的多条切割道120，例如每个显示区AA被一个相应的切割道120包围。需要说明的是，切割道是对区域的定义，在此区域进行切割，而并非是实体结构。
在待切割基板上还布置了多组连接走线SS和多组接触垫140。多组接触垫140位于各个显示基板100之外。每个显示基板100的显示区AA内的多个子像素通过所述多组连接走线SS中的一组连接走线连接到所述多组接触垫140中的一组接触垫。图1中为了简明起见针对每个显示基板100仅示出了两条连接走线SS和两个接触垫140，然而这仅仅是为了示意，实践中可以根据需要设置任意数目的连接走线SS和接触垫140。
连接走线SS和接触垫140可以被用来对显示区AA内的子像素进行单元测试(Cell Test)。例如可以通过向接触垫140上施加用于单元测试的各种测试信号来实现对各个显示基板100的显示区AA内的子像素的单元测试。在完成单元测试之后，可以对待切割基板进行切割，例如沿着各个切割道120进行切割，例如但不限于刀轮切割或激光切割，从而得到多个独立的显示基板100。换句话说，沿每条切割道所限定的切割区域对应一个独立的显示基板100，下面将参考图2至图5对显示基板的结构进行详细说明。
图2示出了根据本公开实施例的显示基板的示意图。
如图2所示，显示基板包括显示区AA以及至少位于所述显示区一侧的周边区PA。图2示出的是待切割基板被切割之前其上的显示基板的结构，因此显示基板的边界由包围该显示区的切割道120限定。在图2中，显示区AA在衬底基板上的投影具有圆形轮廓，切割道120在衬底基板上的投影是围绕显示区AA延伸的条带，条带围绕的图案呈大体圆形。然而本公开的实施例不限于此，切割道和显示区的投影形状可以根据需要来设置。例如，显示区的衬底基板的投影可以为矩形、圆角矩形、椭圆形、多边形等等，围绕显示区的切割道可以根据需要设计成具有相应的投影图案，例如矩形、圆角矩形、圆形、椭圆形、多边形、甚至不规则形状。
如图2所示，在显示基板中，在显示区AA至少一侧的周边区PA内还设置有用于向所述多个子像素传输电信号的多个引脚160。在图2中多个引脚160位于显示区AA的一侧(图2中为靠近切割道的直线边缘的一侧)。在一些实施例中，多个引脚160在所述衬底基板上的正投影可以沿第一方向延伸且沿第二方向间隔分布，例如可以沿着显示区的一侧边缘排成一行或多行，下文将对此进一步详细说明。然而本公开的实施例不限于此，测试相关电路150和引脚160的位置可以根据需要来设置。
如图2所示，周边区PA中还可以设置有测试相关电路150。测试相关电路150可以 包括单元测试电路1501。在一些实施例中，测试相关电路还可以包括驱动电路1502、多路复用电路1503、电源电压线1504和参考信号线1505中的至少之一。测试相关电路150布置在所述多个引脚160面向所述显示区AA的一侧，并且包围所述显示区AA的至少一部分。测试相关电路150可以通过多条信号线与所述显示区AA内的多个子像素连接，并且通过多条引线与所述多个引脚160连接。
如图2所示，单元测试电路1501可以设置在显示区AA的一侧，例如在图2中围绕显示区AA远离多个引脚160的一侧边缘设置。单元测试电路1501可以与显示区AA内的多个子像素连接，用于对显示区内的多个子像素进行单元测试(Cell Test)。单元测试电路1501所连接的多个单元测试控制信号线可以引出到多个引脚160。
驱动电路1502可以围绕显示区AA设置，使得单元测试电路1501位于驱动电路1502与显示区AA之间。驱动电路1502可以包括栅极驱动电路和发光驱动电路，栅极驱动电路用于将显示区AA内的子像素开启，发光驱动电路用于控制开启的子像素发光。驱动电路1502所连接的多条驱动控制信号线和多条驱动测试信号线可以引出到引脚160。
多路复用电路1503可以位于显示区AA远离单元测试电路1501一侧，例如围绕显示区AA远离单元测试电路1501一侧边缘设置。多路复用电路1503用于将接收到的输入信号多路复用成多路复用信号并提供给显示区AA内的多个子像素。多路复用电路1503所连接的多条多路复用控制信号线可以引出到引脚160。
电源电压线1504和参考电压线1505用于向显示基板内的各个元件供电，例如向显示区AA内的子像素供电。电源电压线1504和参考电压线1505还可以用于向上述单元测试电路1501、驱动电路1502和多路复用电路1503中的至少一个供电。如图2所示，电源电压线1504呈环形，围绕显示区AA，并且位于显示区AA与单元测试电路1501和多路复用电路1503之间的区域内；参考电压线1505呈环形，并且围绕上述驱动电路1502设置。在图2中，电源电压线1504通过Y形的电压走线连接至多个引脚160中的至少两个引脚，参考电压线1505通过条形延伸的两个电压走线连接至多个引脚160中的至少另外两个引脚。
继续参考图2，多个引脚160分别与多个连接走线SS连接。从图2可以看出，虚线所示的区域中切割道120与多个连接走线SS交叉延伸，下文将对该交叉区域进行详细描述。
图3示出了图2中的显示区的示意图。
如图3所示，显示区AA中设置有多个子像素Pxl，所述多个子像素布Pxl布置成阵 列的形式。在图3中，多个子像素Pxl排列成N行M列。如图2所示，阵列整体上呈圆形排布，从而使显示区AA在衬底基板110上的投影具有圆形轮廓。然而本公开的实施例不限于此，多个子像素Pxl可以根据需要排列成其他形状的阵列，例如矩形、圆角矩形、多边形等等。
显示区AA中还设置有与所述多个子像素Pxl电连接的多条栅极线G1，G2，…GN。显示区AA中还设置有与所述多个子像素Pxl电连接的多条数据线D1，D2，…DM。在图3中，N行子像素Pxl与N条栅极线G1，G2，…GN一一对应地连接，M列子像素Pxl与M条数据线D1，D2，…DM一一对应地连接，也就是说每行子像素连接一条栅极线，每列子像素连接一条数据线。然而本公开的实施例不限于此，栅极线和数据线的数量和连接方式可以根据需要来选择，例如可以每行子像素连接两条栅极线，栅极线的数量是子像素行数的两倍；或者每两列子像素连接一条数据线，数据线的数量是子像素列数的二分之一，等等。
在工作时，栅极驱动电路向栅极线G1至GN施加栅极驱动信号以将每行子像素Pxl开启，源极驱动电路向数据线D1至DM施加源极驱动信号，以使开启的子像素Pxl根据所施加的源极驱动信号进行显示。在一些实施例中，显示区内还可以设置与多个子像素连接的多条发光控制线，发光驱动电路通过多条发光控制线向所述多个子像素提供发光控制信号。
图4示出了根据本公开另一实施例的显示基板的示意图。在图4中所示的显示基板是从待切割基板上切割得到的显示基板。
如图4所示，显示基板包括衬底基板110、多个引脚、多条引线71、74、75、78和79和多个延长垫130。多个延长垫130是上述多条连接走线经过切割后得到的。多个引脚包括多个第一引脚1601、多个第二引脚1602、多个第三引脚1603和多个第四引脚1604中的至少之一。多个引脚1601至1604通过所述多个引线71、74、75、78和79与所述多个子像素电连接。多个延长垫130位于所述多个引脚1601至1604远离所述显示区AA的一侧，沿所述第一方向延伸且沿所述第二方向间隔分布，所述多个延长垫130与所述多个引脚1601至1604电连接。
显示基板上的测试相关电路可以包括单元测试电路65、驱动电路61、多路复用电路64、电源电压线68和参考电压线69中的至少之一。测试相关电路通过多条信号线与显示区AA内的多个子像素连接，并且通过多条引线71、74、75、78和79与多个引脚1601至1604连接。
如图4所示，多个引脚可以包括多个第一引脚1601、多个第二引脚1602、多个第三引脚1603和多个第四引脚1604中的至少之一。
单元测试电路65可以通过多条数据线与显示区AA内的多个子像素连接，并通过多条引线75与多个第一引脚1601连接。多条引线75可以包括单元测试电路用来接收单元测试控制信号的单元测试控制信号线，其包括但不限于开关走线SW、第一测试数据走线DR、第二测试数据走线DG和第三测试数据走线DB中的至少之一。在一些实施例中，开关走线SW可以包括第一开关走线SWR、第二开关走线SWG和第三开关走线SWB。
驱动电路61可以通过多条驱动信号线与所述显示区AA内的多个子像素连接，并且通过多条引线71与多个第二引脚1602连接。多条驱动信号线可以是驱动电路用来提供驱动信号的走线，包括但不限于栅极线和发光控制线，驱动电路61中的栅极驱动电路通过栅极线向显示区AA内的子像素提供栅极驱动信号，发光驱动电路通过发光控制线向显示区AA内的子像素提供发光驱动信号，从而控制子像素发光。多条引线71可以包括多条驱动控制信号线和多条驱动测试信号线。多条驱动控制信号线包括与栅极驱动电路连接的栅极驱动控制信号线以及与发光驱动电路连接的发光驱动控制信号线。栅极驱动控制信号线用于向栅极驱动电路提供栅极驱动所需要的驱动控制信号，包括但不限于第一启动信号走线GSTV、第一时钟信号走线GCK、第二时钟信号走线GCB。发光驱动控制信号线用于向发光驱动电路提供发光驱动所需要的发光控制信号，包括但不限于第二启动信号走线ESTV、第三时钟信号走线ECK、第四时钟信号走线ECB。驱动测试信号线包括但不限于与栅极驱动电路的输出端连接的栅极输出信号走线Gout以及与发光驱动电路的输出端连接的发光输出信号走线Eout。
多路复用电路64通过多条数据线与所述显示区AA内的多个子像素连接，并且通过多条引线74与所述第三组引脚1603连接。多条引线74可以包括用于控制多路复用电路产生多条多路复用信号的开关控制信号线，例如但不限于与用于将每个输入信号复用为6个输出信号的多路复用电路连接的6条多路控制开关信号线。
电源电压线68可以通过电源电压第一走线连接到显示区内的各个电路元件，并通过引线78(电源电压第二走线)连接到第四引脚1604中的至少一个。参考电压线69可以通过参考电压第一走线连接到显示区内的各个电路元件，并通过引线79(参考电压第二走线)连接到第四引脚1604中的至少另一个。电源电压第二走线78例如可以是图4所示的Y形走线，Y形走线的两个引出端分别连接至两个第四引脚1604。参考电压第二 走线79例如可以是图4所示的两个大体呈直线延伸的条形走线，分别连接至另外两个第四引脚1604。电源电压线68可以包括以下之中的至少之一：第一电源电压线VDD、第二电源电压线ELVDD、第三电源电压线VGH、初始电压线VINT。参考电压线可以69包括以下之中的至少之一：第一参考电压线VSS、第二参考电压线ELVSS、第三参考电压线VGL。
多个引脚1601、1602、1603、1604分别与多个延长垫130连接，例如可以一一对应地连接。但是本公开的实施例不限于此，在一些实施例中一个或多个引脚可以设置成冗余(Dummy)的，即不与其他电路结构电连接。在一些实施例中多个引脚可以连接一个延长垫130，或者一个引脚连接多个延长垫130，本公开对此不作限制。
在一些实施例中，在周边区PA中还可以设置有初始电压线67，初始电压线67通过初始电压第一走线连接至显示区的子像素，并通过初始电压第二走线77连接至第五引脚。在一些实施例中，周边区PA中还可以设置有数据驱动线73，数据驱动线73可以与多路复用电路连接，用于向多路复用电路提供输入数据信号。每条数据驱动线73可对应多条数据线。数据驱动线73可以连接至第六引脚。
虽然在上述实施例中以特定的位置和布局示出了单元测试电路、驱动电路、多路复用电路、电源电压线和参考电压线以及与这些电路连接的信号线和引线，然而这仅仅是为了说明它们的电连接关系，并不对限制它们的实际位置和布局。
图5示出了根据本公开实施例的单元测试电路的原理图。该单元测试电路可以应用于上述任意实施例的显示基板。
如图5所示，与单元测试电路连接的单元测试控制信号线包括第一开关走线SWR、第二开关走线SWG和第三开关走线SWB、第一测试数据走线DR、第二测试数据走线DG和第三测试数据走线DB。
单元测试电路CT可以包括多个测试子电路，所述多个测试子电路中的至少一个包括第一晶体管、第二晶体管和第三晶体管。图5中为了简明起见仅示出了单元测试电路CT中的4个晶体管，其中第一测试子电路包括晶体管T1(第一晶体管)、T2(第二晶体管)和T3(第三晶体管)，而晶体管T1’属于另一个第一测试子电路(作为其第一晶体管)，以此类推。晶体管T1的栅极电连接至第一开关走线SWR，晶体管T2的栅极电连接至所述第二开关走线SWG，晶体管T3的栅极电连接至第三开关走线SWB。晶体管T1的第一极电连接至第一测试数据走线DR，晶体管T2的第一极电连接至第二测试数据走线DG，晶体管T3的第一极电连接至第三测试数据走线DB。晶体管T1 的第二极、晶体管T2的第二极和晶体管T3的第二极分别电连接至三条数据线DATA1、DATA2和DATA3。
虽然在图5的实施例中以三条开关走线SWR、SWG和SWB为例进行了说明，然而本公开的实施例不限于此。在一些实施例中，晶体管T1、T2和T3可以连接至同一条开关走线SW。
下面将参考图6至图9B来描述本公开一实施例的显示基板的交叉区域的结构。
图6示出了根据本公开一实施例的显示基板的交叉区域在切割前的平面示意图。图7示出了图6沿AA’的截面图。图8示出了图6沿BB’的截面图。图6至图8所示的切割前的交叉区域例如可以对应于图2中虚线框所示的区域X1。
参考图6至图8，衬底基板110的周边区中包括位于所述衬底基板110上的第一介质层112A，所述第一介质层112A具有多个沿第二方向(BB’)排布且沿第一方向(AA’)延伸的多个第一开口1201A。第一介质层112A的至少一部分被去除，形成了第一开口1201A。延长垫130A的至少部分位于第一开口1201A中，相邻所述第一开口1201A之间的所述第一介质层112A形成了多个隔断结构。如图6至图8所示，相邻第一开口1201A之间的第一介质层112A形成的多个隔断结构位于多个延长垫130之间且延第二方向延伸，所述多个隔断结构在衬底基板110上的正投影与所述多个延长垫130A在所述衬底基板110上的正投影不交叠，所述多个隔断结构可以使所述多个延长垫130A之间电绝缘。由于在图6至图8的实施例中显示基板尚未从待切割基板上切割下来，所以多个延长垫130A充当了用于与显示基板外部的接触垫连接的连接走线。
显示基板还可以包括依次堆叠在第一介质层112A上的第二介质层113和第三介质层114。多个延长垫130A位于第一介质层112A与第二介质层113之间。第二介质层113和第三介质层114各自的至少一部分被去除，形成了第二开口1202和第三开口1203，切割道的位置可以由第二开口和/或第三开口来限定。第一开口1201A在衬底基板110上的投影位于第二开口1202在衬底基板110上的投影之内，第二开口1202在衬底基板110上的投影位于第三开口1203在衬底基板110上的投影之内。
如图6所示，切割道的延伸方向可以由切割线CL限定，切割线指的是切割道在其延伸方向上的中心线，其是一条虚拟的线，该线与切割道两侧的距离相等。在切割道与多个延长垫130交叉延伸的交叉区域内，第一介质层112A中设置有多个第一开口1201A，使得多个延长垫130通过多个第一开口1201A彼此隔离。多个彼此分离第一开口1201A沿第一方向(由点划线AA’表示的方向)延伸并沿第二方向(由点划线BB’表示的方向) 排列，所述第一方向是所述多个延长垫130A的延伸方向，所述第二方向是所述切割道的延伸方向。
如图6所示的交叉区域内，每个延长垫130A在所述衬底基板110上具有第一投影(同样由130A表示)，每个第一开口1201A在所述衬底基板110上具有第二投影(同样由1201A表示)，其中每个第一投影沿第一方向跨越对应的第二投影，并且该第二投影在第二方向上的尺寸大于或等于该第一投影在第二方向上的尺寸。例如在图6中，对于投影彼此重叠的一个延长垫130A和一个第一开口1201A，延长垫130A的投影沿AA’方向上的尺寸(也称作长度)大于第一开口1201A，在BB’方向上的尺寸(也称作宽度)小于或等于第一开口1201A，使得延长垫130A的投影沿AA’方向跨越第一开口1201A的投影并且在BB方向上完全位于第一开口1201A的投影内。在图6中，每个第一投影130A在第一方向的中心线与所述对应的一个第二投影1201A在第一方向上的中心线重合，即，二者在长度方向上的中心线重合。然而本公开的实施例不限于此，二者的中心线可以彼此具有一定的偏移。在一些示例中，每个第一投影130A与所述对应的一个第二投影1201A在第二方向上的边缘间距在0um-20um范围内。以图6中的一个第一投影130A以及与该第一投影130A重叠的第二投影1201A为例，第一投影130A的左侧边缘与第二投影1201A的左侧边缘之间的距离以及第一投影130A的右侧边缘与第二投影的右侧边缘之间的距离可以均在在0um-20um范围内，二者可以相等，也可以不等。通过这种方式，可以使相邻延长垫130A之间被第一介质层112A的材料隔离，从而避免由于在延长垫130A的刻蚀过程中有金属残留于相邻的延长垫130A之间而导致延长垫130A短路。
在图6中，第一方向(AA’)与所述第二方向(BB’)垂直，第二投影1201A为矩形。然而本公开的实施例不限于此。本公开的技术构思适用于任何其他方式交叉延伸的信号线和切割道，例如信号线和切割道彼此非垂直交叉或者信号线和切割道沿着两个弧形或甚至不规则轨迹延伸并交叉，下文将对此进一步详细说明。
在一些实施例中，如图6所示，多个第一开口1201A中的至少一个还可以被设置为冗余的，冗余的第一开口不与延长垫130A重叠，例如图6中位于最左侧和最右侧的两个第一开口为冗余第一开口。
在一些实施例中，如图7和图8所示，第一介质层112A在垂直于衬底基板110表面方向上的厚度可以在500nm-1000nm范围内，所述延长垫130A在垂直于衬底基板110表面方向上的厚度在200nm-900nm范围内。
在一些实施例中，如图7所示，衬底基板110的周边区中还可以设置有位于第一介质层112A与所述衬底基板110之间的第四介质层111。第四介质层111的一部分被去除，形成第四开口1204。第四开口1204在所述衬底基板110上的投影位于所述第二开口1202在所述衬底基板上的投影内，并且所述第一开口1201A在所述衬底基板110上的投影位于所述第四开口1204在所述衬底基板上的投影内。
图9A示出了根据本公开一实施例的交叉区域在切割前的布局图，例如该交叉区域可以对应于图2中的区域X1。
如图9A所示，多个延长垫130A垂直于切割道的切割线CL延伸。第一开口1201A、第二开口1202和第三开口1203位于切割道内。多个延长垫130A可以包括不同宽度的多个延长垫，例如包括至少一条具有第一宽度的第一延长垫130A_1和至少一条具有第二宽度的第二延长垫130A_2，其中第一宽度小于第二宽度。这里所谓第一宽度和第二宽度可以指的是垂直于延长垫延伸方向上的尺寸，例如在图9A中水平方向上的尺寸。在图9A中，每条第一延长垫130A_1与所述多个引脚160中的一个引脚连接，其宽度可以大致等于一个引脚的宽度。每条第二延长垫130A_2与所述多个引脚160中的至少两个引脚连接，其宽度可以大致等于其连接的引脚所占区域的总宽度，例如两个引脚所占区域的宽度。然而本公开的实施例不限于此，多个延长垫130A还可以包括具有其他宽度的延长垫，例如具有第三宽度的第三延长垫，其中第一宽度、第二宽度和第三宽度互不相同。
如图9A所示，多个延长垫130A_1和130A_2分别与多个引脚160连接，从而例如连接至上述走线SW、DR、DG、DB、GSTV、GCK、GCB、ESTV、ECK、ECB、Gout、Eout、MUX1-MUX6、ELVDD、ELVSS、VINT、VGH、VGL中任意一个或多个走线，进而向所连接的走线提供相应的信号。为例简明起见，图9A仅示出了一个显示基板的多个引脚中的若干个引脚以及与这些引脚连接的延长垫。
图9B示出了根据本公开一实施例的交叉区域在切割后的布局图，例如该交叉区域可以对应于图4中的区域X2。如图9B所示，通过沿着图9A所示的切割线CL对待切割基板进行切割，各个延长垫130A_1和130A_2被切断，得到独立的显示基板。如图9B所示，在切割后得到的显示基板中，延长垫130A_1和130A_2在第一方向(即延长垫的延伸方向)上的长度在0μm-100μm的范围内，例如可以在70μm-90μm的范围内。在一些实施例中，延长垫130A_1和130A_2在第一方向上的长度为80μm。这里所谓延长垫的长度可以指的是从引脚160开始延伸的长度，即，从引脚160的边缘到切割线 的长度。如图9B所示，在切割后得到的显示基板中，第一开口1201A在第一方向上的长度在0μm-90μm的范围内，例如可以在40μm-60μm的范围内。在一些实施例中，第一开口1201A在第一方向上的长度为50μm。
下面将参考图10至图12描述本公开另一实施例的显示基板的交叉区域的结构。
图10示出了根据本公开另一实施例的显示基板的交叉区域的平面示意图。图11示出了图10沿AA’的截面图。图12示出了图10沿BB’的截面图。在图10至图12中，交叉区域可以对应于切割前的交叉区域。
如图10至图12所示，衬底基板110的周边区中包括依次堆叠在衬底基板110上的第一介质层112B、第二介质层113和第三介质层114。多个延长垫130B位于第一介质层112B与第二介质层113之间。第一介质层112B、第二介质层113和第三介质层114各自的至少一部分被去除，形成了第一开口1201B、第二开口1202和第三开口1203，切割道的位置由第二开口和/或第三开口限定。第一开口1201B在衬底基板110上的投影位于第二开口1202在衬底基板110上的投影之内，第二开口1202在衬底基板110上的投影位于第三开口1203在衬底基板110上的投影之内。
如图10所示，与图6至图8不同，多个第一开口1201B充当了多个隔断结构，所述延长垫130B位于相邻所述第一开口1201B之间的第一介质层112B远离所述衬底基板110的一侧，且所述多个第一开口1201B在所述衬底基板110的正投影与所述多个延长垫130B在所述衬底基板的正投影不交叠。
通过这种方式，在切割道与多个延长垫130B交叉延伸的交叉区域内，多个延长垫130B通过多个第一开口1201B彼此隔离。多个彼此分离的第一开口1201B沿第一方向延伸并沿第二方向排列，所述第一方向是所述多个延长垫130B的延伸方向(由点划线AA’表示的方向)，所述第二方向是所述切割道的延伸方向(由点划线BB’表示的方向)。
如图10所示，在交叉区域内，每个延长垫130B在所述衬底基板110上具有第一投影(同样由130B表示)，每个第一开口1201B在所述衬底基板110上具有第二投影(同样由1201B表示)，每个第一投影130B与每个第二投影1201B均不重叠，并且相邻第一投影130B之间通过至少一个第二投影1201B间隔开。例如在图10中，第一投影130B和第二投影1201B交替排列，使得每两个相邻的第一投影130B之间有一个第二投影1201B。在图6中，每个第一投影130B在第一方向上的中心线跟与该第一投影相邻的两个第二投影1201B在一方向的中心线之间的距离相等。然而本公开的实施例不限于此，每个第一投影130B在第一方向上跟与该第一投影相邻的两个第二投影1201B之间的距 离可以根据需要来设置。例如在一些实施例中，可以使第二投影1201B在第二方向上的两个边缘尽可能靠近与该第二投影1201B相邻的第一投影130B的边缘，例如可以将二者之间的距离设置在0um-20um范围内。通过这种方式，可以使延长垫130B被第一介质层112B的材料垫高(如图11所示)，从而避免由于在延长垫130B的刻蚀过程中有金属残留于相邻的延长垫130B之间而导致延长垫130B短路。
在图10中，第一方向(AA’)与所述第二方向(BB’)垂直，第二投影1201B为矩形。然而本公开的实施例不限于此。本公开的技术构思适用于任何其他方式交叉延伸的延长垫和切割道，例如延长垫和切割道彼此非垂直交叉或者信号线和切割道沿着两个弧形或甚至不规则轨迹延伸并交叉，下文将对此进一步详细说明。
在一些实施例中，如图11和图12所示，第一介质层112B在垂直于衬底基板110表面方向上的厚度可以在500nm-1000nm范围内，所述延长垫130B在垂直于衬底基板110表面方向上的厚度在200nm-900nm范围内。
在一些实施例中，如图11所示，衬底基板110的周边区中还可以设置有位于第一介质层112B与所述衬底基板110之间的第四介质层111。第四介质层111可以采用与上述实施例的第四介质层相同的设计，使得每条切割道中除了包括第一开口1201B、第二开口1202、第三开口1203之外，还包括第四开口1204。
图13示出了根据本公开一实施例的显示区的子像素的结构图。
如图13所示，显示基板中多个子像素中的至少一个包含驱动薄膜晶体管和存储电容。驱动薄膜晶体管包括位于所述衬底基板110上的有源层P-Si，位于所述有源层P-Si远离所述衬底基板110一侧的栅极G，位于所述有源层P-Si与所述栅极G之间的第一栅绝缘层202，位于所述栅极G远离所述衬底基板110一侧的第二栅绝缘层203，位于所述第二栅绝缘层203远离所述衬底基板一侧的层间介质层204，以及位于所述层间介质层204远离所述衬底基板一侧的源极S和漏极D。存储电容包括第一电容电极ED1和第二电容电极ED2。所述第一电容电极ED1与所述栅极G位于同一层，所述第二电容电极ED2位于所述第二栅绝缘层203和层间介质层204之间。上述实施例中的多条信号线与所述多个子像素的源极S和漏极D中的至少之一同层设置，上述实施例中的第一介质层与所述层间介质层204同层设置。
如图13所示，所述多个子像素中的至少一个还包括平坦层206、阳极207和像素界定层209。平坦层206位于所述层间介质层204远离所述衬底基板110的一侧。阳极207位于所述平坦层206远离所述衬底基板110的一侧并且穿过所述平坦层206与所述源极 S或所述漏极D连接。像素界定层209位于所述平坦层206远离所述衬底基板110的一侧并且部分地覆盖所述阳极207。上述实施例中的第二介质层可以与所述平坦层206同层设置，所述第三介质层可以与所述像素界定层209同层设置。
在一些实施例中，子像素还可以包括缓冲层201，所述缓冲层201位于所述衬底基板110与所述第一栅绝缘层202之间，驱动薄膜晶体管的有源层P-Si位于缓冲层201和第一栅绝缘层202之间。上述实施例中的第四介质层可以与缓冲层201、第一栅绝缘层202和第二栅绝缘层203中的至少之一同层设置。例如第四介质层可以包括依次堆叠在衬底基板上的第一子层、第二子层和第三子层，其中第一子层与所述缓冲层201同层设置，所述第二子层与所述第一栅绝缘层202同层设置，所述第三子层与所述第二栅绝缘层203同层设置。
在一些实施例中，子像素还可以包括钝化层205，钝化层205位于平坦层206与层间介质层204之间，并且覆盖驱动薄膜晶体管的源极S和漏极D。阳极207穿过层间介质层206和钝化层205与驱动薄膜晶体管的源极S连接。
在一些实施例中，子像素还可以包括发光层211和阴极212。发光层211位于阳极210远离衬底基板110的一侧并且部分地覆盖阳极207。阴极212位于发光层211远离衬底基板110的一侧。
在一些实施例中，子像素还可以包括封装层213。封装层213位于阴极212远离衬底基板110的一侧。在一些实施例中，封装层213可以包括依次堆叠的第一无机封装层、有机封装层和第二无机封装层。
图14示出了根据本公开另一实施例的交叉区域的平面示意图。图14的显示基板的交叉的结构与图6至8所示的结构类似，区别至少在于图14中的第二方向(即切割线CL的方向)与第一方向(即延长垫130C的延伸方向)不垂直。如图14所示，类似于图6至图8，第一介质层、第二介质层和第三介质层中分别形成了第一开口1201C、第二开口1202和第三开口1203，多个延长垫130C与切割道交叉延伸。多个第一开口1201C沿着第一方向延伸，并且沿着切割线CL(第二方向)方向排列，第一方向与第二方向交叉并且彼此不垂直。每个延长垫130C在衬底基板上的投影与相应的一个第一开口1201C在衬底基板上的投影重叠，重叠方式与图6至图8所示类似，这里不再赘述。如图14所示，第一开口1201C在衬底基板上的投影为平行四边形，平行四边形四条边中，两条边平行于第一方向延伸，另外两条边平行于第二方向延伸。
图15示出了根据本公开另一实施例的显示基板的交叉区域的平面示意图。图15的 显示基板的交叉区域的结构与图10至12所示的结构类似，区别至少在于图15中切割道120的延伸方向(即切割线CL的方向)与延长垫130D的延伸方向不垂直。如图15所示，类似于图10至12，第一介质层、第二介质层和第三介质层中分别形成了第一开口1201D、第二开口1202和第三开口1203，多个延长垫130D与切割道120交叉延伸。多个第一开口1201D沿着延长垫130D的延伸方向(第一方向)延伸，并且沿着切割线CL(第二方向)方向排列，第一方向与第二方向交叉并且彼此不垂直。每个延长垫130D在衬底基板上的投影与相应的一个第一开口1201D在衬底基板上的投影重叠，重叠方式与图10至12所示类似，这里不再赘述。如图15所示，第一开口1201D在衬底基板上的投影为平行四边形，平行四边形四条边中，两条边平行于第一方向延伸，另外两条边平行于第二方向延伸。
下面将参考图16至图18描述本公开另一实施例的显示基板的交叉区域的结构。
图16示出了根据本公开另一实施例的交叉区域的平面示意图。图17示出了图16沿AA’的截面图。图18示出了图16沿BB’的截面图。
图16至图18的显示基板的交叉区域的结构与图6至8所示的结构类似，区别至少在于图16至18中衬底基板的周边区中还包括第五介质层115。为了简明起见，下面将主要对区别部分进行详细说明。
如图16至图18所示，显示基板的周边区包括层叠设置在衬底基板110上的第四介质层111、第一介质层112A、多个延长垫130A、第二介质层113、第五介质层115和第三介质层114。延长垫130A以及第一至第四介质层的布局可以与上述参考图6至图8描述的布局相同。第五介质层115位于第二介质层113与第三介质层114之间。第五介质层115的一部分被去除，形成第五开口1205。第五开口1205在衬底基板110上的投影位于第三开口114在衬底基板110上的投影内，并且第二开口113在衬底基板110上的投影位于第五开口1205在所述衬底基板110上的投影内。
图19示出了根据本公开另一实施例的显示区的子像素的结构图。图19的子像素结构与图13类似，区别至少在于图19的子像素的层间介质层包括第一平坦层206和第二平坦层208，并且子像素还包括转接电极210。
如图19所示，多个子像素中的至少一个子像素包括驱动薄膜晶体管和存储电容。驱动薄膜晶体管包括位于所述衬底基板110上的有源层P-Si，位于所述有源层P-Si远离所述衬底基板110一侧的栅极G，位于所述有源层P-Si与所述栅极G之间的第一栅绝缘层202，位于所述栅极G远离所述衬底基板110一侧的第二栅绝缘层203，位于所述第 二栅绝缘层203远离所述衬底基板一侧的层间介质层204，以及位于所述层间介质层204远离所述衬底基板一侧的源极S和漏极D。存储电容包括第一电容电极ED1和第二电容电极ED2。所述第一电容电极ED1与所述栅极G位于同一层，所述第二电容电极ED2位于所述第二栅绝缘层203和层间介质层204之间。图16至图18的实施例中的多条信号线与所述多个子像素的源极S和漏极D中的至少之一同层设置。上述实施例中的第一介质层与所述层间介质层204同层设置。
如图19所示，所述多个子像素中的至少一个还包括第一平坦层206、第二平坦层208、转接电极210、阳极207和像素界定层209。第一平坦层206位于所述层间介质层204远离所述衬底基板110的一侧。转接电极210位于所述第一平坦层206远离所述衬底基板110的一侧，并且通过设置在所述第一平坦层206中的过孔与所述薄膜晶体管的源极S连接。第二平坦层208位于所述转接电极210远离所述衬底基板110的一侧。阳极207位于所述第二平坦层208远离所述衬底基板110的一侧并且通过所述第二平坦层208中的过孔与所述转接电极210连接。像素界定层209位于所述第二平坦层208远离衬底基板的一侧并且至少部分地覆盖所述阳极207。上述图16至图18的实施例中的第二介质层可以与第一平坦层206同层设置，第三介质层可以与所述像素界定层209同层设置，第五介质层可以与第二平坦层208同层设置。
在一些实施例中，子像素还可以包括缓冲层201，所述缓冲层201位于所述衬底基板110与所述第一栅绝缘层202之间，驱动薄膜晶体管的有源层P-Si位于缓冲层201与第一栅绝缘层202之间。上述实施例中的第四介质层可以包括依次堆叠在衬底基板上的第一子层、第二子层和第三子层，其中第一子层与所述缓冲层201同层设置，所述第二子层与所述第一栅绝缘层202同层设置，所述第三子层与所述第二栅绝缘层203同层设置。
在一些实施例中，子像素还可以包括钝化层205，钝化层205位于平坦层206与层间介质层204之间，并且覆盖驱动薄膜晶体管的源极S和漏极D。阳极207穿过层间介质层206和钝化层205与驱动薄膜晶体管的源极S连接。
在一些实施例中，子像素还可以包括发光层211和阴极212。发光层211位于阳极210远离衬底基板110的一侧并且部分地覆盖阳极210。阴极212位于发光层211远离衬底基板110的一侧。
在一些实施例中，子像素还可以包括封装层213。封装层213位于阴极212远离衬底基板110的一侧。在一些实施例中，封装层213可以包括依次堆叠的第一无机封装 层、有机封装层和第二无机封装层。
应当注意的是，在以上的描述中，仅以示例的方式，示出了本公开实施例的技术方案，但并不意味着本公开实施例局限于上述步骤和结构。在可能的情形下，可以根据需要对步骤和结构进行调整和取舍。因此，某些步骤和单元并非实施本公开实施例的总体发明思想所必需的元素。
至此已经结合优选实施例对本公开进行了描述。应该理解，本领域技术人员在不脱离本公开实施例的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本公开实施例的范围不局限于上述特定实施例，而应由所附权利要求所限定。

Claims (27)

  1. 一种显示基板，包括：
    衬底基板，包括显示区和至少位于所述显示区一侧的周边区；
    多个子像素，位于所述显示区；
    多个引脚，位于所述衬底基板的周边区内，被配置为向所述多个子像素传输电信号，所述多个引脚在所述衬底基板上的正投影沿第一方向延伸且沿第二方向间隔分布，所述第一方向与所述第二方向相交；
    多个引线，至少位于所述衬底基板的周边区内，所述多个引脚通过所述多个引线与所述多个子像素电连接；
    多个延长垫，位于所述多个引脚远离所述显示区的一侧，沿所述第一方向延伸且沿所述第二方向间隔分布，所述多个延长垫与所述多个引脚电连接；
    多个隔断结构，位于所述多个延长垫之间且沿所述第一方向延伸，所述多个隔断结构在所述衬底基板上的正投影与所述多个延长垫在所述衬底基板上的正投影不交叠，所述多个隔断结构被配置为使所述多个延长垫之间电绝缘。
  2. 根据权利要求1所述的显示基板，其中，所述多个隔断结构与所述多个延长垫交替分布。
  3. 根据权利要求2所述的显示基板，其中，所述多个隔断结构与所述多个延长垫一一交替分布。
  4. 根据权利要求1所述的显示基板，其中，所述显示基板包括位于所述衬底基板上的第一介质层，所述第一介质层具有多个沿第二方向排布且沿第一方向延伸的多个第一开口，所述延长垫的至少部分位于所述第一开口中，相邻所述第一开口之间的所述第一介质层为所述多个隔断结构。
  5. 根据权利要求1所述的显示基板，其中，所述显示基板包括位于所述衬底基板上的第一介质层，所述第一介质层中具有多个沿第二方向排布且延第一方向延伸的多个第一开口，所述多个第一开口为所述多个隔断结构，所述延长垫位于相邻所述第一开口之间的所述第一介质层远离所述衬底基板的一侧，且所述多个第一开口在所述衬底基板的正投影与所述多个延长垫在所述衬底基板的正投影不交叠。
  6. 根据权利要求4或5所述的显示基板，还包括位于所述周边区的第二介质层和第三介质层，所述第二介质层位于第一介质层远离所述衬底基板的一侧，所述第三介质层位于所述第二介质层远离所述衬底基板的一侧，所述延长垫位于所述第一介质层 与所述第二介质层之间的导体层中，所述第二介质层具有第二开口，所述第三介质层具有第三开口，所述第二开口和所述第三开口暴露至少部分所述延长垫。
  7. 根据权利要求6所述的显示基板，其中，所述多个第一开口在所述衬底基板上的正投影位于所述第二开口在所述衬底基板上的正投影之内，所述第二开口在所述衬底基板上的正投影位于所述第三开口在所述衬底基板上的正投影之内。
  8. 根据权利要求1所述的显示基板，其中，所述多个延长垫中的每个延长垫在所述衬底基板上具有第一正投影，所述多个隔断结构中的每个隔断结构在所述衬底基板上具有第二正投影，每个第一正投影与相邻的第二正投影在第二方向上的间距在0um-20um范围内。
  9. 根据权利要求8所述的显示基板，其中，每个第一正投影在所述第一方向上的中心线跟与该第一正投影相邻的两个第二正投影在所述第一方向的中心线之间的距离相等。
  10. 根据权利要求1至9中任一项所述的显示基板，其中，所述第一方向与所述第二方向垂直。
  11. 根据权利要求10所述的显示基板，其中，所述隔断结构在所述衬底基板上的正投影为矩形。
  12. 根据权利要求1至9中任一项所述的显示基板，其中，所述第一方向与所述第二方向不垂直，所述隔断结构在所述衬底基板上的正投影为平行四边形。
  13. 根据权利要求1至12中任一项所述的显示基板，其中，所述第一介质层的厚度在500nm-1000nm范围内，所述延长垫在垂直于衬底基板表面方向上的厚度在200nm-900nm范围内。
  14. 根据权利要求10或12所述的显示基板，其中，所述隔断结构在所述第一方向上的尺寸小于所述延长垫在所述第一方向上的尺寸。
  15. 根据权利要求1至14中任一项所述的显示基板，还包括：
    测试相关电路，位于所述周边区，布置在所述多个引脚面向所述显示区的一侧，并且包围所述显示区的至少一部分，所述测试相关电路通过多个信号线与所述显示区内的多个子像素连接，并且通过所述多个引线与所述多个引脚连接。
  16. 根据权利要求15所述的显示基板，其中，所述多个延长垫包括至少一个第一延长垫和至少一个第二延长垫，每个第一延长垫与所述多个引脚中的一个引脚连接，每个第二延长垫与所述多个引脚中的至少两个引脚连接，所述第一延长垫的线宽小于 第二延长垫的线宽。
  17. 根据权利要求15所述的显示基板，其中，所述测试相关电路包括单元测试电路，所述多个信号线包括多条数据线，所述多个引线包括多个单元测试控制信号线，所述多个引脚包括多个第一引脚，并且
    其中，所述单元测试电路通过所述多条数据线与所述显示区内的多个子像素连接，并通过所述单元测试控制信号线与所述多个第一引脚连接。
  18. 根据权利要求17所述的显示基板，其中，所述测试相关电路还包括驱动电路，所述多个信号线还包括多个驱动信号线，所述多个引线还包括多个驱动控制信号线和多条驱动测试信号线，所述多个引脚还包括多个第二引脚，并且
    其中，所述驱动电路通过所述多条驱动信号线与所述显示区内的多个子像素连接，并且通过所述多条驱动控制信号线和所述多条驱动测试信号线与所述多个第二引脚连接。
  19. 根据权利要求17所述的显示基板，其中，所述测试相关电路还包括多路复用电路，所述多个引线还包括多个多路复用控制信号线，所述多个引脚还包括多个第三引脚，并且，
    其中，所述多路复用电路通过所述多条数据线与所述显示区内的多个子像素连接，并且通过所述多条多路复用控制信号线与所述多个第三引脚连接。
  20. 根据权利要求17所述的显示基板，其中，所述测试相关电路还包括电源电压线和参考电压线，所述多个信号线还包括电源电压第一走线和参考电压第一走线，所述多个引线还包括电源电压第二走线和参考电压第二走线，所述多个引脚还包括多个第四引脚，并且，
    其中，所述电源电压线通过所述电源电压第一走线连接至所述显示区内的多个子像素，所述参考电压线通过所述参考电压第一走线连接至所述显示区内的多个子像素，所述电源电压线通过所述电源电压第二走线连接至所述多个第四引脚中的至少一个第四引脚，所述参考电压线通过所述参考电压第二走线连接至所述多第四引脚中的至少另一个第四引脚。
  21. 根据权利要求1至20中任一项所述的显示基板，还包括：第四介质层，位于所述周边区，布置在第一介质层与所述衬底基板之间，且具有第四开口，所述第四开口在所述衬底基板上的正投影位于所述第二开口在所述衬底基板上的正投影内，并且所述多个第一开口在所述衬底基板上的正投影位于所述第四开口在所述衬底基板上的 正投影内。
  22. 根据权利要求1至21中任一项所述的显示基板，还包括：第五介质层，位于所述周边区，布置在第二介质层与第三介质层之间且具有第五开口，所述第五开口在所述衬底基板上的正投影位于所述第三开口在所述衬底基板上的正投影内，并且所述第二开口在所述衬底基板上的正投影位于所述第五开口在所述衬底基板上的正投影内。
  23. 根据权利要求1至22中任一项所述的显示基板，其中，所述多个子像素中的至少一个包括驱动薄膜晶体管和存储电容；
    所述驱动薄膜晶体管包括位于所述衬底基板上的有源层，位于所述有源层远离所述衬底基板一侧的栅极，位于所述有源层与所述栅极之间的第一栅绝缘层，位于所述栅极远离所述衬底基板一侧的第二栅绝缘层，位于所述第二栅绝缘层远离所述衬底基板一侧的层间介质层，以及位于所述层间介质层远离所述衬底基板一侧的源极和漏极；
    所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极与所述栅极位于同一层，所述第二电容电极位于所述第二栅绝缘层和层间介质层之间；
    所述多条延长垫与所述多个子像素的源极和漏极中的至少之一同层设置，位于所述周边区的第一介质层与所述层间介质层同层设置。
  24. 根据权利要求23所述的显示基板，其中，所述多个子像素中的至少一个还包括：
    平坦层，位于所述层间介质层远离所述衬底基板的一侧；
    阳极，位于所述平坦层远离所述衬底基板的一侧并且穿过所述平坦层与所述源极或所述漏极连接；
    像素界定层，位于所述平坦层远离所述衬底基板的一侧并且部分地覆盖所述阳极，
    其中，位于周边区的第二介质层与所述平坦层同层设置，位于周边区的第三介质层与所述像素界定层同层设置。
  25. 根据权利要求24所述的显示基板，其中，所述多个子像素中的至少一个还包括：
    第一平坦层，位于所述层间介质层远离所述衬底基板的一侧；
    转接电极，位于所述第一平坦层远离所述衬底基板的一侧，并且通过设置在所述第一平坦层中的过孔与所述薄膜晶体管的源极连接；
    第二平坦层，位于所述转接电极远离所述衬底基板的一侧；
    阳极，位于所述第二平坦层远离所述衬底基板的一侧并且通过所述第二平坦层中 的过孔与所述转接电极连接；
    像素界定层，位于所述第二平坦层远离衬底基板的一侧并且至少部分地覆盖所述阳极，
    其中，所述衬底基板的周边区中还包括位于第二介质层与第三介质层之间的第五介质层，所述第二介质层与所述第一平坦层同层设置，所述第三介质层与所述像素界定层同层设置，所述第五介质层与所述第二平坦层同层设置。
  26. 根据权利要求23至25中任一项所述的显示基板，其中，所述多个子像素中的至少一个还包括缓冲层，所述缓冲层位于所述衬底基板与所述第一栅绝缘层之间；并且
    所述衬底基板的周边区中还包括位于第一介质层与所述衬底基板之间的第四介质层，所述第四介质层与所述缓冲层、所述第一栅绝缘层和所述第二栅绝缘层中的至少之一同层设置。
  27. 一种显示装置，包括如权利要求1至26中任一项所述的显示基板。
PCT/CN2021/115556 2021-08-31 2021-08-31 显示基板和显示装置 WO2023028814A1 (zh)

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