WO2022006769A1 - 显示基板及其制造方法以及显示面板 - Google Patents

显示基板及其制造方法以及显示面板 Download PDF

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Publication number
WO2022006769A1
WO2022006769A1 PCT/CN2020/100798 CN2020100798W WO2022006769A1 WO 2022006769 A1 WO2022006769 A1 WO 2022006769A1 CN 2020100798 W CN2020100798 W CN 2020100798W WO 2022006769 A1 WO2022006769 A1 WO 2022006769A1
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WIPO (PCT)
Prior art keywords
signal line
sub
line
array test
pins
Prior art date
Application number
PCT/CN2020/100798
Other languages
English (en)
French (fr)
Inventor
王予
张毅
刘庭良
罗昶
尚庭华
杨慧娟
周洋
于鹏飞
张顺
韩林宏
张猛
张昊
姜晓峰
李慧君
和玉鹏
张鑫
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/289,705 priority Critical patent/US11657750B2/en
Priority to CN202080001193.6A priority patent/CN114158282B/zh
Priority to PCT/CN2020/100798 priority patent/WO2022006769A1/zh
Publication of WO2022006769A1 publication Critical patent/WO2022006769A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a method for manufacturing the display substrate, and a display panel.
  • an array test (AT, Array Test) is performed on the array substrate of the display panel to ensure product quality.
  • Embodiments of the present disclosure provide a display substrate, including:
  • a base substrate including a display area and a peripheral area surrounding the display area
  • a plurality of data lines located in the display area and extending along the first direction, the plurality of data lines being electrically connected to the plurality of sub-pixels;
  • a plurality of gate lines located in the display area and extending along a second direction, the first direction and the second direction crossing, the plurality of gate lines being electrically connected to the plurality of sub-pixels;
  • a gate drive circuit located in the peripheral region, the gate drive circuit is electrically connected to the plurality of gate lines;
  • a first start-up voltage signal line, a first clock signal line and a second clock signal line are electrically connected to the gate driving circuit;
  • the plurality of array test signal lines include at least one of the first start-up voltage signal line, the first clock signal line, or the second clock signal line;
  • a plurality of second array test pins located between the plurality of first pins and the plurality of second pins and extending along the boundary direction of the display area, the plurality of first array test pins are Located on at least one side of the plurality of second array test pins along the extension direction of the boundary of the display area, the plurality of second array test pins are electrically connected to the plurality of data lines, and the plurality of second array test pins are electrically connected to the plurality of data lines.
  • the second array test pin is configured to receive array test data signals from the plurality of subpixels through the plurality of data lines.
  • the plurality of array test signal lines include the first startup voltage signal line, the first clock signal line, and the second clock signal line.
  • the display area includes a first border, a second border, a third border and a fourth border which are connected in sequence, and the plurality of first array test pins and the plurality of second array test pins are located close to all the the peripheral area of the first boundary;
  • the gate driving circuit includes a first subcircuit and a second subcircuit, the first subcircuit and the second subcircuit are located in the peripheral region near the second boundary and the fourth boundary, respectively;
  • the first startup voltage signal line includes a first subline of the first startup voltage signal line and a second subline of the first startup voltage signal line
  • the first clock signal line includes a first subline of the first clock signal line and a second subline of the first startup voltage signal line.
  • a clock signal line and a second sub-line, the second clock signal line includes a first sub-line of a second clock signal line and a second sub-line of a second clock signal line, the first start-up voltage signal line is a first sub-line, The first sub-line of the first clock signal line and the first sub-line of the second clock signal line are located in the peripheral region near the second boundary, and are electrically connected to the first sub-circuit, the first sub-line The second sub-line of the start-up voltage signal line, the second sub-line of the first clock signal line, and the second sub-line of the second clock signal line are located in the peripheral region near the fourth boundary, and are electrically connected to the the second subcircuit;
  • the plurality of first array test pins include a first group of first array test pins and a second group of first array test pins, the first group of first array test pins and the second group of first array test pins
  • the array test pins are respectively located on both sides of the plurality of second array test pins along the extending direction of the first boundary;
  • the first sub-line of the first start-up voltage signal line, the first sub-line of the first clock signal line and the first sub-line of the second clock signal line are electrically connected to the first group of the first array test leads.
  • the second sub-line of the first start-up voltage signal line, the second sub-line of the first clock signal line and the second sub-line of the second clock signal line are electrically connected to the second group of the first array test leads foot.
  • the display substrate further includes:
  • a plurality of light-emitting control lines located in the display area and extending along the second direction, the plurality of light-emitting control lines being electrically connected to the plurality of sub-pixels;
  • a light-emitting control driving circuit located in the peripheral region and on a side of the gate driving circuit away from the display region;
  • a second startup voltage signal line, a third clock signal line and a fourth clock signal line, the light emission control driving circuit is electrically connected to the second startup voltage signal line, the third clock signal line, and the fourth clock signal line, the plurality of array test signal lines further include at least one of the second start voltage signal line, the third clock signal line or the fourth clock signal line.
  • the plurality of array test signal lines further include the second startup voltage signal line, the third clock signal line and the fourth clock signal line.
  • the display area includes a first border, a second border, a third border and a fourth border which are connected in sequence, and the plurality of first array test pins and the plurality of second array test pins are located close to all the the peripheral area of the first boundary;
  • the light-emitting control driving circuit includes a third sub-circuit and a fourth sub-circuit, and the third sub-circuit and the fourth sub-circuit are respectively located in the peripheral area near the second boundary and the fourth boundary ;
  • the second startup voltage signal line includes a first subline of the second startup voltage signal line and a second subline of the second startup voltage signal line
  • the third clock signal line includes a first subline of the third clock signal line and a second subline of the second startup voltage signal line.
  • the first sub-line of the second start-up voltage signal line, the first sub-line of the third clock signal line and the first sub-line of the fourth clock signal line are located in the peripheral region close to the second boundary, and
  • the third sub-circuit is electrically connected, and the second start-up voltage signal line, the second sub-line, the third clock signal line, and the fourth clock signal line are located close to the second sub-line of the fourth clock signal line.
  • the peripheral area of the four borders is electrically connected to the fourth sub-circuit;
  • the plurality of first array test pins include a first group of first array test pins and a second group of first array test pins, the first group of first array test pins and the second group of first array test pins
  • the array test pins are respectively located on both sides of the plurality of second array test pins;
  • the first sub-line of the second start-up voltage signal line, the first sub-line of the third clock signal line and the first sub-line of the fourth clock signal line are electrically connected to the first group of the first array test leads.
  • the second start voltage signal line second sub-line, the third clock signal line second sub-line and the fourth clock signal line second sub-line are electrically connected to the second group of the first array test leads foot.
  • the display substrate further includes:
  • the multiplexing circuit located between the plurality of second pins and the display area, the multiplexing circuit includes a plurality of multiplexing switches, at least one of the multiplexing switches is multiplexed
  • the switch includes a first transistor and a second transistor, the gate of the first transistor is electrically connected to the first selection signal line, and the gate of the second transistor is electrically connected to the second selection signal line;
  • the plurality of array test signal lines further include the first selection signal line and the second selection signal line.
  • the first selection signal line includes a first sub-line of the first selection signal line and a second sub-line of the first selection signal line
  • the second selection signal line includes a first sub-line and a second sub-line of the second selection signal line Select the second sub-line of the signal line
  • the plurality of first array test pins include a first group of first array test pins and a second group of first array test pins, the first group of first array test pins and the second group of first array test pins
  • the array test pins are respectively located on both sides of the plurality of second array test pins;
  • the first sub-line of the first selection signal line and the first sub-line of the second selection signal line are electrically connected to the first group of the first array test pins, and the second sub-line of the first selection signal line The second sub-line of the second selection signal line is electrically connected to the second group of the first array test pins.
  • the display substrate further includes a plurality of initial voltage signal lines in the display area and an initial voltage signal bus in the peripheral area, the initial voltage signal bus is located between the gate driving circuit and the display area , the plurality of array test signal lines further include the initial voltage signal bus.
  • the initial voltage signal bus includes a first sub-line of the initial voltage signal bus and a second sub-line of the initial voltage signal bus, and the first sub-line of the initial voltage signal bus and the second sub-line of the initial voltage signal bus are respectively located in the peripheral area proximate the second boundary and the fourth boundary;
  • the plurality of first array test pins include a first group of first array test pins and a second group of first array test pins, the first group of first array test pins and the second group of first array test pins
  • the array test pins are respectively located on both sides of the plurality of second array test pins;
  • the first sub-line of the initial voltage signal bus is electrically connected to the first group of the first array test pins
  • the second sub-line of the initial voltage signal bus is electrically connected to the second group of the first array test pins foot.
  • the display substrate further includes a plurality of first power lines located in the display area and a first power bus line located in the peripheral area close to the first boundary, the plurality of first power lines and the first power lines
  • the power bus is electrically connected
  • the plurality of array test signal lines further include the first power bus.
  • the first power bus includes a first sub-line of the first power bus and a second sub-line of the first power bus, and the first sub-line of the first power bus and the second sub-line of the first power bus are respectively located in the peripheral region near the first boundary;
  • the plurality of first array test pins include a first group of first array test pins and a second group of first array test pins, the first group of first array test pins and the second group of first array test pins
  • the array test pins are respectively located on both sides of the plurality of second array test pins;
  • the first sub-line of the first power bus is electrically connected to the first group of the first array test pins
  • the second sub-line of the first power bus is electrically connected to the second group of the first array test pins foot.
  • the display substrate further includes:
  • a first unit test circuit located between the plurality of second pins and the display area, the first unit test circuit includes a plurality of first test sub-circuits, and one of the plurality of first test sub-circuits At least one includes a third transistor, a fourth transistor and a fifth transistor, the gate of the third transistor is electrically connected to the first switch signal line, and the gate of the fourth transistor is electrically connected to the second switch a signal line, the gate of the fifth transistor is electrically connected to the third switch signal line;
  • a second unit test circuit located between the plurality of second pins and the first unit test circuit, the second unit test circuit includes a plurality of second test subcircuits, the plurality of second test subcircuits At least one of the circuits includes a sixth transistor with a gate electrically connected to the fourth switch signal line;
  • the plurality of array test signal lines further include at least one of the first switch signal line, the second switch signal line, the third switch signal line or the fourth switch signal line.
  • the plurality of array test signal lines further include the first switch signal line, the second switch signal line, the third switch signal line, and the fourth switch signal line.
  • the first switch signal line includes a first sub-line of the first switch signal line and a second sub-line of the first switch signal line
  • the second switch signal line includes a first sub-line and a second sub-line of the second switch signal line
  • the second sub-line of the switch signal line, the third switch signal line includes the first sub-line of the third switch signal line and the second sub-line of the third switch signal line, and the fourth switch signal line includes the fourth switch signal line.
  • the plurality of first array test pins include a first group of first array test pins and a second group of first array test pins, the first group of first array test pins and the second group of first array test pins
  • the array test pins are respectively located on both sides of the plurality of second array test pins;
  • the first sub-line of the first switch signal line, the first sub-line of the second switch signal line, the first sub-line of the third switch signal line, and the first sub-line of the fourth switch signal line are electrically connected to The first group of the first array test pins, the second sub-line of the first switch signal line, the second sub-line of the second switch signal line, the second sub-line of the third switch signal line, and the The second sub-line of the fourth switch signal line is electrically connected to the second group of first array test pins.
  • At least a part of the array test signal lines of the plurality of array test signal lines is connected to a part of the second pins of the plurality of second pins in a one-to-one correspondence, and the part of the second pins is connected through a plurality of The first connection lines are connected to at least a part of the first array test pins of the plurality of first array test pins in a one-to-one correspondence.
  • the at least a part of the array test signal lines include the first start voltage signal line, the first clock signal line, the second clock signal line, the second start voltage signal line, the third clock signal line, the Four clock signal lines, a first selection signal line, a second selection signal line and an initial voltage signal bus.
  • another part of the array test signal lines in the plurality of array test signal lines is in a one-to-one correspondence with another part of the first array test pins in the plurality of first array test pins through the plurality of second connection lines connect.
  • the other part of the array test signal lines includes a first switch signal line, a second switch signal line, a third switch signal line, a fourth switch signal line, and a first power bus.
  • the display substrate further includes an electrostatic discharge circuit
  • the electrostatic discharge circuit includes a plurality of electrostatic discharge units
  • the plurality of electrostatic discharge units are located between the plurality of first array test pins and the plurality of second leads
  • the pins are connected one-to-one with the plurality of first array test pins
  • each electrostatic discharge unit includes a seventh transistor and an eighth transistor, and the gate of the seventh transistor is connected to the first electrode to the high voltage signal line, the second pole of the eighth transistor is connected to the low voltage signal line, the second pole of the seventh transistor and the gate and first pole of the eighth transistor are electrically connected to the first array test pin.
  • the plurality of first array test pins and the plurality of second array test pins are arranged in one or more rows along the extending direction of the boundary of the display area.
  • At least one of the plurality of sub-pixels includes a driving thin film transistor and a storage capacitor
  • the driving thin film transistor includes a driving active layer located on the base substrate, a driving gate located on the side of the driving active layer away from the base substrate, and the driving gate is located away from the substrate A gate insulating layer on one side of the substrate, an interlayer dielectric layer on the side of the gate insulating layer away from the base substrate, and a driving source electrode and a driver on the side of the interlayer dielectric layer away from the base substrate drain;
  • the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the drive gate are located on the same layer, and the second capacitor electrode is located on the gate insulating layer and the interlayer dielectric layer between;
  • At least one layer of the plurality of first array test pins and the plurality of second array test pins is located at the same layer as the driving source electrodes and the driving drain electrodes of the plurality of sub-pixels in the display area.
  • the plurality of first connection lines and the driving source electrodes and the driving drain electrodes of the plurality of sub-pixels in the display area are located in the same layer.
  • each of the plurality of second connection lines is partially located in the same layer as the driving source electrodes and the driving drain electrodes of the plurality of sub-pixels in the display area, and is partly located in the display area.
  • the driving gates of the plurality of sub-pixels in are located in the same layer.
  • the display substrate further includes: an anisotropic conductive film covering the plurality of first array test pins and the plurality of second array test pins.
  • Embodiments of the present disclosure also provide a display panel including the above-mentioned display substrate.
  • FIG. 1 shows a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIGS. 2A to 2D illustrate schematic diagrams of various examples of display substrates according to embodiments of the present disclosure.
  • 3A is a schematic diagram illustrating a partial structure of a display substrate according to an embodiment of the present disclosure, wherein the structure of a driving circuit is shown.
  • 3B shows a schematic diagram of a partial structure of a display substrate according to an embodiment of the present disclosure, wherein the structure of a driving circuit and a structure of a display area are shown.
  • FIG. 4A shows a structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 4B shows a partial enlarged view of FIG. 4A.
  • FIG. 5A shows a structural diagram of a display substrate according to another embodiment of the present disclosure.
  • 5B shows a circuit diagram of a multiplexing circuit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 5C shows a partial enlarged view of FIG. 5A.
  • FIG. 6A shows a structural diagram of a display substrate according to another embodiment of the present disclosure.
  • 6B illustrates a circuit diagram of a unit test circuit and a multiplexing circuit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 6C shows a partial enlarged view of FIG. 6A.
  • FIG. 7A shows a structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 7B shows a schematic diagram of a first power bus and a first power line in a display substrate according to an embodiment of the present disclosure.
  • FIG. 7C shows a partial enlarged view of FIG. 7A.
  • FIG. 8A shows a structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 8B shows a schematic diagram of an initial voltage signal bus line and an initial voltage signal line in a display substrate according to an embodiment of the present disclosure.
  • FIG. 8C shows a partial enlarged view of FIG. 8A.
  • FIG. 9A shows a schematic diagram of an electrostatic discharge circuit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 9B shows a circuit diagram of an electrostatic discharge unit of an electrostatic protection circuit according to an embodiment of the present disclosure.
  • FIG. 10A shows a layout diagram of a multiplexing circuit according to an embodiment of the present disclosure.
  • FIG. 10B shows a block diagram of a multiplexing circuit according to an embodiment of the present disclosure.
  • FIG. 11A shows a layout diagram of a first array test circuit according to an embodiment of the present disclosure.
  • FIG. 11B shows a layout diagram of a second array test circuit according to an embodiment of the present disclosure.
  • FIG. 12 shows a layout diagram of an electrostatic discharge circuit according to an embodiment of the present disclosure.
  • FIG. 13 shows a schematic diagram of a pixel structure according to an embodiment of the present disclosure.
  • FIG. 14 shows a flowchart of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • connection may mean that two components are directly connected, or may mean that two components are connected via one or more other components.
  • the two components may be connected or coupled by wired or wireless means.
  • an array test (AT, Array Test) can be performed on the circuit structure on the display substrate to determine the interior of the display substrate. circuit for defects.
  • a plurality of array test pins connected to the display panel are provided outside the display panel. Through these array test pins, an array test can be performed on the pixel circuit inside the display panel. After the array test is completed, the array test pins are removed from the display panel, so as to form the display layer on the display substrate and install the driving circuit. But this brings inconvenience to the manufacture and testing of the display panel.
  • the design of the array test pins does not need to be limited by the pins in the display substrate for connecting with the array test pins.
  • Layout eliminates the need for additional steps to remove the array test pins, simplifies the manufacturing process, and avoids circuit shorts or leakage caused by the removal of test pins.
  • FIG. 1 shows a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • the display substrate 100 includes a base substrate, and the base substrate includes a display area 10 and a peripheral area 11 surrounding the display area 10 .
  • a plurality of sub-pixels are provided in the display area 10, and the plurality of sub-pixels can be arranged in an array.
  • the first pin area 20 provided with a plurality of first pins and the second pin area 30 provided with a plurality of second pins are located in the peripheral area 11, wherein the second pin area 30 is located in the display area 10 and the second pin area 30. between a pin area 20 .
  • a plurality of first array test pins and a plurality of second array test pins are disposed in a region (indicated by 40 in FIG. 1 ) between the first pin region 20 and the second pin region 30 .
  • the plurality of first array test pins are used to provide array test signals, and a plurality of sub-pixels in the display area 10 can generate array test data signals in response to the array test signals.
  • the plurality of second array test pins are used for receiving array test data signals from a plurality of sub-pixels in the display area 10 .
  • an array test of a plurality of sub-pixels in the display area 10 can be implemented to determine whether the pixel circuit in the display area 10 of the display substrate is abnormal, which will be described in further detail below.
  • the first array test pins and the second array test pins may be arranged between the plurality of first pins 20 and the plurality of second pins 30 in various ways, which will be exemplified below with reference to FIGS. 2A to 2D . instruction.
  • FIGS. 2A to 2D illustrate schematic diagrams of various examples of display substrates according to embodiments of the present disclosure.
  • the display substrate 200A includes a display area 10 and a peripheral area 11 .
  • the first pin area 20, the second pin area 30, and a plurality of first array test pins PIN1 and a plurality of second array test pins disposed between the first pin area 20 and the second pin area 30 PIN2 is located in the peripheral area 11 .
  • a plurality of second array test pins PIN2 are arranged in the first area 41 .
  • a part of the first array test pins PIN1 of the plurality of first array test pins (for example, the left three first array test pins PIN1 in FIG. 2A ) are arranged in the second area 42 , and the plurality of first array test pins PIN1 Another part of the first array test pins (the three first array test pins PIN1 on the right side in FIG. 2A ) of the test pins PIN1 is arranged in the third area 43 .
  • the first area 41 , the second area 42 and the third area 43 are all located between the first lead area 20 and the second lead area 30 .
  • the first pin area 20 and the second pin area 30 are arranged along the first direction (the y direction in FIG. 2A ) on one side of the display area 10 , and the first area 41 , the second area 42 and the third area 43 are arranged along the first direction (y direction in FIG. 2A ).
  • a second direction (x direction in FIG. 2A ) perpendicular to the first direction is aligned.
  • the second area 42 and the third area 43 are located on both sides of the first area 41, respectively.
  • the second area 42 is located on the left side of the first area 41
  • the third area 43 is located on the right side of the first area 41.
  • a plurality of first array test pins PIN1 and a plurality of second array test pins PIN2 are arranged in a row along the x direction.
  • the distribution of the first array test pins PIN1 and the second array test pins PIN2 can have higher symmetry.
  • the number of pins in the second region 42 can be made equal to the number of pins in the third region 43 to further improve symmetry.
  • first array test pins PIN1 and the second array test pins PIN2 may be arranged between the first pin area 20 and the second pin area 30 in other ways.
  • the first array test pins PIN1 and the second array test pins PIN2 may be disposed in two areas, respectively.
  • the second array test pins PIN2 are arranged in the first area 41
  • the first array test pins PIN1 are arranged in the second area 42 .
  • Both the first area 41 and the second area 42 are located between the first lead area 20 and the second lead area 30 .
  • the first area 41 and the second area 42 are arranged along the x direction, so that the first array test pins PIN1 and the second array test pins PIN2 are arranged in a row along the x direction.
  • the first area 41 and the second area 42 can also be arranged in other ways, for example, arranged along the y direction or arranged arbitrarily.
  • the first array test pins PIN1 and the second array test pins PIN2 may be distributed in four or more regions.
  • the first array test pins PIN1 and the second array test pins PIN2 may be arranged in multiple rows.
  • a plurality of second array test pins PIN2 are arranged in the first area 41 .
  • a part of the first array test pins PIN1 of the plurality of first array test pins (for example, the left six first array test pins PIN1 in FIG. 2C ) are arranged in the second area 42 , and the plurality of first array test pins PIN1 Another part of the first array test pins (the six first array test pins PIN1 on the right side in FIG. 2C ) in the test pins PIN1 is arranged in the third area 43 .
  • the first area 41 , the second area 42 and the third area 43 are disposed between the first lead area 20 and the second lead area 30 in a manner similar to that shown in FIG. 2A .
  • the second array test pins PIN2 in the first area 41 and the first array test pins PIN2 in the second area 42 and the third area 43 are arranged in two rows along the x direction, so that the first array test pins PIN1 And the second array test pins PIN2 are also arranged in two rows along the x direction as a whole.
  • the embodiment of the present disclosure is not limited thereto, and the first array test pins PIN1 and the second array test pins PIN2 may also be arranged in three or more rows.
  • array test pins the size of the space occupied by the first array test pins and the second array test pins (hereinafter collectively referred to as array test pins) in the x-th direction, or the space in the x-direction of the display substrate can be reduced More array test pins can be placed in the case of limited size.
  • the first array test pins PIN1 and the second array test pins PIN2 may be partially arranged in one row and partially arranged in multiple rows.
  • a plurality of second array test pins PIN2 are arranged in the first area 41 , and a part of the first array test pins PIN1 of the plurality of first array test pins PIN1 (for example, the left side 3 in FIG. 2D )
  • the first array test pins PIN1 are arranged in the second area 42, and another part of the first array test pins PIN1 in the plurality of first array test pins (the three first array test pins on the right side in FIG.
  • the pin PIN1) is arranged in the third area 43 .
  • the plurality of second array test pins PIN2 in the first area 41 are arranged in two rows along the x direction, and are arranged in a 2 ⁇ 6 array in FIG. 2D .
  • Both the first array test pins PIN1 in the second area 42 and the first array test pins PIN1 in the third area 43 are arranged in a row, and are arranged in a 1 ⁇ 3 array in FIG. 2D .
  • first array detection pins and the second array detection pins of the embodiments of the present disclosure are described above through specific examples, the embodiments of the present disclosure are not limited thereto.
  • the first array detection pins and the second array detection pins may be disposed between the second pin array 20 and the first pin array 30 in any other manner as required.
  • FIG. 3A shows a schematic diagram of a partial structure of a display substrate 300 according to an embodiment of the present disclosure, in which driving circuits and structures are shown.
  • 3B is a schematic diagram illustrating a partial structure of the display substrate 300 according to an embodiment of the present disclosure, wherein the structure of the driving circuit and the structure of the display area are shown.
  • a plurality of sub-pixels P are provided in the display area 10 of the display substrate 300, and the plurality of sub-pixels P can be arranged in an array, for example, in the form of a plurality of rows, including the first row of sub-pixels P1, The second row of sub-pixels P2, . . . , the n-th row of sub-pixels Pn.
  • the data line DATA1 is connected to the sub-pixels P in the first column
  • the data line DATA2 is connected to the sub-pixels P in the second column
  • the data line DATAk is connected to the sub-pixels in the k-th column.
  • a plurality of gate lines GATE1 , GATE2 , . . . , GATEn are located in the display area 10 and extend along the second direction (x direction). The first direction (y direction) and the second direction (x direction) intersect.
  • a plurality of gate lines GATE1 , GATE2 , . . . , GATEn are electrically connected to the plurality of sub-pixels P.
  • the gate line GATE1 is connected to the sub-pixels P1 in the first row
  • the gate line GATE2 is connected to the sub-pixels P2 in the second row
  • the gate line GATEn is connected to the sub-pixels Pn in the nth row.
  • the gate driving circuit 50 is located in the peripheral region 11 , and the gate driving circuit 50 is connected to a plurality of gate lines GATE1 , GATE2 , . . . , GATEn.
  • the gate driving circuit 50 includes a plurality of shift registers GOA0, GOA1, .
  • the reset terminal of the 1st stage first shift register GOA(i+1).
  • the first shift register GOA1 of the first stage is connected to the gate line GATA1 to provide gate driving signals to the sub-pixels P1 in the first row
  • the first shift register GOA2 of the second stage is connected to the gate line GATA2 to provide the sub-pixels P1 of the second row with gate driving signals.
  • Pixel P2 provides gate drive signals, and so on.
  • the gate driving signal for the sub-pixel Pi in the i-th row generated by the shift register GOAi of the i-th stage is also used as the reset signal RST(i) for the sub-pixel P(i+1) in the i+1-th row +1).
  • the gate driving signal for the sub-pixel P0 in the 0th row generated by the first shift register GOA0 in the 0th stage is also used as the reset signal RST1 for the sub-pixel P1 in the 1st row.
  • the first shift register GOA1 in the first stage The generated gate driving signal for the sub-pixels P1 in the first row is also used as the reset signal RST2 for the sub-pixels P2 in the second row, and so on.
  • the gate driving circuit 50 is also electrically connected to the first start-up voltage signal line GSTV, the first clock signal line GCK and the second clock signal line GCB to generate gate driving signals under its control.
  • the 0th stage first shift register GOA0 in the gate driving circuit 50 is electrically connected to the first start voltage signal line GSTV, the first clock signal line GCK and the second clock signal line GCB, so that the first start voltage signal A gate driving signal for the 0th row of sub-pixels is generated under the control of the line GSTV, the first clock signal line GCK and the second clock signal line GCB, which is also used as the reset signal RST1 in FIG. 3B .
  • the first-stage first shift register GOA0 in the gate driving circuit 50 is electrically connected to the first clock signal line GCK and the second clock signal line GCB, so that the first clock signal line GCK and the second clock signal line
  • the gate driving signal GATE1 for the sub-pixels in the first row is generated under the control of the GCB, which is also used as the reset signal RST2 in FIG. 3B .
  • the display substrate may further include a plurality of light emission control lines EM1 , EM2 , . . . , EMn and a light emission control driving circuit 60 .
  • a plurality of light emission control lines EM1, EM2, . . . , EMn pass through the display area 10 and extend along the second direction (x direction).
  • the plurality of light emission control lines EM1 , EM2 , . . . , EMn are electrically connected to the plurality of sub-pixels P.
  • the emission control line EM1 is electrically connected to the sub-pixels P1 in the first row
  • the emission control line EM2 is electrically connected to the sub-pixels P2 in the second row, and so on.
  • the light emission control driving circuit 60 is located in the peripheral area 11 and is located on the side of the gate driving circuit 50 away from the display area 10 .
  • the light emission control driving circuit 60 includes multi-stage cascaded second shift registers EOA0, EOA1, . . .
  • the 0th stage second shift register EOA0 is connected to the light emission control lines EM1 and EM2 , so as to provide light-emitting control signals to the first row of sub-pixels P1 and the second row of sub-pixels P2, respectively, and the first-stage second shift register EOA1 is connected to the light-emitting control lines EM3 and EM4 to respectively provide the third row of sub-pixels P3 and EM4.
  • the fourth row of sub-pixels P4 provides light emission control signals.
  • the number of second shift registers may be one-half the number of first shift registers .
  • the embodiments of the present disclosure are not limited to this, and the number and cascading manner of the first shift register and the second shift register can be set as required.
  • a second start-up voltage signal line ESTV, a third clock signal line ECK, and a fourth clock signal line ECB may also be arranged in the peripheral region 11.
  • the light emission control driving circuit 60 is also electrically connected to the second start voltage signal line ESTV, the third clock signal line ECK and the fourth clock signal line ECB, so as to generate light emission control signals under its control.
  • the 0th stage second shift register EOA0 in the light emission control driving circuit 60 is electrically connected to the second start voltage signal line ESTV, the third clock signal line ECK and the fourth clock signal line ECB so that the second start voltage signal line is
  • the light emission control signals for the sub-pixels P1 in the first row and the sub-pixels P2 in the second row are generated under the control of the line ESTV, the third clock signal line ECK and the fourth clock signal line ECB.
  • the first-stage second shift register EOA1 in the light emission control driving circuit 60 is electrically connected to the third clock signal line ECK and the fourth clock signal line ECB so that the third clock signal line ECK and the fourth clock signal line Under the control of the ECB, the emission control signals for the sub-pixels P2 in the second row and the sub-pixels P3 in the third row are generated.
  • FIG. 4A shows a structural diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 4B shows an enlarged view of the area indicated by the dashed box AA in FIG. 4A.
  • the display substrate 400 includes a base substrate 1 , and the base substrate 1 includes a display area 10 and a peripheral area 11 surrounding the display area 10 .
  • a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines may be arranged in the display area 10 in the manner described above with reference to FIGS. 3A and 3B .
  • a gate driving circuit and a plurality of gate lines such as the gate driving circuit 50 and a plurality of gate lines GATE1 , GATE2 , . . . , GATEn described above with reference to FIGS.
  • the driving circuit 50 includes a plurality of first shift registers GOA0, GOA1, . . . , GOAn cascaded in multiple stages.
  • the first start voltage signal line GSTV, the first clock signal line GCK, and the second clock signal line GCB connected to the gate driving circuit may also be arranged in the peripheral region 11 in the manner described above with reference to FIGS. 3A and 3B .
  • a plurality of first pins and a plurality of second pins may be provided in the peripheral area 11, and the plurality of second pins are located between the display area 10 and the plurality of first pins.
  • the plurality of first pins may be disposed in the first pin area 20 as described above with reference to FIGS. 2A to 2D
  • the plurality of second pins may be as described above with reference to FIGS. 2A to 2D .
  • the way is set in the second pin area 30 .
  • a plurality of first array test pins PIN1 and a plurality of second array test pins PIN2 may also be provided in the peripheral area 11 .
  • the multiple first array test pins PIN1 and the multiple second array test pins PIN2 are located between the area 20 where the multiple first pins are located and the area 30 where the multiple second pins are located. between.
  • the plurality of second array test pins PIN2 extend along the boundary direction of the display area 10, and the plurality of first array test pins PIN1 are located in the plurality of second array test pins along the extension direction along the boundary of the display area 10. at least one side of pin PIN2.
  • the plurality of first array test pins PIN1 are respectively electrically connected to a plurality of array test signal lines, and the plurality of array test signal lines include a first start-up voltage signal line GSTV, a first clock signal line GCK and a second clock signal line At least one of the GCBs.
  • the plurality of array test signal lines may include a first start-up voltage signal line GSTV, a first clock signal line GCK and a second clock signal line GCB, which are respectively associated with the plurality of first array test leads Pin PIN1 is electrically connected.
  • the plurality of second array test pins PIN2 are respectively electrically connected to a plurality of data lines DATA1, DATA2, . . . , DATAk, and the plurality of second array test pins PIN2 can pass through the plurality of data lines DATA1, DATA2, . , DATAk receives array test data signals from a plurality of sub-pixels in the display area 10 .
  • the display area 10 includes a first border 101, a second border 102, a third border 103, and a fourth border 104 (eg, a lower border, an upper border, a left border, and a right border) connected in sequence, and the plurality of first borders
  • a fourth border 104 eg, a lower border, an upper border, a left border, and a right border
  • An array of test pins PIN1 and the plurality of second array test pins PIN2 are located in the peripheral region 11 close to the first boundary (lower boundary).
  • the gate driving circuit may include a first sub-circuit and a second sub-circuit, the first sub-circuit and the second sub-circuit are located near the second boundary (left boundary) and the The peripheral area 11 of the fourth border (right border).
  • the first sub-circuit includes a group of first shift registers GOA0, GOA1, . . . , GOAn located on the left side of the display area 10
  • the second sub-circuit includes another group of first shift registers located on the right side of the display area 10. Shift registers GOA0, GOA1, ..., GOAn.
  • Each of the first start voltage signal line GSTV, the first clock signal line GCK, and the second clock signal line GCB may also be divided into two parts, which are respectively disposed on both sides of the display area 10 .
  • the first startup voltage signal line GSTV includes a first sub-line of the first startup voltage signal line and a second sub-line of the first startup voltage signal line located on the left and right sides of the display area 10 respectively.
  • the first clock The signal line GCK includes a first sub-line of the first clock signal line and a second sub-line of the first clock signal line respectively located on the left and right sides of the display area 10
  • the second clock signal line GCB includes a second sub-line of the first clock signal line located on the left and right sides of the display area 10 respectively.
  • the first sub-line of the first start-up voltage signal line, the first sub-line of the first clock signal line and the first sub-line of the second clock signal line located on the left side of the display area 10 are electrically connected to the first sub-circuit, and are located in the display area.
  • the second sub-line of the first startup voltage signal line, the second sub-line of the first clock signal line, and the second sub-line of the second clock signal line on the right side of the region 10 are electrically connected to the second sub-circuit.
  • the plurality of first array test pins PIN1 may include a first group of first array test pins and a second group of first array test pins, the first group of first array test pins and the second group of first array test pins
  • the first array test pins are respectively located on both sides of the plurality of second array test pins PIN2 along the extending direction of the first boundary.
  • the plurality of first array test pins PIN1 and the plurality of second array test pins PIN2 are set as described above with reference to FIG.
  • the plurality of second array test pins PIN2 are set In the first area 41
  • the plurality of first array test pins PIN1 are disposed in the second area 42 and the third area 43 respectively located on both sides of the first area 41 .
  • the first sub-line of the first start-up voltage signal line (indicated by GSTV in FIG. 4B ) and the first sub-line of the first clock signal line (indicated by GCK in FIG. 4B ) located on the left side of the display area 10 ) and the first sub-line of the second clock signal line (indicated by GCB in FIG. 4B ) are electrically connected to the first group of the first array test pins PIN1 in the second region 42 .
  • the second sub-line of the first start-up voltage signal line, the second sub-line of the first clock signal line, and the second sub-line of the second clock signal line located on the right side of the display area 10 are electrically connected to those in the third region 43 .
  • the second group of the first array test pins PIN1 will not be repeated here.
  • the peripheral region 11 of the display substrate 400 may further be provided with a light-emitting control driving circuit and a plurality of light-emitting control lines, such as the light-emitting control circuit 60 and the light-emitting control lines EM1 and EM2 described above with reference to FIGS. 3A and 3B . , ..., EMn.
  • the light emission control circuit 60 includes a plurality of second shift registers EOA0, EOA1, . . . , EOAm cascaded in multiple stages.
  • the peripheral region 11 may also have a second start voltage signal line ESTV, a third clock signal line ECK, and a fourth clock signal line ECB connected to the light emission control driving circuit arranged in the manner described above with reference to FIGS. 3A and 3B .
  • the light emission control driving circuit may electrically connect the second start voltage signal line ESTV, the third clock signal line ECK, and the fourth clock signal line ECB in the manner described above with reference to FIGS. 3A and 3B .
  • the plurality of array test signal lines may also include a second start voltage signal line ESTV, At least one of the third clock signal line ECK and the fourth clock signal line ECB.
  • the first start voltage signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, the second start voltage signal line ESTV, the third clock signal line ECK and the fourth clock signal line ECB are respectively connected with The six first array test pins PIN are electrically connected in one-to-one correspondence.
  • the lighting control driving circuit may also include a third sub-circuit and a fourth sub-circuit respectively located on both sides of the display area 10.
  • the third sub-circuit and the fourth sub-circuit may be located close to each other.
  • the peripheral area 11 of the second border (left border) and the fourth border (right border) of the area 10 is displayed.
  • the first sub-circuit of the light-emitting control driving circuit includes a group of second shift registers EOA0, EOA1, .
  • Each of the second start voltage signal line ESTV, the third clock signal line ECK, and the fourth clock signal line ECB may also be divided into two parts, which are respectively disposed on both sides of the display area 10 .
  • the second start-up voltage signal line ESTV includes a first sub-line of the second start-up voltage signal line ESTV and a second sub-line of the second start-up voltage signal line ESTV located on the left and right sides of the display area 10 respectively.
  • the clock signal line ECK includes the first sub-line of the third clock signal line and the second sub-line of the third clock signal line respectively located on the left and right sides of the display area 10
  • the fourth clock signal line ECB includes the second sub-line of the third clock signal line located on the left and right sides of the display area 10 respectively.
  • Four clock signal lines are the first sub-line and the fourth clock signal line is the second sub-line.
  • the first sub-line of the second start-up voltage signal line, the first sub-line of the third clock signal line, and the first sub-line of the fourth clock signal line located on the left side of the display area 10 are electrically connected to the first sub-circuit of the light-emitting control driving circuit, located in The second sub-line of the second start-up voltage signal line, the second sub-line of the third clock signal line and the second sub-line of the fourth clock signal line on the right side of the display area 10 are electrically connected to the second sub-circuit of the lighting control driving circuit.
  • the first sub-line of the second start-up voltage signal line (indicated by ESTV in FIG. 4B ) and the first sub-line of the third clock signal line (indicated by ECK in FIG. 4B ) located on the left side of the display area 10 ) and the first sub-line of the fourth clock signal line (indicated by ECB in FIG. 4B ) are electrically connected to the first group of the first array test pins PIN1 in the second region 42 .
  • the second sub-line of the second start-up voltage signal line, the second sub-line of the third clock signal line, and the second sub-line of the fourth clock signal line located on the right side of the display area 10 are electrically connected to those in the third region 43 .
  • the second group of the first array test pins PIN1 will not be repeated here.
  • At least a part of the array test signal lines of the plurality of array test signal lines may be connected to a part of the second pins of the plurality of second pins in a one-to-one correspondence, and the part of the second pins
  • the plurality of first connection lines are connected to at least a part of the first array test pins of the plurality of first array test pins in a one-to-one correspondence. As shown in FIG.
  • the plurality of array test signal lines include a first start voltage signal line GSTV, a first clock signal line GCK, a second clock signal line GCB, a second start voltage signal line ESTV, a third clock signal line ECK and
  • the fourth clock signal lines ECB are respectively connected with the six second pins OUT in one-to-one correspondence.
  • the six second pins OUT are respectively connected to the six first array test pins PIN through the six first connection wires W1 in a one-to-one correspondence.
  • a plurality of connection pins may also be provided in the peripheral area 11 of the display substrate 400 , and the plurality of first pins located in the first pin area 20 may be connected with all connection pins.
  • the plurality of connection pins FOP are electrically connected so as to be connected to the flexible circuit board.
  • FIG. 5A shows a structural diagram of a display substrate according to another embodiment of the present disclosure.
  • 5B shows a circuit diagram of a multiplexing circuit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 5C shows an enlarged view of the area indicated by the dashed box BB in FIG. 5A .
  • the display substrate 500 of FIGS. 5A to 5C is similar to the display substrate 400 of FIGS. 4A to 4B , and the difference is at least that the display substrate 500 further includes a multiplexing circuit MUX.
  • the different parts are mainly described in detail below.
  • the peripheral region 11 of the display substrate 500 is further provided with a multiplexing circuit MUX and a first selection signal line MUX1 and a second selection signal line MUX2 .
  • the multiplexing circuit MUX is located between the plurality of second pins (second pin regions 30 ) and the display region 11 . As shown in FIG. 5B, the multiplexing circuit MUX includes multiple multiplexing switches M1, M2, . . . at least one multiplexing switch in the multiple multiplexing switches M1, M2, . Two transistors T2. The gate of the first transistor T1 is electrically connected to the first selection signal line MUX1, and the gate of the second transistor T2 is electrically connected to the second selection signal line MUX2. The first poles of the first transistor T1 and the second transistor T2 are connected to one second pin, and the second pole of the first transistor T1 and the second pole of the second transistor T2 are respectively connected to two data signal lines.
  • the plurality of array test signal lines may further include a first selection signal line MUX1 and a second selection signal line MUX2.
  • the first array test pin PIN1 is connected to the first start voltage signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, the second start voltage signal line ESTV, the third clock signal line
  • the plurality of first array test pins PIN1 electrically connected to the signal line ECK and the fourth clock signal line ECB there are also a plurality of first array test pins PIN1 electrically connected to the first selection signal line MUX1 and the second selection signal line MUX2. connect.
  • the first selection signal line MUX1 and the second selection signal line MUX2 are respectively connected to the two second pins OUT in one-to-one correspondence, and the two second pins OUT are respectively connected through the two first connection lines W1 Connect with the two first array test pins PIN1 in one-to-one correspondence.
  • each of the first selection signal line MUX1 and the second selection signal line MUX2 may include two parts, which are located on both sides of the display area 10, respectively.
  • the first selection signal line MUX1 includes a first sub-line of the first selection signal line located on the left side of the display area 10 and a second sub-line of the first selection signal line located on the right side of the display area 10
  • the second selection signal line MUX2 includes a line located on the right side of the display area 10.
  • the first sub-line of the second selection signal line on the left side of the display area 10 and the second sub-line of the second selection signal line on the right side of the display area 10 As shown in FIG. 5A and FIG.
  • the first group of the first array test pins PIN1 and the first sub-line of the first selection signal line (represented by MUX1 in FIG. 5C ) located in the second area 42 and the second selection signal line
  • the first sub-line of the signal line (indicated by MUX2 in FIG. 5C ) is electrically connected.
  • the second group of the first array test pins located in the third region 43 are electrically connected to the second sub-line of the first selection signal line and the second sub-line of the second selection signal line, which will not be repeated here.
  • FIG. 6A shows a structural diagram of a display substrate according to another embodiment of the present disclosure.
  • 6B illustrates a circuit diagram of a unit test circuit and a multiplexing circuit in a display substrate according to an embodiment of the present disclosure.
  • FIG. 6C shows a partial enlarged view of the area indicated by the dashed box CC in FIG. 6A.
  • the display substrate 600 of FIGS. 6A to 6C is similar to the display substrate 500 of FIGS. 5A to 5C , and the difference is at least that the display substrate 600 further includes a unit test circuit CT.
  • the different parts are mainly described in detail below.
  • the peripheral region 11 of the display substrate 500 is further provided with a unit test circuit CT, a first switch signal line SWR, a second switch signal line SWG, a third switch signal line SWB and a fourth switch signal line Line SWD.
  • the unit test circuit CT may include a first unit test circuit CT1 and a second unit test circuit CT2.
  • the first unit test circuit CT1 is located between the plurality of second pins (the second pin area 30 ) and the display area 10
  • the second unit test circuit CT2 is located between the plurality of second pins (the second pin area 30 ) and the display area 10 . Between the first unit test circuit CT1.
  • the first unit test circuit CT1 includes a plurality of first test sub-circuits, at least one of the plurality of first test sub-circuits includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5,
  • the gate of the third transistor T3 is electrically connected to the first switch signal line SWR
  • the gate of the fourth transistor T4 is electrically connected to the second switch signal line SWG
  • the gate of the fifth transistor T5 is electrically connected to the third switch Signal line SWB.
  • the first electrode of the third transistor T4 is electrically connected to the first unit test signal line DR
  • the first electrode of the fourth transistor T4 is electrically connected to the second unit test signal line DG
  • the first electrode of the fifth transistor T5 is electrically connected to the first unit test signal line DG.
  • the second electrode of the third transistor T3, the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5 are electrically connected to the three data signal lines DATA1, DATA2 and DATA3, respectively.
  • the second unit test circuit CT2 includes a plurality of second test sub-circuits, at least one of the plurality of second test sub-circuits includes a sixth transistor T6 whose gate is electrically connected to The fourth switch signal line SWD.
  • the first electrode of the sixth transistor is connected to the fourth unit test signal line.
  • the first pole of the sixth transistor T6 in the first second array test sub-circuit on the left is electrically connected to the fourth unit test signal line D1
  • the sixth transistor in the second array test sub-circuit is electrically connected to the fourth unit test signal line D1.
  • the first pole of is electrically connected to the fourth unit test signal line D2, and so on.
  • the second poles of the sixth transistors T6 in each of the second test sub-circuits are electrically connected to the plurality of data signal lines DATA1, DATA2, . . . respectively.
  • the plurality of array test signal lines of the display substrate 600 further include a first switch signal line SWR, a second switch signal line SWG, a third switch signal line SWB and a fourth switch signal at least one of the lines SWD.
  • a first switch signal line SWR a first switch signal line SWR
  • a second switch signal line SWG a second switch signal line SWG
  • a third switch signal line SWB a fourth switch signal at least one of the lines SWD.
  • the first array test pin PIN1 is connected to the first start voltage signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, the second start voltage signal line ESTV, the third clock signal line
  • the plurality of first array test pins PIN1 electrically connected to the line ECK, the fourth clock signal line ECB, the first selection signal line MUX1 and the second selection signal line MUX2
  • another part of the array test signal lines in the plurality of array test signal lines is tested through the plurality of second connecting lines W2 and another part of the first array test pins PIN1 of the plurality of first array test pins
  • the pins PIN1 are connected in one-to-one correspondence.
  • the first switch signal line SWR, the second switch signal line SWG, the third switch signal line SWB and the fourth switch signal line SWD pass through four second connection lines W2 and four first array test pins respectively. PIN1 one-to-one electrical connection.
  • Each of the first switch signal line SWR, the second switch signal line SWG, the third switch signal line SWB, and the fourth switch signal line SWD includes two parts, which are respectively located on both sides of the display area 10 .
  • the first switch signal line SWR, the second switch signal line SWG, the third switch signal line SWB, and the fourth switch signal line SWD includes two parts, which are respectively located on both sides of the display area 10 .
  • the first switch signal line SWR includes a first sub-line of the first switch signal line and a second sub-line of the first switch signal line respectively located on the left and right sides of the display area 10
  • the second switch signal line SWG includes two respectively located on the left and right sides of the display area 10 .
  • the first sub-line of the second switch signal line and the second sub-line of the second switch signal line on the side, the third switch signal line SWB includes the first sub-line and the third sub-line of the third switch signal line respectively located on the left and right sides of the display area 10
  • the second sub-line of the switch signal line, the fourth switch signal line SWD includes the first sub-line of the fourth switch signal line and the second sub-line of the fourth switch signal line located on the left and right sides of the display area 10 respectively.
  • the second sub-line of the first switch signal line, the second sub-line of the second switch signal line, the second sub-line of the third switch signal line and the second sub-line of the fourth switch signal line located on the right side of the display area 10
  • the wires are electrically connected to four first array test pins PIN1 in the second group of first array test pins PIN1 in the third area 43 .
  • FIG. 7A shows a structural diagram of a display substrate according to another embodiment of the present disclosure.
  • 7B shows a schematic diagram of a first power bus and a first power line in a display substrate according to an embodiment of the present disclosure.
  • FIG. 7C shows a partial enlarged view of the area indicated by the dotted line DD in FIG. 7A .
  • the display substrate 700 of FIGS. 7A to 7C is similar to the display substrate 500 of FIGS. 6A to 6C , except that the display substrate 700 further includes a first power bus VDD. For the sake of brevity, the difference will be described in detail below.
  • the display substrate 700 further includes a plurality of first power supply lines VD located in the display area 10 and a first power supply located in the peripheral area 11 close to the first boundary (lower boundary) of the display area 10
  • the bus VDD, the plurality of first power lines VD are electrically connected to the first power bus VDD.
  • each column of sub-pixels P is electrically connected to a first power supply line VD, and a plurality of first power supply lines VD electrically connected to the plurality of columns of sub-pixels P are drawn out from the display area 10 to connect to the first power supply bus VDD located in the peripheral area 11 .
  • the plurality of array test signal lines further include a first power bus VDD, in addition to being connected to the first start-up voltage signal line GSTV and the first clock signal respectively.
  • first selection signal line MUX1, second selection signal line MUX2 In addition to the plurality of first array test pins PIN1 electrically connected to the line SWR, the second switch signal line SWG, the third switch signal line SWB and the fourth switch signal line SWD, there are at least one first array test pin PIN1 and The first power bus VDD is connected.
  • the first switch signal line SWR, the second switch signal line SWG, the third switch signal line SWB, the fourth switch signal line SWD and the first power bus VDD pass through five second connection lines W2 and five third An array of test pins PIN1 are electrically connected in one-to-one correspondence.
  • the first power bus VDD may include a first sub-line of the first power bus and a second sub-line of the first power bus.
  • the first power bus VDD may include a first portion extending in a horizontal direction and two second portions extending in a vertical direction, and the two second portions are respectively located on the left and right sides of the display substrate 700 . side.
  • the second part on the left side can be used as the first sub-line of the first power bus, and the second part on the right side can be used as the second sub-line of the first power bus.
  • the first sub-line of the first power bus on the left side (represented by VDD in FIG. 7C ) is electrically connected to the first group of first array test pins PIN1 located in the second region 42 .
  • the second sub-line of the first power bus located on the right side is electrically connected to the second group of the first array test pins PIN1 located in the third area 43 , which will not be repeated here.
  • FIG. 8A shows a structural diagram of a display substrate according to another embodiment of the present disclosure.
  • FIG. 8B shows a schematic diagram of an initial voltage signal bus line and an initial voltage signal line in a display substrate according to an embodiment of the present disclosure.
  • FIG. 8C shows a partial enlarged view of the area indicated by the dashed box EE in FIG. 8A .
  • the display substrate 800 of FIGS. 8A to 8C is similar to the display substrate 700 of FIGS. 7A to 7C , except that the display substrate 800 further includes the initial voltage signal bus Vinit. For the sake of brevity, the difference will be mainly described in detail below.
  • the display substrate 800 further includes a plurality of initial voltage signal lines VI located in the display area 10 and an initial voltage signal bus Vinit located in the peripheral area 11 .
  • the initial voltage signal bus Vinit is located between the gate driving circuits ( GOA0 , GOA1 , . . . , GOAn ) and the display area 10 .
  • GOA0 , GOA1 , . . . , GOAn the gate driving circuits
  • each row of sub-pixels P is electrically connected to an initial voltage signal line VI, and a plurality of initial voltage signal lines VI that are respectively electrically connected to the sub-pixels P of the rows are drawn out from the display area 10 , thereby Connected to the initial voltage signal bus Vinit located in the peripheral area 11 .
  • the plurality of array test signal lines further include an initial voltage signal bus Vinit.
  • the first start voltage signal line GSTV the first clock signal line GCK, the second clock signal line GCB, the second start voltage signal line ESTV, the third clock signal line ECK, the fourth clock signal line line ECB, first selection signal line MUX1, second selection signal line MUX2, first switch signal line SWR, second switch signal line SWG, third switch signal line SWB, fourth switch signal line SWD, and first power bus VDD
  • at least one first array test pin PIN1 is electrically connected to the initial voltage signal bus Vinit.
  • the initial voltage signal bus Vinit is electrically connected to a second pin OUT
  • the second pin OUT is electrically connected to a first array test pin PIN1 through a first connection wire W1.
  • the initial voltage signal bus Vinit may include a first sub-line of the initial voltage signal bus and a second sub-line of the initial voltage signal bus, the initial voltage signal bus first sub-line and the second sub-line of the initial voltage signal bus are respectively located in the peripheral area 11 near the second boundary (left boundary) of the display area 10 and the fourth boundary (right boundary) of the display area 10 .
  • the first sub-line of the initial voltage signal bus (indicated by Vinit in FIG. 8C ) located on the left side of the display area 10 is electrically connected to the first group of first array test pins PIN1 located in the second area 42 .
  • the second sub-line of the initial voltage signal bus is electrically connected to the second group of the first array test pins PIN1 located in the third region 43 , which will not be repeated here.
  • 9A shows a schematic diagram of an electrostatic discharge circuit in a display substrate according to an embodiment of the present disclosure.
  • 9B shows a circuit diagram of an electrostatic discharge unit of an electrostatic protection circuit according to an embodiment of the present disclosure.
  • the electrostatic discharge circuit of FIGS. 9A and 9B may be applied to the display substrate of any of the above-mentioned embodiments.
  • the display substrate further includes an electrostatic discharge circuit
  • the electrostatic discharge circuit includes a plurality of electrostatic discharge units ESD1 , ESD2 , . . . , ESDh.
  • a plurality of electrostatic discharge units ESD1, ESD2, . . . , ESDH are located between the plurality of first array test pins PIN1 and the plurality of second pins in the second pin area 30 and are connected with the plurality of first array test pins PIN1
  • the test pins PIN1 are connected in one-to-one correspondence.
  • ESDh includes a seventh transistor T7 and an eighth transistor T8, the gate and first electrode of the seventh transistor are connected to the high voltage signal line VGH, The gate and second electrode of the eighth transistor are connected to the low voltage signal line VGL, the second electrode of the seventh transistor T7 and the gate and first electrode of the eighth transistor T8 are electrically connected to the first array Test pin PIN1.
  • the seventh transistor T7 is turned on to control the first array test pin PIN1 at the potential of the high voltage signal line VGH, thereby The high level is released through the seventh transistor T7.
  • the eighth transistor T8 When the low level of the signal on the first array test pin PIN1 is lower than the preset low level value, the eighth transistor T8 is turned on to control the first array test pin PIN1 at the potential of the low voltage signal line VGL, thereby The excessive low level is released through the eighth transistor T8.
  • FIG. 10A shows a layout diagram of a multiplexing switch in a multiplexing circuit according to an embodiment of the present disclosure.
  • a multiplexing switch includes a first transistor T1 and a second transistor T2 (as shown by the dotted box), wherein the first transistor T1 and the second transistor T2 share a first pole of the transistor.
  • FIG. 10A shows a layout diagram of a multiplexing switch in a multiplexing circuit according to an embodiment of the present disclosure.
  • a multiplexing switch includes a first transistor T1 and a second transistor T2 (as shown by the dotted box), wherein the first transistor T1 and the second transistor T2 share a first pole of the transistor.
  • 210 denotes an active layer for forming the active regions of the first transistor T1 and the second transistor T2, and K1 denotes the first electrode of the first transistor T1 and the second transistor T2 that are electrically connected together
  • the first pole, K2 represents the gate of the first transistor T1
  • K3 represents the gate of the second transistor T2
  • K4 represents the second pole of the first transistor T1
  • K5 represents the second pole of the second transistor T2.
  • the first control line MUX1 extends in the horizontal direction and is electrically connected to K2
  • the second control line MUX2 is arranged in the horizontal direction and is electrically connected to K3.
  • the lead 220 is electrically connected to K1 for electrically connecting the first electrode of the first transistor T1 and the first electrode of the second transistor T2 to a pin (eg, a second pin) of the chip for outputting data signals.
  • the lead 230 is electrically connected to K4 for sending the data signal received by the first transistor T1 to the data line in the display area.
  • the lead 240 is electrically connected to K5 for sending the data signal received by the second transistor T2 to the data line in the display area.
  • Figure 10B shows a cross-sectional view taken along line HH' in Figure 10A.
  • a buffer layer 211 a first gate insulating layer 212 , a second gate insulating layer 213 , an interlayer insulating layer 214 , a passivation layer 215 and a first planarization layer are sequentially stacked on the base substrate 1 216.
  • the active layer 210 is located between the buffer layer 211 and the first gate insulating layer 212 .
  • the gate K2 of the first transistor T1 and the gate K3 of the second transistor T2 are located between the first gate insulating layer 212 and the second gate insulating layer 213 .
  • the first electrode K1 shared by the first transistor T1 and the second transistor T1 , the second electrode K4 of the first transistor T1 and the second electrode K5 of the second transistor T2 are located between the interlayer insulating layer 214 and the passivation layer 215 .
  • the second electrode K4 of the first transistor T1 and the second electrode K5 of the second transistor T2 are respectively connected to the active layer 210 through via holes, and the via holes pass through the first gate insulating layer 212 and the second gate insulating layer 213 in turn. and the interlayer insulating layer 214 .
  • the active layer 210 for forming the active regions of the first transistor T1 and the second transistor T2 and the driving active layer of the driving thin film transistor included in at least one sub-pixel P of the plurality of sub-pixels P in the above-mentioned display area 10 on the same level.
  • the gate K2 of the first transistor T1 and the gate K3 of the second transistor T2 are located in the same layer as the driving gate of the driving thin film transistor included in at least one sub-pixel P of the plurality of sub-pixels P in the display area 10 .
  • the driving source and the driving drain of the driving thin film transistor included in the pixel P are located in the same layer.
  • FIG. 11A shows a layout diagram of a first array test circuit according to an embodiment of the present disclosure.
  • the first unit test circuit CT1 includes a plurality of first test sub-circuits, each of the first test sub-circuits includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5, wherein the third transistor T3 has The gate is electrically connected to the first switch signal line SWR, the gate of the fourth transistor T4 is electrically connected to the second switch signal line SWG, and the gate of the fifth transistor T5 is electrically connected to the third switch signal line SWB.
  • the first electrode of the third transistor T4 is electrically connected to the first unit test signal line DR
  • the first electrode of the fourth transistor T4 is electrically connected to the second unit test signal line DG
  • the first electrode of the fifth transistor T5 is electrically connected to the first unit test signal line DG.
  • the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 are electrically connected to one data line DATA1
  • the second electrode of the fifth transistor T5 is electrically connected to another data line DATA2.
  • DATA1 and DATA2 are only used to represent two different data lines, and are not intended to limit the arrangement order of the data lines.
  • FIG. 11B shows a layout diagram of a second array test circuit according to an embodiment of the present disclosure.
  • the second unit test circuit CT2 includes a plurality of second test sub-circuits, each of the second test sub-circuits includes a sixth transistor T6, and the gate of the sixth transistor T6 is electrically connected to the fourth switch signal line SWD .
  • the first pole of the sixth transistor T6 in the first second array test sub-circuit on the left is electrically connected to the fourth unit test signal line D1
  • the sixth transistor in the second array test sub-circuit has its first pole electrically connected to the fourth unit test signal line D1.
  • the first electrode is electrically connected to the fourth unit test signal line D2, and so on.
  • the second poles of the sixth transistors T6 in each of the second test sub-circuits are electrically connected to the plurality of data signal lines DATA1, DATA2, . . . respectively.
  • the electrostatic discharge circuit includes a plurality of electrostatic discharge units ESD, and one of the electrostatic discharge units is marked with a dotted frame in FIG. 12 .
  • the electrostatic discharge unit ESD is electrically connected to the plurality of first array test pins PIN1.
  • the plurality of first array test pins PIN1 are the first array test pins PIN1 used for electrical connection with VDD, Vinit, ESTV, ECB, ECK, GSTV, and GCB in sequence from left to right, and the first array test pins PIN1 are used for electrical connection with VDD, Vinit, ESTV, ECB, ECK, GSTV and GCB.
  • the two first array test pins electrically connected to Vinit are not connected to the electrostatic discharge unit.
  • a plurality of redundant array test pins Dummy are also shown in FIG. 12, and the redundant array test pins Dummy are not electrically connected with other circuit structures in the display substrate, so that the first area 41, the second area 42 and the The number and arrangement of the respective pins of the three regions 43 can be set as required.
  • the layout of the array detection pins on the array substrate is easier to match with the pin layout of the detection equipment, so as to achieve a good connection; on the other hand, the number of pins in the second area 42 and the third area 43 can be equal, thereby improving the symmetry of the pin layout.
  • setting the redundant array test pin Dummy is also beneficial to improve process uniformity.
  • at least some of the redundant array test pins Dummy are also each connected to ESD cells.
  • the electrostatic discharge unit ESD includes four transistors connected in series, that is, in addition to the seventh transistor T7 and the eighth transistor T8 described above, may also include another two transistors T7' and T8'.
  • the gate and first pole of the transistor T7' are connected to the high voltage signal line VGH, the second pole of the transistor T7' is connected to the gate and the first pole of the seventh transistor T7; the second pole of the transistor T8' is connected to the low voltage signal On the line VGL, the gate and first electrode of the transistor T8' are connected to the second electrode of the eighth transistor T8; the second electrode of the seventh transistor T7 and the gate and first electrode of the eighth transistor T8 are electrically connected to the second electrode of the eighth transistor T8.
  • FIG. 13 shows a schematic diagram of a pixel structure according to an embodiment of the present disclosure. As shown in FIG. 13 , at least one of the plurality of sub-pixels in the display substrate includes a driving thin film transistor and a storage capacitor.
  • the driving thin film transistor may include a driving active layer P-Si located on a base substrate, a driving gate GATE located on a side of the driving active layer P-Si away from the base substrate, and a driving gate GATE located away from the base substrate
  • the gate insulating layer GI2 (second gate insulating layer) on one side, the interlayer dielectric layer ILD on the side of the gate insulating layer GI2 away from the base substrate, and the driver on the side of the interlayer dielectric layer ILD away from the base substrate source and drive drain SD1.
  • the storage capacitor may include a first capacitor electrode ED1 and a second capacitor electrode ED2, the first capacitor electrode ED1 and the driving gate GATE are located on the same layer, and the second capacitor electrode ED2 is located on the gate insulating layer GI2 and the interlayer dielectric layer ILD. between.
  • the sub-pixel may further include a first gate insulating layer GI1, a blocking layer BUF, a passivation layer PVX, a flat layer PLN1, a pixel defining layer PDL, a light blocking layer PS, an anode 1301, a light emitting layer 1302, a cathode 1303, a first inorganic layer
  • the encapsulation layer 1304 , the organic encapsulation layer 1305 and the second inorganic encapsulation layer 1306 .
  • the blocking layer BUF is located between the base substrate 1 and the driving active layer P-Si.
  • the first gate insulating layer GI1 is located on the side of the blocking layer BUF away from the base substrate 1, so that the driving active layer P-Si is located between the first gate insulating layer GI1 and the blocking layer BUF.
  • the passivation layer PVX is located on the side of the interlayer dielectric layer ILD away from the base substrate 1 .
  • the flat layer PLN1 is located on the side of the passivation layer PVX away from the base substrate 1 .
  • the anode 1301 is located on the side of the flat layer PLN1 away from the base substrate and is electrically connected to the driving source or the driving drain SD1 through the flat layer PLN1 and the passivation layer PVX.
  • the pixel defining layer PDL is located on the side of the flat layer PNL1 away from the base substrate 1 and partially covers the anode 1301 .
  • the light blocking layer PS is located on the side of the pixel defining layer PDL away from the base substrate 1 and partially covers the pixel defining layer PDL.
  • the light emitting layer 1302 partially covers the anode 1301, the pixel defining layer PDL and the light blocking layer PS.
  • the cathode 1303 is located on the side of the light emitting layer 1302 away from the base substrate 1 .
  • the cathode 1303 is disposed on the first inorganic encapsulation layer 1304 , the organic encapsulation layer 1305 and the second inorganic encapsulation layer 1306 in sequence on the side of the cathode 1303 away from the base substrate 1 .
  • At least one of the plurality of first array test pins PIN1 and the plurality of second array test pins PIN2 in the above embodiment can be connected with the driving source and driving drain of the plurality of sub-pixels in the display area.
  • SD1 is on the same floor.
  • the plurality of first connection lines W1 in the above embodiment may be located in the same layer as the driving source electrodes and the driving drain electrodes SD1 of the plurality of sub-pixels in the display area.
  • each of the plurality of second connection lines W2 is partially located in the same layer as the driving source electrode and the driving drain electrode SD1 of the plurality of sub-pixels in the display area, and is partially The driving gates GATE of the plurality of sub-pixels in the display area are located in the same layer.
  • the display substrate of the embodiment of the present disclosure may further include an anisotropic conductive film ACF covering the plurality of first array test pins and the plurality of second array test pins.
  • Embodiments of the present disclosure also provide a display panel, including the display substrate of any of the foregoing embodiments.
  • FIG. 14 shows a flowchart of a method of manufacturing a display substrate according to an embodiment of the present disclosure.
  • a display area and a peripheral area surrounding the display area are formed on a base substrate.
  • the display area and the peripheral area can be set in the manner of any of the above-mentioned embodiments.
  • a plurality of sub-pixels, a plurality of data lines and a plurality of gate lines may be arranged in the display area according to the method in the above-mentioned embodiment, and the first scanning gate driving circuit, a first startup voltage signal line, a first clock signal line, a second clock signal line, a plurality of first pins, a plurality of second pins, a plurality of first array test pins, and a plurality of second array test pins .
  • step S102 a protective layer covering the plurality of first array test pins and the plurality of second array test pins is formed, and the protective layer includes but is not limited to an anisotropic conductive film.

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Abstract

本公开的实施例提供了一种显示基板和显示面板。所述显示基板包括衬底基板，所述衬底基板包括显示区域和围绕所述显示区域的周边区域；多个子像素、多条数据线和多条栅极线，位于显示区域中；栅极驱动电路、第一启动电压信号线、第一时钟信号线、第二时钟信号线、多个第一引脚和多个第二引脚，位于周边区域；多个第一阵列测试引脚，位于所述多个第一引脚和所述多个第二引脚之间，所述多个第一阵列测试引脚分别电连接至多条阵列测试信号线；多个第二阵列测试引脚，位于所述多个第一引脚和所述多个第二引脚之间且沿显示区域边界方向延伸，所述多个第一阵列测试引脚在沿显示区域边界的延伸方向上位于所述多个第二阵列测试引脚的至少一侧。

Description

显示基板及其制造方法以及显示面板 技术领域
本公开涉及显示技术领域，具体涉及一种显示基板、显示基板的制造方法以及显示面板。
背景技术
通常，在显示面板在制造过程中或者在制造完成后会进行各种测试，例如对显示面板的阵列基板进行阵列测试(AT，Array Test)，以确保产品质量。
发明内容
本公开的实施例提供了一种显示基板，包括：
衬底基板，包括显示区域和围绕所述显示区域的周边区域；
多个子像素，位于所述显示区域中；
多条数据线，位于所述显示区域中且沿第一方向延伸，所述多条数据线电连接至所述多个子像素；
多条栅极线，位于所述显示区域中且沿第二方向延伸，所述第一方向和所述第二方向交叉，所述多条栅极线电连接至所述多个子像素；
栅极驱动电路，位于所述周边区域，所述栅极驱动电路与所述多条栅极线电连接；
第一启动电压信号线、第一时钟信号线和第二时钟信号线与所述栅极驱动电路电连接；
多个第一引脚，位于所述周边区域；
多个第二引脚，位于所述周边区域，且位于所述显示区域和所述多个第一引脚之间；
多个第一阵列测试引脚，位于所述多个第一引脚和所述多个第二引脚之间，所述多个第一阵列测试引脚分别电连接至多条阵列测试信号线，所述多条阵列测试信号线包括所述第一启动电压信号线、所述第一时钟信号线或所述第二时钟信号线中的至少一条；以及
多个第二阵列测试引脚，位于所述多个第一引脚和所述多个第二引脚之间且沿所 述显示区域边界方向延伸，所述多个第一阵列测试引脚在沿所述显示区域边界的延伸方向上位于所述多个第二阵列测试引脚的至少一侧，所述多个第二阵列测试引脚电连接至所述多条数据线，所述多个第二阵列测试引脚被配置为通过所述多条数据线从所述多个子像素接收阵列测试数据信号。
例如，所述多条阵列测试信号线包括所述第一启动电压信号线、所述第一时钟信号线和所述第二时钟信号线。
例如，所述显示区域包括依次连接的第一边界、第二边界、第三边界和第四边界，所述多个第一阵列测试引脚和所述多个第二阵列测试引脚位于靠近所述第一边界的所述周边区域；
所述栅极驱动电路包括第一子电路和第二子电路，所述第一子电路和所述第二子电路分别位于靠近所述第二边界和所述第四边界的所述周边区域；
所述第一启动电压信号线包括第一启动电压信号线第一子线和第一启动电压信号线第二子线，所述第一时钟信号线包括第一时钟信号线第一子线和第一时钟信号线第二子线，所述第二时钟信号线包括第二时钟信号线第一子线和第二时钟信号线第二子线，所述第一启动电压信号线第一子线、所述第一时钟信号线第一子线和所述第二时钟信号线第一子线位于靠近所述第二边界的所述周边区域，且电连接所述第一子电路，所述第一启动电压信号线第二子线、所述第一时钟信号线第二子线和所述第二时钟信号线第二子线位于靠近所述第四边界的所述周边区域，且电连接所述第二子电路；
所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚在沿所述第一边界的延伸方向上分别位于所述多个第二阵列测试引脚的两侧；
其中，所述第一启动电压信号线第一子线、所述第一时钟信号线第一子线和所述第二时钟信号线第一子线电连接所述第一组第一阵列测试引脚，所述第一启动电压信号线第二子线、所述第一时钟信号线第二子线和所述第二时钟信号线第二子线电连接所述第二组第一阵列测试引脚。
例如，所述显示基板还包括：
多条发光控制线，位于所述显示区域且沿所述第二方向延伸，所述多条发光控制线电连接至所述多个子像素；
发光控制驱动电路，位于所述周边区域且位于所述栅极驱动电路远离所述显示区域的一侧；
第二启动电压信号线、第三时钟信号线和第四时钟信号线，所述发光控制驱动电路电连接所述第二启动电压信号线、所述第三时钟信号线、所述第四时钟信号线，所述多条阵列测试信号线还包括所述第二启动电压信号线、第三时钟信号线或第四时钟信号线中的至少一条。
例如，所述多条阵列测试信号线还包括所述第二启动电压信号线、所述第三时钟信号线和所述第四时钟信号线。
例如，所述显示区域包括依次连接的第一边界、第二边界、第三边界和第四边界，所述多个第一阵列测试引脚和所述多个第二阵列测试引脚位于靠近所述第一边界的所述周边区域；
所述发光控制驱动电路包括第三子电路和第四子电路，多所述第三子电路和所述第四子电路分别位于靠近所述第二边界和所述第四边界的所述周边区域；
所述第二启动电压信号线包括第二启动电压信号线第一子线和第二启动电压信号线第二子线，所述第三时钟信号线包括第三时钟信号线第一子线和第三时钟信号线第二子线，所述第四时钟信号线第四时钟信号线第一子线和第四时钟信号线第二子线；
所述第二启动电压信号线第一子线、所述第三时钟信号线第一子线和所述第四时钟信号线第一子线位于靠近所述第二边界的所述周边区域，且电连接所述第三子电路，所述第二启动电压信号线第二子线、所述第三时钟信号线第二子线和所述第四时钟信号线第二子线位于靠近所述第四边界的所述周边区域，且电连接所述第四子电路；
所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多个第二阵列测试引脚的两侧；
其中，所述第二启动电压信号线第一子线、所述第三时钟信号线第一子线和所述第四时钟信号线第一子线电连接所述第一组第一阵列测试引脚，所述第二启动电压信号线第二子线、所述第三时钟信号线第二子线和所述第四时钟信号线第二子线电连接所述第二组第一阵列测试引脚。
例如，所述显示基板还包括：
第一选择信号线和第二选择信号线；以及
多路复用电路，位于所述多个第二引脚与所述显示区域之间，所述多路复用电路包括多个复用开关，所述多个复用开关中的至少一个复用开关包括第一晶体管和第二晶体管，所述第一晶体管的栅极电连接至所述第一选择信号线，所述第二晶体管的栅 极电连接至所述第二选择信号线；
其中，所述多条阵列测试信号线还包括所述第一选择信号线和所述第二选择信号线。
例如，所述第一选择信号线包括第一选择信号线第一子线和第一选择信号线第二子线，所述第二选择信号线包括第二选择信号线第一子线和第二选择信号线第二子线；
所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多个第二阵列测试引脚的两侧；
其中，所述第一选择信号线第一子线和所述第二选择信号线第一子线电连接所述第一组第一阵列测试引脚，所述第一选择信号线第二子线和所述第二选择信号线第二子线电连接所述第二组第一阵列测试引脚。
例如，所述显示基板还包括位于显示区域的多条初始电压信号线和位于所述周边区域的初始电压信号总线，所述初始电压信号总线位于所述栅极驱动电路和所述显示区域之间，所述多条阵列测试信号线还包括所述初始电压信号总线。
例如，所述初始电压信号总线包括初始电压信号总线第一子线和初始电压信号总线第二子线，所述初始电压信号总线第一子线和所述初始电压信号总线第二子线分别位于靠近所述第二边界和所述第四边界的所述周边区域；
所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多个第二阵列测试引脚的两侧；
其中，所述初始电压信号总线第一子线电连接至所述第一组第一阵列测试引脚，所述初始电压信号总线第二子线电连接至所述第二组第一阵列测试引脚。
例如，所述显示基板还包括位于显示区域的多条第一电源线和位于靠近所述第一边界的所述周边区域的第一电源总线，所述多条第一电源线和所述第一电源总线电连接，所述多条阵列测试信号线还包括所述第一电源总线。
例如，所述第一电源总线包括第一电源总线第一子线和第一电源总线第二子线，所述第一电源总线第一子线和所述第一电源总线第二子线分别位于靠近所述第一边界的所述周边区域；
所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多 个第二阵列测试引脚的两侧；
其中，所述第一电源总线第一子线电连接至所述第一组第一阵列测试引脚，所述第一电源总线第二子线电连接至所述第二组第一阵列测试引脚。
例如，所述显示基板还包括：
第一开关信号线、第二开关信号线、第三开关信号线和第四开关信号线；
第一单元测试电路，位于所述多个第二引脚和所述显示区域之间，所述第一单元测试电路包括多个第一测试子电路，所述多个第一测试子电路中的至少一个包括第三晶体管、第四晶体管和第五晶体管，所述第三晶体管的栅极电连接至所述第一开关信号线，所述第四晶体管的栅极电连接至所述第二开关信号线，所述第五晶体管的栅极电连接至所述第三开关信号线；
第二单元测试电路，位于所述多个第二引脚和所述第一单元测试电路之间，所述第二单元测试电路包括多个第二测试子电路，所述多个第二测试子电路中的至少一个包括第六晶体管，所述第六晶体管的栅极电连接至所述第四开关信号线；
其中，所述多条阵列测试信号线还包括所述第一开关信号线、所述第二开关信号线、所述第三开关信号线或所述第四开关信号线中的至少一条。
例如，所述多条阵列测试信号线还包括所述第一开关信号线、所述第二开关信号线、所述第三开关信号线和所述第四开关信号线。
例如，所述第一开关信号线包括第一开关信号线第一子线和第一开关信号线第二子线，所述第二开关信号线包括第二开关信号线第一子线和第二开关信号线第二子线，所述第三开关信号线包括第三开关信号线第一子线和第三开关信号线第二子线，所述第四开关信号线包括第四开关信号线第一子线和第四开关信号线第二子线；
所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多个第二阵列测试引脚的两侧；
所述第一开关信号线第一子线、所述第二开关信号线第一子线、所述第三开关信号线第一子线和所述第四开关信号线第一子线电连接至所述第一组第一阵列测试引脚，所述第一开关信号线第二子线、所述第二开关信号线第二子线、所述第三开关信号线第二子线和所述第四开关信号线第二子线电连接至所述第二组第一阵列测试引脚。
例如，所述多条阵列测试信号线中的至少一部分阵列测试信号线与所述多个第二引脚中的一部分第二引脚一一对应地连接，所述一部分第二引脚通过多条第一连接 线与所述多个第一阵列测试引脚中的至少一部分第一阵列测试引脚一一对应地连接。
例如，所述至少一部分阵列测试信号线包括所述第一启动电压信号线、所述第一时钟信号线、所述第二时钟信号线、第二启动电压信号线、第三时钟信号线、第四时钟信号线、第一选择信号线、第二选择信号线和初始电压信号总线。
例如，所述多条阵列测试信号线中的另一部分阵列测试信号线通过多条第二连接线与所述多个第一阵列测试引脚中的另一部分第一阵列测试引脚一一对应地连接。
例如，所述另一部分阵列测试信号线包括第一开关信号线、第二开关信号线、第三开关信号线、第四开关信号线和第一电源总线。
例如，所述显示基板还包括静电放电电路，所述静电放电电路包括多个静电放电单元，所述多个静电放电单元位于所述多个第一阵列测试引脚与所述多个第二引脚之间并且与所述多个第一阵列测试引脚一一对应地连接，其中，每个静电放电单元包括第七晶体管和第八晶体管，所述第七晶体管的栅极和第一极连接至高电压信号线，所述第八晶体管的第二极连接至低电压信号线，所述第七晶体管的第二极以及所述第八晶体管的栅极和第一极电连接至第一阵列测试引脚。
例如，所述多个第一阵列测试引脚和所述多个第二阵列测试引脚在沿所述显示区域边界的延伸方向上排列成一行或多行。
例如，所述多个子像素中的至少一个包含驱动薄膜晶体管和存储电容；
所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱动有源层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的栅绝缘层，位于所述栅绝缘层远离所述衬底基板一侧的层间介质层，以及位于所述层间介质层远离所述衬底基板一侧的驱动源极和驱动漏极；
所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极与所述驱动栅极位于同一层，所述第二电容电极位于所述栅绝缘层和所述层间介质层之间；
所述多个第一阵列测试引脚和所述多个第二阵列测试引脚中的至少一层与所述显示区域中的所述多个子像素的驱动源极和驱动漏极位于同一层。
例如，所述多条第一连接线与所述显示区域中的所述多个子像素的驱动源极和驱动漏极位于同一层。
例如，所述多条第二连接线中的每一条第二连接线部分与所述显示区域中的所述多个子像素的驱动源极和驱动漏极位于同一层，并且部分与所述显示区域中的所述多个子像素的驱动栅极位于同一层。
例如，所述显示基板还包括：各向异性导电膜，所述各向异性导电膜覆盖所述多个第一阵列测试引脚和所述多个第二阵列测试引脚。
本公开的实施例还提供了一种显示面板，包括上述显示基板。
附图说明
图1示出了根据本公开实施例的显示基板的示意图。
图2A至图2D示出了根据本公开实施例的显示基板的多个示例的示意图。
图3A示出了根据本公开实施例的显示基板的局部结构的示意图，其中示出了驱动电路的结构。
图3B示出了根据本公开实施例的显示基板的局部结构的示意图，其中示出了驱动电路的结构和显示区域的结构。
图4A示出了根据本公开一实施例的显示基板的结构图。
图4B示出了图4A的局部放大图。
图5A示出了根据本公开另一实施例的显示基板的结构图。
图5B示出了根据本公开实施例的显示基板中的多路复用电路的电路图。
图5C示出了图5A的局部放大图。
图6A示出了根据本公开另一实施例的显示基板的结构图。
图6B示出了根据本公开实施例的显示基板中的单元测试电路和多路复用电路的电路图。
图6C示出了图6A的局部放大图。
图7A示出了根据本公开另一实施例的显示基板的结构图。
图7B示出了根据本公开实施例的显示基板中的第一电源总线与第一电源线的示意图。
图7C示出了图7A的局部放大图。
图8A示出了根据本公开另一实施例的显示基板的结构图。
图8B示出了根据本公开实施例的显示基板中的初始电压信号总线与初始电压信号线的示意图。
图8C示出了图8A的局部放大图。
图9A示出了根据本公开实施例的显示基板中的静电放电电路的示意图。
图9B示出了根据本公开实施例的静电防护电路的静电放电单元的电路图。
图10A示出了根据本公开实施例的多路复用电路的布局图。
图10B示出了根据本公开实施例的多路复用电路的结构图。
图11A示出了根据本公开实施例的第一阵列测试电路的布局图。
图11B示出了根据本公开实施例的第二阵列测试电路的布局图。
图12示出了根据本公开实施例的静电放电电路的布局图。
图13示出了根据本公开实施例的像素结构的示意图。
图14示出了根据本公开实施例的显示基板的制造方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或配置。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“相连”或“连接至”可以是指两个组件直接连接，也可以是指两个组件之间经由一个或多个其他组件相连。此外，这两个组件可以通过有线或无线方式相连或相耦合。
显示面板的制造过程中，在形成其显示基板的电路结构之后，在显示基板上形成发光层之前，可以对显示基板上的电路结构进行阵列测试(AT，Array Test)，以确定显示基板的内部电路是否存在缺陷。相关技术中，在显示面板外部设有与显示面板连接的多个阵列测试引脚。通过这些阵列测试引脚，可以对显示面板内部的像素电路进行阵列测试。在阵列测试完成后，将阵列测试引脚从显示面板上去除，以便于在显示基板上形成显示层并安装驱动电路。但是这给显示面板的制造和测试带来不便。
本公开的实施例通过将用于阵列测试的阵列测试引脚设置在显示基板内部，一方面 使阵列测试引脚的设计不必受限于显示基板中用于与阵列测试引脚连接的引脚的布局，另一方面无需额外的步骤来去除阵列测试引脚，简化了制造流程，避免了去除测试引脚导致的电路短路或漏电。
图1示出了根据本公开实施例的显示基板的示意图。
如图1所示，显示基板100包括衬底基板，衬底基板包括显示区域10和围绕所述显示区域10的周边区域11。
显示区域10中设有多个子像素，所述多个子像素可以排列成阵列。
设有多个第一引脚的第一引脚区域20和设有多个第二引脚的第二引脚区域30位于周边区域11中，其中第二引脚区域30位于显示区域10和第一引脚区域20之间。
在第一引脚区域20与第二引脚区域30之间的区域(图1中由40表示)中设置有多个第一阵列测试引脚和多个第二阵列测试引脚。所述多个第一阵列测试引脚用于提供阵列测试信号，显示区域10的多个子像素响应于所述阵列测试信号可以产生阵列测试数据信号。所述多个第二阵列测试引脚用于从显示区域10的多个子像素接收阵列测试数据信号。利用阵列测试信号和阵列测试数据信号，可以实现对显示区域10中的多个子像素的阵列测试，从而确定显示基板的显示区域10中的像素电路是否存在异常，下文将对此进一步详细说明。
第一阵列测试引脚和第二阵列测试引脚可以以各种方式布置在多个第一引脚20与多个第二引脚30之间，下面将参考图2A至图2D对此进行示例说明。
图2A至图2D示出了根据本公开实施例的显示基板的多个示例的示意图。
如图2A所示，显示基板200A包括显示区域10和周边区域11。第一引脚区域20、第二引脚区域30以及设置在第一引脚区域20与第二引脚区域30之间的多个第一阵列测试引脚PIN1和多个第二阵列测试引脚PIN2位于周边区域11中。
多个第二阵列测试引脚PIN2被设置在第一区域41中。多个第一阵列测试引脚PIN1中的一部分第一阵列测试引脚(例如图2A中为左侧3个第一阵列测试引脚PIN1)被设置在第二区域42中，多个第一阵列测试引脚PIN1中的另一部分第一阵列测试引脚(图2A中为右侧三个第一阵列测试引脚PIN1)被设置在第三区域43中。第一区域41、第二区域42和第三区域43均位于第一引脚区域20与第二引脚区域30之间。第一引脚区域20和第二引脚区域30在显示区域10的一侧沿第一方向(在图2A中为y方向)排列，第一区域41、第二区域42和第三区域43沿垂直于第一方向的第二方向(图2A中为x方向)排列。第二区域42和第三区域43分别位于第一区域41的两侧，在图2A中第二 区域42位于第一区域41左侧，第三区域43位于第一区域41右侧。在图2A中，多个第一阵列测试引脚PIN1和多个第二阵列测试引脚PIN2沿x方向排列成一行。通过将第二区域42和第三区域43设置在第一区域41两侧，可以使第一阵列测试引脚PIN1和第二阵列测试引脚PIN2的分布具有更高的对称性。在一些实施例中，可以使第二区域42中的引脚数量等于第三区域43中的引脚数量，从而进一步提高对称性。
然而本公开的实施例不限于此，第一阵列测试引脚PIN1和第二阵列测试引脚PIN2可以以其他方式布置在第一引脚区域20与第二引脚区域30之间。
在一些实施例中，如图2B所示，第一阵列测试引脚PIN1和第二阵列测试引脚PIN2可以分别设置在两个区域中。在图2B中，第二阵列测试引脚PIN2被设置在第一区域41中，第一阵列测试引脚PIN1被设置在第二区域42中。第一区域41和第二区域42均位于第一引脚区域20与第二引脚区域30之间。在图2B中，第一区域41和第二区域42沿x方向排列，使得第一阵列测试引脚PIN1和第二阵列测试引脚PIN2沿x方向排列成一行。第一区域41和第二区域42也可以以其他方式排列，例如沿y方向排列或者任意排列。在一些实施例中，第一阵列测试引脚PIN1和第二阵列测试引脚PIN2可以分布在四个或更多个区域中。
在一些实施例中，如图2C所示，第一阵列测试引脚PIN1和第二阵列测试引脚PIN2可以排列成多行。在图2C中，多个第二阵列测试引脚PIN2被设置在第一区域41中。多个第一阵列测试引脚PIN1中的一部分第一阵列测试引脚(例如图2C中为左侧6个第一阵列测试引脚PIN1)被设置在第二区域42中，多个第一阵列测试引脚PIN1中的另一部分第一阵列测试引脚(图2C中为右侧6个第一阵列测试引脚PIN1)被设置在第三区域43中。第一区域41、第二区域42和第三区域43以类似于图2A所示的方式设置在第一引脚区域20与第二引脚区域30之间。第一区域41中的第二阵列测试引脚PIN2以及第二区域42和第三区域43中的第一阵列测试引脚PIN2均沿着x方向排列成两行，使得第一阵列测试引脚PIN1和第二阵列测试引脚PIN2整体上也沿着x方向排列成两行。然而本公开的实施例不限于此，第一阵列测试引脚PIN1和第二阵列测试引脚PIN2也可以排列成3行或更多行。通过这种方式，可以减小第一阵列测试引脚和第二阵列测试引脚(下文统称为阵列测试引脚)在第x方向上占用的空间尺寸，或者在显示基板在x方向上的空间尺寸有限的情况下可以布置更多的阵列测试引脚。
在一些实施例中，如图2D所示，第一阵列测试引脚PIN1和第二阵列测试引脚PIN2可以部分排列成一行，而部分排列成多行。在图2D中，多个第二阵列测试引脚PIN2 被设置在第一区域41中，多个第一阵列测试引脚PIN1中的一部分第一阵列测试引脚(例如图2D中为左侧3个第一阵列测试引脚PIN1)被设置在第二区域42中，多个第一阵列测试引脚PIN1中的另一部分第一阵列测试引脚(图2D中为右侧三个第一阵列测试引脚PIN1)被设置在第三区域43中。第一区域41中的多个第二阵列测试引脚PIN2沿x方向排列成两行，在图2D中排列成2×6阵列。第二区域42中的第一阵列测试引脚PIN1和第三区域43中的第一阵列测试引脚PIN1均排列成一行，在图2D中排列成1×3阵列。
虽然以上通过特定的示例描述了本公开实施例的第一阵列检测引脚和第二阵列检测引脚的布局，然而本公开的实施例不限于此。第一阵列检测引脚和第二阵列检测引脚可以根据需要以任何其他方式设置在第二引脚阵列20与第一引脚阵列30之间。
下面将参考图3A和图3B来说明本公开实施例的显示基板的驱动电路。图3A示出了根据本公开实施例的显示基板300的局部结构的示意图，其中示出了驱动电路和结构。图3B示出了根据本公开实施例的显示基板300的局部结构的示意图，其中示出了驱动电路的结构和显示区域的结构。
如图3A和图3B所示，在显示基板300的显示区域10中设有多个子像素P，多个子像素P可以布置成阵列，例如排列成多行的形式，包括第一行子像素P1，第二行子像素P2，……，第n行子像素Pn。
多条数据线DATA1，DATA2，…，DATAk位于所述显示区域中且沿第一方向(y方向)延伸，所述多条数据线DATA1，DATA2，…，DATAk电连接至所述多个子像素P。例如在图3B中，数据线DATA1连接至第一列子像素P，数据线DATA2连接至第2列子像素P，以此类推，数据线DATAk连接至第k列子像素。
多条栅极线GATE1，GATE2，…，GATEn位于显示区域10中且沿第二方向(x方向)延伸。第一方向(y方向)和第二方向(x方向)交叉。多条栅极线GATE1，GATE2，…，GATEn电连接至所述多个子像素P。例如栅极线GATE1连接至第一行子像素P1，栅极线GATE2连接至第二行子像素P2，以此类推，栅极线GATEn连接至第n行子像素Pn。
栅极驱动电路50位于周边区域11，栅极驱动电路50与多条栅极线GATE1，GATE2，…，GATEn。例如，在图3B中，栅极驱动电路50包括多级级联的多个移位寄存器GOA0，GOA1，…，GOAn，即，第i级第一移位寄存器GOAi的输出端连接至第i+1级第一移位寄存器GOA(i+1)的复位端。第一级第一移位寄存器GOA1连接至栅极线GATA1以向第一行子像素P1提供栅极驱动信号，第二级第一移位寄存器GOA2连接 至栅极线GATA2以向第二行子像素P2提供栅极驱动信号，以此类推。在图3B中，第i级移位寄存器GOAi产生的针对第i行子像素Pi的栅极驱动信号也被用作针对第i+1行子像素P(i+1)的复位信号RST(i+1)。例如，第0级第一移位寄存器GOA0产生的针对第0行子像素P0的栅极驱动信号也被用作针对第1行子像素P1的复位信号RST1，第1级第一移位寄存器GOA1产生的针对第1行子像素P1的栅极驱动信号也被用作针对第2行子像素P2的复位信号RST2，以此类推。
如图3A所示，栅极驱动电路50还与第一启动电压信号线GSTV、第一时钟信号线GCK和第二时钟信号线GCB电连接，以便在其控制下产生栅极驱动信号。例如，栅极驱动电路50中的第0级第一移位寄存器GOA0与第一启动电压信号线GSTV、第一时钟信号线GCK和第二时钟信号线GCB电连接，以便在第一启动电压信号线GSTV、第一时钟信号线GCK和第二时钟信号线GCB的控制下产生针对第0行子像素的栅极驱动信号，其在图3B中也被用作复位信号RST1。类似地，栅极驱动电路50中的第1级第一移位寄存器GOA0与第一时钟信号线GCK和第二时钟信号线GCB电连接，以便在第一时钟信号线GCK和第二时钟信号线GCB的控制下产生针对第1行子像素的栅极驱动信号GATE1，其在图3B中也被用作复位信号RST2。
如图3A和图3B所示，显示基板还可以包括多条发光控制线EM1，EM2，…，EMn和发光控制驱动电路60。多条发光控制线EM1，EM2，…，EMn穿过显示区域10且沿第二方向(x方向)延伸。多条发光控制线EM1，EM2，…，EMn电连接至多个子像素P。例如在图3B中，发光控制线EM1电连接至第一行子像素P1，发光控制线EM2电连接至第二行子像素P2，以此类推。
发光控制驱动电路60位于所述周边区域11且位于栅极驱动电路50远离显示区域10的一侧。在图3A和图3B中，发光控制驱动电路60包括多级级联的第二移位寄存器EOA0，EOA1，…，EOAm，其中第0级第二移位寄存器EOA0连接至发光控制线EM1和EM2，以分别向第一行子像素P1和第二行子像素P2提供发光控制信号，第1级第二移位寄存器EOA1连接至发光控制线EM3和EM4，以分别向第三行子像素P3和第四行子像素P4提供发光控制信号。在图3A和图3B的示例中，由于每个第二移位寄存器向两行子像素提供发光控制信号，因此第二移位寄存器的数量可以是第一移位寄存器的数量的二分之一。当然本公开的实施例不限于此，第一移位寄存器和第二移位寄存器的数量和级联方式可以根据需要来设置。
周边区域11中还可以布置第二启动电压信号线ESTV、第三时钟信号线ECK和第 四时钟信号线ECB。发光控制驱动电路60还与第二启动电压信号线ESTV、第三时钟信号线ECK和第四时钟信号线ECB电连接，以便在其控制下产生发光控制信号。例如，发光控制驱动电路60中的第0级第二移位寄存器EOA0与第二启动电压信号线ESTV、第三时钟信号线ECK和第四时钟信号线ECB电连接，以便在第二启动电压信号线ESTV、第三时钟信号线ECK和第四时钟信号线ECB的控制下产生针对第1行子像素P1和第2行子像素P2的发光控制信号。类似地，发光控制驱动电路60中的第1级第二移位寄存器EOA1与第三时钟信号线ECK和第四时钟信号线ECB电连接，以便在第三时钟信号线ECK和第四时钟信号线ECB的控制下产生针对第2行子像素P2和第3行子像素P3的发光控制信号。
图4A示出了根据本公开一实施例的显示基板的结构图。图4B示出了图4A中由虚线框AA表示的区域的放大图。
如图4A所示，显示基板400包括衬底基板1，衬底基板1包括显示区域10和围绕显示区域10的周边区域11。
显示区域10中可以如以上参考图3A和3B所描述的方式布置有多个子像素、多条数据线和多条栅极线。
周边区域11中可以设置有栅极驱动电路和多条栅极线，例如以上参考图3A和图3B描述的栅极驱动电路50和多条栅极线GATE1，GATE2，…，GATEn，其中栅极驱动电路50包括多级级联的多个第一移位寄存器GOA0，GOA1，…，GOAn。周边区域11中还可以如以上参考图3A和图3B所描述的方式布置有与栅极驱动电路连接的第一启动电压信号线GSTV、第一时钟信号线GCK和第二时钟信号线GCB。
周边区域11中可以设有多个第一引脚和多个第二引脚，所述多个第二引脚位于显示区域10和所述多个第一引脚之间。例如所述多个第一引脚可以如以上参考图2A至图2D描述的方式设置于第一引脚区域20中，所述多个第二引脚可以如以上参考图2A至图2D描述的方式设置于第二引脚区域30中。
周边区域11中还可以设有多个第一阵列测试引脚PIN1和多个第二阵列测试引脚PIN2。所述多个第一阵列测试引脚PIN1和所述多个第二阵列测试引脚PIN2位于所述多个第一引脚所在的区域20和所述多个第二引脚所在的区域30之间。所述多个第二阵列测试引脚PIN2沿显示区域10边界方向延伸，所述多个第一阵列测试引脚PIN1在沿显示区域10边界的延伸方向上位于所述多个第二阵列测试引脚PIN2的至少一侧。
所述多个第一阵列测试引脚PIN1分别电连接至多条阵列测试信号线，所述多条阵 列测试信号线包括第一启动电压信号线GSTV、第一时钟信号线GCK和第二时钟信号线GCB中的至少一条。例如在图4A中，所述多条阵列测试信号线可以包括第一启动电压信号线GSTV、第一时钟信号线GCK和第二时钟信号线GCB，它们分别与所述多个第一阵列测试引脚PIN1电连接。
所述多个第二阵列测试引脚PIN2分别电连接至多条数据线DATA1，DATA2，…，DATAk，所述多个第二阵列测试引脚PIN2可以通过所述多条数据线DATA1，DATA2，…，DATAk从显示区域10中的多个子像素接收阵列测试数据信号。
显示区域10包括依次连接的第一边界101、第二边界102、第三边界103和第四边界104(例如下侧边界、上侧边界、左侧边界和右侧边界)，所述多个第一阵列测试引脚PIN1和所述多个第二阵列测试引脚PIN2位于靠近所述第一边界(下侧边界)的所述周边区域11中。
在图4A中，栅极驱动电路可以包括第一子电路和第二子电路，所述第一子电路和所述第二子电路分别位于靠近所述第二边界(左侧边界)和所述第四边界(右侧边界)的周边区域11。例如在图4A中，第一子电路包括位于显示区域10左侧的一组第一移位寄存器GOA0，GOA1，…，GOAn，第二子电路包括位于显示区域10右侧的另一组第一移位寄存器GOA0，GOA1，…，GOAn。
第一启动电压信号线GSTV、第一时钟信号线GCK和第二时钟信号线GCB中的每一个也可以分为两部分，分别设置在显示区域10两侧。例如，如图4A所示，第一启动电压信号线GSTV包括分别位于显示区域10左右两侧的第一启动电压信号线第一子线和第一启动电压信号线第二子线，第一时钟信号线GCK包括分别位于显示区域10左右两侧的第一时钟信号线第一子线和第一时钟信号线第二子线，第二时钟信号线GCB包括分别位于显示区域10左右两侧第二时钟信号线第一子线和第二时钟信号线第二子线。位于显示区域10左侧的第一启动电压信号线第一子线、所述第一时钟信号线第一子线和所述第二时钟信号线第一子线电连接第一子电路，位于显示区域10右侧的第一启动电压信号线第二子线、第一时钟信号线第二子线和第二时钟信号线第二子线电连接所述第二子电路。
所述多个第一阵列测试引脚PIN1可以包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚在沿所述第一边界的延伸方向上分别位于所述多个第二阵列测试引脚PIN2的两侧。例如在图4A中，所述多个第一阵列测试引脚PIN1和多个第二阵列测试引脚PIN2按照以上 参考图2A描述的方式设置，其中所述多个第二阵列测试引脚PIN2设置于第一区域41中，所述多个第一阵列测试引脚PIN1设置于分别位于所述第一区域41两侧的第二区域42和第三区域43中。
如图4A和图4B所示，位于显示区域10左侧的第一启动电压信号线第一子线(图4B中由GSTV表示)、第一时钟信号线第一子线(图4B中由GCK表示)和第二时钟信号线第一子线(图4B中由GCB表示)电连接第二区域42中的第一组第一阵列测试引脚PIN1。以类似的方式，位于显示区域10右侧的第一启动电压信号线第二子线、第一时钟信号线第二子线和第二时钟信号线第二子线电连接第三区域43中的第二组第一阵列测试引脚PIN1，这里不在赘述。
在一些实施例中，显示基板400的周边区域11中还可以设置有发光控制驱动电路和多条发光控制线，例如以上参考图3A和图3B描述的发光控制电路60和发光控制线EM1，EM2，…，EMn。发光控制电路60包括多级级联的多个第二移位寄存器EOA0，EOA1，…，EOAm。周边区域11中还可以如以上参考图3A和图3B所描述的方式布置有与发光控制驱动电路连接的第二启动电压信号线ESTV、第三时钟信号线ECK和第四时钟信号线ECB。发光控制驱动电路可以按照以上参考图3A和图3B描述的方式电连接第二启动电压信号线ESTV、第三时钟信号线ECK、第四时钟信号线ECB。所述多条阵列测试信号线除了包括上述第一启动电压信号线GSTV、第一时钟信号线CK和第二时钟信号线CB中的至少一条之外，还可以包括第二启动电压信号线ESTV、第三时钟信号线ECK和第四时钟信号线ECB中的至少一条。在图4B中，第一启动电压信号线GSTV、第一时钟信号线GCK、第二时钟信号线GCB、第二启动电压信号线ESTV、第三时钟信号线ECK和第四时钟信号线ECB分别与六个第一阵列测试引脚PIN一一对应地电连接。
类似于栅极驱动电路，发光控制驱动电路也可以包括分别位于显示区域10两侧的第三子电路和第四子电路，例如所述第三子电路和所述第四子电路可以分别位于靠近显示区域10的第二边界(左侧边界)和第四边界(右侧边界)的周边区域11。在图4A中，发光控制驱动电路的第一子电路包括位于显示区域10左侧的一组第二移位寄存器EOA0，EOA1，…，EOAm，第二子电路包括位于显示区域10右侧的另一组第二移位寄存器EOA0，EOA1，…，EOAm。
第二启动电压信号线ESTV、第三时钟信号线ECK和第四时钟信号线ECB中的每一个也可以分为两部分，分别设置在显示区域10两侧。例如，如图4A所示，第二启 动电压信号线ESTV包括分别位于显示区域10左右两侧的第二启动电压信号线ESTV第一子线和第二启动电压信号线第二子线，第三时钟信号线ECK包括分别位于显示区域10左右两侧的第三时钟信号线第一子线和第三时钟信号线第二子线，第四时钟信号线ECB包括分别位于显示区域10左右两侧第四时钟信号线第一子线和第四时钟信号线第二子线。位于显示区域10左侧的第二启动电压信号线第一子线、第三时钟信号线第一子线和第四时钟信号线第一子线电连接发光控制驱动电路的第一子电路，位于显示区域10右侧的第二启动电压信号线第二子线、第三时钟信号线第二子线和第四时钟信号线第二子线电连接发光控制驱动电路的第二子电路。
如图4A和图4B所示，位于显示区域10左侧的第二启动电压信号线第一子线(图4B中由ESTV表示)、第三时钟信号线第一子线(图4B中由ECK表示)和第四时钟信号线第一子线(图4B中由ECB表示)电连接第二区域42中的第一组第一阵列测试引脚PIN1。以类似的方式，位于显示区域10右侧的第二启动电压信号线第二子线、第三时钟信号线第二子线和第四时钟信号线第二子线电连接第三区域43中的第二组第一阵列测试引脚PIN1，这里不在赘述。
在一些实施例中，多条阵列测试信号线中的至少一部分阵列测试信号线可以与所述多个第二引脚中的一部分第二引脚一一对应地连接，所述一部分第二引脚通过多条第一连接线与所述多个第一阵列测试引脚中的至少一部分第一阵列测试引脚一一对应地连接。如图4B所示，多条阵列测试信号线包括第一启动电压信号线GSTV、第一时钟信号线GCK、第二时钟信号线GCB、第二启动电压信号线ESTV、第三时钟信号线ECK和第四时钟信号线ECB，分别与与六个第二引脚OUT一一对应地连接。这六个第二引脚OUT分别通过六条第一连接线W1与六个第一阵列测试引脚PIN一一对应地连接。
在一些实施例中，显示基板400的周边区域11中还可以设有多个连接引脚(图4B中表示为FOP)，位于第一引脚区域20中的多个第一引脚可以与所述多个连接引脚FOP电连接，以便连接到柔性电路板。
图5A示出了根据本公开另一实施例的显示基板的结构图。图5B示出了根据本公开实施例的显示基板中的多路复用电路的电路图。图5C示出了图5A中由虚线框BB表示的区域的放大图。图5A至图5C的显示基板500与图4A至图4B的显示基板400类似，区别至少在于显示基板500还包括多路复用电路MUX，为了简明起见，下面主要对区 别部分进行详细描述。
如图5A至图5C所示，显示基板500的周边区域11中还设置有多路复用电路MUX以及第一选择信号线MUX1和第二选择信号线MUX2。
多路复用电路MUX位于多个第二引脚(第二引脚区域30)与显示区域11之间。如图5B所示，多路复用电路MUX包括多个复用开关M1，M2，…，所述多个复用开关M1，M2，…中的至少一个复用开关包括第一晶体管T1和第二晶体管T2。第一晶体管T1的栅极电连接至第一选择信号线MUX1，第二晶体管T2的栅极电连接至第二选择信号线MUX2。第一晶体管T1和第二晶体管T2的第一极连接至一个第二引脚，第一晶体管T1的第二极和第二晶体管T2的第二极分别连接至两条数据信号线。
在显示基板500中，相比于显示基板400，所述多条阵列测试信号线还可以包括第一选择信号线MUX1和第二选择信号线MUX2。如图5B所示，第一阵列测试引脚PIN1中除了分别与第一启动电压信号线GSTV、第一时钟信号线GCK、第二时钟信号线GCB、第二启动电压信号线ESTV、第三时钟信号线ECK和第四时钟信号线ECB电连接的多个第一阵列测试引脚PIN1以外，还有多个第一阵列测试引脚PIN1与第一选择信号线MUX1和第二选择信号线MUX2电连接。在图5C中，第一选择信号线MUX1和第二选择信号线MUX2分别与与两个第二引脚OUT一一对应地连接，两个第二引脚OUT分别通过两条第一连接线W1与两个第一阵列测试引脚PIN1一一对应地连接。
在图5A中，第一选择信号线MUX1和第二选择信号线MUX2中的每一个可以包括两部分，分别位于显示区域10的两侧。例如第一选择信号线MUX1包括位于显示区域10左侧的第一选择信号线第一子线和位于显示区域10右侧的第一选择信号线第二子线，第二选择信号线MUX2包括位于显示区域10左侧的第二选择信号线第一子线和位于显示区域10右侧的第二选择信号线第二子线。如图5A和图5C所示，位于第二区域42中的第一组第一阵列测试引脚PIN1与第一选择信号线第一子线(图5C中由MUX1表示)和所述第二选择信号线第一子线(图5C中由MUX2表示)电连接。以类似的方式，位于第三区域43中的第二组第一阵列测试引脚与第一选择信号线第二子线和所述第二选择信号线第二子线电连接，这里不在赘述。
图6A示出了根据本公开另一实施例的显示基板的结构图。图6B示出了根据本公开实施例的显示基板中的单元测试电路和多路复用电路的电路图。图6C示出了图6A中由虚线框CC表示的区域的局部放大图。图6A至图6C的显示基板600与图5A至图5C的 显示基板500类似，区别至少在于显示基板600还包括单元测试电路CT，为了简明起见，下面主要对区别部分进行详细描述。
如图6A至图6C所示，显示基板500的周边区域11中还设置有单元测试电路CT以及第一开关信号线SWR、第二开关信号线SWG、第三开关信号线SWB和第四开关信号线SWD。单元测试电路CT可以包括第一单元测试电路CT1和第二单元测试电路CT2。第一单元测试电路CT1位于多个第二引脚(第二引脚区域30)和显示区域10之间，第二单元测试电路CT2位于多个第二引脚(第二引脚区域30)和第一单元测试电路CT1之间。
如图6B所示，第一单元测试电路CT1包括多个第一测试子电路，所述多个第一测试子电路中的至少一个包括第三晶体管T3、第四晶体管T4和第五晶体管T5，其中第三晶体管T3的栅极电连接至第一开关信号线SWR，第四晶体管T4的栅极电连接至所述第二开关信号线SWG，第五晶体管T5的栅极电连接至第三开关信号线SWB。第三晶体管T4的第一极电连接至第一单元测试信号线DR，第四晶体管T4的第一极电连接至第二单元测试信号线DG，第五晶体管T5的第一极电连接至第三单元测试信号线DB。第三晶体管T3的第二极、第四晶体管T4的第二极和第五晶体管T5的第二极分别电连接至三条数据信号线DATA1、DATA2和DATA3。
如图6B所示，第二单元测试电路CT2包括多个第二测试子电路，所述多个第二测试子电路中的至少一个包括第六晶体管T6，第六晶体管T6的栅极电连接至第四开关信号线SWD。第六晶体管的第一极连接至第四单元测试信号线。例如在图6B中，左侧第一个第二阵列测试子电路中的第六晶体管T6的第一极电连接至第四单元测试信号线D1，第二个阵列测试子电路中的第六晶体管的第一极电连接至第四单元测试信号线D2，以此类推。各个第二测试子电路中的第六晶体管T6的第二极分别电连接至多条数据信号线DATA1，DATA2，…。
如图6C所示，相比于显示基板500，显示基板600的多条阵列测试信号线还包括第一开关信号线SWR、第二开关信号线SWG、第三开关信号线SWB和第四开关信号线SWD中的至少一条。在图6C中，第一阵列测试引脚PIN1中除了分别与第一启动电压信号线GSTV、第一时钟信号线GCK、第二时钟信号线GCB、第二启动电压信号线ESTV、第三时钟信号线ECK、第四时钟信号线ECB、第一选择信号线MUX1和第二选择信号线MUX2电连接的多个第一阵列测试引脚PIN1之外，还有多个第一阵列测试引脚PIN1分别与第一开关信号线SWR、第二开关信号线SWG、第三开关 信号线SWB和第四开关信号线SWD电连接。在一些实施例中，所述多条阵列测试信号线中的另一部分阵列测试信号线通过多条第二连接线W2与所述多个第一阵列测试引脚PIN1中的另一部分第一阵列测试引脚PIN1一一对应地连接。例如在图6C中，第一开关信号线SWR、第二开关信号线SWG、第三开关信号线SWB和第四开关信号线SWD分别通过四条第二连接线W2与四个第一阵列测试引脚PIN1一一对应的电连接。
第一开关信号线SWR、第二开关信号线SWG、第三开关信号线SWB和第四开关信号线SWD中的每一个包括两部分，分别位于显示区域10的两侧。例如，
第一开关信号线SWR包括分别位于显示区域10左右两侧的第一开关信号线第一子线和第一开关信号线第二子线，第二开关信号线SWG包括分别位于显示区域10左右两侧的第二开关信号线第一子线和第二开关信号线第二子线，第三开关信号线SWB包括分别位于显示区域10左右两侧的第三开关信号线第一子线和第三开关信号线第二子线，第四开关信号线SWD包括分别位于显示区域10左右两侧的第四开关信号线第一子线和第四开关信号线第二子线。
如图6C所示，位于显示区域10左侧的第一开关信号线第一子线(在图6C中由SWR表示)、第二开关信号线第一子线(在图6C中由SWG表示)、第三开关信号线第一子线(在图6C中由SWB表示)和第四开关信号线第一子线(在图6C中由SWD表示)电连接至位于第二区域42中的第一组第一阵列测试引脚PIN1中的四个第一阵列测试引脚PIN。以类似的方式，位于显示区域10右侧的第一开关信号线第二子线、第二开关信号线第二子线、第三开关信号线第二子线和第四开关信号线第二子线电连接至第三区域43中的第二组第一阵列测试引脚PIN1中的四个第一阵列测试引脚PIN1。
图7A示出了根据本公开另一实施例的显示基板的结构图。图7B示出了根据本公开实施例的显示基板中的第一电源总线与第一电源线的示意图。图7C示出了图7A中由虚线DD表示的区域的局部放大图。图7A至图7C的显示基板700与图6A至图6C的显示基板500类似，区别至少在于显示基板700还包括第一电源总线VDD，为了简明起见，下面主要对区别部分进行详细描述。
如图7A和图7B所示，显示基板700还包括位于显示区域10中的多条第一电源线VD和位于靠近显示区域10的第一边界(下侧边界)的周边区域11的第一电源总线VDD，所述多条第一电源线VD和第一电源总线VDD电连接。例如在图7B中，在显示区域10中，每一列子像素P电连接一条第一电源线VD，与多列子像素P分别电连接的多条 第一电源线VD从显示区域10引出，从而连接到位于周边区域11中的第一电源总线VDD。
如图7C所示，在显示基板700中，相比于显示基板600，所述多条阵列测试信号线还包括第一电源总线VDD，除了分别与第一启动电压信号线GSTV、第一时钟信号线GCK、第二时钟信号线GCB、第二启动电压信号线ESTV、第三时钟信号线ECK、第四时钟信号线ECB、第一选择信号线MUX1、第二选择信号线MUX2、第一开关信号线SWR、第二开关信号线SWG、第三开关信号线SWB和第四开关信号线SWD电连接的多条第一阵列测试引脚PIN1之外，还有至少一个第一阵列测试引脚PIN1与第一电源总线VDD连接。在图7C中，第一开关信号线SWR、第二开关信号线SWG、第三开关信号线SWB、第四开关信号线SWD和第一电源总线VDD分别通过五条第二连接线W2与五个第一阵列测试引脚PIN1一一对应的电连接。
在一些实施例中，第一电源总线VDD可以包括第一电源总线第一子线和第一电源总线第二子线。例如在图7A和图7B中，第一电源总线VDD可以包括沿水平方向延伸的第一部分以及沿垂直方向延伸的两个第二部分，所述两个第二部分分别位于显示基板700的左右两侧。可以将位于左侧的第二部分作为第一电源总线第一子线，将位于右侧的第二部分作为第一电源总线第二子线。
如图7C所示，位于左侧的第一电源总线第一子线(在图7C中由VDD表示)电连接至位于第二区域42中的第一组第一阵列测试引脚PIN1。以类似的方式，位于右侧的第一电源总线第二子线电连接位于第三区域43中的第二组第一阵列测试引脚PIN1，这里不在赘述。
图8A示出了根据本公开另一实施例的显示基板的结构图。图8B示出了根据本公开实施例的显示基板中的初始电压信号总线与初始电压信号线的示意图。图8C示出了图8A中由虚线框EE表示的区域的局部放大图。图8A至图8C的显示基板800与图7A至图7C的显示基板700类似，区别至少在于显示基板800还包括初始电压信号总线Vinit，为了简明起见，下面主要对区别部分进行详细描述。
如图8A和图8B所示，显示基板800还包括位于显示区域10的多条初始电压信号线VI和位于周边区域11的初始电压信号总线Vinit。初始电压信号总线Vinit位于栅极驱动电路(GOA0，GOA1，…，GOAn)和显示区域10之间。例如在图8B中，在显示区域10中，每一行子像素P电连接一条初始电压信号线VI，与多行子像素P分别电连接的多条初始电压信号线VI从显示区域10引出，从而连接到位于周边区域11中的初始 电压信号总线Vinit。
在显示装置800中，相比于显示装置700，所述多条阵列测试信号线还包括初始电压信号总线Vinit。如图8C所示，除了分别与第一启动电压信号线GSTV、第一时钟信号线GCK、第二时钟信号线GCB、第二启动电压信号线ESTV、第三时钟信号线ECK、第四时钟信号线ECB、第一选择信号线MUX1、第二选择信号线MUX2、第一开关信号线SWR、第二开关信号线SWG、第三开关信号线SWB、第四开关信号线SWD和第一电源总线VDD电连接的多个第一阵列测试引脚PIN1之外，还有至少一个第一阵列测试引脚PIN1与初始电压信号总线Vinit电连接。在图8C中，初始电压信号总线Vinit与一个第二引脚OUT电连接，该第二引脚OUT通过一条第一连接线W1与一个第一阵列测试引脚PIN1电连接。
在一些实施例中，如图8A和图8B所示，初始电压信号总线Vinit可以包括初始电压信号总线第一子线和初始电压信号总线第二子线，所述初始电压信号总线第一子线和所述初始电压信号总线第二子线分别位于靠近显示区域10第二边界(左侧边界)和显示区域10第四边界(右侧边界)的周边区域11。在图8C中，位于显示区域10左侧的初始电压信号总线第一子线(在图8C中由Vinit表示)电连接至位于第二区域42中的第一组第一阵列测试引脚PIN1。以类似的方式，初始电压信号总线第二子线电连接至位于第三区域43中的第二组第一阵列测试引脚PIN1，这里不在赘述。
图9A示出了根据本公开实施例的显示基板中的静电放电电路的示意图。图9B示出了根据本公开实施例的静电防护电路的静电放电单元的电路图。图9A和图9B的静电放电电路可以应用于上述任意实施例的显示基板。
如图9A和图9B所示，显示基板还包括静电放电电路，所述静电放电电路包括多个静电放电单元ESD1，ESD2，…，ESDh。多个静电放电单元ESD1，ESD2，…，ESDh位于所述多个第一阵列测试引脚PIN1与第二引脚区域30中的多个第二引脚之间并且与所述多个第一阵列测试引脚PIN1一一对应地连接。如图9B所示，静电放电单元ESD1，ESD2，…，ESDh中的每一个包括第七晶体管T7和第八晶体管T8，所述第七晶体管的栅极和第一极连接至高电压信号线VGH，所述第八晶体管的栅极和第二极连接至低电压信号线VGL，所述第七晶体管T7的第二极以及所述第八晶体管T8的栅极和第一极电连接至第一阵列测试引脚PIN1。当第一阵列测试引脚PIN1上的信号高电平高于预设高电平值时，第七晶体管T7导通以将第一阵列测试引脚PIN1控制在高电压信号线VGH的电位，从而使过高电平通过第七晶体管T7释放。当第一阵列测试引脚PIN1 上的信号低电平低于预设低电平值时，第八晶体管T8导通以将第一阵列测试引脚PIN1控制在低电压信号线VGL的电位，从而使过低电平通过第八晶体管T8释放。
图10A示出了根据本公开实施例的多路复用电路中一个多路复用开关的布局图。如图10A所示，一个多路复用开关包括第一晶体管T1和第二晶体管T2(如虚线框所示)，其中第一晶体管T1和第二晶体管T2共用晶体管的第一极。如图10A所示，210表示用于形成第一晶体管T1和第二晶体管T2的有源区的有源层，K1表示电连接在一起的第一晶体管T1的第一极和第二晶体管T2的第一极，K2表示第一晶体管T1的栅极，K3表示第二晶体管T2的栅极，K4表示第一晶体管T1的第二极，K5表示第二晶体管T2的第二极。在图10A中，第一控制线MUX1沿水平方向延伸并且与K2电连接，第二控制线MUX2沿水平方向设置并且与K3电连接。引线220与K1电连接，用于将第一晶体管T1的第一极和第二晶体管T2的第一极电连接至用于输出数据信号的芯片的引脚(例如第二引脚)。引线230与K4电连接，用于将第一晶体管T1接收到的数据信号发送至显示区域中的数据线。引线240与K5电连接，用于将第二晶体管T2接收到的数据信号发送至显示区域中的数据线。
图10B示出了图10A中沿HH′线截取的截面图。如图2C所示，在衬底基板1上依次叠置有缓冲层211、第一栅绝缘层212、第二栅绝缘层213、层间绝缘层214、钝化层215和第一平坦化层216。有源层210位于缓冲层211与第一栅绝缘层212之间。第一晶体管T1的栅极K2和第二晶体管T2的栅极K3位于第一栅绝缘层212与第二栅绝缘层213之间。第一晶体管T1和第二晶体管T1共用的第一极K1、第一晶体管T1的第二极K4和第二晶体管T2的第二极K5位于层间绝缘层214与钝化层215之间。第一晶体管T1的第二极K4和第二晶体管T2的第二极K5分别通过过孔与有源层210连接，所述过孔依次穿过第一栅绝缘层212、第二栅绝缘层213和层间绝缘层214。
用于形成第一晶体管T1和第二晶体管T2的有源区的有源层210与上述显示区域10中的多个子像素P中的至少一个子像素P所包含的驱动薄膜晶体管的驱动有源层位于相同的层。第一晶体管T1的栅极K2和第二晶体管T2的栅极K3与上述显示区域10中的多个子像素P中的至少一个子像素P所包含的驱动薄膜晶体管的驱动栅极位于相同的层。第一晶体管T1和第二晶体管T1共用的第一极K1、第一晶体管T1的第二极K4和第二晶体管T2的第二极K5与显示区域10中的多个子像素P中的至少一个子像素P所包含的驱动薄膜晶体管的驱动源极和驱动漏极位于相同的层。
图11A示出了根据本公开实施例的第一阵列测试电路的布局图。如图11A所示，第 一单元测试电路CT1包括多个第一测试子电路，每个第一测试子电路包括第三晶体管T3、第四晶体管T4和第五晶体管T5，其中第三晶体管T3的栅极电连接至第一开关信号线SWR，第四晶体管T4的栅极电连接至所述第二开关信号线SWG，第五晶体管T5的栅极电连接至第三开关信号线SWB。第三晶体管T4的第一极电连接至第一单元测试信号线DR，第四晶体管T4的第一极电连接至第二单元测试信号线DG，第五晶体管T5的第一极电连接至第三单元测试信号线DB。第三晶体管T3的第二极和第四晶体管T4的第二极电连接一条数据线DATA1，第五晶体管T5的第二极电连接另一条数据线DATA2。这里DATA1和DATA2仅用于表示两条不同的数据线，而并不旨在限制数据线的排列顺序。
图11B示出了根据本公开实施例的第二阵列测试电路的布局图。如图11B所示，第二单元测试电路CT2包括多个第二测试子电路，每个第二测试子电路包括第六晶体管T6，第六晶体管T6的栅极电连接至第四开关信号线SWD。在图11B中，左侧第一个第二阵列测试子电路中的第六晶体管T6的第一极电连接至第四单元测试信号线D1，第二个阵列测试子电路中的第六晶体管的第一极电连接至第四单元测试信号线D2，以此类推。各个第二测试子电路中的第六晶体管T6的第二极分别电连接至多条数据信号线DATA1，DATA2，…。
图12示出了根据本公开实施例的静电放电电路的布局图。如图12所示，静电放电电路包括多个静电放电单元ESD，在图12中用虚线框标注了其中一个静电放电单元。静电放电单元ESD与多个第一阵列测试引脚PIN1电连接。在图12中，多个第一阵列测试引脚PIN1从左至右依次为用于与VDD、Vinit、ESTV、ECB、ECK、GSTV、GCB电连接的第一阵列测试引脚PIN1，其中与VDD和Vinit电连接的两个第一阵列测试引脚未连接静电放电单元。上述实施例中虽然以特定的顺序来说明各信号线VDD、Vinit、ESTV、ECB、ECK、GSTV、GCB的位置关系，然而本公开的实施例不限于此，这些信号线可以根据需要以其他顺序来布置。
在图12中还示出了多个冗余阵列测试引脚Dummy，冗余阵列测试引脚Dummy不与显示基板中的其他电路结构电连接，以使第一区域41、第二区域42和第三区域43各自的引脚数量和排列方式可以根据需要来设置。这一方面使阵列基板上的阵列检测引脚的布局更易于与检测设备的引脚布局匹配，从而实现良好的连接；另一方面可以使第二区域42与第三区域43中的引脚数量相等，从而提高引脚布局的对称性。另外，设置冗余阵列测试引脚Dummy还有利于提高工艺均匀性。在图12中，至少部分冗余阵列测试 引脚Dummy也各自连接有静电放电单元。
如图12所示，静电放电单元ESD包括四个串联的晶体管，即，除了包括上述的第七晶体管T7和第八晶体管T8，还可以包括另外两个晶体管T7’和T8’。晶体管T7’的栅极和第一极连接至高电压信号线VGH，晶体管T7’的第二极连接至第七晶体管T7的栅极和第一极；晶体管T8’的第二极连接至低电压信号线VGL，晶体管T8’的栅极和第一极连接至第八晶体管T8的第二极；第七晶体管T7的第二极以及所述第八晶体管T8的栅极和第一极电连接至第一阵列测试引脚PIN1或者冗余阵列测试引脚Dummy。
图13示出了根据本公开实施例的像素结构的示意图。如图13所示，显示基板中多个子像素中的至少一个包含驱动薄膜晶体管和存储电容。
驱动薄膜晶体管可以包含位于衬底基板上的驱动有源层P-Si，位于所述驱动有源层P-Si远离衬底基板一侧的驱动栅极GATE，位于驱动栅极GATE远离衬底基板一侧的栅绝缘层GI2(第二栅绝缘层)，位于栅绝缘层GI2远离衬底基板一侧的层间介质层ILD，以及位于层间介质层ILD远离所述衬底基板一侧的驱动源极和驱动漏极SD1。
存储电容可以包括第一电容电极ED1和第二电容电极ED2，第一电容电极ED1与驱动栅极GATE位于同一层，第二电容电极ED2位于所述栅绝缘层GI2和所述层间介质层ILD之间。
此外，子像素还可以包括第一栅绝缘层GI1、阻挡层BUF、钝化层PVX、平坦层PLN1、像素界定层PDL、阻光层PS、阳极1301、发光层1302、阴极1303、第一无机封装层1304、有机封装层1305和第二无机封装层1306。阻挡层BUF位于衬底基板1与驱动有源层P-Si之间。第一栅绝缘层GI1位于阻挡层BUF远离衬底基板1的一侧，使得驱动有源层P-Si位于第一栅绝缘层GI1与阻挡层BUF之间。钝化层PVX位于层间介质层ILD远离衬底基板1的一侧。平坦层PLN1位于钝化层PVX远离衬底基板1的一侧。阳极1301位于平坦层PLN1远离衬底基板的一侧并且穿过平坦层PLN1和钝化层PVX与驱动源极或驱动漏极SD1电连接。像素界定层PDL位于平坦层PNL1远离衬底基板1的一侧并且部分地覆盖阳极1301。阻光层PS位于像素界定层PDL远离衬底基板1的一侧并且部分地覆盖像素界定层PDL。发光层1302部分地覆盖阳极1301、像素界定层PDL和阻光层PS。阴极1303位于发光层1302远离衬底基板1的一侧。在阴极1303远离衬底基板1的一侧依次设置于第一无机封装层1304、有机封装层1305和第二无机封装层1306。
上述实施例中的所述多个第一阵列测试引脚PIN1和所述多个第二阵列测试引脚 PIN2中的至少一层可以与显示区域中的多个子像素的驱动源极和驱动漏极SD1位于同一层。上述实施例中的所述多条第一连接线W1可以与显示区域中的多个子像素的驱动源极和驱动漏极SD1位于同一层。
上述实施例中的所述多条第二连接线W2中的每一条第二连接线W2部分与显示区域中的所述多个子像素的驱动源极和驱动漏极SD1位于同一层，并且部分与显示区域中的所述多个子像素的驱动栅极GATE位于同一层。
本公开实施例的显示基板还可以包括各向异性导电膜ACF，所述各向异性导电膜ACF覆盖所述多个第一阵列测试引脚和所述多个第二阵列测试引脚。
本公开的实施例还提供了一种显示面板，包括上述任意实施例的显示基板。
图14示出了根据本公开实施例的显示基板的制造方法的流程图。
在步骤S101，在衬底基板上形成显示区域和围绕所述显示区域的周边区域。显示区域和周边区域可以采用上述任意实施例的方式设置。例如显示区域中可以按照上述实施例中的方式设有多个子像素、多条数据线和多条栅极线，周边区域中可以按照上述实施例中的方式设置有第一扫描栅极驱动电路、第一启动电压信号线、第一时钟信号线、第二时钟信号线、多个第一引脚、多个第二引脚、多个第一阵列测试引脚以及多个第二阵列测试引脚。
在步骤S102，形成覆盖所述多个第一阵列测试引脚和所述多个第二阵列测试引脚的保护层，所述保护层包括但不限于各向异性导电膜。
应当注意的是，在以上的描述中，仅以示例的方式，示出了本公开实施例的技术方案，但并不意味着本公开实施例局限于上述步骤和结构。在可能的情形下，可以根据需要对步骤和结构进行调整和取舍。因此，某些步骤和单元并非实施本公开实施例的总体发明思想所必需的元素。
至此已经结合优选实施例对本公开进行了描述。应该理解，本领域技术人员在不脱离本公开实施例的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本公开实施例的范围不局限于上述特定实施例，而应由所附权利要求所限定。

Claims (26)

  1. 一种显示基板，包括：
    衬底基板，包括显示区域和围绕所述显示区域的周边区域；
    多个子像素，位于所述显示区域中；
    多条数据线，位于所述显示区域中且沿第一方向延伸，所述多条数据线电连接至所述多个子像素；
    多条栅极线，位于所述显示区域中且沿第二方向延伸，所述第一方向和所述第二方向交叉，所述多条栅极线电连接至所述多个子像素；
    栅极驱动电路，位于所述周边区域，所述栅极驱动电路与所述多条栅极线电连接；
    第一启动电压信号线、第一时钟信号线和第二时钟信号线与所述栅极驱动电路电连接；
    多个第一引脚，位于所述周边区域；
    多个第二引脚，位于所述周边区域，且位于所述显示区域和所述多个第一引脚之间；
    多个第一阵列测试引脚，位于所述多个第一引脚和所述多个第二引脚之间，所述多个第一阵列测试引脚分别电连接至多条阵列测试信号线，所述多条阵列测试信号线包括所述第一启动电压信号线、所述第一时钟信号线或所述第二时钟信号线中的至少一条；以及
    多个第二阵列测试引脚，位于所述多个第一引脚和所述多个第二引脚之间且沿所述显示区域边界方向延伸，所述多个第一阵列测试引脚在沿所述显示区域边界的延伸方向上位于所述多个第二阵列测试引脚的至少一侧，所述多个第二阵列测试引脚电连接至所述多条数据线，所述多个第二阵列测试引脚被配置为通过所述多条数据线从所述多个子像素接收阵列测试数据信号。
  2. 根据权利要求1所述的显示基板，其中，所述多条阵列测试信号线包括所述第一启动电压信号线、所述第一时钟信号线和所述第二时钟信号线。
  3. 根据权利要求1或2所述的显示基板，其中，所述显示区域包括依次连接的第一边界、第二边界、第三边界和第四边界，所述多个第一阵列测试引脚和所述多个第二阵列测试引脚位于靠近所述第一边界的所述周边区域；
    所述栅极驱动电路包括第一子电路和第二子电路，所述第一子电路和所述第二子电路分别位于靠近所述第二边界和所述第四边界的所述周边区域；
    所述第一启动电压信号线包括第一启动电压信号线第一子线和第一启动电压信号线第二子线，所述第一时钟信号线包括第一时钟信号线第一子线和第一时钟信号线第二子线，所述第二时钟信号线包括第二时钟信号线第一子线和第二时钟信号线第二子线，所述第一启动电压信号线第一子线、所述第一时钟信号线第一子线和所述第二时钟信号线第一子线位于靠近所述第二边界的所述周边区域，且电连接所述第一子电路，所述第一启动电压信号线第二子线、所述第一时钟信号线第二子线和所述第二时钟信号线第二子线位于靠近所述第四边界的所述周边区域，且电连接所述第二子电路；
    所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚在沿所述第一边界的延伸方向上分别位于所述多个第二阵列测试引脚的两侧；
    其中，所述第一启动电压信号线第一子线、所述第一时钟信号线第一子线和所述第二时钟信号线第一子线电连接所述第一组第一阵列测试引脚，所述第一启动电压信号线第二子线、所述第一时钟信号线第二子线和所述第二时钟信号线第二子线电连接所述第二组第一阵列测试引脚。
  4. 根据权利要求1或2所述的显示基板，还包括：
    多条发光控制线，位于所述显示区域且沿所述第二方向延伸，所述多条发光控制线电连接至所述多个子像素；
    发光控制驱动电路，位于所述周边区域且位于所述栅极驱动电路远离所述显示区域的一侧；
    第二启动电压信号线、第三时钟信号线和第四时钟信号线，所述发光控制驱动电路电连接所述第二启动电压信号线、所述第三时钟信号线、所述第四时钟信号线，所述多条阵列测试信号线还包括所述第二启动电压信号线、第三时钟信号线或第四时钟信号线中的至少一条。
  5. 根据权利要求4所述的显示基板，其中，所述多条阵列测试信号线还包括所述第二启动电压信号线、所述第三时钟信号线和所述第四时钟信号线。
  6. 根据权利要求4或5所述的显示基板，其中，所述显示区域包括依次连接的第一边界、第二边界、第三边界和第四边界，所述多个第一阵列测试引脚和所述多个第二阵列测试引脚位于靠近所述第一边界的所述周边区域；
    所述发光控制驱动电路包括第三子电路和第四子电路，多所述第三子电路和所述第四子电路分别位于靠近所述第二边界和所述第四边界的所述周边区域；
    所述第二启动电压信号线包括第二启动电压信号线第一子线和第二启动电压信号线第二子线，所述第三时钟信号线包括第三时钟信号线第一子线和第三时钟信号线第二子线，所述第四时钟信号线第四时钟信号线第一子线和第四时钟信号线第二子线；
    所述第二启动电压信号线第一子线、所述第三时钟信号线第一子线和所述第四时钟信号线第一子线位于靠近所述第二边界的所述周边区域，且电连接所述第三子电路，所述第二启动电压信号线第二子线、所述第三时钟信号线第二子线和所述第四时钟信号线第二子线位于靠近所述第四边界的所述周边区域，且电连接所述第四子电路；
    所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多个第二阵列测试引脚的两侧；
    其中，所述第二启动电压信号线第一子线、所述第三时钟信号线第一子线和所述第四时钟信号线第一子线电连接所述第一组第一阵列测试引脚，所述第二启动电压信号线第二子线、所述第三时钟信号线第二子线和所述第四时钟信号线第二子线电连接所述第二组第一阵列测试引脚。
  7. 根据权利要求1至6中任一项权利要求所述的显示基板，还包括：
    第一选择信号线和第二选择信号线；以及
    多路复用电路，位于所述多个第二引脚与所述显示区域之间，所述多路复用电路包括多个复用开关，所述多个复用开关中的至少一个复用开关包括第一晶体管和第二晶体管，所述第一晶体管的栅极电连接至所述第一选择信号线，所述第二晶体管的栅极电连接至所述第二选择信号线；
    其中，所述多条阵列测试信号线还包括所述第一选择信号线和所述第二选择信号线。
  8. 根据权利要求7所述的显示基板，其中，所述第一选择信号线包括第一选择信号线第一子线和第一选择信号线第二子线，所述第二选择信号线包括第二选择信号线第一子线和第二选择信号线第二子线；
    所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多个第二阵列测试引脚的两侧；
    其中，所述第一选择信号线第一子线和所述第二选择信号线第一子线电连接所述第一组第一阵列测试引脚，所述第一选择信号线第二子线和所述第二选择信号线第二 子线电连接所述第二组第一阵列测试引脚。
  9. 根据权利要求1至8中任一项权利要求所述的显示基板，还包括位于显示区域的多条初始电压信号线和位于所述周边区域的初始电压信号总线，所述初始电压信号总线位于所述栅极驱动电路和所述显示区域之间，所述多条阵列测试信号线还包括所述初始电压信号总线。
  10. 根据权利要求9所述的显示基板，其中，所述初始电压信号总线包括初始电压信号总线第一子线和初始电压信号总线第二子线，所述初始电压信号总线第一子线和所述初始电压信号总线第二子线分别位于靠近所述第二边界和所述第四边界的所述周边区域；
    所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多个第二阵列测试引脚的两侧；
    其中，所述初始电压信号总线第一子线电连接至所述第一组第一阵列测试引脚，所述初始电压信号总线第二子线电连接至所述第二组第一阵列测试引脚。
  11. 根据权利要求1至10中任一项权利要求所述的显示基板，还包括位于显示区域的多条第一电源线和位于靠近所述第一边界的所述周边区域的第一电源总线，所述多条第一电源线和所述第一电源总线电连接，所述多条阵列测试信号线还包括所述第一电源总线。
  12. 根据权利要求11所述的显示基板，其中，所述第一电源总线包括第一电源总线第一子线和第一电源总线第二子线，所述第一电源总线第一子线和所述第一电源总线第二子线分别位于靠近所述第一边界的所述周边区域；
    所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多个第二阵列测试引脚的两侧；
    其中，所述第一电源总线第一子线电连接至所述第一组第一阵列测试引脚，所述第一电源总线第二子线电连接至所述第二组第一阵列测试引脚。
  13. 根据权利要求1至12中任一项权利要求所述的显示基板，还包括：
    第一开关信号线、第二开关信号线、第三开关信号线和第四开关信号线；
    第一单元测试电路，位于所述多个第二引脚和所述显示区域之间，所述第一单元测试电路包括多个第一测试子电路，所述多个第一测试子电路中的至少一个包括第三 晶体管、第四晶体管和第五晶体管，所述第三晶体管的栅极电连接至所述第一开关信号线，所述第四晶体管的栅极电连接至所述第二开关信号线，所述第五晶体管的栅极电连接至所述第三开关信号线；
    第二单元测试电路，位于所述多个第二引脚和所述第一单元测试电路之间，所述第二单元测试电路包括多个第二测试子电路，所述多个第二测试子电路中的至少一个包括第六晶体管，所述第六晶体管的栅极电连接至所述第四开关信号线；
    其中，所述多条阵列测试信号线还包括所述第一开关信号线、所述第二开关信号线、所述第三开关信号线或所述第四开关信号线中的至少一条。
  14. 根据权利要求13所述的显示基板，其中，所述多条阵列测试信号线还包括所述第一开关信号线、所述第二开关信号线、所述第三开关信号线和所述第四开关信号线。
  15. 根据权利要求14所述的显示基板，其中，所述第一开关信号线包括第一开关信号线第一子线和第一开关信号线第二子线，所述第二开关信号线包括第二开关信号线第一子线和第二开关信号线第二子线，所述第三开关信号线包括第三开关信号线第一子线和第三开关信号线第二子线，所述第四开关信号线包括第四开关信号线第一子线和第四开关信号线第二子线；
    所述多个第一阵列测试引脚包括第一组第一阵列测试引脚和第二组第一阵列测试引脚，所述第一组第一阵列测试引脚和所述第二组第一阵列测试引脚分别位于所述多个第二阵列测试引脚的两侧；
    所述第一开关信号线第一子线、所述第二开关信号线第一子线、所述第三开关信号线第一子线和所述第四开关信号线第一子线电连接至所述第一组第一阵列测试引脚，所述第一开关信号线第二子线、所述第二开关信号线第二子线、所述第三开关信号线第二子线和所述第四开关信号线第二子线电连接至所述第二组第一阵列测试引脚。
  16. 根据权利要求1至15中任一项权利要求所述的显示基板，其中，所述多条阵列测试信号线中的至少一部分阵列测试信号线与所述多个第二引脚中的一部分第二引脚一一对应地连接，所述一部分第二引脚通过多条第一连接线与所述多个第一阵列测试引脚中的至少一部分第一阵列测试引脚一一对应地连接。
  17. 根据权利要求16所述的显示基板，其中，所述至少一部分阵列测试信号线包括所述第一启动电压信号线、所述第一时钟信号线、所述第二时钟信号线、第二启动电压信号线、第三时钟信号线、第四时钟信号线、第一选择信号线、第二选择信 号线和初始电压信号总线。
  18. 根据权利要求16所述的显示基板，其中，所述多条阵列测试信号线中的另一部分阵列测试信号线通过多条第二连接线与所述多个第一阵列测试引脚中的另一部分第一阵列测试引脚一一对应地连接。
  19. 根据权利要求18所述的显示基板，其中，所述另一部分阵列测试信号线包括第一开关信号线、第二开关信号线、第三开关信号线、第四开关信号线和第一电源总线。
  20. 根据权利要求1至19中任一项权利要求所述的显示基板，还包括静电放电电路，所述静电放电电路包括多个静电放电单元，所述多个静电放电单元位于所述多个第一阵列测试引脚与所述多个第二引脚之间并且与所述多个第一阵列测试引脚一一对应地连接，其中，每个静电放电单元包括第七晶体管和第八晶体管，所述第七晶体管的栅极和第一极连接至高电压信号线，所述第八晶体管的第二极连接至低电压信号线，所述第七晶体管的第二极以及所述第八晶体管的栅极和第一极电连接至第一阵列测试引脚。
  21. 根据权利要求1至10中任一项权利要求所述的显示基板，其中，所述多个第一阵列测试引脚和所述多个第二阵列测试引脚在沿所述显示区域边界的延伸方向上排列成一行或多行。
  22. 根据权利要求1至21中任一项权利要求所述的显示基板，其中，所述多个子像素中的至少一个包含驱动薄膜晶体管和存储电容；
    所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱动有源层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的栅绝缘层，位于所述栅绝缘层远离所述衬底基板一侧的层间介质层，以及位于所述层间介质层远离所述衬底基板一侧的驱动源极和驱动漏极；
    所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极与所述驱动栅极位于同一层，所述第二电容电极位于所述栅绝缘层和所述层间介质层之间；
    所述多个第一阵列测试引脚和所述多个第二阵列测试引脚中的至少一层与所述显示区域中的所述多个子像素的驱动源极和驱动漏极位于同一层。
  23. 根据权利要求22所述的显示基板，其中，所述多条第一连接线与所述显示区域中的所述多个子像素的驱动源极和驱动漏极位于同一层。
  24. 根据权利要求22所述的显示基板，其中，所述多条第二连接线中的每一条第 二连接线部分与所述显示区域中的所述多个子像素的驱动源极和驱动漏极位于同一层，并且部分与所述显示区域中的所述多个子像素的驱动栅极位于同一层。
  25. 根据权利要求1至24中任一项权利要求所述的显示基板，还包括：各向异性导电膜，所述各向异性导电膜覆盖所述多个第一阵列测试引脚和所述多个第二阵列测试引脚。
  26. 一种显示面板，包括根据权利要求1至25所述的显示基板。
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