WO2023024595A1 - 半导体结构和半导体结构的制备方法 - Google Patents

半导体结构和半导体结构的制备方法 Download PDF

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WO2023024595A1
WO2023024595A1 PCT/CN2022/093364 CN2022093364W WO2023024595A1 WO 2023024595 A1 WO2023024595 A1 WO 2023024595A1 CN 2022093364 W CN2022093364 W CN 2022093364W WO 2023024595 A1 WO2023024595 A1 WO 2023024595A1
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doped region
substrate
layer
region
gate
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PCT/CN2022/093364
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English (en)
French (fr)
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沈宇桐
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长鑫存储技术有限公司
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Publication of WO2023024595A1 publication Critical patent/WO2023024595A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration

Definitions

  • Embodiments of the present disclosure relate to but are not limited to a semiconductor structure and a method for fabricating the semiconductor structure.
  • MOS transistor
  • process nodes such as high dielectric material metal gate (HKMG) and fin transistor (Finfet)
  • HKMG high dielectric material metal gate
  • Finfet fin transistor
  • Embodiments of the present disclosure provide a semiconductor structure and a method for preparing the semiconductor structure, which can solve the problems of existing semiconductor structures with shallow junction depth and excessive substrate leakage caused by too deep contact vias.
  • an embodiment of the present disclosure provides a method for fabricating a semiconductor structure, including: providing a substrate, the substrate includes a core region and a peripheral region, and both the core region and the peripheral region have gates on the substrate.
  • first doped region in the substrate on opposite sides of the gate structure in the core region and a second doped region in the substrate on the opposite sides of the gate structure in the peripheral region; on the substrate in the peripheral region Forming a barrier layer, the barrier layer is located on the surface of the second doped region; forming a mask layer with openings on the substrate of the core area and the peripheral area, and the mask layer is also located on the surface of the barrier layer, the material of the mask layer and the barrier layer different materials; using the mask layer as a mask, etch the dielectric layer in the core region and the first doped region along the opening to form a first trench in the first doped region, and at the same time etch along the opening
  • the barrier layer in the peripheral region and the second doped region are used to form a second trench in the second doped region, and the depth of the first trench is greater than the depth of the second trench; a first conductive column is formed, and the first conductive The column fills the first groove and protrudes from the surface of the substrate; the second conductive
  • the embodiments of the present disclosure also provide a semiconductor structure, including: a substrate, the substrate includes a core region and a peripheral region, and both the core region and the peripheral region have a gate structure on the substrate There is a first doped region in the substrate on opposite sides of the gate structure in the core region, and a second doped region in the substrate on opposite sides of the gate structure in the peripheral region; the first conductive column, the first conductive column Located in the first doped region, and protruding from the substrate surface; the second conductive column, the second conductive column is located in the second doped area, and protruded from the substrate surface, and the second conductive column is located in the second doped The depth in the impurity region is smaller than the depth of the first conductive column in the first doped region.
  • the technical solutions provided by some embodiments of the present disclosure have at least the following advantages:
  • etching of different materials The etch depth is adjusted by adjusting the etching rate, thereby increasing the distance between the bottom of the conductive contact structure and the depletion region of the PN junction directly formed between the source and drain regions and the substrate, thereby improving the leakage problem at the contact between the conductive contact structure and the semiconductor substrate.
  • the depth of the second conductive pillar located in the second doped region is reduced, so that the second conductive pillar is far away from the depletion region of the PN junction formed between the source drain region and the substrate, which is beneficial to improve the stability of the semiconductor structure. Stability;
  • the first conductive column is located in the first doped region and protrudes from the substrate surface;
  • the second conductive column is located in the second doped region and protrudes from the substrate surface, and the second conductive column
  • the depth in the second doped region is smaller than the depth of the first conductive pillar in the first doped region.
  • the depth of the first conductive pillar in the first doped region ensures good electrical conductivity between the core region and the conductive pillar.
  • the depth of the second conductive pillar located in the second doped region is extremely large, which may cause the second conductive pillar to touch the depletion region of the PN junction directly formed between the source and drain regions and the substrate, which is beneficial to improve semiconductor performance.
  • the problem of excessive leakage of the substrate of the structure is extremely large.
  • Fig. 1 is a structural schematic diagram of a semiconductor structure
  • FIGS. 2 to 10 are structural schematic diagrams corresponding to each step in the method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 11 is another structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • 12 to 20 are structural schematic diagrams corresponding to each step in the method for forming a semiconductor structure provided by another embodiment of the present disclosure.
  • the junction depth of the source and drain regions of the existing semiconductor structure becomes shallow, but the depth of the contact through hole is too deep, which will lead to leakage between the substrate and the substrate.
  • FIG. 1 is a schematic diagram of a semiconductor structure, which is now analyzed in conjunction with FIG. 1 , wherein the substrate 100 includes a core region 101 and a peripheral region 102, and the core region 101 has a first gate 112, and the peripheral region 102 has a second gate.
  • Pole 122 the core region 101 on opposite sides of the first gate 112 has a first doped region 111, and the peripheral region 102 on opposite sides of the second gate 122 has a second doped region 121; the dielectric layer 103 is located The top surface of the core region 101; the first conductive column 146, the first conductive column 146 is partially located in the first doped region 111, and partially protrudes from the surface of the substrate 100; the second conductive column 156, the second conductive column 156 is partially located In the second doped region 121, and partially protrude from the surface of the substrate 100, and due to the uniformity of the production process, the depth of the second conductive pillar 156 in the second doped region 121 is the same as that of the first conductive pillar 146 in the dielectric layer.
  • the semiconductor PN junction due to the difference in the original chemical potential of the semiconductors on both sides of the interface (the contact surface between the P-type semiconductor and the N-type semiconductor), the energy band near the interface is bent, and the interface region where the carrier concentration in the energy band bending area decreases is In the depletion region, since there is a PN interface between the source drain region and the substrate, the depth of the second conductive pillar 156 in the second doped region 121 is relatively large, and the distance between the second conductive pillar 156 and the depletion region is also small, Therefore, the leakage current of the conductive contact structure and the substrate contact of the semiconductor structure increases.
  • the doped region can be used as the source or drain of the semiconductor structure, and the ion concentration of the doped region is a Gaussian doping distribution, wherein, the closer to the substrate surface, the lower the doping concentration.
  • the doping is high, the carrier concentration difference in the semiconductor located on both sides of the depletion region is large, the diffusion movement of the majority carriers is severe, and the space charge region is theoretically widened, but the internal electric field generated by the space charge region leads to a minority carrier The drift motion of the carrier is also intense, and the space charge region is theoretically narrowed. Finally, the diffusion rate of the majority carrier and the drift rate of the minority carrier reach a dynamic balance.
  • the time for carriers to reach dynamic equilibrium is shorter, the recombination time of electrons and holes is shortened, and the width of the depletion region is narrowed.
  • both ends of the depletion region are in low-doped regions, and the thickness of the formed depletion region is relatively thick, resulting in the second conductive column 156 and
  • the distance between the depletion region becomes narrower, and as the size of the device shrinks, the distance between the conductive pillar and the depletion region becomes smaller, and the contact leakage between the conductive contact structure and the substrate of the semiconductor structure increases, which seriously affects the stability of the semiconductor structure.
  • Some embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the semiconductor structure.
  • the etching depth is adjusted, thereby increasing the density of the PN junction formed between the bottom of the conductive contact structure and the source/drain terminal/substrate distance, thereby reducing leakage between the conductive contact structure and the semiconductor substrate.
  • the embodiments of the present disclosure reduce the depth of the second conductive column located in the second doped region, so that the second conductive column is far away from the depletion region, and at the same time ion-dope the second doped region through pretreatment, therefore, the conductive contact structure
  • the contact resistance with the semiconductor is small, which is beneficial to improve the conductivity of the semiconductor structure, and the contact leakage between the conductive contact structure and the substrate of the semiconductor structure is small, which is conducive to improving the stability of the semiconductor structure.
  • FIGS. 2 to 10 are schematic structural diagrams corresponding to each step in the method for forming a semiconductor structure provided by an embodiment of the present disclosure.
  • a substrate 200 is provided, the substrate 200 includes a core region 201 and a peripheral region 202, and the substrate 200 of the core region 201 has a first gate 212, and the first gate 212 of the core region 201 is on opposite sides There is a first doped region 211 in the substrate 200, the substrate 200 exposes the top surface of the first doped region 211, and the top surface of the first doped region 211 has a dielectric layer 203; the substrate 200 of the peripheral region 202 has The second gate 222 has a second doped region 221 in the substrate 200 on opposite sides of the second gate 222 of the peripheral region 202 .
  • the core area 201 is used to connect the conductive structure to form a memory unit
  • the peripheral area 202 is used to connect the conductive structure to form a logic unit to ensure that the functions of the core area are realized.
  • the material of the substrate 200 is a semiconductor material. In some embodiments, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon germanium or silicon carbide.
  • the first gate 212 of the core region 201 is a buried gate
  • the second gate 222 of the peripheral region 202 is a planar gate
  • the core region 201 further includes a first gate spacer 232 and a first gate capping layer 242 .
  • the first gate spacer 232 covers the bottom wall and the sidewall of the first gate 212 , and is used to block the particles of the first gate 212 from interdiffusion with the particles of the first doped region 211 .
  • the material of the first gate spacer 232 is metal oxide, such as titanium nitride, tantalum nitride, titanium or tantalum.
  • the first gate capping layer 242 covers the surface of the first gate 212 for isolating the first gate 212 from the dielectric layer 203, wherein the material of the first gate capping layer 242 is an insulating material, such as silicon dioxide , silicon carbide or silicon nitride.
  • the material of the first gate 212 is metal tungsten, and in other embodiments, the material of the first gate may also be other metal materials such as copper or aluminum.
  • the first gate 212 includes a first gate first conductive layer. In other embodiments, the first gate includes a first gate first conductive layer, a first gate dielectric layer stacked in sequence. and the second conductive layer of the first gate, and the materials of the first conductive layer of the first gate and the second conductive layer of the first gate may be different.
  • the peripheral region 202 further includes a second gate oxide layer 252 covering the substrate 200 , and the second gate oxide layer 252 is located between the substrate 200 and the second gate 222 .
  • the material of the second gate oxide layer 252 is an insulating material for isolating the second gate 222 from the substrate 200 , such as silicon dioxide, silicon carbide or silicon nitride.
  • the material of the second gate oxide layer 252 is the same as that of the first gate capping layer 242 , and in other embodiments, the material of the second gate oxide layer and the first gate capping layer may also be different.
  • the material of the second gate 222 is metal tungsten, and in other embodiments, the material of the second gate 222 may also be other metal materials such as copper or aluminum. In some embodiments, the materials of the first gate 212 and the second gate 222 are the same, and in other embodiments, the materials of the first gate and the second gate may also be different.
  • the second gate 222 includes the first conductive layer of the second gate, and in other embodiments, the second gate includes the first conductive layer of the second gate, the second gate dielectric layer stacked in sequence. and the second conductive layer of the second grid, and the materials of the first conductive layer of the second grid and the second conductive layer of the second grid may be different.
  • the first doped region 211 is an N-type doped region
  • the second doped region 221 can be an N-type doped region or a P-type doped region; in some embodiments, the first doped region 211 and the second doped region
  • the region 221 is an N-type doped region
  • the substrate 200 is a P-type doped region
  • the first doped region 211 and the second doped region 221 are doped with N-type ions
  • the substrate 200 is doped with P-type ions.
  • the doped region is a P-type doped region
  • the substrate is an N-type doped region
  • the doped region is doped with P-type ions
  • the substrate is doped with N-type ions.
  • the doping ions in the second doping region 221 are boron ions in the P-type ions, and in other embodiments, the doping ions can also be phosphorus ions in the N-type ions, arsenic ions, and aluminum in the P-type ions. ions, boron fluoride ions, etc.
  • the first doped region 211 on one side of the first gate 212 is used as a source, and the first doped region 211 on the other side of the first gate 212 is used as a drain; similarly, for the second gate 222 , the second doped region 221 located on one side of the second gate 222 serves as a source, and the second doped region 221 located on the other side of the second gate 222 serves as a drain.
  • the dielectric layer 203 is located on the top surface of the first doped region 211, wherein the material of the dielectric layer 203 can be silicon, silicon oxide, silicon carbide, silicon nitride and other insulating materials or other high dielectric constant materials, in some embodiments Among them, the dielectric layer 203 covers the top surface of the first doped region 211 , and the dielectric layer 203 also covers the top surface of the first gate capping layer 242 .
  • a barrier layer 230 is formed on the substrate 200 in the peripheral region 202 , and the barrier layer 230 is located on the surface of the second doped region 221 .
  • the blocking layer 230 is also located on the sidewall of the second gate 222 in the peripheral region 202 , and the material of the blocking layer 230 is different from that of the dielectric layer 203 .
  • the material of the barrier layer 230 is silicon oxide, and in other embodiments, the material of the barrier layer can also be SiNx, C.
  • the etching rate of the barrier layer 230 is lower than the etching rate of the dielectric layer 203 .
  • the barrier layer 230 By forming a barrier layer 230 on the substrate 200 in the peripheral region 202, and the barrier layer 230 is located on the surface of the second doped region 221, wherein, in the process of being etched by the same material, the rate of etching of the barrier layer 230 is lower than that of the dielectric layer 203 is etched, therefore, there is a difference between the time of adjusting the via hole formed on the barrier layer 230 and the time of the via hole formed on the dielectric layer 203, so that in the process of forming the via hole on the dielectric layer 203, Part of the second doped region 221 is etched, thereby increasing the distance between the bottom of the conductive contact structure subsequently formed in the trench of the second doped region 221 and the subsequent PN junction with the second doped region 221 as the source and drain terminals, Consequently, the leakage current between the conductive contact structure and the substrate of the semiconductor structure is reduced.
  • the process step of forming the barrier layer includes: forming a continuous initial barrier film on the surface of the substrate 200 in the core region 201 and the peripheral region 202, and then removing the initial barrier film located in the core region 201, and the remaining initial barrier film film as barrier layer 230.
  • the surface of the formed barrier layer 230 is flush with the surface of the dielectric layer 203; thus, the surfaces of the dielectric layer 203 and the barrier layer 230 on the substrate 200 are a flat surface, which simplifies the morphology of the semiconductor structure.
  • the depth of the groove formed in the second doped region 221 depends on the etching selectivity ratio of the dielectric layer 203 and the barrier layer 230, thereby achieving precise control
  • the depth of the trench is formed in the second doped region 221 , so as to precisely control the distance between the subsequently formed conductive contact structure and the PN junction.
  • the initial barrier film is formed using an atomic deposition process. In other embodiments, a chemical vapor deposition process may also be used to form the initial barrier film.
  • a mask layer 240 is formed on the substrate 200 in the core region 201 and the peripheral region 202, and the mask layer 240 is also located on the surface of the barrier layer 230 and the dielectric layer 203.
  • the material of the mask layer 240 is the same as that of the barrier layer 230. The materials are different.
  • the mask layer 240 is patterned to form an opening, and then the dielectric layer 203 of the core region 201 is etched along the opening to form a first trench 261 in the dielectric layer 203, the first The trench 261 exposes the top surface of the first doped region 211, and also etches the barrier layer 230 and part of the second doped region 221 of the peripheral region 202 along the opening, so that the barrier layer 230 and the second doped region 221
  • the second trench 262 is formed, and the depth of the first trench 261 located in the first doped region 211 is greater than the depth of the second trench 262 located in the second doped region 221, thus further increasing the second trench 262
  • the distance between the bottom (the bottom of the subsequently formed conductive contact structure) and the PN junction is conducive to reducing the contact leakage between the subsequently formed conductive contact structure and the substrate of the semiconductor structure, and is conducive to improving the stability of the semiconductor structure.
  • a wet etching process is used to remove part of the mask layer 240 and the dielectric layer 203 to form the first trench 261; thus, the first trench 261 exposes the top surface of the first doped region 211, followed by Forming the conductive column filling the first trench 261 can contact the region with the highest dopant ion concentration in the first doped region 211 , which is beneficial to improve the metal/semiconductor contact performance.
  • a dry etching process may also be used to remove part of the mask layer and dielectric layer to form the first trench; similarly, in some embodiments, a wet etching process is used to remove part of the mask layer 240 , the barrier layer 230 and the second doped region 221 to form the second trench 262; thus, the second trench 262 exposes the sidewall of the second doped region 221, and the subsequent formation of conductive columns filling the second trench 262 is just It can be in contact with the region with the highest dopant ion concentration in the second doped region 221 , which is beneficial to improve the metal/semiconductor contact performance.
  • a dry etching process may also be used to remove part of the mask layer, the barrier layer and the second doped region to form the second trench.
  • a first mask layer 241 is formed on the substrate 200 in the core region 201, and the second trench 262 is pretreated to increase the doping ion content of the second doped region 221 exposed by the second trench 262. concentration; the first mask layer 241 is removed after pretreatment.
  • the pretreatment includes: the first step of pretreatment exposing the surface of the second doped region 221 to the second trench 262 doped with fluorine ions; the second step of pretreatment exposing the second doped region 221 exposed to the second trench 262
  • the surface of the impurity region 221 is doped with the same ion type as that of the second doping region 221 .
  • the dopant ions are boron ions and aluminum ions in the P-type ions, and in some other embodiments, the dopant ions can also be phosphorus ions and arsenic ions in the N-type ions.
  • pretreatment is performed on both the first trench and the second trench.
  • a metal layer 204 is formed, and the metal layer 204 is located on the surface of the first groove 261, the surface of the second groove 262, and the surface of the mask layer 240.
  • the material of the metal layer 204 is cobalt, and in other implementations
  • the material of the metal layer can also be nickel, titanium and other metals.
  • the metal layer 204 is formed by vacuum evaporation technology, and in other embodiments, the metal layer can also be formed by sputtering technology or vapor deposition technology.
  • a metal layer is formed, and the metal layer is only located on the surface of the second trench and the surface of the mask layer directly above the second trench.
  • a first metal silicide layer 245 and a second metal silicide layer 255 are formed.
  • the process steps of forming the first metal silicide layer 245 and the second metal silicide layer 255 include: annealing the metal layer 204, and the metal layer 204 reacts with the first doped region 211 to form the first metal silicide layer 245 , the metal layer 204 reacts with the second doped region 221 to form a second metal silicide layer 255 ; the unreacted metal layer 204 is removed.
  • the material of the first metal silicide layer 245 is cobalt silicide, which is used to reduce the resistance of the diffusion region and the contact resistance of the metal/semiconductor contact hole; in other embodiments, the first metal silicide layer can be Metal silicides such as titanium silicide or nickel silicide; similarly, in some embodiments, the material of the second metal silicide layer 255 is cobalt silicide, which is used to reduce the resistance of the diffusion region and the contact resistance of the metal/semiconductor contact hole. In other embodiments, the second metal silicide layer may be metal silicide such as titanium silicide or nickel silicide.
  • the materials of the second metal silicide layer 255 and the first metal silicide layer 245 are the same, and in other embodiments, the materials of the second metal silicide layer and the first metal silicide layer may also be different.
  • only the second metal suicide layer is formed.
  • a first conductive pillar 246 and a second conductive pillar 256 are formed.
  • the first conductive pillar 246 fills the first trench 261 and protrudes from the surface of the substrate 200
  • the second conductive pillar 256 fills the second trench 262 and protrudes from the surface of the substrate 200 .
  • the process steps of forming the first conductive pillar 246 and the second conductive pillar 256 include: forming a conductive film 250 that fills the first trench 261, the second trench 262 and the opening, and the conductive film 250 is also located on the top surface of the mask layer 240 Remove the conductive film 250 higher than the top surface of the mask layer 240, the remaining conductive film 250 located in the core area 201 is used as the first conductive column 246, and the remaining conductive film 250 located in the peripheral area 202 is used as the second conductive column 256, and the mask is removed Layer 240.
  • a conductive film 250 filling the first trench 261 , the second trench 262 and the opening is formed, and the conductive film 250 is also located on the top surface of the mask layer 240 .
  • the material of the conductive film 250 is tungsten; in other embodiments, the material of the conductive film can also be metal such as silver.
  • the conductive film 250 higher than the top surface of the mask layer 240 is removed, the remaining conductive film 250 located in the core region 201 is used as the first conductive column 246, and the remaining conductive film 250 located in the peripheral area 202 is used as the second conductive column 256, Remove the masking layer.
  • the first metal silicide layer 245 is located on the bottom surface of the first trench 261, and is located between the first conductive pillar 246 and the first doped region 211; the second metal silicide layer 255 It is located at the bottom of the second trench 262 and between the second conductive pillar 256 and the second doped region 221 .
  • the contact resistance between the first metal silicide layer 245 and the second metal silicide layer 255 is small, which is beneficial to improve the conductive contact structure and the second doped region 221 to have a better conductive effect.
  • the second metal silicide layer 255 is located on the bottom surface of the second trench and forms a groove on the side wall of the second doped region 221; thus, the second metal silicide layer 255 has a relatively Large contact area, the larger the contact area, the smaller the contact resistance between the second metal silicide layer 255 and the second doped region 221, which is conducive to improving the contact resistance between the second metal silicide layer 255 and the second doped region 221. Conductive effect, thereby improving the performance of semiconductor structures.
  • the etching depth is adjusted by the etching rate of different materials, thereby increasing the distance between the bottom of the conductive contact structure and the surface of the second doped region.
  • the first conductive column is located in the first doped region and protrudes from the substrate surface; the second conductive column is located in the second doped region and protrudes from the substrate surface, and the second The depth of the conductive pillar in the second doped region is smaller than the depth of the first conductive pillar in the first doped region.
  • the depth of the first conductive pillar in the first doped region ensures that the core region and the conductive pillar have a good relationship.
  • 12 to 20 are structural schematic diagrams corresponding to each step in the method for forming a semiconductor structure provided by another embodiment of the present disclosure.
  • a substrate 300 is provided, the substrate 300 includes a core region 301 and a peripheral region 302, and the substrate 300 of the core region 301 has a first gate 312, and the first gate 312 of the core region 301 on opposite sides There is a first doped region 311 in the substrate 300, the top surface of the first doped region 311 is exposed by the substrate 300, and the top surface of the first doped region 311 has a dielectric layer 303; the substrate 300 of the peripheral region 302 has The second gate 322 has a second doped region 321 in the substrate 300 on opposite sides of the second gate 322 in the peripheral region 302 .
  • a barrier layer is deposited on the substrate 300 in the peripheral region 302 and the core region 301, and then chemical mechanical polishing or etching is performed to form a barrier layer 330 with a preset thickness, and the barrier layer 330 is located in the second doped region 321 surface and the surface of the dielectric layer 303 .
  • the barrier layer 330 has a thickness of 5-20nm.
  • the inventors have found that when the thickness is 5-20nm, the etching depth of the second conductive column in the second doped region is lower than that of the second conductive column.
  • the method for forming the semiconductor structure corresponding to each step in FIGS. 14 to 20 is the same as the method for forming the semiconductor structure corresponding to each step in FIGS. 4 to 10 , and will not be repeated here.
  • the barrier layer is formed on the substrate of the peripheral region and the core region, and the barrier layer is located on the surface of the second doped region and the surface of the dielectric layer.
  • the thickness of the barrier layer on the surface of the dielectric layer and then adjusting the depth of the first conductive pillar located in the first doped region, it is ensured that the first conductive pillar and the first doped region have good electrical conductivity; on the other hand, By adjusting the thickness of the barrier layer on the surface of the second doped region, the etching rate of different materials is different to ensure that the etching depth in the second doped region is lower than that in the first doped region, so that the second conductive pillar is far away from the
  • the depletion region helps to improve the problem of excessive leakage of the substrate of the semiconductor structure, and further helps to improve the stability of the semiconductor structure.
  • Some embodiments of the present disclosure provide a method for preparing a semiconductor structure, which can form the semiconductor structure provided in the following embodiments.
  • the semiconductor structure provided in some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • FIG. 10 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 200, the substrate 200 includes a core region 201 and a peripheral region 202, and the substrate 200 of the core region 201 has a first gate 212, and the first gate 212 of the core region 201 is opposite to
  • the substrate 200 on both sides has a first doped region 211, the substrate 200 exposes the top surface of the first doped region 211, and the top surface of the first doped region 211 has a dielectric layer 203;
  • the substrate of the peripheral region 202 200 has a second gate 222, and the substrate 200 on opposite sides of the second gate 222 of the peripheral region 202 has a second doped region 221;
  • the first conductive column 246 is located in the first doped region 211, and the convex Out of the surface of the substrate 200;
  • the second conductive pillar 256 is located in the second doped region 221, and protrudes from the surface of the substrate 200, and the depth of the second conductive pillar 256 in the second doped region 221 is smaller than
  • the core area 201 is used to connect the conductive structure to form a memory unit
  • the peripheral area 202 is used to connect the conductive structure to form a logic unit to ensure that the functions of the core area are realized.
  • the material of the substrate 200 is a semiconductor material. Specifically, in some embodiments, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon germanium or silicon carbide.
  • the first gate 212 of the core region 201 is a buried gate
  • the second gate 222 of the peripheral region 202 is a planar gate
  • the core region 101 further includes a first gate spacer 232 and a first gate capping layer 242 .
  • the first gate spacer 232 covers the bottom wall and the sidewall of the first gate 212 , and is used to block the particles of the first gate 212 from interdiffusion with the particles of the first doped region 211 .
  • the material of the first gate spacer 232 is metal oxide, such as titanium nitride, tantalum nitride, titanium or tantalum.
  • the first gate capping layer 242 covers the surface of the first gate 212 for isolating the first gate 212 from the dielectric layer 203, wherein the material of the first gate capping layer 242 is an insulating material, such as silicon dioxide , silicon carbide or silicon nitride.
  • the material of the first gate 212 is metal tungsten, and in other embodiments, the material of the first gate may also be other metal materials such as copper or aluminum.
  • the first gate 212 includes a first gate first conductive layer. In other embodiments, the first gate includes a first gate first conductive layer, a first gate dielectric layer stacked in sequence. and the second conductive layer of the first gate, and the materials of the first conductive layer of the first gate and the second conductive layer of the first gate may be different.
  • the peripheral region 202 further includes a second gate oxide layer 252 covering the substrate 200 , and the second gate oxide layer 252 is located between the substrate 200 and the second gate 222 .
  • the material of the second gate oxide layer 252 is an insulating material for isolating the second gate 222 from the substrate 200 , such as silicon dioxide, silicon carbide or silicon nitride.
  • the material of the second gate oxide layer 252 is the same as that of the first gate capping layer 242 , and in other embodiments, the material of the second gate oxide layer and the first gate capping layer may also be different.
  • the material of the second gate 222 is metal tungsten, and in other embodiments, the material of the second gate 222 may also be other metal materials such as copper or aluminum. In some embodiments, the materials of the first gate 212 and the second gate 222 are the same, and in other embodiments, the materials of the first gate and the second gate may also be different.
  • the second gate 222 includes the first conductive layer of the second gate, and in other embodiments, the second gate includes the first conductive layer of the second gate, the second gate dielectric layer stacked in sequence. and the second conductive layer of the second grid, and the materials of the first conductive layer of the second grid and the second conductive layer of the second grid may be different.
  • the first doped region 211 is an N-type doped region
  • the second doped region 221 can be an N-type doped region or a P-type doped region; in some embodiments, the first doped region 211 and the second doped region
  • the region 221 is an N-type doped region
  • the substrate 200 is a P-type doped region
  • the first doped region 211 and the second doped region 221 are doped with N-type ions
  • the substrate 200 is doped with P-type ions.
  • the doped region is a P-type doped region
  • the substrate is an N-type doped region
  • the doped region is doped with P-type ions
  • the substrate is doped with N-type ions.
  • the doping ions in the second doping region 221 are boron ions in the P-type ions, and in other embodiments, the doping ions can also be phosphorus ions in the N-type ions, arsenic ions, and aluminum in the P-type ions. ions, boron fluoride ions, etc.
  • the first doped region 211 on one side of the first gate 212 is used as a source, and the first doped region 211 on the other side of the first gate 212 is used as a drain; similarly, for the second gate 222 , the second doped region 221 located on one side of the second gate 222 serves as a source, and the second doped region 221 located on the other side of the second gate 222 serves as a drain.
  • the dielectric layer 203 is located on the top surface of the first doped region 211, wherein the material of the dielectric layer 203 can be silicon, silicon oxide, silicon carbide, silicon nitride and other insulating materials or other high dielectric constant materials, in some embodiments Among them, the dielectric layer 203 covers the top surface of the first doped region 211 , and the dielectric layer 203 also covers the top surface of the first gate capping layer 242 .
  • the first conductive pillars 246 are located in the first doped region 211 and protrude from the surface of the substrate 200 , which is beneficial for the core region and the conductive pillars to have good electrical conductivity.
  • the material of the second conductive pillar 256 is the same as that of the first conductive pillar 246 , which is tungsten. In other embodiments, the materials of the second conductive pillar and the first conductive pillar may be different.
  • the second conductive column 256 is located in the second doped region 221 and protrudes from the surface of the substrate 200 , and the depth of the second conductive column 256 located in the second doped region 221 is smaller than that of the first conductive column 246 located in the dielectric layer 203 depth.
  • the distance between the second conductive pillar 256 and the PN junction depletion region in the second doping 221 increases, and the width of the PN junction depletion region is narrowed under the influence of high dopant ion concentration, which is beneficial for doping ions /Semiconductor contact is prepared by high doping ion concentration to prepare excellent ohmic contact, which can effectively avoid the situation that the contact resistance between the conductive contact structure and the semiconductor is too large, and is conducive to improving the stability of the semiconductor structure.
  • the first metal silicide layer 245 is located between the first conductive pillar 246 and the first doped region 211; the second metal silicide layer 255 is located between the second conductive pillar 256 and the second doped region 221, and the second metal silicide layer 255 is located between the second conductive pillar 256 and the second doped region 221, and The two metal silicide layer 255 is located on the bottom surface of the second conductive pillar 256 .
  • the material of the first metal silicide layer 245 is cobalt silicide, which is used to reduce the resistance of the diffusion region and the contact resistance of the metal/semiconductor contact hole; in other embodiments, the first metal silicide layer can also be It is a metal silicide such as titanium silicide or nickel silicide.
  • the second metal silicide layer 255 is made of the same material as the first metal silicide layer 245. In other embodiments, the second metal silicide layer The materials of the second metal silicide layer and the first metal silicide layer can also be different. Therefore, the contact resistance of the second metal silicide layer is small, which is beneficial to improve the conductive effect of the second conductive column and the second doped region.
  • FIG. 11 is another structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the second metal silicide layer is located on the bottom and side surfaces of the second conductive pillar, therefore, the second metal silicide layer has a larger contact area with the second doped region, and the larger the contact area. The smaller the contact resistance between the second metal silicide layer and the second doped region, the better the conduction effect between the second metal silicide layer and the second doped region, thereby improving the stability of the semiconductor structure.
  • the second metal silicide layer 255 also contains fluorine ions.
  • fluorine ions By doping fluorine ions and additionally implanting ions of the same type as the doping ions in the second doping region, the concentration of doping ions in the second doping region exposed by the second trench is increased, and the contact resistance of the metal/semiconductor is reduced.
  • Another embodiment of the present disclosure also provides a semiconductor structure.
  • the semiconductor structure provided by another embodiment of the present disclosure is substantially the same as the semiconductor structure provided by the foregoing embodiment, and the main difference includes the first aspect of the semiconductor structure provided by another embodiment of the present disclosure.
  • the depth of the conductive column in the first doped region is smaller than the depth of the first conductive column in the first doped region of the semiconductor structure provided in the foregoing embodiments, and the second conductive column of the semiconductor structure provided in another embodiment of the present disclosure
  • the depth in the second doped region is also smaller than the depth of the second conductive pillar of the semiconductor structure provided in the foregoing embodiments in the second doped region.
  • FIG. 20 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 300, the substrate 300 includes a core region 301 and a peripheral region 302, and the substrate 300 of the core region 301 has a first gate 312, and the first gate 312 of the core region 301 is opposite to
  • the substrate 300 on both sides has a first doped region 311, the substrate 300 exposes the top surface of the first doped region 311, and the top surface of the first doped region 311 has a dielectric layer 303;
  • the substrate of the peripheral region 302 300 has a second gate 322, and the substrate 300 on opposite sides of the second gate 322 of the peripheral region 302 has a second doped region 321;
  • the first conductive column 346 is located in the first doped region 311, and the convex Out of the surface of the substrate 300;
  • the second conductive pillar 356 is located in the second doped region 321, and protrudes from the surface of the substrate 300, and the depth of the second conductive pillar 356 in the second doped region 321 is smaller than that of the first conductive
  • the semiconductor structure provided by another embodiment of the present disclosure is substantially the same as the semiconductor structure provided by the foregoing embodiments, so details are not repeated here.
  • the semiconductor structure and the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure can solve the problem of excessive substrate leakage caused by shallow junction depth and excessively deep contact vias in the existing semiconductor structure, and improve the stability of the semiconductor structure.

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Abstract

本公开公布一种半导体结构及其制备方法，其中，半导体结构包括：衬底，衬底包括核心区以及外围区，且核心区的衬底内具有第一栅极，核心区的第一栅极相对两侧的衬底内具有第一掺杂区，衬底暴露出第一掺杂区的顶面，第一掺杂区的顶面具有介质层；外围区的衬底上具有第二栅极，外围区的第二栅极相对两侧的衬底内具有第二掺杂区；第一导电柱，所述第一导电柱位于所述第一掺杂区内，且凸出于所述衬底表面；第二导电柱，第二导电柱位于第二掺杂区内，且凸出于衬底表面，且第二导电柱位于第二掺杂区内的深度小于第一导电柱位于第一掺杂区内的深度。

Description

半导体结构和半导体结构的制备方法
本公开基于申请号为202110996603.1、申请日为2021年08月27日、申请名称为“半导体结构和半导体结构的制备方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及但不限于一种半导体结构及半导体结构的制备方法。
背景技术
随着集成电路工艺、制程技术的不断发展，为了提高集成电路的集成度，晶体管(MOS)器件的特征尺寸不断缩小。在高介电材料金属栅(HKMG)、鳍式晶体管(Finfet)等工艺节点下，在提升MOS器件的工作速度和降低它的功耗的同时，需要面对一系列问题。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体结构及半导体结构的制备方法，可以解决现有半导体结构结深变浅，接触通孔过深导致的衬底漏电过大的问题。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制备方法，包括：提供衬底，衬底包括核心区以及外围区，且核心区以及外围区的衬底上均具有栅极结构，核心区的栅极结构相对两侧的衬底内具有第一掺杂区，外围区的栅极结构相对两侧的衬底内具有第二掺杂区；在外围区的衬底上形成阻挡层，阻挡层位于第二掺杂区表面；在核心区以及外围区的衬底上形成具有开口的掩膜层，且掩膜层还位于阻挡层表面，掩膜层的材料与阻挡层的材料不同；以掩膜层为掩膜，沿所述开口刻蚀核心区的介质层以及第一掺杂区，以在第一掺杂区内形成第一沟槽，同时还沿开口刻蚀外围区的阻挡层以及第二掺杂区，以在第二掺杂区内形成第二沟槽，且第一沟槽的深度大于第二沟槽的深度；形成第一导电柱，第一导电柱填充满第一沟槽且凸出于衬底表面；形成第二导电柱，第二导电柱填充满第二沟槽且凸出于衬底表面。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，包括：衬底，衬底包括核心区以及外围区，且核心区以及外围区的衬底上均具有栅极结构，核心区的栅极结构相对两侧的衬底内具有第一掺杂区，外围区的栅极结构相对两侧的衬底内具有第二掺杂区；第一导电柱，第一导电柱位于第一掺杂区内，且凸出于衬底表面；第二导电柱，第二导电柱位于第二掺杂区内，且凸出于衬底表面，且第二导电柱位于第二掺杂区内的深度小于第一导电柱位于第一掺杂区内的深度。
本公开一些实施例提供的技术方案至少具有以下优点：本公开一些实施例中，通过在外围区的衬底上形成阻挡层，且阻挡层位于第二掺杂区表面，通过不同材质的刻蚀速率来调整刻蚀深度，从而增大导电接触结构底部与源漏区和衬底直接形成的PN结的耗尽区的距离，进而改善此导电接触结构与半导体衬底的接触处漏电问题。本公开一些实施例降低了第二导电柱位于第二掺杂区内的深度，使得第二导电柱远离源漏区和衬底之间形成的PN结的耗尽区，有利于提高半导体结构的稳定性；另外，第一导电柱位于第一掺杂区内，且凸出于衬底表面；第二导电柱位于第二掺杂区内，且凸出于衬底表面，且第二导电柱位于第二掺杂区内的深度小于第一导电 柱位于第一掺杂区内的深度，一方面第一导电柱位于第一掺杂区内的深度保证了核心区与导电柱具有良好的导电性，另一方面可以避免第二导电柱位于第二掺杂区内的深度极大导致第二导电柱可能触及到源漏区和衬底直接形成的PN结的耗尽区，有利于改善半导体结构的衬底漏电过大的问题。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为一种半导体结构的结构示意图；
图2～图10为本公开一实施例提供的半导体结构的形成方法中各步骤对应的结构示意图；
图11为本公开一实施例提供的半导体结构的另一种结构示意图；
图12～图20为本公开另一实施例提供的半导体结构的形成方法中各步骤对应的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
目前，现有半导体结构的源漏区结深变浅，但是接触通孔的深度过深，会导致和衬底之间的漏电。
分析发现，导致上述问题的主要原因包括：随着器件尺寸的不断缩小，导电接触结构与源漏极的耗尽区的距离不断变窄，会导致与衬底之间的漏电通道的形成。图1为一种半导体结构示意图，现结合图1进行分析，其中，衬底100包括核心区101以及外围区102，且核心区101内具有第一栅极112，外围区102上具有第二栅极122，第一栅极112相对两侧的核心区101内具有第一掺杂区111，第二栅极122相对两侧的外围区102内具有第二掺杂区121；介质层103，位于核心区101顶部表面；第一导电柱146，第一导电柱146部分位于第一掺杂区111内，且部分凸出于衬底100表面；第二导电柱156，第二导电柱156部分位于第二掺杂区121内，且部分凸出于衬底100表面，且由于生产工艺的统一性，第二导电柱156位于第二掺杂区121内的深度与第一导电柱146位于介质层103内的深度相同。其中，对于半导体PN结，由于界面(P型半导体与N型半导体的接触面)两侧半导体原有化学势的差异导致界面附近能带弯曲，能带弯曲区域载流子浓度下降的界面区域为耗尽区，由于源漏区和衬底之间存在PN界面，第二导电柱156位于第二掺杂区121内的深度比较大，第二导电柱156与耗尽区的距离也较小，因此导电接触结构与半导体结构的衬底接触漏电增大。
其中，掺杂区可以作为半导体结构的源极或漏极，掺杂区离子浓度为高斯掺杂分布，其中，越靠近衬底表面的区域掺杂浓度越小。高掺杂时位于耗尽区两侧的半导体中载流子的浓度差大，多数载流子的扩散运动剧烈，空间电荷区理论上变宽，但是空间电荷区产生的内电场导致少数载流子的漂移运动也剧烈，空间电荷区理论 上变窄，最终多数载流子的扩散运动速率与少数载流子的漂移运动速率达到动态平衡，高掺杂时载流子达到动态平衡的时间相比低掺杂时载流子达到动态平衡的时间更短，电子和空穴复合时间缩短，耗尽区的宽度变窄。当第二导电柱156位于第二掺杂区121内的深度相对比较大时，耗尽区两端处于低掺杂区，所形成的耗尽区的厚度较厚，导致第二导电柱156与耗尽区的距离变窄，而且随着器件尺寸微缩，导电柱与耗尽区的距离更小，导电接触结构与半导体结构的衬底接触漏电增大，严重影响半导体结构的稳定性。
本公开一些实施例提供一种半导体结构和半导体结构的制备方法。通过在外围区的衬底上形成阻挡层，且阻挡层位于第二掺杂区表面，来调整刻蚀深度，从而增大导电接触结构底部与源漏端/衬底之间形成的PN结的距离，进而减少此导电接触结构与半导体的衬底之间的漏电。本公开实施例降低了第二导电柱位于第二掺杂区内的深度，使得第二导电柱远离耗尽区，同时通过预处理对第二掺杂区进行离子掺杂，因此，导电接触结构与半导体的接触电阻较小，有利于提高半导体结构的导电性能，且导电接触结构与半导体结构的衬底接触漏电较小，进而有利于提高半导体结构的稳定性。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图2～图10本公开一实施例提供的半导体结构的形成方法中各步骤对应的结构示意图。
参考图2，提供衬底200，衬底200包括核心区201以及外围区202，且核心区201的衬底200内具有第一栅极212，核心区201的第一栅极212相对两侧的衬底200内具有第一掺杂区211，衬底200暴露出第一掺杂区211的顶面，第一掺杂区211的顶面具有介质层203；外围区202的衬底200上具有第二栅极222，外围区202的第二栅极222相对两侧的衬底200内具有第二掺杂区221。
在一些实施例中，核心区201用于连接导电结构形成存储单元，外围区202用于连接导电结构形成逻辑单元用于保证核心区的功能得以实现。
衬底200的材料为半导体材料。在一些实施例中，衬底200的材料为硅。在其他实施例中，衬底的材料也可以为锗、锗硅或碳化硅。
在一些实施例中，核心区201的第一栅极212为埋置栅，外围区202的第二栅极222为平面栅。
其中，核心区201还包括第一栅极侧墙232和第一栅极盖层242。
第一栅极侧墙232覆盖于第一栅极212的底壁和侧壁，用于阻挡第一栅极212的粒子与第一掺杂区211的粒子的相互扩散。其中，第一栅极侧墙232的材料为金属氧化物，例如，氮化钛、氮化钽、钛或钽。
第一栅极盖层242覆盖在第一栅极212表面，用于将第一栅极212与介质层203隔离，其中，第一栅极盖层242的材料为绝缘材料，例如，二氧化硅、碳化硅或氮化硅。在一些实施例中，第一栅极212的材料为金属钨，在其他实施例中，第一栅极的材料也可以为铜或者铝等其他金属材料。
在一些实施例中，第一栅极212包括第一栅极第一导电层，在其他实施例中，第一栅极包括依次堆叠的第一栅极第一导电层、第一栅极介质层及第一栅极第二导电层，且第一栅极第一导电层和第一栅极第二导电层的材料可以不同。
外围区202还包括覆盖在衬底200上的第二栅极氧化层252，且第二栅极氧化层 252位于衬底200与第二栅极222之间。
第二栅极氧化层252的材料为绝缘材料，用于将第二栅极222与衬底200隔离，例如，二氧化硅、碳化硅或氮化硅。在一些实施例中，第二栅极氧化层252与第一栅极盖层242材料相同，在其他实施例中，第二栅极氧化层与第一栅极盖层材料也可以不同。
在一些实施例中，第二栅极222的材料为金属钨，在其他实施例中，第二栅极222的材料也可以为铜或者铝等其他金属材料。在一些实施例中，第一栅极212与第二栅极222材料相同，在其他实施例中，第一栅极与第二栅极材料也可以不同。
在一些实施例中，第二栅极222包括第二栅极第一导电层，在其他实施例中，第二栅极包括依次堆叠的第二栅极第一导电层、第二栅极介质层及第二栅极第二导电层，且第二栅极第一导电层和第二栅极第二导电层的材料可以不同。
第一掺杂区211为N型掺杂区，第二掺杂区221可以为N型掺杂区或P型掺杂区；在一些实施例中，第一掺杂区211和第二掺杂区221为N型掺杂区，衬底200为P型掺杂区，第一掺杂区211和第二掺杂区221内掺杂有N型离子，衬底200掺杂有P型离子。在其他实施例中，掺杂区为P型掺杂区，衬底为N型掺杂区，掺杂区掺杂有P型离子，衬底掺杂有N型离子。其中，第二掺杂区221的掺杂离子为P型离子中的硼离子，在其他实施例中，掺杂离子还可为N型离子中的磷离子、砷离子和P型离子中的铝离子、氟化硼离子等。
对于第一栅极212，位于第一栅极212一侧的第一掺杂区211作为源极，位于第一栅极212另一侧的第一掺杂区211作为漏极；同理，对于第二栅极222，位于第二栅极222一侧的第二掺杂区221作为源极，位于第二栅极222另一侧的第二掺杂区221作为漏极。
介质层203，位于第一掺杂区211的顶面，其中，介质层203的材料可以为硅、氧化硅、碳化硅、氮化硅等绝缘材料或其他高介电常数材料，在一些实施例中，介质层203覆盖在第一掺杂区211顶面，介质层203还覆盖第一栅极盖层242的上表面。
参考图3，在外围区202的衬底200上形成阻挡层230，阻挡层230位于第二掺杂区221表面。
其中，阻挡层230还位于外围区202的第二栅极222的侧壁，阻挡层230的材料与介质层203的材料不同。在一些实施例中，阻挡层230的材料为氧化硅，在其他实施例中，阻挡层的材料还可为SiNx、C。
其中，被同一材料刻蚀的过程中，阻挡层230的被刻蚀速率小于介质层203的被刻蚀速率。
通过在外围区202的衬底200上形成阻挡层230，且阻挡层230位于第二掺杂区221表面，其中，被同一材料刻蚀的过程中，阻挡层230的被刻蚀速率小于介质层203的被刻蚀速率，因此，来调整在阻挡层230上形成的通孔的时间和在介质层203上形成的通孔的时间存在差异，使在介质层203上形成通孔的过程中，部分第二掺杂区221被刻蚀，从而增大后续在第二掺杂区221沟槽内形成的导电接触结构的底部与后续以第二掺杂区221作为源漏端的PN结的距离，进而减小导电接触结构与半导体结构的衬底之间的漏电电流。
本公开一些实施例中，形成阻挡层的工艺步骤包括：在核心区201以及外围区202的衬底200表面形成连续的初始阻挡膜，然后去除位于核心区201的初始阻挡膜，剩余的初始阻挡膜作为阻挡层230。
形成的阻挡层230的表面与介质层203的表面齐平；如此，衬底200上的介质层203和阻挡层230的表面为一个平整的面，简化了半导体结构的形貌。通过保证介质 层203和阻挡层230的表面为一个平整的面，使得在第二掺杂区221中形成沟槽的深度取决于介质层203和阻挡层230的刻蚀选择比，从而实现精准控制在第二掺杂区221中形成沟槽的深度，进而实现精准控制后续形成的导电接触结构与PN结的距离。
在一些实施例中，采用原子沉积工艺形成初始阻挡膜。在其他实施例中，也可以采用化学气相沉积工艺形成初始阻挡膜。
参考图4，在核心区201以及外围区202的衬底200上形成掩膜层240，且掩膜层240还位于阻挡层230和介质层203表面，掩膜层240的材料与阻挡层230的材料不同。
参考图5，以掩膜层240为掩膜，图案化掩膜层240形成开口，再沿开口刻蚀核心区201的介质层203，以在介质层203内形成第一沟槽261，第一沟槽261暴露出第一掺杂区211的顶面，且还沿开口刻蚀外围区202的阻挡层230以及部分第二掺杂区221，以在阻挡层230和第二掺杂区221内形成第二沟槽262，且第一沟槽261位于第一掺杂区211的深度大于第二沟槽262位于第二掺杂区221中的深度，如此，进一步增加了，第二沟槽262底部(后续形成导电接触结构的底部)与PN结的距离，有利于减小后续形成的导电接触结构与半导体结构的衬底接触漏电，有利于提高半导体结构的稳定性。
在一些实施例中，采用湿法刻蚀工艺去除部分掩膜层240和介质层203，形成第一沟槽261；如此，第一沟槽261暴露出第一掺杂区211的顶面，后续形成填充第一沟槽261的导电柱就可以和第一掺杂区211内掺杂离子浓度最大的区域接触，有利于提高金属/半导体接触性能。在其他实施例中，也可以采用干法刻蚀工艺去除部分掩膜层和介质层，形成第一沟槽；同理，在一些实施例中，采用湿法刻蚀工艺去除部分掩膜层240、阻挡层230和第二掺杂区221，形成第二沟槽262；如此，第二沟槽262暴露出第二掺杂区221的侧壁，后续形成填充第二沟槽262的导电柱就可以和第二掺杂区221内掺杂离子浓度最大的区域接触，有利于提高金属/半导体接触性能。在其他实施例中，也可以采用干法刻蚀工艺去除部分掩膜层、阻挡层和第二掺杂区，形成第二沟槽。
参考图6，在核心区201的衬底200上形成第一掩膜层241，对第二沟槽262进行预处理，以提高第二沟槽262露出的第二掺杂区221的掺杂离子的浓度；预处理后去除第一掩膜层241。
在一些实施例中，预处理包括：第一步预处理向第二沟槽262露出第二掺杂区221表面掺杂氟离子；第二步预处理向第二沟槽262露出的第二掺杂区221表面掺杂与第二掺杂区221的掺杂离子类型相同的离子。通过掺杂氟离子和额外注入与第二掺杂区的掺杂离子类型相同的离子，提高第二沟槽露出的第二掺杂区的掺杂离子的浓度，降低金属/半导体的接触电阻。
在一些实施例中，掺杂离子为P型离子中的硼离子和铝离子，其他一些实施例中，掺杂离子还可为N型离子中的磷离子、砷离子等。
在其他实施例中，对第一沟槽以及第二沟槽都进行预处理。
参考图7，形成金属层204，金属层204位于第一沟槽261表面、第二沟槽262表面以及掩膜层240表面，在一些实施例中，金属层204的材料为钴，在其他实施例中，金属层的材料还可为镍，钛等金属。
在一些实施例中，通过真空蒸发技术形成金属层204，在其他实施例中，还可通过溅射技术或气相沉积技术形成金属层。
在其他实施例中，形成金属层，金属层仅位于第二沟槽表面以及第二沟槽正上方的掩膜层表面。
参考图8，形成第一金属硅化物层245以及第二金属硅化物层255。
形成第一金属硅化物层245以及第二金属硅化物层255的工艺步骤包括：对金属层204进行退火处理，金属层204与第一掺杂区211发生反应，以形成第一金属硅化物层245，金属层204与第二掺杂区221发生反应，以形成第二金属硅化物层255；去除未发生反应的金属层204。
在一些实施例中，第一金属硅化物层245的材料为硅化钴，用于降低扩散区的电阻和金属/半导体接触孔的接触电阻；在其他实施例中，第一金属硅化物层可以为硅化钛或硅化镍等金属硅化物；同理，在一些实施例中，第二金属硅化物层255的材料为硅化钴，用于降低扩散区的电阻和金属/半导体接触孔的接触电阻，在其他实施例中，第二金属硅化物层可以为硅化钛或硅化镍等金属硅化物。
在一些实施例中，第二金属硅化物层255和第一金属硅化物层245的材料相同，在其他实施例中，第二金属硅化物层和第一金属硅化物层的材料也可以不同。
在其他实施例中，仅形成第二金属硅化物层。
参考图9和图10，形成第一导电柱246以及第二导电柱256。其中，第一导电柱246填充满第一沟槽261且凸出于衬底200表面，第二导电柱256填充满第二沟槽262且凸出于衬底200表面。
形成第一导电柱246以及第二导电柱256的工艺步骤包括：形成填充满第一沟槽261、第二沟槽262以及开口的导电膜250，且导电膜250还位于掩膜层240顶面；去除高于掩膜层240顶面的导电膜250，位于核心区201的剩余导电膜250作为第一导电柱246，位于外围区202的剩余导电膜250作为第二导电柱256，去除掩膜层240。
参考图9，形成填充满第一沟槽261、第二沟槽262以及开口的导电膜250，且导电膜250还位于掩膜层240顶面。
在一些实施例中，导电膜250的材料为钨；在其他实施例中，导电膜的材料还可以为银等金属。
参考图10，去除高于掩膜层240顶面的导电膜250，位于核心区201的剩余导电膜250作为第一导电柱246，位于外围区202的剩余导电膜250作为第二导电柱256，去除掩膜层。
需要说明的是，在一些实施例中，第一金属硅化物层245位于第一沟槽261底面，且位于第一导电柱246与第一掺杂区211之间；第二金属硅化物层255位于第二沟槽262底面，且位于第二导电柱256与所述第二掺杂区221之间。
第一金属硅硅化物245与第二金属硅化物层255的接触电阻较小，有利于提高导电接触结构和第二掺杂区221具有更好的导电效果。
在一些实施例中，第二金属硅化物层255位于第二沟槽底面和第二掺杂区221侧璧形成凹槽；如此，第二金属硅化物层255与第二掺杂区221具有较大的接触面积，接触面积越大，第二金属硅化物层255与第二掺杂区221之间的接触电阻越小，有利于提高第二金属硅化物层255与第二掺杂区221的导电效果，进而提高半导体结构的性能。
在一些实施例中，通过在外围区的衬底上形成阻挡层，且阻挡层位于第二掺杂区表面，通过不同材质的刻蚀速率来调整刻蚀深度，从而增大导电接触结构底部与源漏端/衬底之间形成的PN结的距离，进而调整此导电接触结构与半导体结构的衬底之间的接触漏电。本公开一些实施例降低了第二导电柱位于第二掺杂区内的深度，使得第二导电柱远离耗尽区，有利于改善半导体结构的衬底漏电过大的问题，进而有利于提高半导体结构的稳定性；另外，第一导电柱位于第一掺杂区内，且凸出于衬底表面；第二导电柱位于第二掺杂区内，且凸出于衬底表面，且第二导电柱位于第二掺杂区内的深度小于第一导电柱位于第一掺杂区内的深度，一方面第一导电柱 位于第一掺杂区内的深度保证了核心区与导电柱具有良好的导电性，另一方面可以避免第二导电柱位于第二掺杂区内的深度极大而导致半导体结构的衬底漏电过大的问题。图12～图20为本公开另一实施例提供的半导体结构的形成方法中各步骤对应的结构示意图。
参考图12，提供衬底300，衬底300包括核心区301以及外围区302，且核心区301的衬底300内具有第一栅极312，核心区301的第一栅极312相对两侧的衬底300内具有第一掺杂区311，衬底300暴露出第一掺杂区311的顶面，第一掺杂区311的顶面具有介质层303；外围区302的衬底300上具有第二栅极322，外围区302的第二栅极322相对两侧的衬底300内具有第二掺杂区321。
参考图13，在外围区302和核心区301的衬底300上沉积阻挡层，再通过化学机械抛光或者刻蚀，形成具有预设厚度的阻挡层330，阻挡层330位于第二掺杂区321表面以及介质层303表面。
垂直于衬底300的方向上，阻挡层330的厚度为5-20nm，经发明人发现，厚度为5-20nm的时候，第二导电柱在第二掺杂区内的刻蚀深度低于第一导电柱在第一掺杂区内的刻蚀深度。
图14～图20中各步骤对应的半导体结构的形成方法与图4～图10中各步骤对应的半导体结构的形成方法相同，在这里不过多赘述。
在一些实施例中，通过在外围区和核心区的衬底上形成阻挡层，阻挡层位于第二掺杂区表面以及介质层表面。一方面，通过调整阻挡层在介质层表面的厚度，进而调整第一导电柱位于第一掺杂区的深度，保证第一导电柱与第一掺杂区有良好的导电性能；另一方面，通过调整阻挡层在第二掺杂区表面的厚度，利用不同材质的刻蚀速率不同保证在第二掺杂区刻蚀深度低于在第一掺杂区刻蚀深度，从而第二导电柱远离耗尽区，有利于改善半导体结构的衬底漏电过大的问题，进而有利于提高半导体结构的稳定性。
本公开一些实施例提供一种半导体结构的制备方法，该半导体结构的制备方法可以形成下一些实施例提供的半导体结构，以下将结合附图对本公开一些实施例提供的半导体结构进行详细说明。
图10为本公开一实施例提供的半导体结构的一种结构示意图。
参考图10，半导体结构包括：衬底200，衬底200包括核心区201以及外围区202，且核心区201的衬底200内具有第一栅极212，核心区201的第一栅极212相对两侧的衬底200内具有第一掺杂区211，衬底200暴露出第一掺杂区211的顶面，第一掺杂区211的顶面具有介质层203；外围区202的衬底200上具有第二栅极222，外围区202的第二栅极222相对两侧的衬底200内具有第二掺杂区221；第一导电柱246位于第一掺杂区211内，且凸出于衬底200表面；第二导电柱256位于第二掺杂区221内，且凸出于衬底200表面，且第二导电柱256位于第二掺杂区221内的深度小于第一导电柱246位于第一掺杂区211内的深度。
在一些实施例中，核心区201用于连接导电结构形成存储单元，外围区202用于连接导电结构形成逻辑单元用于保证核心区的功能得以实现。
衬底200的材料为半导体材料。具体地，在一些实施例中，衬底200的材料为硅。在其他实施例中，衬底的材料也可以为锗、锗硅或碳化硅。
在一些实施例中，核心区201的第一栅极212为埋置栅，外围区202的第二栅极222为平面栅。
其中，核心区101还包括第一栅极侧墙232和第一栅极盖层242。
第一栅极侧墙232覆盖于第一栅极212的底壁和侧壁，用于阻挡第一栅极212的粒子与第一掺杂区211的粒子的相互扩散。其中，第一栅极侧墙232的材料为金属氧 化物，例如，氮化钛、氮化钽、钛或钽。
第一栅极盖层242覆盖在第一栅极212表面，用于将第一栅极212与介质层203隔离，其中，第一栅极盖层242的材料为绝缘材料，例如，二氧化硅、碳化硅或氮化硅。在一些实施例中，第一栅极212的材料为金属钨，在其他实施例中，第一栅极的材料也可以为铜或者铝等其他金属材料。
在一些实施例中，第一栅极212包括第一栅极第一导电层，在其他实施例中，第一栅极包括依次堆叠的第一栅极第一导电层、第一栅极介质层及第一栅极第二导电层，且第一栅极第一导电层和第一栅极第二导电层的材料可以不同。
外围区202还包括覆盖在衬底200上的第二栅极氧化层252，且第二栅极氧化层252位于衬底200与第二栅极222之间。
第二栅极氧化层252的材料为绝缘材料，用于将第二栅极222与衬底200隔离，例如，二氧化硅、碳化硅或氮化硅。在一些实施例中，第二栅极氧化层252与第一栅极盖层242材料相同，在其他实施例中，第二栅极氧化层与第一栅极盖层材料也可以不同。
在一些实施例中，第二栅极222的材料为金属钨，在其他实施例中，第二栅极222的材料也可以为铜或者铝等其他金属材料。在一些实施例中，第一栅极212与第二栅极222材料相同，在其他实施例中，第一栅极与第二栅极材料也可以不同。
在一些实施例中，第二栅极222包括第二栅极第一导电层，在其他实施例中，第二栅极包括依次堆叠的第二栅极第一导电层、第二栅极介质层及第二栅极第二导电层，且第二栅极第一导电层和第二栅极第二导电层的材料可以不同。
第一掺杂区211为N型掺杂区，第二掺杂区221可以为N型掺杂区或P型掺杂区；在一些实施例中，第一掺杂区211和第二掺杂区221为N型掺杂区，衬底200为P型掺杂区，第一掺杂区211和第二掺杂区221内掺杂有N型离子，衬底200掺杂有P型离子。在其他实施例中，掺杂区为P型掺杂区，衬底为N型掺杂区，掺杂区掺杂有P型离子，衬底掺杂有N型离子。其中，第二掺杂区221的掺杂离子为P型离子中的硼离子，在其他实施例中，掺杂离子还可为N型离子中的磷离子、砷离子和P型离子中的铝离子、氟化硼离子等。
对于第一栅极212，位于第一栅极212一侧的第一掺杂区211作为源极，位于第一栅极212另一侧的第一掺杂区211作为漏极；同理，对于第二栅极222，位于第二栅极222一侧的第二掺杂区221作为源极，位于第二栅极222另一侧的第二掺杂区221作为漏极。
介质层203，位于第一掺杂区211的顶面，其中，介质层203的材料可以为硅、氧化硅、碳化硅、氮化硅等绝缘材料或其他高介电常数材料，在一些实施例中，介质层203覆盖在第一掺杂区211顶面，介质层203还覆盖第一栅极盖层242的上表面。
第一导电柱246位于第一掺杂区211内，且凸出于衬底200表面，有利于核心区与导电柱具有良好的导电性。
在一些实施例中，第二导电柱256和第一导电柱246的材料一样，均为钨，其他实施例中，第二导电柱和第一导电柱的材料可以不同。
第二导电柱256位于第二掺杂区221内，且凸出于衬底200表面，且第二导电柱256位于第二掺杂区221内的深度小于第一导电柱246位于介质层203内的深度。
这样，第二导电柱256与第二掺杂221内的PN结耗尽区的距离增大，受高掺杂离子浓度影响，PN结耗尽区的宽度变窄，有利于掺杂离子在金属/半导体接触处通过高掺杂离子浓度制备优良的欧姆接触，有效避免导电接触结构与半导体的接触电阻阻值过大的情况，有利于提高半导体结构的稳定性。
第一金属硅化物层245位于第一导电柱246与第一掺杂区211之间；第二金属硅化物层255位于第二导电柱256与所述第二掺杂区221之间，且第二金属硅化物层255位于第二导电柱256底面。
在一些实施例中，第一金属硅化物层245的材料为硅化钴，用来降低扩散区的电阻和金属/半导体接触孔的接触电阻；在其他实施例中，第一金属硅化物层还可为硅化钛或硅化镍等金属硅化物，同理，在一些实施例中，第二金属硅化物层255和第一金属硅化物层245的材料相同，在其他实施例中，第二金属硅化物层和第一金属硅化物层的材料也可以不同，因此，第二金属硅化物层的接触电阻较小，有利于提高第二导电柱和第二掺杂区的导电效果。
图11为本公开一实施例提供的半导体结构的另一种结构示意图。
参考图11，在其他实施例中，第二金属硅化物层位于第二导电柱底面和侧面，因此，第二金属硅化物层与第二掺杂区具有较大的接触面积，接触面积越大，第二金属硅化物层与第二掺杂区之间的接触电阻越小，有利于提高第二金属硅化物层与第二掺杂区的导电效果，进而提高半导体结构的稳定性。
继续参考图10，第二金属硅化物层255内还具有氟离子。通过掺杂氟离子和额外注入与第二掺杂区的掺杂离子类型相同的离子，提高第二沟槽露出的第二掺杂区的掺杂离子的浓度，降低金属/半导体的接触电阻。
本公开另一实施例还提供一种半导体结构，本公开另一实施例提供的半导体结构与前述实施例提供的半导体结构大致相同，主要区别包括本公开另一实施例提供的半导体结构的第一导电柱位于第一掺杂区内的深度小于前述实施例提供的半导体结构的第一导电柱位于第一掺杂区内的深度，且本公开另一实施例提供的半导体结构的第二导电柱位于第二掺杂区内的深度也小于前述实施例提供的半导体结构的第二导电柱位于第二掺杂区内的深度。以下将结合附图对本公开另一实施例提供的半导体结构进行详细说明。
图20为本公开另一实施例提供的半导体结构的一种结构示意图。
参考图20，半导体结构包括：衬底300，衬底300包括核心区301以及外围区302，且核心区301的衬底300内具有第一栅极312，核心区301的第一栅极312相对两侧的衬底300内具有第一掺杂区311，衬底300暴露出第一掺杂区311的顶面，第一掺杂区311的顶面具有介质层303；外围区302的衬底300上具有第二栅极322，外围区302的第二栅极322相对两侧的衬底300内具有第二掺杂区321；第一导电柱346位于第一掺杂区311内，且凸出于衬底300表面；第二导电柱356位于第二掺杂区321内，且凸出于衬底300表面，且第二导电柱356位于第二掺杂区321内的深度小于第一导电柱346位于第一掺杂区311内的深度。
本公开另一实施例提供的半导体结构与前述实施例提供的半导体结构大致相同，在这里就不过多赘述。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系 为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构和半导体结构的制备方法，可以解决现有半导体结构结深变浅，接触通孔过深导致的衬底漏电过大的问题，提高了半导体结构的稳定性。

Claims (16)

  1. 一种半导体结构的制备方法，包括：
    提供衬底，所述衬底包括核心区以及外围区，且所述核心区的所述衬底内具有第一栅极，所述核心区的所述第一栅极相对两侧的所述衬底内具有第一掺杂区，所述衬底暴露出所述第一掺杂区的顶面，所述第一掺杂区的顶面具有介质层；所述外围区的所述衬底上具有第二栅极，所述外围区的所述第二栅极相对两侧的所述衬底内具有第二掺杂区；
    在所述外围区的所述衬底上形成阻挡层，所述阻挡层位于所述第二掺杂区表面；
    在所述核心区以及所述外围区的所述衬底上形成具有开口的掩膜层，且所述掩膜层还位于所述阻挡层和所述介质层表面，所述掩膜层的材料与所述阻挡层的材料不同；
    以所述掩膜层为掩膜，沿所述开口刻蚀所述核心区的所述介质层以及所述第一掺杂区，以在所述第一掺杂区内形成第一沟槽，且还沿所述开口刻蚀所述外围区的所述阻挡层以及所述第二掺杂区，以在所述第二掺杂区内形成第二沟槽，且所述第一沟槽的深度大于所述第二沟槽的深度；
    形成第一导电柱，所述第一导电柱填充满所述第一沟槽且凸出于所述衬底表面；
    形成第二导电柱，所述第二导电柱填充满所述第二沟槽且凸出于所述衬底表面。
  2. 如权利要求1所述的半导体结构的制备方法，所述阻挡层还位于所述外围区的所述第二栅极的侧壁。
  3. 如权利要求1所述的半导体结构的制备方法，其中，所述阻挡层的材料包括氧化硅或者氮化硅。
  4. 如权利要求1所述的半导体结构的制备方法，其中，形成所述阻挡层的工艺步骤包括：
    在所述核心区以及所述外围区的所述衬底表面形成连续的初始阻挡膜；
    去除位于所述核心区的所述初始阻挡膜，剩余的所述初始阻挡膜作为所述阻挡层。
  5. 如权利要求1所述的半导体结构的制备方法，所述第二掺杂区内具有掺杂离子，所述掺杂离子为N型离子或者P型离子中的一者，所述制备方法还包括：
    对所述第二沟槽进行预处理，以提高所述第二沟槽露出的所述第二掺杂区的所述掺杂离子的浓度。
  6. 如权利要求5所述的半导体结构的制备方法，其中，所述预处理包括：第一步预处理，所述第一步预处理向所述第二沟槽露出的所述第二掺杂区表面掺杂氟离子；第二步预处理，所述第二步预处理向所述第二沟槽露出的所述第二掺杂区表面掺杂与第二掺杂区的掺杂离子类型相同的离子，且所述与第二掺杂区的掺杂离子类型相同的离子为N型离子或者P型离子。
  7. 如权利要求6所述的半导体结构的制备方法，其中，所述掺杂离子为P型离子，所述掺杂离子类型相同的离子包括氟化硼离子。
  8. 如权利要求1所述的半导体结构的制备方法，在形成所述第一导电柱和所述第二导电柱之前，还包括：
    在所述第一沟槽表面形成第一金属硅化物层，所述第一金属硅化物层位于所述第一导电柱与所述第一掺杂区之间；
    在所述第二沟槽表面形成第二金属硅化物层，所述第二金属硅化物层位于所述第二导电柱与所述第二掺杂区之间。
  9. 如权利要求8所述的半导体结构的制备方法，其中，形成所述第一金属硅化物层以及所述第二金属硅化物层的工艺步骤包括：
    形成金属层，所述金属层位于所述第一沟槽表面、所述第二沟槽表面以及所述第二沟槽正上方的所述阻挡层表面；
    进行退火处理，所述金属层与所述第一掺杂区发生反应，以形成所述第一金属硅化物层，所述金属层与所述第二掺杂区发生反应，以形成所述第二金属硅化物层；
    去除未发生反应的所述金属层。
  10. 如权利要求1所述的半导体结构的制备方法，其中，形成所述第一导电柱以及所述第二导电柱的工艺步骤包括：
    形成填充满所述第一沟槽、所述第二沟槽以及所述开口的导电膜，且所述导电膜还位于所述掩膜层顶面；
    去除高于所述掩膜层顶面的所述导电膜，位于所述核心区的剩余所述导电膜作为所述第一导电柱，位于所述外围区的剩余所述导电膜作为所述第二导电柱。
  11. 如权利要求1所述的半导体结构的制备方法，在形成所述第一导电柱以及所述第二导电柱之后，还包括：去除所述掩膜层。
  12. 一种半导体结构，包括：
    衬底，所述衬底包括核心区以及外围区，且所述核心区的所述衬底内具有第一栅极，所述核心区的所述第一栅极相对两侧的所述衬底内具有第一掺杂区，所述衬底暴露出所述第一掺杂区的顶面，所述第一掺杂区的顶面具有介质层；所述外围区的所述衬底上具有第二栅极，所述外围区的所述第二栅极相对两侧的所述衬底内具有第二掺杂区；
    第一导电柱，所述第一导电柱位于所述第一掺杂区内，且凸出于所述衬底表面；
    第二导电柱，所述第二导电柱位于所述第二掺杂区内，且凸出于所述衬底表面，且所述第二导电柱位于所述第二掺杂区内的深度小于所述第一导电柱位于所述第一掺杂区内的深度。
  13. 如权利要求12所述的半导体结构，还包括：
    第一金属硅化物层，所述第一金属硅化物层位于所述第一导电柱与所述第一掺杂区之间；
    第二金属硅化物层，所述第二金属硅化物层位于所述第二导电柱与所述第二掺杂区之间。
  14. 如权利要求13所述的半导体结构，其中，所述第二金属硅化物层位于所述第二导电柱底面。
  15. 如权利要求14所述的半导体结构，所述第二金属硅化物层还位于所述第二导电柱侧面。
  16. 如权利要求13所述的半导体结构，所述第二金属硅化物层内还具有氟离子。
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