WO2023019866A1 - 显示面板的驱动电路和驱动装置 - Google Patents

显示面板的驱动电路和驱动装置 Download PDF

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Publication number
WO2023019866A1
WO2023019866A1 PCT/CN2021/143430 CN2021143430W WO2023019866A1 WO 2023019866 A1 WO2023019866 A1 WO 2023019866A1 CN 2021143430 W CN2021143430 W CN 2021143430W WO 2023019866 A1 WO2023019866 A1 WO 2023019866A1
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Prior art keywords
signal
electronic switch
module
sub
gate
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PCT/CN2021/143430
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English (en)
French (fr)
Inventor
何静
康报虹
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to JP2022573523A priority Critical patent/JP2023541753A/ja
Priority to US18/002,341 priority patent/US11978377B2/en
Priority to EP21942129.4A priority patent/EP4390903A1/en
Priority to KR1020227041978A priority patent/KR102612202B1/ko
Publication of WO2023019866A1 publication Critical patent/WO2023019866A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, in particular to a driving circuit and a driving device of a display panel.
  • GDL Gate Driver Less, array substrate row drive
  • GDL technology refers to the gate driver circuit (Gate driver IC) is directly produced on the array (Array) substrate to realize the driving method of progressive scanning of the gate.
  • GDL technology can simplify the manufacturing process of the display panel, save the chip bonding (Bonding) process in the direction of the horizontal scanning line, and reduce the production cost. At the same time, it can improve the integration of the display panel and make the display panel lighter and thinner.
  • One of the purposes of the embodiments of the present application is to provide a driving circuit and a driving device for a display panel, aiming at solving the problem that the output of the gate driving signal in the existing GDL technology is unstable and affects the display effect.
  • a driving circuit including a control module and a bootstrap module, wherein the driving circuit further includes a stretching module and an output module, and the control module is connected to the stretching module and the bootstrap module respectively. module and the output module are electrically connected, and the bootstrap module is electrically connected to the output module;
  • the stretching module is used to receive a first level signal, generate a stretching signal according to the first level signal when receiving a first transfer signal, and send the stretching signal to a control module; the first transfer The signal includes at least two sub-transmission signals with different time sequences, and the time length of the extended signal is determined according to the time length of the first transmission signal;
  • the control module is configured to receive the first level signal, generate a control signal according to the first level signal when receiving the widening signal, and send the control signal to the output module and the self- lift module;
  • the bootstrap module is used to receive the control signal, and send the bootstrap signal to the output module when the control signal is switched to a low level;
  • the output module is also used to receive a clock signal, and when receiving the bootstrap signal, generate a gate drive signal and a second transfer signal according to the clock signal, and send the gate drive signal to the display and sending the second transfer signal to the sub-pixels of the panel.
  • a driving device including 2a clock signal generators and n driving circuits provided in the first aspect of the embodiments of the present application;
  • the j-th clock signal generator is connected to the output module of the j+2ka-th driving circuit, the first stretching unit of the i+2a-th driving circuit is connected to the second output unit of the i-th driving circuit, and the i+2a-th
  • the second output unit of the driving circuit is connected to the second output unit of the i-th driving circuit, and the second stretching unit of the i+2a-th driving circuit is connected to the second output unit of the i+a-th driving circuit;
  • the jth clock signal generator is used to generate a clock signal and send it to the output module of the j+2kath driving circuit, and the clock signal generated by the jth clock signal generator is the same as that of the j+1th clock signal generator
  • the phase difference of the clock signal generated by the clock signal generator is ⁇ /2a;
  • the first stretching unit of the i+2a-th driving circuit is configured to send the first sub-spreading signal to the control unit when receiving the first sub-transmission signal sent by the second output unit of the i-th driving circuit module;
  • the second stretching unit of the i+2a-th driving circuit is configured to send the second sub-spreading signal to the said control module;
  • the second output unit of the i+2a-th driving circuit is used to receive the first sub-transfer signal sent by the second output unit of the i-th driving circuit, and the second output unit of the i+2a-th driving circuit When the second output unit receives the control signal and the clock signal, it discharges the clock signal;
  • a is an integer greater than or equal to 1
  • n is an integer greater than 2a
  • j 1, 2,...,2a
  • k 0,1,2,..., ⁇ n /2a ⁇
  • j+2ka is less than or equal to n.
  • the stretching signal generated by the stretching module can make the bootstrap module have enough time to charge, and ensure that the output module can reach or exceed the preset potential when receiving the bootstrap signal, thereby avoiding When outputting the gate drive signal, the voltage is unstable and avoids the phenomenon that the gate drive signal stops outputting in advance, so as to improve the stability of the output gate drive signal, thereby improving the display brightness of the display panel while improving the refresh rate and resolution of the display panel and display stability.
  • the driving device of the display panel provided by the embodiment of the present application is configured by cascading the driving circuit and cooperating with the driving device of the clock signal generator.
  • the input signal used is small and the structure is simple, so that the driving device can run in a stable cycle and continuously output
  • the multi-sequence gate drive signal has the advantages of strong anti-interference performance, low cost, and stable output.
  • FIG. 1 is a first structural schematic diagram of a driving circuit of a display panel provided by an embodiment of the present application
  • Fig. 2 is a timing schematic diagram of the first level signal, the first transfer signal, the stretch signal, the control signal, the potential of the input port of the output module, the clock signal, the gate drive signal and the second transfer signal provided by the embodiment of the present application;
  • FIG. 3 is a second structural schematic diagram of a driving circuit of a display panel provided by an embodiment of the present application.
  • Fig. 4 is a timing diagram of the first level signal, the first sub-transmission signal, the first sub-spreading signal, the second sub-transmission signal, the second sub-spreading signal, the stretching signal and the control signal provided by the embodiment of the present application;
  • FIG. 5 is a schematic diagram of a third structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a fourth structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a fifth structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • Figure 8 is the timing sequence of the first sub-transfer signal, the second sub-transfer signal, the control signal, the bootstrap signal, the potential of the input port of the output module, the clock signal, the gate drive signal and the second transfer signal provided by the embodiment of the present application schematic diagram;
  • FIG. 9 is a schematic diagram of a sixth structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a seventh structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of an eighth structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 12 is a timing diagram of the control signal sent to the reset module, the bootstrap signal, the potential of the input port of the output module, and the third transfer signal when the third transfer signal provided by the embodiment of the present application is switched to a low level;
  • FIG. 13 is a ninth structural schematic diagram of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of a first structure of a driving device for a display panel provided by an embodiment of the present application.
  • Figure 16 shows the first level signal, the first sub-transfer signal, the first sub-spread signal, the second sub-transfer signal, the second sub-spread signal, and the second sub-spread signal of the i+2a-th drive circuit provided by the embodiment of the present application Schematic diagram of the time sequence of the transfer signal, the second sub-broadening signal, the stretching signal, the control signal, the bootstrap signal, the potential of the input port of the output module, the clock signal, the gate drive signal and the second transfer signal;
  • Figure 17 is the first sub-transmission signal sent by the second output unit of the i+1th driving circuit received by the first stretching unit of the i+2ath driving circuit provided by the embodiment of the present application, and the i+2ath driving circuit
  • the second stretching unit of the i+a-1th driving circuit receives the second sub-transmission signal sent by the second output unit of the i+a-1th drive circuit, the first level signal, the first sub-transmission signal, the first sub-spreading signal, the second sub-transmission signal Transfer signal, second sub-spread signal, second sub-transfer signal, second sub-spread signal, stretch signal, control signal, bootstrap signal, potential of input port of output module, clock signal, gate drive signal, and second transfer
  • the timing diagram of the signal
  • Figure 18 is the control signal and bootstrap of the i+2a-th drive circuit provided by the embodiment of the present application when the reset module of the i+2a-th drive circuit is connected to the second output unit of the i+3a+1-th drive circuit Schematic diagram of the timing of the signal, the potential of the input port of the output module and the third transfer signal.
  • the gate driver needs to be charged before outputting the gate driving signal, and the gate driver outputs the gate driving signal after the charging is completed.
  • the charging time of the traditional gate driver is shortened each time the gate driver outputs the gate driving signal.
  • the predetermined potential cannot be reached, and the gate driving signal is likely to have a voltage drop phenomenon during the output process, resulting in a decrease in the stability of the gate driving signal output and making the display brightness of the display panel unstable.
  • the embodiment of the present application provides a display panel driving circuit, which can be applied to the display panel.
  • the stretching signal generated by the stretching module can make the bootstrap module have enough time to charge, and can ensure that the output module reaches Preset potential, so as to avoid voltage instability when outputting the gate drive signal and avoid the phenomenon that the gate drive signal stops outputting in advance, so as to improve the stability of the output gate drive signal, thereby improving the refresh rate and resolution of the display panel at the same time Improve the display brightness of the display panel and the stability of the display effect.
  • the display panel can be a liquid crystal display panel based on TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display) technology, a liquid crystal display panel based on LCD (Liquid Crystal Display, liquid crystal display) technology, a liquid crystal display panel based on OLED ( Organic Light-Emitting Organic electro-laser display panels based on Diode (Organic Light Emitting Diode) technology, based on QLED (Quantum Dot Light Emitting Diodes, quantum dot light emitting diode) technology quantum dot light emitting diode display panel or curved display panel, etc.
  • TFT-LCD Thi Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display
  • LCD Liquid Crystal Display, liquid crystal display
  • OLED Organic Light-Emitting Organic electro-laser display panels based on Diode (Organic Light Emitting Diode) technology
  • QLED Quantum Dot Light Emitting Diodes, quantum dot light emit
  • the driving circuit 1 provided in Embodiment 1 of the present application includes a stretching module 10 , a control module 20 , a bootstrap module 30 and an output module 40 , and the control module 20 is connected to the stretching module 10 , the bootstrap module 30 and the output module 40 respectively.
  • the module 40 is electrically connected, and the bootstrap module 30 is electrically connected to the output module 40;
  • the stretching module 10 is used to receive the first level signal, and when receiving the first transfer signal, generate the stretching signal according to the first level signal, and send the stretching signal to the control module 20;
  • the first transfer signal includes at least two time sequences For different sub-transmission signals, the time length of the extended signal is determined according to the time length of the first transmission signal;
  • the control module 20 is used to receive the first level signal, and when receiving the widening signal, generate a control signal according to the first level signal, and send the control signal to the output module 40 and the bootstrap module 30;
  • the bootstrap module 30 is used to receive the control signal, and send the bootstrap signal to the output module 40 when the control signal is switched to a low level;
  • the output module 40 is also used to receive the clock signal, when receiving the bootstrap signal, generate the gate drive signal and the second transfer signal according to the clock signal, and send the gate drive signal to the sub-pixel 210 of the display panel 2 and send the second transfer signal Second, transmit the signal.
  • the drive circuit can include electronic components such as multiple transistors, comparators, logic gates, resistors, capacitors, or inductors; the level signal and clock signal can be passed through a timing controller (Timer Control Register, TCON) or on-chip ( System on Chip, SOC) is generated and input to the drive circuit; the level signal can be a high-level signal or a low-level signal, and the clock signal can be phase-shifted by TCON or SOC according to actual needs to obtain multiple a clock signal.
  • TCON Timer Control Register
  • SOC System on Chip
  • the first transfer signal received by the stretching module may be the second transfer signal output by the output module of another drive circuit of the display panel; the first level signal may be a DC high level signal, and the stretching module may receive Turn on and output the first level signal when the first transfer signal is reached, and turn off and stop outputting the first level signal when the first transfer signal is not received, thereby generating a stretched signal, by prolonging the time of the first transfer signal Length, which can extend the time length of the stretched signal.
  • the first transmission signal may include at least two sub-transmission signals with different time sequences, and the time length of the stretched signal is the same as that of the first transmission signal.
  • the control module can turn on and output the first level signal when receiving the widening signal, and turn off and stop outputting the first level signal when not receiving the widening signal, so as to generate a control signal and send it to the output module and the bootstrap module; the time length of the control signal and the time length of the extended signal can be the same. Specifically, since the extended unit can extend the time length of the extended signal, the control module can extend the conduction time to realize the extension of the time length of the control signal.
  • the output module when the output module receives a high-level control signal, the potential of the input port of the output module is pulled up to the first high potential, but the first high potential is lower than the preset potential, which will cause the output gate of the output module to The drive signal is unstable.
  • the bootstrap module can send the bootstrap signal to the output module when the control signal is switched from high level to low level; when the output module receives the bootstrap signal, the potential of the input port of the output module can be pulled up to The second high potential enables the input port of the output module to reach the preset potential or exceed the preset potential.
  • the gate drive signal sent according to the frequency of the refresh rate can be used to control the deflection of the sub-pixels. Therefore, the output module can output stable gate drive signals to the sub-pixels according to the frequency of the refresh rate.
  • the unstable gate driving signal when the unstable gate driving signal is output before the stable gate driving signal, the unstable gate driving signal can be used to precharge the sub-pixels.
  • the preset potential is determined according to the voltage and time length of the gate drive signal actually required by the display panel. If the input port of the output module can reach the preset potential through charging, a complete and stable gate drive signal can be generated. In addition, when the output module receives the bootstrap signal, it can also generate and send a second transfer signal. Wherein, at the same moment when the control signal is switched from high level to low level, the clock signal can be switched from low level to high level; the connection between the control module, the output module and the bootstrap module is the input port of the output module.
  • the bootstrap module is used for receiving a control signal, and charging is performed when the control signal is at a high level.
  • the bootstrap module charges to accumulate charges when the control signal is at a high level, and releases the accumulated charges when the control signal is switched from a high level to a low level, thereby generating a bootstrap signal.
  • the output module can provide independent signals for different output objects.
  • the output module can provide a stable gate drive signal.
  • the stable gate drive signal can Charge one or more rows of sub-pixels of the display panel to drive the display panel to display images, wherein a display panel may include at least one driving circuit, and the number of driving circuits is determined according to the number of clock signals used by the above-mentioned display panel; when the output object When it is another driving circuit of the display panel, the output module can provide a second transmission signal, so as to provide the first transmission signal to the stretching module of the other driving circuit.
  • the stretching signal generated by the stretching module can make the bootstrap module have enough time to charge, ensure that the output module can reach or exceed the preset potential when receiving the bootstrap signal, and make the output module send the gate drive signal and During the second transmission signal, it can be fully turned on and improve the signal transmission efficiency, and avoid the gate drive signal and the second transmission signal from suspending the output caused by the early shutdown of the module, so as to improve the stability of the output gate drive signal and the second transmission signal sex.
  • Fig. 2 exemplarily shows a timing diagram of the first level signal, the first transfer signal, the stretch signal, the control signal, the potential of the input port of the output module, the clock signal, the gate driving signal and the second transfer signal.
  • the stretching module 10 includes a first stretching unit 110 and a second stretching unit 120 , the first stretching unit 110 and the second stretching unit 120 are respectively electrically connected to the control module 20;
  • the first stretching unit 110 is configured to receive the first level signal, generate a first sub-spreading signal according to the first level signal when receiving the first sub-transmission signal, and send the first sub-spreading signal to the control module 20;
  • the second stretching unit 120 is configured to receive the first level signal, and when receiving the second sub-transmission signal, generate a second sub-spreading signal according to the first level signal, and send the second sub-spreading signal to the control module 20;
  • the stretched signal includes a first sub-spread signal and a second sub-spread signal.
  • the stretching module can include at least two stretching units, and the working principle of each stretching unit is the same as that of the stretching module provided in the previous embodiment, the difference is that each stretching unit is connected to an output module of a different drive circuit
  • each stretching unit can generate a sub-spreading signal according to the sub-transmission signal.
  • the time length of each sub-spreading signal can be the same as the time length of the corresponding sub-transmission signal, because the time length of each sub-transmission signal Timings are different, and the stretching signal sent by the stretching module is composed of all sub-spreading signals. Therefore, the time length of the stretching signal is determined according to the number and timing of the sub-transmission signals. By extending the time length of the stretched signal, the time length of the control signal output by the control module can be extended.
  • the stretching module may include a first stretching unit and a second stretching unit, the first stretching unit and the second stretching unit are respectively connected to output modules of different driving circuits, in order to distinguish different transmission signals received by different stretching units, define
  • the transmission signal received by the first stretching unit is the first sub-transmission signal
  • the transmission signal received by the second stretching unit is the second sub-transmission signal.
  • Figure 4 exemplarily shows the timing diagram of the first level signal, the first sub-transmission signal, the first sub-spreading signal, the second sub-transmission signal, the second sub-spreading signal, the stretching signal and the control signal, the following is combined with the figure 4 Explain the working principles of the first stretching unit and the second stretching unit:
  • the first stretching unit and the second stretching unit keep receiving the first level signal; the first stretching unit can be turned on and output the first level signal at time t0 when it receives the first sub-transmission signal, and The t1 moment when the sub-transmission signal is turned off and stops outputting the first level signal, thereby generating a high-level first sub-broadening signal in the first time period t01; the second widening unit can receive the second sub-transmission signal turn on and output the first level signal at time t1, and turn off and stop outputting the first level signal at time t2 when the second sub-transmission signal is not received, so as to generate the second sub-broadening signal in the second time period t12; Wherein, the timing of the first sub-transmission signal and the timing of the first sub-spreading signal may be the same.
  • the timing of the second sub-transmission signal and the timing of the second sub-spreading signal may also be the same.
  • the first sub-transmission signal and the second sub-transmission signal can be high-level signals with the same voltage and a phase difference of 90 degrees. It consists of a sub-spreading signal and a second sub-spreading signal.
  • the source of the first electronic switch 111 is connected to the source of the second electronic switch 121, and the drain of the first electronic switch 111 is electrically connected to the drain of the second electronic switch 121 and the control module 20;
  • the source of the first electronic switch 111 is used to receive the first level signal.
  • the drain of the first electronic switch 111 is used to generating a first sub-broadening signal, and sending the first sub-broadening signal to the control module 20;
  • the source of the second electronic switch 121 is used to receive the first level signal.
  • the gate of the second electronic switch 121 receives the second sub-transfer signal
  • the drain of the second electronic switch 121 is used to The signal generates a second sub-spread signal, and sends the second sub-spread signal to the control module 20 .
  • the first electronic switch and the second electronic switch can be any device or circuit with electronic switch function, for example, triode or metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), specifically, it may be a thin film field effect transistor (Thin Film Transistor, TFT).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • TFT Thin Film Transistor
  • the source of the first electronic switch and the source of the second electronic switch are used to receive the first level signal; the gate of the first electronic switch is turned on at the time t0 when receiving the first sub-transmission signal, so that the first electronic switch The drain of the first electronic switch outputs the first level signal, and the gate of the first electronic switch is turned off at the time t1 when the first sub-transmission signal is not received, so that the drain of the first electronic switch stops outputting the first level signal, thereby in The first time period t01 generates a high-level first sub-broadening signal; the gate of the second electronic switch is turned on at the moment t1 when receiving the second sub-transmission signal, so that the drain of the second electronic switch outputs the first level signal, the gate of the second electronic switch is turned off at time t2 when the first sub-transmission signal is not received, so that the drain of the second electronic switch stops outputting the first level signal, thereby generating a high voltage in the second time period t12 Flat second sub-broadened signal.
  • the first stretching unit composed of the first electronic switch and the second stretching unit composed of the second electronic switch have the advantages of simple structure, easy control, stable output and low cost, which can improve the stability of the driving circuit and reduce the The production cost of the display panel.
  • the control module 20 includes a third electronic switch 201, and the gate of the third electronic switch 201 is connected to the The drain of the first electronic switch 111 is connected to the drain of the second electronic switch 121, and the drain of the third electronic switch 201 is electrically connected to the bootstrap module 30 and the output module 40 respectively;
  • the source of the third electronic switch 201 is used to receive the first level signal, and when the gate of the third electronic switch 201 receives the stretch signal, the drain of the third electronic switch 201 is used to generate the control signal according to the first level signal. signal, and send the control signal to the bootstrap module 30 and the output module 40 .
  • the selection of the third electronic switch is consistent with the selection of the above-mentioned first electronic switch and the second electronic switch, which will not be repeated here.
  • the source of the third electronic switch is used to receive the first level signal; the gate of the third electronic switch is turned on at the time t0 when receiving the widening signal, so that the drain of the third electronic switch outputs the first level signal, and the third electronic switch
  • the gates of the three electronic switches are turned off at time t2 when the first sub-transmission signal is not received, so that the drain of the third electronic switch stops outputting the first level signal, so that the first time period t01 and the second time period t12 A high-level control signal is continuously generated.
  • control module composed of the third electronic switch has the advantages of simple structure, easy control, stable output and low cost. Cooperating with the first widening unit and the second widening unit with the same advantages can further improve the stability of the driving circuit performance and reduce the production cost of the display panel.
  • the output module 40 includes a first output unit 410 and a second output unit 420 , the first output unit 410 is electrically connected with the third electronic switch 201 and the bootstrap module 30 respectively, the second output unit 420 is electrically connected with the third electronic switch 201 and the bootstrap module 30 respectively, the input port of the first output unit 410 is connected with the second output unit 420 The input port of is connected to constitute the input port 430 of the output module 40;
  • the first output unit 410 is used to receive a clock signal, and when receiving a bootstrap signal, generate a gate drive signal according to the clock signal, and send the gate drive signal to the sub-pixel 210 of the display panel 2;
  • the second output unit 420 is used to receive the clock signal, and when receiving the bootstrap signal, generate a second transfer signal according to the clock signal, and send the second transfer signal;
  • the second output unit 420 is also used for receiving the first sub-transfer signal, and discharging the clock signal when receiving the control signal and the clock signal.
  • the output module may include multiple output units, and the working principle of each output unit is consistent with the working principle of the output module provided in the foregoing embodiments.
  • the number of output units may be determined according to the number of output objects connected to the output module.
  • An output unit is used to provide an independent signal for an output object.
  • Fig. 8 exemplarily shows a timing diagram of the first sub-transfer signal, the second sub-transfer signal, the control signal, the bootstrap signal, the potential of the input port of the output module, the clock signal, the gate drive signal and the second transfer signal , the working principles of the first output unit and the second output unit are described below in conjunction with FIG. 8:
  • the first output unit and the second output unit keep receiving the clock signal; the first output unit can start charging at the time t0 when receiving the control signal and continue until the time t2, so as to pull up the potential of the input port of the first output unit to the second A high potential, so that the first output unit outputs an unstable gate drive signal during the first time period t01; at time t2, the first output unit does not receive the control signal (the control signal is switched from high level to low level) , and when the first output unit receives the bootstrap signal, the potential of the input port of the first output unit is further pulled up to the second high potential, so that the first output unit is fully turned on and starts to output a stable gate drive signal; The first output unit is turned off and stops outputting the clock signal at time t3 when no bootstrap signal is received, so as to keep outputting a stable gate driving signal during the third time period t23.
  • the working principle of the second output unit is the same as that of the first output unit, and will not be repeated. The difference is that the second output unit can discharge the clock signal during the time period t01 so as not to output the second transmission signal.
  • the third time period t23 can output a stable second transfer signal.
  • the potentials of the input port of the first output unit, the input port of the second output unit and the input port of the output module are equal, and the potential of the input port of the output module is determined according to the voltage of the control signal and the voltage of the bootstrap signal, The voltage of the control signal and the voltage of the bootstrap signal can be set according to actual needs.
  • the gate of the fourth electronic switch 411 is connected to the drain of the third electronic switch 201, the drain of the fourth electronic switch 411 is connected to the sub-pixel 210 of the display panel 2, the gate of the fourth electronic switch 411, the fourth electronic switch
  • the drain of 411 and the gate of the fifth electronic switch 421 are electrically connected to the bootstrap module 30 respectively, and the gate of the fourth electronic switch 411 constitutes the input port 412 of the first output unit 410;
  • the gate of the fifth electronic switch 421 is connected to the drain of the third electronic switch, the drain of the fifth electronic switch 421 is connected to the source of the sixth electronic switch 422, and the gate of the fifth electronic switch 421 constitutes the second output unit input port 423;
  • the source of the fourth electronic switch 411 is used to receive a clock signal, and when the gate of the fourth electronic switch 411 receives a bootstrap signal, the drain of the fourth electronic switch 411 is used to generate a gate drive signal according to the clock signal, and sending the gate driving signal to the display panel 2;
  • the source of the fifth electronic switch 421 is used to receive the clock signal.
  • the drain of the fifth electronic switch 421 is used to generate the second transfer signal according to the clock signal, and send second transmission signal;
  • the gate of the sixth electronic switch 422 is used to receive the first sub-transfer signal.
  • the gate of the fifth electronic switch 421 receives the control signal and the source of the fifth electronic switch 421 receives the clock signal
  • the sixth electronic switch The drain of 422 is used to drain the clock signal according to the first sub-transfer signal.
  • the selection of the fourth electronic switch and the fifth electronic switch is consistent with the selection of the above-mentioned first electronic switch and the second electronic switch, and will not be repeated here.
  • the source electrode of the fourth electronic switch and the source electrode of the fifth electronic switch keep receiving the clock signal; the gate of the fourth electronic switch can start charging at the t0 moment receiving the control signal and continue until the t2 moment, so that the fourth electronic switch
  • the gate of the fourth electronic switch is pulled up to the first high potential, so that the drain of the fourth electronic switch outputs an unstable gate drive signal during the first time period t01; at the time t2, the gate of the fourth electronic switch does not receive the control signal (the control signal is switched from high level to low level), and the gate of the fourth electronic switch receives the bootstrap signal, the potential of the gate of the fourth electronic switch is further pulled up to the second high potential, so that the fourth The electronic switch is fully turned on and starts to output a stable gate drive signal; the gate of the fourth electronic switch is turned off at time t3 when no bootstrap signal is received, and the drain of the fourth electronic switch stops outputting the clock signal, so that the fourth electronic switch The drain of the four-electronic switch keeps outputting a stable gate driving signal
  • the working principle of the fifth electronic switch is the same as that of the fourth electronic switch, and will not be described again.
  • the clock signal is released, so that the fifth electronic switch does not output the second transfer signal during the first time period t01, and in addition, the drain of the fifth electronic switch can output a stable second transfer signal during the third time period t23.
  • the first output unit composed of the fourth electronic switch, the second output unit composed of the fifth electronic switch and the sixth electronic switch have the advantages of simple structure, easy control, stable output and low cost, and the same advantages are achieved in combination
  • the first widening unit, the second widening unit and the control module can further improve the stability of the driving circuit and reduce the production cost of the display panel.
  • the bootstrap module 30 includes a first capacitor 301 , and the first end of the first capacitor 301 is connected to the first terminal of the first capacitor 301 respectively.
  • the drain of the third electronic switch 201, the gate of the fourth electronic switch 411 and the gate of the fifth electronic switch 421 are connected, and the second end of the first capacitor 301 is respectively connected with the drain of the fourth electronic switch 411 and the display panel ;
  • the first end of the first capacitor 301 is used to receive a control signal, and charge the first capacitor 301 when the control signal is at a high level;
  • the first end of the first capacitor 301 is also used to send a bootstrap signal to the gate of the fourth electronic switch 411 and the gate of the fifth electronic switch 421 when the control signal is switched to a low level, so that the fourth electronic switch 411 and the gate of the fifth electronic switch 421 are pulled up to the second high potential.
  • the maximum amount of charge that the first capacitor can accumulate can be determined according to the capacitance value of the first capacitor.
  • the capacitance value of the first capacitor can be set according to actual needs, and the second high potential is greater than or equal to the preset potential.
  • the first end of the first capacitor starts charging at time t0 when it receives a high-level control signal, so that the first capacitor accumulates charge, and the charging continues until the time t2 when the control signal is switched from high level to low level, at time t2 , the first end of the first capacitor releases the charge accumulated in the first time period t01 and the second time period t12, that is, sends a bootstrap signal to the gate of the fourth electronic switch and the gate of the fifth electronic switch, so that the first The gates of the four electronic switch and the fifth electronic switch are pulled up to the second high potential.
  • the capacitor is selected as the energy storage element of the bootstrap module to perform fast and stable cycle charging and discharging, while ensuring the charging efficiency and charging speed of the driving circuit, it can also improve the durability and reliability of the driving circuit.
  • the driving circuit 1 of the display panel provided by the eighth embodiment of the present application further includes a reset module 50, and the reset module 50 is connected to the control module 20 and the bootstrap module respectively. 30 and the output module 40 are electrically connected;
  • the reset module 50 is used to receive the control signal, and when receiving the third transfer signal, send the control signal to the ground terminal;
  • the reset module 50 includes a seventh electronic switch 501, the source of the seventh electronic switch 501 is respectively connected to the drain of the third electronic switch 201, the gate of the fourth electronic switch 411, the gate of the fifth electronic switch 421 and the first capacitor The first end of the connection;
  • the source of the seventh electronic switch 501 is used to receive the control signal, and when the gate of the seventh electronic switch 501 receives the third transmission signal, the drain of the seventh electronic switch 501 is used to send the control signal to the ground terminal.
  • the third transfer signal can be sent to the reset module at any time after the output module sends the gate drive signal and the second transfer signal, and the specific sending time can be when the gate drive signal or the second transfer signal is switched to low power Usually, it can also be at one-sixth cycle of the clock signal after the gate drive signal or the second transfer signal is switched to low level, the reset module can send the control signal to the ground terminal when receiving the third transfer signal , to prevent the control module from continuing to output control signals outside the first time period and the second time period, and can export the control signal remaining in the drive circuit so that the potential of the input port of the output module is returned to zero, so as to improve the control module The stability of the output control signal and the stability of the drive circuit operation.
  • the reset module is also used for receiving the bootstrap signal, and sending the bootstrap signal to the ground terminal when receiving the third transmission signal.
  • the third transmission signal can also be sent to the reset module at any time after the bootstrap module sends the bootstrap signal.
  • the specific sending time can be when the bootstrap signal is switched to low level, or when the bootstrap signal is switched At one-sixth cycle of the clock signal after reaching the low level, the reset module can send the control signal to the ground terminal when receiving the third transfer signal, so as to prevent the bootstrap module from continuing to output the self-
  • the bootstrap signal can be exported, and the bootstrap signal remaining in the drive circuit can be derived to return the potential of the input port of the output module to zero, so as to improve the stability of the bootstrap signal output by the bootstrap module and the stability of the drive circuit operation.
  • the selection of the seventh electronic switch is consistent with the selection of the above-mentioned first electronic switch and the second electronic switch, and will not be repeated here.
  • FIG. 12 exemplarily shows a timing diagram of the control signal sent to the reset module, the bootstrap signal, the potential of the input port of the output module and the third transfer signal when the third transfer signal is switched to low level.
  • the source of the seventh electronic switch keeps receiving the control signal and the bootstrap signal; the gate of the seventh electronic switch can be turned on at time t3 when the third transfer signal is received and the bootstrap signal is sent to the ground terminal; 3. Turn off the signal at time t4 and stop sending the bootstrap signal to the ground terminal, so that the bootstrap signal is sent to the ground terminal in the fourth time period t34, so that the potential of the input port of the output module returns to zero.
  • the time length of the third transmission signal can be set according to actual needs.
  • the driving circuit 1 of the display panel provided by the ninth embodiment of the present application further includes a cut-off module 60, and the cut-off module 60 is electrically connected to the output module;
  • the cut-off module 60 is used to receive the gate drive signal, and when receiving the cut-off signal, send the gate drive signal to the ground terminal;
  • the cut-off module 60 includes an eighth electronic switch 601;
  • the source of the eighth electronic switch 601 is respectively connected to the drain of the fourth electronic switch 411 and the second end of the first capacitor 301;
  • the source of the eighth electronic switch 601 is used to receive the gate driving signal, and the drain of the eighth electronic switch 601 is used to send the gate driving signal to the ground terminal when the gate of the eighth electronic switch 601 receives the cut-off signal.
  • the selection of the eighth electronic switch is consistent with the selection of the above-mentioned first electronic switch and the second electronic switch, and will not be repeated here.
  • the cut-off signal can be the inverse signal of the control signal, and the cut-off signal can be obtained by inputting the control signal of the drive circuit to the inverter, and the type of the inverter can be TTL (Transistor Transistor Logic, transistor-transistor logic level) NOT gate, CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) inverter.
  • the cut-off signal is used to ground the second output unit during the period when the output module is not being charged, so as to avoid redundant or residual gate drive signals from being sent to the display panel, which can improve the stability of the gate drive signal output, thereby improving the display panel display effect.
  • the driving circuit of the display panel includes a stretching module, a control module, a bootstrap module and an output module, the control module is electrically connected to the stretching module, the bootstrap module and the output module, and the bootstrap module is electrically connected to the output module , the stretching signal generated by the stretching module can make the bootstrap module have enough time to charge, and ensure that the output module can reach or exceed the preset potential when receiving the bootstrap signal, thereby avoiding voltage instability when outputting the gate drive signal and avoiding The phenomenon that the output of the gate drive signal is stopped in advance to improve the stability of the output gate drive signal, thereby improving the display brightness and the stability of the display effect of the display panel while improving the refresh rate and resolution of the display panel.
  • the display panel driving device provided in the tenth embodiment of the present application includes 2a clock signal generators and n driving circuits provided in the above-mentioned first to eighth embodiments;
  • the jth clock signal generator is connected to the output module of the j+2ka driving circuit, the first stretching unit of the i+2a driving circuit 1001 is connected to the second output unit of the i driving circuit 1002, and the i+
  • the second output unit of the 2a driving circuit 1001 is connected to the second output unit of the i driving circuit 1002, and the second stretching unit of the i+2a driving circuit 1001 is connected to the second output unit of the i+a driving circuit 1003 unit connection;
  • the jth clock signal generator is used to generate a clock signal and send it to the output module of the j+2kath driving circuit.
  • the clock signal generated by the jth clock signal generator is the same as that generated by the j+1th clock signal generator
  • the phase difference of the clock signal is ⁇ /2a;
  • the first stretching unit of the i+2a-th driving circuit 1001 is configured to send the first sub-spreading signal to the control module when receiving the first sub-transmission signal sent by the second output unit of the i-th driving circuit 1002;
  • the second stretching unit of the i+2a-th driving circuit 1001 is configured to send the second sub-spreading signal to the control module when receiving the second sub-transmission signal sent by the second output unit of the i+a-th driving circuit 1003;
  • a is an integer greater than or equal to 1
  • n is an integer greater than 2a
  • j 1, 2,...,2a
  • k 0,1,2,..., ⁇ n /2a ⁇
  • j+2ka is less than or equal to n.
  • FIG. 14 exemplarily shows a schematic structural diagram when the i-th driving circuit receives the clock signal sent by the first clock signal generator, and shows the first sub-transfer signal of the i+2a-th driving circuit 1001, The input-output relationship between the second sub-transfer signal and the third sub-transfer signal.
  • the drive device includes n cascaded drive circuits, the first output unit of each drive circuit is connected to the sub-pixels of the display panel; the number of drive circuits is determined according to the number of sub-pixel rows of the display panel, for example, the drive circuit The number of may be equal to the number of sub-pixel rows of the display panel, or equal to the number of sub-pixel rows of the display panel plus 2a.
  • the gate drive signal can be sent to the sub-pixel in the first row to the sub-pixel in the n-th row of the display panel in sequence according to the order of the first drive circuit to the n-th drive circuit, the gate drive signal sent last time and The time interval of the gate driving signal sent next time is ⁇ /2a.
  • the time interval of the gate drive signal is determined according to the number of clock signal generators, and the number of clock signal generators can be determined according to the actual performance of the display panel; when TCON or SOC needs to output the gate drive signal through the driving device, Send a high-level signal consistent with the waveform of the stretched signal to the control module of any driving circuit to trigger the driving device to start working.
  • the driving device includes 6 clock signal generators and 7 driving circuits, and the first clock signal generator to the sixth clock signal generator are respectively connected with the first clock signal generator of the first driving circuit.
  • the output unit is connected to the first output unit of the sixth drive circuit in one-to-one correspondence, and the first clock signal generator is also connected to the seventh drive circuit;
  • the second output unit of the first (i) drive circuit is respectively connected to the first The second stretching unit of the 4th (i+a) driving circuit, the first stretching unit of the 7th (i+2a) driving circuit, and the second output unit of the 7th (i+2a) driving circuit are connected and send the Two transmission signals;
  • the second output unit of the second drive circuit is respectively connected with the second widening unit of the fifth driving circuit, the first widening unit of the first driving circuit, and the second output unit of the first driving circuit and Send the second transmission signal;
  • the second output unit of the third drive circuit is connected with the second widening unit of the sixth driving circuit, the first widening unit of the second driving
  • the output unit is connected and sends the second transmission signal; the second output unit of the fifth driving circuit is respectively connected with the second widening unit of the first driving circuit, the first widening unit of the fourth driving circuit, and the first widening unit of the fourth driving circuit.
  • the second output unit is connected and sends the second transmission signal;
  • the second output unit of the sixth driving circuit is connected with the second widening unit of the second driving circuit, the first widening unit of the fifth driving circuit, and the fifth driving circuit respectively.
  • the second output unit of the circuit is connected and sends the second transmission signal;
  • the second output unit of the seventh drive circuit is respectively connected with the second widening unit of the third driving circuit, the first widening unit of the sixth driving circuit, and the sixth widening unit of the sixth driving circuit.
  • the second output unit of a driving circuit is connected to and sends a second transfer signal.
  • the driving device includes 2 clock signal generators and 4 driving circuits, the first clock signal generator is connected with the first output unit of the first driving circuit and the third driving circuit respectively The first output unit of the second clock signal generator is respectively connected to the first output unit of the second drive circuit and the first output unit of the fourth drive circuit; the second clock signal generator of the first (i) drive circuit The output unit is respectively connected with the second stretching unit of the 2nd (i+a) driving circuit, the first stretching unit of the 3rd (i+2a) driving circuit, and the second output of the 3rd (i+2a) driving circuit The unit is connected and sends the second transmission signal; the second output unit of the second drive circuit is respectively connected with the second widening unit of the third driving circuit, the first widening unit of the fourth driving circuit, and the first widening unit of the fourth driving circuit.
  • the second output unit is connected and sends the second transfer signal;
  • the second output unit of the third drive circuit is respectively connected with the second widening unit of the fourth driving circuit, the first widening unit of the first driving circuit, and the first driving circuit
  • the second output unit of the second drive circuit is connected and sends the second transmission signal;
  • the second output unit of the fourth drive circuit is respectively connected with the second widening unit of the first driving circuit, the first widening unit of the second driving circuit, and the second widening unit of the second driving circuit.
  • the second output unit of the driving circuit is connected and sends a second transfer signal.
  • the waveforms of the second transfer signal generated by each driving circuit and the stable gate driving signal are the same; the first sub-transfer signal and the second sub-transfer signal of each driving circuit can be sent according to the remaining driving circuits of the driving device
  • the second transmission signal is obtained, specifically, the second output unit of the i-th driving circuit is connected to the first stretching unit and the second output unit of the i+2a-th driving circuit, and can send the second transmission signal to the i-th
  • the first widening unit and the second output unit of the +2a driving circuit are used as the first sub-transmission signal of the first widening unit and the second output unit of the i+2a driving circuit; the i+a driving circuit
  • the second output unit is connected to the second widening unit of the i+2a-th driving circuit, and can send a second transfer signal to the second widening unit of the i+2a-th driving circuit, as the i+2a-th driving circuit.
  • the stable gate driving signal (second transfer signal) generated by the i-th driving circuit is the same as the stable gate driving signal generated by the i+1th driving circuit
  • the phase difference of the signal (second transmission signal) is also ⁇ /2a, and the phase difference between the first sub-transmission signal received by the i+2ath driving circuit and the gate driving signal generated by the i+2ath driving circuit is ⁇ /2, the phase difference between the second sub-transfer signal received by the i+2a-th driving circuit and the gate driving signal generated by the i+2a-th driving circuit is ⁇ .
  • Figure 16 exemplarily shows the first level signal, the first sub-transfer signal, the first sub-spread signal, the second sub-transfer signal, the second sub-spread signal, the second sub-transfer signal of the i+2a-th drive circuit signal, the second sub-spread signal, the stretch signal, the control signal, the bootstrap signal, the potential of the input port of the output module, the clock signal, the gate drive signal and the timing diagram of the second transfer signal.
  • the jth clock signal generator is connected to the output module of the j+2kath driving circuit, and the first stretching unit of the i+2ath driving circuit is connected to the second output module of the i+1th driving circuit unit connection, the second stretching unit of the i+2th driving circuit is connected to the second output unit of the i+a-1th driving circuit;
  • the first stretching unit of the i+2a-th driving circuit is configured to send the first sub-spreading signal to the control module when receiving the first sub-transmission signal sent by the second output unit of the i+1th driving circuit;
  • the second stretching unit of the i+2a-th driving circuit is configured to send the second sub-spreading signal to the control module when receiving the second sub-transmission signal sent by the second output unit of the i+a-1th driving circuit;
  • Fig. 17 exemplarily shows that the first stretching unit of the i+2ath driving circuit receives the first sub-transfer signal sent by the second output unit of the i+1th driving circuit, and the i+2ath driving circuit
  • the second stretching unit receives the second sub-transfer signal sent by the second output unit of the i+a-1th drive circuit, the first level signal, the first sub-transfer signal, the first sub-spread signal, the second sub-transfer signal signal, a second sub-spread signal, a second sub-transfer signal, a second sub-spread signal, a stretch signal, a control signal, a bootstrap signal, a potential of an input port of an output module, a clock signal, a gate drive signal, and a second transfer signal timing diagram.
  • the transmission of the first sub-spreading signal and the second sub-spreading signal may have a delay, thus
  • the composed widening signal also has a delay, so there is a risk that the control signal remains output after time t2, causing the potential of the input port of the output module to fail to be pulled up to the second highest potential in time during the third time period t23, affecting the third time period
  • the stability and time length of the gate drive signal output by segment t23 may have a delay, thus the composed widening signal also has a delay, so there is a risk that the control signal remains output after time t2, causing the potential of the input port of the output module to fail to be pulled up to the second highest potential in time during the third time period t23, affecting the third time period
  • the stability and time length of the gate drive signal output by segment t23 may have a delay, thus
  • the composed widening signal also has a delay, so there is a risk that the control signal remains output after time t2, causing the potential of the
  • the i+2ath drive circuit can be adjusted under the premise that the time length of the control signal can satisfy the potential of the input port of the output module to reach the second highest potential
  • the connection relationship between the first stretching unit and the second stretching unit specifically, the first stretching unit of the i+2a driving circuit can be connected to the second output unit of the i+1 driving circuit, and the i+ The second stretching units of the two driving circuits are connected to the second output unit of the i+a-1th driving circuit to reduce the time length of the stretching signal, and reserve a time of ⁇ /a to avoid the stretching signal at time t2 The output remains after that.
  • the input signal used is small and the structure is simple, so that the driving device can run stably and continuously output multi-sequence gate driving signals. It has the advantages of strong anti-interference performance, low cost and stable output.
  • the reset module of the i+2a-th driving circuit 1001 is connected to the second output unit of the i+3a+1-th driving circuit 1004;
  • the reset module of the i+2a-th driving circuit 1001 is configured to send a control signal to the ground terminal when receiving the third transmission signal sent by the second output unit of the i+3a+1-th driving circuit 1004 .
  • the reset module of the i+2a-th driving circuit is connected to the second output unit of the i+3a+1-th driving circuit, and can receive the signal sent by the second output unit of the i+3a+1-th driving circuit
  • the second transfer signal as the third transfer signal of the reset module of the i+2a drive circuit, can further multiplex the second transfer signal sent by the second output unit of each drive circuit to improve signal utilization and Drive integration.
  • the reset module of the n-ath driver circuit to the reset module of the nth driver circuit do not have corresponding output modules to provide the third transfer signal, and the reset module of the n-ath driver circuit to the reset of the nth driver circuit
  • the module can be connected with TCON or SOC to get the third transfer signal.
  • the reset module of the i+2a-th driving circuit can be connected with the second output unit of the i+3a-th driving circuit, and the second output unit of any driving circuit after the second output unit of the i+3a-th driving circuit Two output units are connected, and the connection relationship can be determined according to the reset speed.
  • the reset module of the 1+2a driving circuit can be connected to the second output unit of the i+3a driving circuit, and the third transmission signal and The phase difference of the control signal is ⁇ /2, or it can be connected to the second output unit of the i+3a+1th drive circuit, then the phase difference between the third transmission signal and the control signal is ⁇ /2+ ⁇ /a, Or it can be connected to the second output unit of the i+3a+2 drive circuit, then the phase difference between the third transmission signal and the control signal is ⁇ /2+2 ⁇ /a, and the embodiment of the present application is for the i+2a drive
  • the drive circuit specifically connected to the reset module of the circuit is not limited in any way.
  • Figure 18 exemplarily shows that when the reset module of the i+2a-th driving circuit is connected to the second output unit of the i+3a+1-th driving circuit, the control signal and bootstrap signal of the i+2a-th driving circuit , the potential of the input port of the output module and the timing diagram of the third transfer signal.

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Abstract

一种显示面板的驱动电路和驱动装置，该显示面板的驱动电路(1)包括展宽模块(10)、控制模块(20)、自举模块(30)和输出模块(40)，控制模块(20)分别与展宽模块(10)、自举模块(30)以及输出模块(40)电连接，自举模块(30)与输出模块(40)电连接，通过展宽模块(10)生成的展宽信号可以使自举模块(30)有足够的时间进行充电，保证输出模块(40)在接收自举信号时可以达到或超过预设电位，从而避免输出栅极驱动信号时电压不稳定以及避免栅极驱动信号提前中止输出的现象，以提高输出栅极驱动信号的稳定性，进而在提高显示面板刷新率和分辨率的同时提升显示面板的显示亮度和显示效果的稳定性。

Description

显示面板的驱动电路和驱动装置
本申请要求于2021年08月16日在中国专利局提交的、申请号为202110935013.8、发明名称为“显示面板的驱动电路和驱动装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，具体涉及一种显示面板的驱动电路和驱动装置。
 背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。随着显示技术的不断发展，显示面板在娱乐、教育、安防等各种领域得到广泛应用。GDL(Gate Driver Less，阵列基板行驱动)技术是指将栅极驱动电路(Gate driver IC)直接制作在阵列(Array)基板上，实现对栅极逐行扫描的驱动方式。GDL技术能够简化显示面板的制备工序，省去水平扫描线方向的芯片邦定（Bonding）工序，并降低生产成本，同时可以提高显示面板的集成度，使显示面板更轻薄化。
目前，用户对显示面板刷新率和分辨率的要求越来越高，需要提高栅极扫描的频率，从而栅极驱动器输出栅极驱动信号的频率也要提高，导致栅极驱动器每次输出栅极驱动信号时的充电时间减少，栅极驱动信号容易在输出过程中出现电压不稳定的现象，影响显示效果。
 技术问题
本申请实施例的目的之一在于：提供一种显示面板的驱动电路和驱动装置，旨在解决现有的GDL技术栅极驱动信号输出不稳定，影响显示效果的问题。
 技术解决方案
本申请实施例采用的技术方案是：
第一方面，提供了一种驱动电路，包括控制模块和自举模块，其特征在于，所述驱动电路还包括展宽模块和输出模块，所述控制模块分别与所述展宽模块、所述自举模块以及所述输出模块电连接，所述自举模块与所述输出模块电连接；
所述展宽模块用于接收第一电平信号，在接收到第一传递信号时，根据所述第一电平信号生成展宽信号，并将所述展宽信号发送至控制模块；所述第一传递信号包括至少两个时序不同的子传递信号，所述展宽信号的时间长度根据所述第一传递信号的时间长度确定；
所述控制模块用于接收所述第一电平信号，在接收到所述展宽信号时，根据第一电平信号生成控制信号，并将所述控制信号发送至所述输出模块和所述自举模块；
所述自举模块用于接收所述控制信号，在所述控制信号切换至低电平时，发送所述自举信号至所述输出模块；
所述输出模块还用于接收时钟信号，在接收到所述自举信号时，根据所述时钟信号生成栅极驱动信号和第二传递信号，并将所述栅极驱动信号发送至所述显示面板的子像素以及发送所述第二传递信号。
第二方面，提供了一种驱动装置，包括2a个时钟信号发生器和n个本申请实施例的第一方面提供的驱动电路；
第j个时钟信号发生器与第j+2ka个驱动电路的输出模块连接，第i+2a个驱动电路的第一展宽单元与第i个驱动电路的第二输出单元连接，第i+2a个驱动电路的第二输出单元与第i个驱动电路的第二输出单元连接，第i+2a个驱动电路的第二展宽单元与第i+a个驱动电路的第二输出单元连接；
所述第j个时钟信号发生器用于生成一个时钟信号，并发送至所述第j+2ka个驱动电路的输出模块，所述第j个时钟信号发生器生成的时钟信号与第j+1个时钟信号发生器生成的时钟信号的相位差为π/2a；
所述第i+2a个驱动电路的第一展宽单元用于接收到所述第i个驱动电路的第二输出单元发送的第一子传递信号时，将第一子展宽信号发送至所述控制模块；
所述第i+2a个驱动电路的第二展宽单元用于接收到所述第i+a个驱动电路的第二输出单元发送的第二子传递信号时，将第二子展宽信号发送至所述控制模块；
所述第i+2a个驱动电路的第二输出单元用于接收到所述第i个驱动电路的第二输出单元发送的第一子传递信号，在所述第i+2a个驱动电路的第二输出单元接收到控制信号和时钟信号时，泄放所述时钟信号；
其中，a为大于或等于1的整数，n为大于2a的整数，i∈[1，n-2a]，j=1，2,…,2a，k=0,1,2,…,⌊n/2a⌋，j+2ka小于或等于n。
 有益效果
本申请实施例提供的显示面板的驱动电路，通过展宽模块生成的展宽信号可以使自举模块有足够的时间进行充电，保证输出模块在接收自举信号时可以达到或超过预设电位，从而避免输出栅极驱动信号时电压不稳定以及避免栅极驱动信号提前中止输出的现象，以提高输出栅极驱动信号的稳定性，进而在提高显示面板刷新率和分辨率的同时提升显示面板的显示亮度和显示效果的稳定性。
本申请实施例提供的显示面板的驱动装置，通过将驱动电路进行级联设置并配合时钟信号发生器构成的驱动装置，使用的输入信号少且结构简单，使驱动装置可以稳定循环运行并持续输出多时序的栅极驱动信号，具有抗干扰性能强、成本低廉、输出稳定的优点。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本申请实施例提供的显示面板的驱动电路的第一种结构示意图；
图2是本申请实施例提供的第一电平信号、第一传递信号、展宽信号、控制信号、输出模块的输入端口的电位、时钟信号、栅极驱动信号及第二传递信号的时序示意图；
图3是本申请实施例提供的显示面板的驱动电路的第二种结构示意图；
图4是本申请实施例提供的第一电平信号、第一子传递信号、第一子展宽信号、第二子传递信号、第二子展宽信号、展宽信号及控制信号的时序示意图；
图5是本申请实施例提供的显示面板的驱动电路的第三种结构示意图；
图6是本申请实施例提供的显示面板的驱动电路的第四种结构示意图；
图7是本申请实施例提供的显示面板的驱动电路的第五种结构示意图；
图8是本申请实施例提供的第一子传递信号、第二子传递信号、控制信号、自举信号、输出模块的输入端口的电位、时钟信号、栅极驱动信号及第二传递信号的时序示意图；
图9是本申请实施例提供的显示面板的驱动电路的第六种结构示意图；
图10是本申请实施例提供的显示面板的驱动电路的第七种结构示意图；
图11是本申请实施例提供的显示面板的驱动电路的第八种结构示意图；
图12是本申请实施例提供的第三传递信号在自举信号切换至低电平时发送至复位模块的控制信号、自举信号、输出模块的输入端口的电位及第三传递信号的时序示意图；
图13是本申请实施例提供的显示面板的驱动电路的第九种结构示意图；
图14是本申请实施例提供的显示面板的驱动装置的第一种结构示意图；
图15是本申请实施例提供的当a=3，第1个时钟信号发生器生成的第1个时钟信号至第7个时钟信号发生器生成的第7个时钟信号的时序示意图；
图16是本申请实施例提供的第i+2a个驱动电路的第一电平信号、第一子传递信号、第一子展宽信号、第二子传递信号、第二子展宽信号、第二子传递信号、第二子展宽信号、展宽信号、控制信号、自举信号、输出模块的输入端口的电位、时钟信号、栅极驱动信号及第二传递信号的时序示意图；
图17是本申请实施例提供的在第i+2a个驱动电路的第一展宽单元接收第i+1个驱动电路的第二输出单元发送的第一子传递信号，第i+2a个驱动电路的第二展宽单元接收第i+a-1个驱动电路的第二输出单元发送的第二子传递信号时，第一电平信号、第一子传递信号、第一子展宽信号、第二子传递信号、第二子展宽信号、第二子传递信号、第二子展宽信号、展宽信号、控制信号、自举信号、输出模块的输入端口的电位、时钟信号、栅极驱动信号及第二传递信号的时序示意图；
图18是本申请实施例提供的当第i+2a个驱动电路的复位模块与第i+3a+1个驱动电路的第二输出单元连接，第i+2a个驱动电路的控制信号、自举信号、输出模块的输入端口的电位和第三传递信号的时序示意图。
 本发明的实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所提供的技术方案，以下结合具体附图及实施例进行详细说明。
在应用中，栅极驱动器在输出栅极驱动信号之前需要进行充电，栅极驱动器在充电结束后输出栅极驱动信号，栅极驱动器的充电时间越长，栅极驱动信号的稳定性越好。随着用户对显示面板刷新率和分辨率的要求越来越高，在提高栅极驱动器输出栅极驱动信号的频率时，传统的栅极驱动器每次输出栅极驱动信号时的充电时间变短从而无法达到预设电位，栅极驱动信号容易在输出过程中出现电压骤降现象，导致栅极驱动信号输出的稳定性下降，使显示面板的显示亮度不稳定。
本申请实施例提供一种显示面板的驱动电路，可以应用于显示面板，通过展宽模块生成的展宽信号可以使自举模块有足够的时间进行充电，可以保证输出模块在输出栅极驱动信号前达到预设电位，从而避免输出栅极驱动信号时电压不稳定以及避免栅极驱动信号提前中止输出的现象，以提高输出栅极驱动信号的稳定性，进而在提高显示面板刷新率和分辨率的同时提升显示面板的显示亮度和显示效果的稳定性。
在应用中，显示面板可以是基于TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器）技术的液晶显示面板、基于LCD（Liquid Crystal Display，液晶显示器）技术的液晶显示面板、基于OLED（Organic Light-Emitting Diode，有机发光二极管）技术的有机电激光显示面板、基于QLED（Quantum Dot Light Emitting Diodes，量子点发光二极管）技术的量子点发光二极管显示面板或曲面显示面板等。
实施例一
如图1所示，本申请实施例一提供的驱动电路1，包括展宽模块10、控制模块20、自举模块30和输出模块40，控制模块20分别与展宽模块10、自举模块30以及输出模块40电连接，自举模块30与输出模块40电连接；
展宽模块10用于接收第一电平信号，在接收到第一传递信号时，根据第一电平信号生成展宽信号，并将展宽信号发送至控制模块20；第一传递信号包括至少两个时序不同的子传递信号，展宽信号的时间长度根据第一传递信号的时间长度确定；
控制模块20用于接收第一电平信号，在接收到展宽信号时，根据第一电平信号生成控制信号，并将控制信号发送至输出模块40和自举模块30；
自举模块30用于接收控制信号，在控制信号切换至低电平时，发送自举信号至输出模块40；
输出模块40还用于接收时钟信号，在接收到自举信号时，根据时钟信号生成栅极驱动信号和第二传递信号，并将栅极驱动信号发送至显示面板2的子像素210以及发送第二传递信号。
在应用中，驱动电路可以包括多个晶体管、比较器、逻辑门、电阻、电容或电感等电子元器件；电平信号和时钟信号可以通过时序控制器（Timer Control Register，TCON）或片上芯片（System on Chip，SOC）生成并输入至驱动电路；电平信号可以是高电平信号，也可以是低电平信号，时钟信号可以根据实际需要通过TCON或SOC进行移相得到具有相位差的多个时钟信号。
在应用中，展宽模块接收的第一传递信号可以是显示面板的另一个驱动电路的输出模块输出的第二传递信号；第一电平信号可以是直流的高电平信号，展宽模块可以在接收到第一传递信号时导通并输出第一电平信号，并在未接收到第一传递信号时关断并停止输出第一电平信号，从而生成展宽信号，通过延长第一传递信号的时间长度，可以延长展宽信号的时间长度。具体的，第一传递信号可以包括至少两个时序不同的子传递信号，展宽信号的时间长度和第一传递信号的时间长度相同。通过将展宽信号发送至控制模块，可以对控制模块的导通和关断进行控制。
在应用中，控制模块可以在接收到展宽信号时导通并输出第一电平信号，在未接收到展宽信号时关断并停止输出第一电平信号，从而生成控制信号并发送至输出模块和自举模块；控制信号的时间长度和展宽信号的时间长度可以相同，具体的，由于展宽单元可以延长展宽信号的时间长度，因此控制模块可以延长导通时间，实现延长控制信号的时间长度。
在应用中，输出模块在接收到高电平的控制信号时，输出模块的输入端口的电位上拉至第一高电位，然而第一高电位小于预设电位，会导致输出模块输出的栅极驱动信号不稳定。
在应用中，自举模块可以在控制信号从高电平切换至低电平时，发送自举信号至输出模块；输出模块在接收到自举信号时，输出模块的输入端口的电位可以上拉至第二高电位，使输出模块的输入端口可以达到预设电位或超过预设电位。需要说明的是，由于显示面板的显示特性，根据刷新率的频率发送的栅极驱动信号才能用于控制子像素偏转，因此，输出模块可以按照刷新率的频率输出稳定的栅极驱动信号至子像素，以控制子像素偏转，容易理解的是，不稳定的栅极驱动信号和稳定的栅极驱动信号具有一定的时间差，从而不稳定的栅极驱动信号不会用于控制子像素偏转；此外，当不稳定的栅极驱动信号在稳定的栅极驱动信号之前输出时，不稳定的栅极驱动信号可以用于对子像素进行预充电。
其中，预设电位是根据显示面板实际需要的栅极驱动信号电压大小和时间长度确定的，如果输出模块的输入端口可以通过充电达到预设电位，则可以生成完整且稳定的栅极驱动信号。此外，输出模块在接收到自举信号时，还可以生成并发送第二传递信号。其中，控制信号从高电平切换至低电平时的同一时刻，时钟信号可以从低电平切换至高电平；控制模块与输出模块、自举模块的连接处为输出模块的输入端口。
在一个实施例中，自举模块用于接收控制信号，在控制信号为高电平时进行充电。
在应用中，自举模块在控制信号为高电平时进行充电以积累电荷，并在控制信号为高电平切换至低电平时释放上述积累的电荷，从而生成自举信号。
在应用中，输出模块可以为不同的输出对象提供独立的信号，具体的，当输出对象为显示面板的子像素时，输出模块可以提供一个稳定的栅极驱动信号，稳定的栅极驱动信号可以对显示面板的一行或多行子像素进行充电，以驱动显示面板显示画面，其中，一个显示面板可以包括至少一个驱动电路，驱动电路的数量根据上述显示面板使用的时钟信号数量确定；当输出对象为显示面板的另一个驱动电路时，输出模块可以提供一个第二传递信号，从而为上述另一个驱动电路的展宽模块提供第一传递信号。通过为不同的输出对象提供独立的信号，可以避免输出至不同的输出对象的信号之间出现干扰，提高显示面板工作的稳定性。本申请实施例对输出模块的输出对象的类型和数量不做任何限制。
在应用中，通过展宽模块生成的展宽信号可以使自举模块有足够的时间进行充电，保证输出模块在接收自举信号时可以达到或超过预设电位，使输出模块在发送栅极驱动信号和第二传递信号时，可以充分导通并提高信号传输效率，以及避免模块提前关断导致的栅极驱动信号和第二传递信号中止输出，以提高输出栅极驱动信号和第二传递信号的稳定性。
图2示例性的示出了第一电平信号、第一传递信号、展宽信号、控制信号、输出模块的输入端口的电位、时钟信号、栅极驱动信号及第二传递信号的时序图。
实施例二
如图3所示，基于图1所对应的实施例一，本申请实施例二提供的显示面板的驱动电路1，展宽模块10包括第一展宽单元110和第二展宽单元120，第一展宽单元110和第二展宽单元120分别与控制模块20电连接；
第一展宽单元110用于接收第一电平信号，在接收到第一子传递信号时，根据第一电平信号生成第一子展宽信号，并将第一子展宽信号发送至控制模块20；
第二展宽单元120用于接收第一电平信号，在接收到第二子传递信号时，根据第一电平信号生成第二子展宽信号，并将第二子展宽信号发送至控制模块20；
其中，展宽信号包括第一子展宽信号和第二子展宽信号。
在应用中，展宽模块可以包括至少两个展宽单元，每个展宽单元的工作原理和前述实施例提供的展宽模块的工作原理一致，区别在于，每个展宽单元通过连接不同的驱动电路的输出模块获取子传递信号，每个展宽单元可以根据子传递信号生成一个子展宽信号，需要说明的是，每个子展宽信号的时间长度可以与对应的子传递信号的时间长度相同，由于每个子传递信号的时序不同，且展宽模块发送的展宽信号由所有子展宽信号组成，因此，展宽信号的时间长度根据子传递信号的数量和时序确定。通过延长展宽信号的时间长度，可以延长控制模块输出的控制信号的时间长度。
具体的，展宽模块可以包括第一展宽单元和第二展宽单元，第一展宽单元和第二展宽单元分别连接不同的驱动电路的输出模块，为了区分不同的展宽单元接收的不同的传递信号，定义第一展宽单元接收的传递信号为第一子传递信号，第二展宽单元接收的传递信号为第二子传递信号。
图4示例性的示出了第一电平信号、第一子传递信号、第一子展宽信号、第二子传递信号、第二子展宽信号、展宽信号及控制信号的时序图，以下结合图4对第一展宽单元和第二展宽单元的工作原理进行说明：
第一展宽单元和第二展宽单元保持接收第一电平信号；第一展宽单元可以在接收到第一子传递信号的t0时刻导通并输出第一电平信号，并在未接收到第一子传递信号时的t1时刻关断并停止输出第一电平信号，从而在第一时间段t01生成高电平的第一子展宽信号；第二展宽单元可以在接收到第二子传递信号的t1时刻导通并输出第一电平信号，并在未接收到第二子传递信号的t2时刻关断并停止输出第一电平信号，从而在第二时间段t12生成第二子展宽信号；其中，第一子传递信号的时序和第一子展宽信号的时序可以相同，同理，第二子传递信号的时序和第二子展宽信号的时序也可以相同，通过控制第一子传递信号和第二子传递信号的时序，可以确定展宽信号的时序，具体的，第一子传递信号和第二子传递信号可以是电压大小相同，相位相差九十度的高电平信号，展宽信号由第一子展宽信号和第二子展宽信号组成。
实施例三
如图5所示，基于图3所对应的实施例二，本申请实施例三提供的显示面板的驱动电路1，第一展宽单元110包括第一电子开关111，第二展宽单元120包括第二电子开关121，第一电子开关111的源极与第二电子开关121的源极连接，第一电子开关111的漏极分别与第二电子开关121的漏极和控制模块20电连接；
第一电子开关111的源极用于接收第一电平信号，在第一电子开关111的栅极接收到第一子传递信号时，第一电子开关111的漏极用于根据第一电平信号生成第一子展宽信号，并将第一子展宽信号发送至控制模块20；
第二电子开关121的源极用于接收第一电平信号，在第二电子开关121的栅极接收到第二子传递信号时，第二电子开关121的漏极用于根据第一电平信号生成第二子展宽信号，并将第二子展宽信号发送至控制模块20。
在应用中，第一电子开关和第二电子开关可以是任意的具有电子开关功能的器件或电路，例如，三极管或金属氧化物半导体场效应晶体管（Metal Oxide Semiconductor Field Effect Transistor，MOSFET），具体的，可以是薄膜场效应晶体管（Thin Film Transistor，TFT）。
以下结合图4的时序图和图5的结构图对第一电子开关和第二电子开关的工作原理进行说明：
第一电子开关的源极和第二电子开关的源极用于接收第一电平信号；第一电子开关的栅极在接收到第一子传递信号的t0时刻导通，使第一电子开关的漏极输出第一电平信号，第一电子开关的栅极在未接收到第一子传递信号的t1时刻关断，使第一电子开关的漏极停止输出第一电平信号，从而在第一时间段t01生成高电平的第一子展宽信号；第二电子开关的栅极在接收到第二子传递信号的t1时刻导通，使第二电子开关的漏极输出第一电平信号，第二电子开关的栅极在未接收到第一子传递信号的t2时刻关断，使第二电子开关的漏极停止输出第一电平信号，从而在第二时间段t12生成高电平的第二子展宽信号。
在应用中，第一电子开关构成的第一展宽单元和第二电子开关构成的第二展宽单元，具有结构简单、容易控制、输出稳定和低成本的优点，可以提高驱动电路的稳定性并降低显示面板的生产成本。
实施例四
如图6所示，基于图5所对应的实施例三，本申请实施例四提供的显示面板的驱动电路1，控制模块20包括第三电子开关201，第三电子开关201的栅极分别与第一电子开关111的漏极和第二电子开关121的漏极连接，第三电子开关201的漏极分别与自举模块30和输出模块40电连接；
第三电子开关201的源极用于接收第一电平信号，在第三电子开关201的栅极接收到展宽信号时，第三电子开关201的漏极用于根据第一电平信号生成控制信号，并将控制信号发送至自举模块30和输出模块40。
在应用中，第三电子开关的选型与上述第一电子开关和第二电子开关的选型一致，在此不再赘述。
以下结合图4的时序图对第三电子开关的工作原理进行说明：
第三电子开关的源极用于接收第一电平信号；第三电子开关的栅极在接收到展宽信号的t0时刻导通，使第三电子开关的漏极输出第一电平信号，第三电子开关的栅极在未接收到第一子传递信号的t2时刻关断，使第三电子开关的漏极停止输出第一电平信号，从而在第一时间段t01和第二时间段t12连续生成高电平的控制信号。
在应用中，第三电子开关构成的控制模块，具有结构简单、容易控制、输出稳定和低成本的优点，配合具有相同优点的第一展宽单元和第二展宽单元，可以进一步提高驱动电路的稳定性并降低显示面板的生产成本。
实施例五
如图7所示，基于图6所对应的实施例四，本申请实施例五提供的显示面板的驱动电路1，输出模块40包括第一输出单元410和第二输出单元420，第一输出单元410分别与第三电子开关201和自举模块30电连接，第二输出单元420分别与第三电子开关201和自举模块30电连接，第一输出单元410的输入端口与第二输出单元420的输入端口连接构成输出模块40的输入端口430；
第一输出单元410用于接收时钟信号，在接收到自举信号时，根据时钟信号生成栅极驱动信号，并将栅极驱动信号发送至显示面板2的子像素210；
第二输出单元420用于接收时钟信号，在接收到自举信号时，根据时钟信号生成第二传递信号，发送第二传递信号；
第二输出单元420还用于接收第一子传递信号，在接收到控制信号和时钟信号时，泄放时钟信号。
在应用中，输出模块可以包括多个输出单元，每个输出单元的工作原理和前述实施例提供的输出模块的工作原理一致，输出单元的数量可以根据输出模块连接的输出对象的数量确定，每个输出单元用于为一个输出对象提供独立的信号。
图8示例性的示出了第一子传递信号、第二子传递信号、控制信号、自举信号、输出模块的输入端口的电位、时钟信号、栅极驱动信号及第二传递信号的时序图，以下结合图8对第一输出单元和第二输出单元的工作原理进行说明：
第一输出单元和第二输出单元保持接收时钟信号；第一输出单元可以在接收到控制信号的t0时刻开始充电并持续到t2时刻，以将第一输出单元的输入端口的电位上拉至第一高电位，从而在第一时间段t01第一输出单元输出不稳定的栅极驱动信号；在t2时刻，第一输出单元未接收到控制信号（控制信号由高电平切换至低电平），且第一输出单元接收到自举信号时，第一输出单元的输入端口的电位被进一步拉高至第二高电位，使第一输出单元充分导通并开始输出稳定的栅极驱动信号；第一输出单元在未接收到自举信号的t3时刻关断并停止输出时钟信号，从而在第三时间段t23保持输出稳定的栅极驱动信号。第二输出单元与第一输出单元的工作原理一致，不再赘述，区别在于，第二输出单元在t01时间段可以将时钟信号进行泄放从而不输出第二传递信号，第二输出单元在第三时间段t23可以输出稳定的第二传递信号。其中，第一输出单元的输入端口、第二输出单元的输入端口和输出模块的输入端口的电位相等，输出模块的输入端口的电位大小根据控制信号的电压大小和自举信号的电压大小确定，控制信号的电压大小和自举信号的电压大小可以根据实际需要进行设置。
实施例六
如图9所示，基于图7所对应的实施例五，本申请实施例六提供的显示面板的驱动电路1，第一输出单元410包括第四电子开关411，第二输出单元420包括第五电子开关421和第六电子开关422；
第四电子开关411的栅极与第三电子开关201的漏极连接，第四电子开关411的漏极与显示面板2的子像素210连接，第四电子开关411的栅极、第四电子开关411的漏极及第五电子开关421的栅极分别与自举模块30电连接，第四电子开关411的栅极构成第一输出单元410的输入端口412；
第五电子开关421的栅极与第三电子开关的漏极连接，第五电子开关421的漏极与第六电子开关422的源极连接，第五电子开关421的栅极构成第二输出单元的输入端口423；
第四电子开关411的源极用于接收时钟信号，在第四电子开关411的栅极接收到自举信号时，第四电子开关411的漏极用于根据时钟信号生成栅极驱动信号，并将栅极驱动信号发送至显示面板2；
第五电子开关421的源极用于接收时钟信号，在第五电子开关421的栅极接收到自举信号时，第五电子开关421的漏极用于根据时钟信号生成第二传递信号，发送第二传递信号；
第六电子开关422的栅极用于接收第一子传递信号，在第五电子开关421的栅极接收到控制信号，且第五电子开关421的源极接收到时钟信号时，第六电子开关422的漏极用于根据第一子传递信号泄放时钟信号。
在应用中，第四电子开关和第五电子开关的选型与上述第一电子开关和第二电子开关的选型一致，在此不再赘述。
以下结合图8的时序图对第四电子开关、第五电子开关及第六电子开关的工作原理进行说明：
第四电子开关的源极和第五电子开关的源极保持接收时钟信号；第四电子开关的栅极可以在接收到控制信号的t0时刻开始充电并持续到t2时刻，以将第四电子开关的栅极上拉至第一高电位，从而在第一时间段t01第四电子开关的漏极输出不稳定的栅极驱动信号；在t2时刻，第四电子开关的栅极未接收到控制信号（控制信号由高电平切换至低电平），且第四电子开关的栅极接收到自举信号，第四电子开关的栅极的电位被进一步拉高至第二高电位，使第四电子开关充分导通并开始输出稳定的栅极驱动信号；第四电子开关的栅极在未接收到自举信号的t3时刻关断，且第四电子开关的漏极停止输出时钟信号，从而第四电子开关的漏极在第三时间段t23保持输出稳定的栅极驱动信号。第五电子开关与第四电子开关的工作原理一致，不再赘述，区别在于，第六电子开关的栅极在第一时间段t01接收第一子传递信号，使第六电子开关导通并泄放时钟信号，从而使第五电子开关在第一时间段t01不输出第二传递信号，此外，第五电子开关的漏极在第三时间段t23可以输出稳定的第二传递信号。
在应用中，第四电子开关构成的第一输出单元，第五电子开关和第六电子开关构成的第二输出单元，具有结构简单、容易控制、输出稳定和低成本的优点，配合具有相同优点的第一展宽单元、第二展宽单元及控制模块，可以进一步提高驱动电路的稳定性并降低显示面板的生产成本。
实施例七
如图10所示，基于图9所对应的实施例六，本申请实施例七提供的显示面板的驱动电路1，自举模块30包括第一电容301，第一电容301的第一端分别与第三电子开关201的漏极、第四电子开关411的栅极以及第五电子开关421的栅极连接，第一电容301的第二端分别与第四电子开关411的漏极和显示面板连接；
第一电容301的第一端用于接收控制信号，在控制信号为高电平时对第一电容301进行充电；
第一电容301的第一端还用于在控制信号切换至低电平时，发送自举信号至第四电子开关411的栅极和第五电子开关421的栅极，以将第四电子开关411的栅极和第五电子开关421的栅极上拉至第二高电位。
在应用中，根据第一电容的电容值可以确定第一电容能够积累的最大电荷量，第一电容的电容值越大，第二高电位与第一高电位的电位差越大，其中，第一电容的电容值可以根据实际需要进行设置，第二高电位大于或等于预设电位。
以下结合图8的时序图对第一电容的工作原理进行说明：
第一电容的第一端在接收到高电平的控制信号的t0时刻开始充电，使第一电容积累电荷，充电持续到控制信号由高电平切换至低电平的t2时刻，在t2时刻，第一电容的第一端释放在第一时间段t01和第二时间段t12积累的电荷，即发送自举信号至第四电子开关的栅极和第五电子开关的栅极，以将第四电子开关的栅极和第五电子开关的栅极上拉至第二高电位。
在应用中，选用电容作为自举模块的储能元件可以进行快速且稳定的循环充放电，保证驱动电路的充电效率和充电速度的同时，可以提高驱动电路的耐用性和可靠性。
实施例八
如图11所示，基于图10所对应的实施例七，本申请实施例八提供的显示面板的驱动电路1，驱动电路还包括复位模块50，复位模块50分别与控制模块20、自举模块30及输出模块40电连接；
复位模块50用于接收控制信号，在接收到第三传递信号时，将控制信号发送至接地端；
复位模块50包括第七电子开关501，第七电子开关501的源极分别与第三电子开关201的漏极、第四电子开关411的栅极、第五电子开关421的栅极和第一电容的第一端连接；
第七电子开关501的源极用于接收控制信号，在第七电子开关501的栅极接收到第三传递信号时，第七电子开关501的漏极用于发送控制信号至接地端。
在应用中，第三传递信号可以在输出模块发送栅极驱动信号和第二传递信号之后的任意时刻发送至复位模块，具体发送时刻可以是在栅极驱动信号或第二传递信号切换至低电平时，也可以是在栅极驱动信号或第二传递信号切换至低电平后的时钟信号的六分之一周期处，复位模块可以在接收到第三传递信号时将控制信号发送至接地端，避免控制模块在第一时间段和第二时间段以外的时间继续输出控制信号，并可以将残留在驱动电路中的控制信号导出从而使输出模块的输入端口的电位归零，以提高控制模块输出控制信号的稳定性以及驱动电路运行的稳定性。
在一个实施例中，复位模块还用于接收自举信号，在接收到第三传递信号时，将自举信号发送至接地端。
在应用中，第三传递信号还可以在自举模块发送自举信号之后的任意时刻发送至复位模块，具体发送时刻可以是在自举信号切换至低电平时，也可以是在自举信号切换至低电平后的时钟信号的六分之一周期处，复位模块可以在接收到第三传递信号时将控制信号发送至接地端，避免自举模块在第三时间段以外的时间继续输出自举信号，并可以将残留在驱动电路中的自举信号导出从而使输出模块的输入端口的电位归零，以提高自举模块输出自举信号的稳定性以及驱动电路运行的稳定性。
在应用中，第七电子开关的选型与上述第一电子开关和第二电子开关的选型一致，在此不再赘述。
图12示例性的示出了第三传递信号在自举信号切换至低电平时发送至复位模块的控制信号、自举信号、输出模块的输入端口的电位及第三传递信号的时序图。
以下结合图12对第七电子开关的工作原理进行说明：
第七电子开关的源极保持接收控制信号和自举信号；第七电子开关的栅极可以在接收到第三传递信号的t3时刻导通并发送自举信号至接地端，在未接收到第三传递信号的t4时刻关断并停止发送自举信号至接地端，从而在第四时间段t34将自举信号发送至接地端，使输出模块的输入端口的电位归零。其中，第三传递信号的时间长度可以根据实际需要进行设置。
实施例九
如图13所示，基于图11所对应的实施例八，本申请实施例九提供的显示面板的驱动电路1，驱动电路还包括截止模块60，截止模块60与输出模块电连接；
截止模块60用于接收栅极驱动信号，在接收到截止信号时，发送栅极驱动信号至接地端；
截止模块60包括第八电子开关601；
第八电子开关601的源极分别与第四电子开关411的漏极和第一电容301的第二端连接；
第八电子开关601的源极用于接收栅极驱动信号，在第八电子开关601的栅极接收到截止信号时，第八电子开关601的漏极用于发送栅极驱动信号至接地端。
在应用中，第八电子开关的选型与上述第一电子开关和第二电子开关的选型一致，在此不再赘述。
在应用中，截止信号可以是控制信号的反相信号，截止信号可以通过将驱动电路的控制信号输入至反相器得到，反相器的类型可以是TTL（Transistor Transistor Logic，晶体管-晶体管逻辑电平）非门、CMOS（Complementary Metal Oxide Semiconductor，互补金属氧化物半导体）反相器。截止信号用于在输出模块未进行充电的时间段将第二输出单元接地，避免多余或残留的栅极驱动信号发送至显示面板，可以提高栅极驱动信号输出的稳定性，进而提升显示面板的显示效果。
本申请实施例提供的显示面板的驱动电路，包括展宽模块、控制模块、自举模块和输出模块，控制模块分别与展宽模块、自举模块以及输出模块电连接，自举模块与输出模块电连接，通过展宽模块生成的展宽信号可以使自举模块有足够的时间进行充电，保证输出模块在接收自举信号时可以达到或超过预设电位，从而避免输出栅极驱动信号时电压不稳定以及避免栅极驱动信号提前中止输出的现象，以提高输出栅极驱动信号的稳定性，进而在提高显示面板刷新率和分辨率的同时提升显示面板的显示亮度和显示效果的稳定性。
实施例十
如图14所示，本申请实施例十提供的显示面板的驱动装置，包括2a个时钟信号发生器和n个上述第一至第八实施例提供的驱动电路；
第j个时钟信号发生器与第j+2ka个驱动电路的输出模块连接，第i+2a个驱动电路1001的第一展宽单元与第i个驱动电路1002的第二输出单元连接，第i+2a个驱动电路1001的第二输出单元与第i个驱动电路1002的第二输出单元连接，第i+2a个驱动电路1001的第二展宽单元与第i+a个驱动电路1003的第二输出单元连接；
第j个时钟信号发生器用于生成一个时钟信号，并发送至第j+2ka个驱动电路的输出模块，第j个时钟信号发生器生成的时钟信号与第j+1个时钟信号发生器生成的时钟信号的相位差为π/2a；
第i+2a个驱动电路1001的第一展宽单元用于接收到第i个驱动电路1002的第二输出单元发送的第一子传递信号时，将第一子展宽信号发送至控制模块；
第i+2a个驱动电路1001的第二展宽单元用于接收到第i+a个驱动电路1003的第二输出单元发送的第二子传递信号时，将第二子展宽信号发送至控制模块；
其中，a为大于或等于1的整数，n为大于2a的整数，i∈[1，n-2a]，j=1，2,…,2a，k=0,1,2,…,⌊n/2a⌋，j+2ka小于或等于n。
图14示例性的示出了当第i个驱动电路接收第1个时钟信号发生器发送的时钟信号时的结构示意图，并示出了第i+2a个驱动电路1001的第一子传递信号、第二子传递信号及第三传递信号的输入输出关系。
在应用中，驱动装置包括n个级联的驱动电路，每个驱动电路的第一输出单元与显示面板的子像素连接；驱动电路的数量根据显示面板的子像素行数确定，例如，驱动电路的数量可以等于显示面板的子像素行数，也可以等于显示面板的子像素行数加2a。
在应用中，栅极驱动信号可以根据第1个驱动电路至第n个驱动电路的顺序依次发送至显示面板的第1行子像素至第n行子像素，上一次发送的栅极驱动信号和下一次发送的栅极驱动信号的时间间隔为π/2a。其中，上述栅极驱动信号的时间间隔根据时钟信号发生器的数量确定，可以根据显示面板的实际性能确定时钟信号发生器的数量；TCON或SOC可以在需要通过驱动装置输出栅极驱动信号时，向任意一个驱动电路的控制模块发送与展宽信号波形一致的高电平信号，以触发驱动装置开始工作。
下面分别以a=3，n=7以及a=1，n=4为例对驱动装置中驱动电路之间的连接关系进行举例说明：
当a=3，n=7时，驱动装置包括6个时钟信号发生器和7个驱动电路，第1个时钟信号发生器至第6个时钟信号发生器分别与第1个驱动电路的第一输出单元至第6个驱动电路的第一输出单元一一对应连接，第1个时钟信号发生器还与第7个驱动电路连接；第1（i）个驱动电路的第二输出单元分别与第4（i+a）个驱动电路的第二展宽单元、第7（i+2a）个驱动电路的第一展宽单元、第7（i+2a）个驱动电路的第二输出单元连接并发送第二传递信号；第2个驱动电路的第二输出单元分别与第5个驱动电路的第二展宽单元、第1个驱动电路的第一展宽单元、第1个驱动电路的第二输出单元连接并发送第二传递信号；第3个驱动电路的第二输出单元分别与第6个驱动电路的第二展宽单元、第2个驱动电路的第一展宽单元、第2个驱动电路的第二输出单元连接并发送第二传递信号；第4个驱动电路的第二输出单元分别与第7个驱动电路的第二展宽单元、第3个驱动电路的第一展宽单元、第3个驱动电路的第二输出单元连接并发送第二传递信号；第5个驱动电路的第二输出单元分别与第1个驱动电路的第二展宽单元、第4个驱动电路的第一展宽单元、第4个驱动电路的第二输出单元连接并发送第二传递信号；第6个驱动电路的第二输出单元分别与第2个驱动电路的第二展宽单元、第5个驱动电路的第一展宽单元、第5个驱动电路的第二输出单元连接并发送第二传递信号；第7个驱动电路的第二输出单元分别与第3个驱动电路的第二展宽单元、第6个驱动电路的第一展宽单元、第6个驱动电路的第二输出单元连接并发送第二传递信号。
当a=1，n=4时，驱动装置包括2个时钟信号发生器和4个驱动电路，第1个时钟信号发生器分别与第1个驱动电路的第一输出单元和第3个驱动电路的第一输出单元连接，第2个时钟信号发生器分别与第2个驱动电路的第一输出单元和第4个驱动电路的第一输出单元连接；第1（i）个驱动电路的第二输出单元分别与第2（i+a）个驱动电路的第二展宽单元、第3（i+2a）个驱动电路的第一展宽单元、第3（i+2a）个驱动电路的第二输出单元连接并发送第二传递信号；第2个驱动电路的第二输出单元分别与第3个驱动电路的第二展宽单元、第4个驱动电路的第一展宽单元、第4个驱动电路的第二输出单元连接并发送第二传递信号；第3个驱动电路的第二输出单元分别与第4个驱动电路的第二展宽单元、第1个驱动电路的第一展宽单元、第1个驱动电路的第二输出单元连接并发送第二传递信号；第4个驱动电路的第二输出单元分别与第1个驱动电路的第二展宽单元、第2个驱动电路的第一展宽单元、第2个驱动电路的第二输出单元连接并发送第二传递信号。
在应用中，每个驱动电路生成的第二传递信号和稳定的栅极驱动信号的波形相同；每个驱动电路的第一子传递信号和第二子传递信号可以根据驱动装置的其余驱动电路发送的第二传递信号得到，具体的，第i个驱动电路的第二输出单元与第i+2a个驱动电路的第一展宽单元和第二输出单元连接，并可以发送第二传递信号至第i+2a个驱动电路的第一展宽单元和第二输出单元，以作为第i+2a个驱动电路的第一展宽单元和第二输出单元的第一子传递信号；第i+a个驱动电路的第二输出单元与第i+2a个驱动电路的第二展宽单元连接，并可以发送第二传递信号至第i+2a个驱动电路的第二展宽单元，以作为第i+2a个驱动电路的第二展宽单元的第二子传递信号。
在应用中，由于第j个时钟信号发生器生成的时钟信号与第j+1个时钟信号发生器生成的时钟信号的相位差为π/2a，且第j个时钟信号发生器生成的时钟信号发送至第j+2ka个驱动电路的输出模块，因此，第i个驱动电路生成的稳定的栅极驱动信号（第二传递信号），与第i+1个驱动电路生成的稳定的栅极驱动信号（第二传递信号）的相位差也为π/2a，且上述第i+2a个驱动电路接收的第一子传递信号与第i+2a个驱动电路生成的栅极驱动信号的相位差为π/2，上述第i+2a个驱动电路接收的第二子传递信号与第i+2a个驱动电路生成的栅极驱动信号的相位差为π。根据第一子传递信号和第二子传递信号生成的展宽信号使自举模块有足够的时间进行充电的工作原理可以参照前述第一实施例至第八实施例提供的工作原理，在此不在赘述。
图15示例性的示出了当a=3，第1个时钟信号发生器生成的第1个时钟信号至第7个时钟信号发生器生成的第7个时钟信号的时序示意图。
图16示例性的示出了第i+2a个驱动电路的第一电平信号、第一子传递信号、第一子展宽信号、第二子传递信号、第二子展宽信号、第二子传递信号、第二子展宽信号、展宽信号、控制信号、自举信号、输出模块的输入端口的电位、时钟信号、栅极驱动信号及第二传递信号的时序图。
在一个实施例中，第j个时钟信号发生器与第j+2ka个驱动电路的输出模块连接，第i+2a个驱动电路的第一展宽单元与第i+1个驱动电路的第二输出单元连接，第i+2个驱动电路的第二展宽单元与第i+a-1个驱动电路的第二输出单元连接；
第i+2a个驱动电路的第一展宽单元用于接收到第i+1个驱动电路的第二输出单元发送的第一子传递信号时，将第一子展宽信号发送至控制模块；
第i+2a个驱动电路的第二展宽单元用于接收到第i+a-1个驱动电路的第二输出单元发送的第二子传递信号时，将第二子展宽信号发送至控制模块；
图17示例性的示出了在第i+2a个驱动电路的第一展宽单元接收第i+1个驱动电路的第二输出单元发送的第一子传递信号，第i+2a个驱动电路的第二展宽单元接收第i+a-1个驱动电路的第二输出单元发送的第二子传递信号时，第一电平信号、第一子传递信号、第一子展宽信号、第二子传递信号、第二子展宽信号、第二子传递信号、第二子展宽信号、展宽信号、控制信号、自举信号、输出模块的输入端口的电位、时钟信号、栅极驱动信号及第二传递信号的时序图。
在应用中，由于传输第一子展宽信号的第一电子开关和传输第二子展宽信号的第二电子开关的硬件限制，第一子展宽信号和第二子展宽信号的传输可能具有延迟，从而组成的展宽信号也具有延迟，因此存在控制信号在t2时刻之后仍保持输出的风险，导致输出模块的输入端口的电位在第三时间段t23无法及时上拉至第二高电位，影响第三时间段t23输出的栅极驱动信号的稳定性和时间长度。
在应用中，为了避免控制信号在t2时刻之后仍保持输出，在控制信号的时间长度能够满足让输出模块的输入端口的电位达到第二高电位的前提下，可以调整第i+2a个驱动电路的第一展宽单元和第二展宽单元的连接关系，具体的，可以将第i+2a个驱动电路的第一展宽单元与第i+1个驱动电路的第二输出单元连接，将第i+2个驱动电路的第二展宽单元与第i+a-1个驱动电路的第二输出单元连接，以缩减展宽信号的时间长度，并预留π/a的时间用于避免展宽信号在t2时刻之后仍保持输出。
在应用中，通过将驱动电路进行级联设置并配合时钟信号发生器构成的驱动装置，使用的输入信号少且结构简单，使驱动装置可以稳定循环运行并持续输出多时序的栅极驱动信号，具有抗干扰性能强、成本低廉、输出稳定的优点。
实施例十一
如图14所示，本申请实施例十一提供的驱动装置，第i+2a个驱动电路1001的复位模块与第i+3a+1个驱动电路1004的第二输出单元连接；
第i+2a个驱动电路1001的复位模块用于接收到第i+3a+1个驱动电路1004的第二输出单元发送的第三传递信号时，将控制信号发送至接地端。
在应用中，第i+2a个驱动电路的复位模块与第i+3a+1个驱动电路的第二输出单元连接，并可以接收第i+3a+1个驱动电路的第二输出单元发送的第二传递信号，以作为第i+2a个驱动电路的复位模块的第三传递信号，可以进一步将每个驱动电路的第二输出单元发送的第二传递信号进行复用，提高信号利用率和驱动装置的集成性。
需要说明的是，第n-a个驱动电路的复位模块至第n个驱动电路的复位模块不具有对应的输出模块提供第三传递信号，第n-a个驱动电路的复位模块至第n个驱动电路的复位模块可以与TCON或SOC连接，以获取第三传递信号。
在应用中，第i+2a个驱动电路的复位模块可以与第i+3a个驱动电路的第二输出单元，以及第i+3a个驱动电路的第二输出单元之后的任意一个驱动电路的第二输出单元连接，可以根据复位的速度快慢确定连接关系，具体的，第1+2a个驱动电路的复位模块可以与第i+3a个驱动电路的第二输出单元连接，则第三传递信号与控制信号的相位差为π/2，或者，可以与第i+3a+1个驱动电路的第二输出单元连接，则第三传递信号与控制信号的相位差为π/2+π/a，或者可以与第i+3a+2个驱动电路的第二输出单元连接，则第三传递信号与控制信号的相位差为π/2+2π/a，本申请实施例对第i+2a个驱动电路的复位模块具体连接的驱动电路不作任何限制。
图18示例性的示出了当第i+2a个驱动电路的复位模块与第i+3a+1个驱动电路的第二输出单元连接，第i+2a个驱动电路的控制信号、自举信号、输出模块的输入端口的电位和第三传递信号的时序图。
以上仅为本申请的可选实施例而已，并不用于限制本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (15)

  1. 一种显示面板的驱动电路，包括控制模块和自举模块，其中，所述驱动电路还包括展宽模块和输出模块，所述控制模块分别与所述展宽模块、所述自举模块以及所述输出模块电连接，所述自举模块与所述输出模块电连接；
    所述展宽模块用于接收第一电平信号，在接收到第一传递信号时，根据所述第一电平信号生成展宽信号，并将所述展宽信号发送至控制模块；所述第一传递信号包括至少两个时序不同的子传递信号，所述展宽信号的时间长度根据所述第一传递信号的时间长度确定；
    所述控制模块用于接收所述第一电平信号，在接收到所述展宽信号时，根据第一电平信号生成控制信号，并将所述控制信号发送至所述输出模块和所述自举模块；
    所述自举模块用于接收所述控制信号，在所述控制信号切换至低电平时，发送自举信号至所述输出模块；
    所述输出模块还用于接收时钟信号，在接收到所述自举信号时，根据所述时钟信号生成栅极驱动信号和第二传递信号，并将所述栅极驱动信号发送至所述显示面板的子像素以及发送所述第二传递信号。
  2. 根据权利要求1所述的驱动电路，其中，所述展宽模块包括第一展宽单元和第二展宽单元，所述第一展宽单元和所述第二展宽单元分别与所述控制模块电连接，所述第一传递信号包括第一子传递信号和第二子传递信号；
    所述第一展宽单元用于接收所述第一电平信号，在接收到所述第一子传递信号时，根据所述第一电平信号生成第一子展宽信号，并将所述第一子展宽信号发送至所述控制模块；
    所述第二展宽单元用于接收所述第一电平信号，在接收到所述第二子传递信号时，根据所述第一电平信号生成第二子展宽信号，并将所述第二子展宽信号发送至所述控制模块；
    其中，所述展宽信号包括所述第一子展宽信号和所述第二子展宽信号。
  3. 根据权利要求2所述的驱动电路，其中，所述第一展宽单元包括第一电子开关，所述第二展宽单元包括第二电子开关，所述第一电子开关的源极与所述第二电子开关的源极连接，所述第一电子开关的漏极分别与所述第二电子开关的漏极和所述控制模块电连接。
  4. 根据权利要求3所述的驱动电路，其中，所述第一电子开关的源极用于接收所述第一电平信号，在所述第一电子开关的栅极接收到所述第一子传递信号时，所述第一电子开关的漏极用于根据所述第一电平信号生成第一子展宽信号，并将所述第一子展宽信号发送至所述控制模块；
    所述第二电子开关的源极用于接收所述第一电平信号，在所述第二电子开关的栅极接收到所述第二子传递信号时，所述第二电子开关的漏极用于根据所述第一电平信号生成第二子展宽信号，并将所述第二子展宽信号发送至所述控制模块。
  5. 根据权利要求1所述的驱动电路，其中，所述控制模块包括第三电子开关，所述第三电子开关的栅极分别与第一电子开关的漏极和第二电子开关的漏极连接，所述第三电子开关的漏极分别与所述自举模块和所述输出模块电连接；
    所述第三电子开关的源极用于接收所述第一电平信号，在所述第三电子开关的栅极接收到所述展宽信号时，所述第三电子开关的漏极用于根据第一电平信号生成控制信号，并将所述控制信号发送至所述自举模块和所述输出模块。
  6. 根据权利要求1所述的驱动电路，其中，所述输出模块包括第一输出单元和第二输出单元，所述第一输出单元分别与第三电子开关和所述自举模块电连接，所述第二输出单元分别与第三电子开关和所述自举模块电连接，所述第一输出单元的输入端口与所述第二输出单元的输入端口连接构成所述输出模块的输入端口；
    所述第一输出单元用于接收所述时钟信号，在接收到所述自举信号时，根据所述时钟信号生成栅极驱动信号，并将所述栅极驱动信号发送至所述显示面板的子像素；
    所述第二输出单元用于接收所述时钟信号，在接收到所述自举信号时，根据所述时钟信号生成第二传递信号，发送所述第二传递信号；
    所述第二输出单元还用于接收第一子传递信号，在接收到所述控制信号和时钟信号时，泄放所述时钟信号。
  7. 根据权利要求6所述的驱动电路，其中，所述第一输出单元包括第四电子开关，所述第二输出单元包括第五电子开关和第六电子开关；
    所述第四电子开关的栅极与第三电子开关的漏极连接，所述第四电子开关的漏极与所述显示面板的子像素连接，所述第四电子开关的栅极、所述第四电子开关的漏极及所述第五电子开关的栅极分别与所述自举模块电连接，所述第四电子开关的栅极构成所述第一输出单元的输入端口；
    所述第五电子开关的栅极与第三电子开关的漏极连接，所述第五电子开关的漏极与所述第六电子开关的源极连接，所述第五电子开关的栅极构成所述第二输出单元的输入端口。
  8. 根据权利要求7所述的驱动电路，其中，所述第四电子开关的源极用于接收所述时钟信号，在所述第四电子开关的栅极接收到所述自举信号时，所述第四电子开关的漏极用于根据所述时钟信号生成栅极驱动信号，并将所述栅极驱动信号发送至所述显示面板。
  9. 根据权利要求7所述的驱动电路，其中，所述第五电子开关的源极用于接收所述时钟信号，在所述第五电子开关的栅极接收到所述自举信号时，所述第五电子开关的漏极用于根据所述时钟信号生成所述第二传递信号，发送所述第二传递信号；
    所述第六电子开关的栅极用于接收所述第一子传递信号，在所述第五电子开关的栅极接收到所述控制信号，且所述第五电子开关的源极接收到所述时钟信号时，所述第六电子开关的漏极用于根据所述第一子传递信号泄放所述时钟信号。
  10. 根据权利要求1所述的驱动电路，其中，所述自举模块包括第一电容，所述第一电容的第一端分别与第三电子开关的漏极、第四电子开关的栅极以及第五电子开关的栅极连接，所述第一电容的第二端分别与第四电子开关的漏极和所述显示面板连接。
  11. 根据权利要求10所述的驱动电路，其中，所述第一电容的第一端用于接收所述控制信号，在所述控制信号为高电平时对所述第一电容进行充电；
    所述第一电容的第一端还用于在所述控制信号切换至低电平时，发送所述自举信号至所述第四电子开关的栅极和所述第五电子开关的栅极。
  12. 根据权利要求1所述的驱动电路，其中，所述驱动电路还包括复位模块，所述复位模块分别与所述控制模块、所述自举模块及所述输出模块电连接；
    所述复位模块用于接收所述控制信号，在接收到第三传递信号时，将所述控制信号发送至接地端。
  13. 根据权利要求12所述的驱动电路，其中，所述复位模块包括第七电子开关，所述第七电子开关的源极分别与第三电子开关的漏极、第四电子开关的栅极、第五电子开关的栅极和第一电容的第一端连接；
    所述第七电子开关的源极用于接收所述控制信号，在所述第七电子开关的栅极接收到所述第三传递信号时，所述第七电子开关的漏极用于发送所述控制信号至接地端。
  14. 一种显示面板的驱动装置，其中，包括2a个时钟信号发生器和n个如权利要求1所述的驱动电路；
    第j个时钟信号发生器与第j+2ka个驱动电路的输出模块连接，第i+2a个驱动电路的第一展宽单元与第i个驱动电路的第二输出单元连接，第i+2a个驱动电路的第二输出单元与第i个驱动电路的第二输出单元连接，第i+2a个驱动电路的第二展宽单元与第i+a个驱动电路的第二输出单元连接；
    所述第j个时钟信号发生器用于生成一个时钟信号，并发送至所述第j+2ka个驱动电路的输出模块，所述第j个时钟信号发生器生成的时钟信号与第j+1个时钟信号发生器生成的时钟信号的相位差为π/2a；
    所述第i+2a个驱动电路的第一展宽单元用于接收到所述第i个驱动电路的第二输出单元发送的第一子传递信号时，将第一子展宽信号发送至所述控制模块；
    所述第i+2a个驱动电路的第二展宽单元用于接收到所述第i+a个驱动电路的第二输出单元发送的第二子传递信号时，将第二子展宽信号发送至所述控制模块；
    所述第i+2a个驱动电路的第二输出单元用于接收到所述第i个驱动电路的第二输出单元发送的第一子传递信号，在所述第i+2a个驱动电路的第二输出单元接收到控制信号和时钟信号时，泄放所述时钟信号；
    其中，a为大于或等于1的整数，n为大于2a的整数，i∈[1，n-2a]，j=1，2,…,2a，k=0,1,2,…,⌊n/2a⌋，j+2ka小于或等于n。
  15. 根据权利要求14所述的驱动装置，其中，第i+2a个驱动电路的复位模块与第i+3a+1个驱动电路的第二输出单元连接；
    所述第i+2a个驱动电路的复位模块用于接收到所述第i+3a+1个驱动电路的第二输出单元发送的第三传递信号时，将所述控制信号发送至接地端。
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