WO2023005592A1 - 显示面板的驱动电路和显示装置 - Google Patents

显示面板的驱动电路和显示装置 Download PDF

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Publication number
WO2023005592A1
WO2023005592A1 PCT/CN2022/103022 CN2022103022W WO2023005592A1 WO 2023005592 A1 WO2023005592 A1 WO 2023005592A1 CN 2022103022 W CN2022103022 W CN 2022103022W WO 2023005592 A1 WO2023005592 A1 WO 2023005592A1
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WO
WIPO (PCT)
Prior art keywords
signal
output
electronic switch
control signal
switch
Prior art date
Application number
PCT/CN2022/103022
Other languages
English (en)
French (fr)
Inventor
沈婷婷
袁海江
Original Assignee
惠科股份有限公司
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Publication date
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to EP22848197.4A priority Critical patent/EP4379703A1/en
Priority to JP2023541328A priority patent/JP2024506132A/ja
Priority to KR1020237027341A priority patent/KR20230129534A/ko
Priority to US18/256,715 priority patent/US11875726B2/en
Publication of WO2023005592A1 publication Critical patent/WO2023005592A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present application relates to the field of display technology, in particular to a driving circuit of a display panel and a display device.
  • the refresh rate (Frames Per Second, FPS) is an important index to measure the display effect of the display panel.
  • the refresh rate determines the number of frames transmitted per second. The higher the refresh rate, the shorter the time interval of each frame, which can improve The clarity and fluency of the display screen can effectively improve the display effect.
  • One of the objectives of the embodiments of the present application is to provide a display panel driving circuit and a display device, aiming at solving the problem of high power consumption of the existing high refresh rate display panel.
  • a driving circuit of a display panel including a generation module, an output module and a switch control module;
  • the output module is electrically connected to the generation module and the switch control module respectively;
  • the generating module is configured to receive a first clock signal, a second clock signal, a first control signal, and a second control signal, and generate the first clock signal and the second control signal according to the first control signal and the second control signal.
  • the second clock signal is processed to obtain a generated signal, and the generated signal is output to the output module; the first clock signal and the second clock signal have a preset phase difference;
  • the switch control module is configured to output a switch control signal to the output module according to the received first level signal, second level signal and third control signal;
  • the output module When the third control signal is at low level, the output module is configured to output the generated signal to the gate driver according to the switch control signal; when the third control signal is at high level, the output module It is also used for outputting the first clock signal or the second clock signal to the gate driver according to the switch control signal.
  • a display device including a display panel, a control unit, a source driver, and a gate driver;
  • the display panel is connected to the source driver and the gate driver respectively, and the control unit is connected to the source driver and the gate driver respectively;
  • the control unit includes the drive circuit described in the first aspect above;
  • the drive circuit of the control unit is connected to the gate driver.
  • the first aspect of the embodiment of the present application provides a driving circuit for a display panel, including a generating module, an output module, and a switch control module; the output module is electrically connected to the generating module and the switch control module; the output module is used to output Generate a signal to the gate driver; the output module is also used to output the first clock signal and the second clock signal to the gate driver according to the switch control signal, which can change the refresh rate of the display panel in real time and reduce the power consumption of the high refresh rate display panel.
  • the output signal of the output module can be continuous without interruption, so as to improve the display effect of the display panel and prolong the life of the display panel.
  • FIG. 1 is a first structural schematic diagram of a driving circuit of a display panel provided by an embodiment of the present application
  • Fig. 2 is a schematic diagram of the timing of the first clock signal, the second clock signal and the generated signal provided by the embodiment of the present application;
  • Fig. 3 is a timing schematic diagram of the first clock signal, the second clock signal, the third control signal, the generated signal, and the output signal including the first clock signal and the generated signal provided by the embodiment of the present application;
  • FIG. 4 is a second structural schematic diagram of a driving circuit of a display panel provided by an embodiment of the present application.
  • Figure 5 shows the first clock signal, the second clock signal, the first control signal, the second control signal, the third control signal, the first generated signal, the second generated signal, the first output signal and the second generated signal provided by the embodiment of the present application.
  • FIG. 6 is a schematic diagram of a third structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a fourth structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a fifth structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a sixth structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a seventh structure of a driving circuit of a display panel provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • An embodiment of the present application provides a driving circuit for a display panel, which can be applied to a display panel.
  • the refresh rate of the display panel can be changed in real time, so that the display panel can operate at a high refresh rate or a low refresh rate while ensuring the display effect. Switch between to reduce the power consumption of the high refresh rate display panel and prolong the life of the display panel.
  • the display panel can be based on TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display) technology liquid crystal display panel, liquid crystal display panel based on LCD (Liquid Crystal Display, liquid crystal display) technology, OLED (Organic Light-Emitting Organic electro-laser display panels based on Diode (Organic Light Emitting Diode) technology, based on QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) technology quantum dot light-emitting diode display panel or curved display panel, etc.
  • TFT-LCD Thi Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display
  • LCD Liquid Crystal Display, liquid crystal display
  • OLED Organic Light-Emitting Organic electro-laser display panels based on Diode (Organic Light Emitting Diode) technology
  • QLED Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode
  • the display panel drive circuit 1 provided in the first embodiment of the present application includes a generation module 10 , a switch control module 20 and an output module 30 ;
  • the output module 30 is electrically connected to the generation module 10 and the switch control module 20 respectively;
  • the generating module 10 is configured to receive the first clock signal, the second clock signal, the first control signal and the second control signal, and process the first clock signal and the second clock signal according to the first control signal and the second control signal to obtain Generate a signal, and output the generated signal to the output module 30; the first clock signal and the second clock signal have a preset phase difference;
  • the switch control module 20 is used to output the switch control signal to the output module 30 according to the received first level signal, second level signal and third control signal;
  • the output module 30 When the third control signal is at a low level, the output module 30 is used to output the generated signal to the gate driver 2 according to the switch control signal; when the third control signal is at a high level, the output module 30 is also used to output the first A clock signal or a second clock signal is sent to the gate driver 2 .
  • the driving circuit may include electronic components such as multiple transistors, comparators, logic gates, resistors, capacitors or inductors; the first clock signal, the second clock signal, the first level signal, the second level signal, The first control signal, the second control signal and the third control signal may be input to the driving circuit by a timing controller (Timer Control Register, TCON) or an on-chip chip (System on Chip, SOC); the second clock signal may be through The TCON or the SOC shifts the phase of the first clock signal, and the preset phase difference between the phase shifted second clock signal and the first clock signal may range from 0° to 180°.
  • TCON Timer Control Register
  • SOC System on Chip
  • the cycle of the first clock signal and the cycle of the second clock signal can have the same preset cycle, and the cycle of the first clock signal and the second clock signal
  • the preset phase difference can be specifically 90 degrees, then when the first clock signal is at a high level, the second clock signal is at a low level, similarly, when the second clock signal is at a high level, the first clock signal is at a low level flat;
  • the input of the generation module is the first clock signal and the second clock signal.
  • the generated signal can include the first clock signal in the first time period, and include the second clock signal in the second time period.
  • the timing end point of can be located at a quarter of any period of the first clock signal, then the timing end point of the first time period and the timing start point of the second time period are located at a quarter of any period of the first clock signal or, the timing start point of the first time period and the timing end point of the second time period can be located at three-quarters of any cycle of the first clock signal, then the timing end point of the first time period and the second time period
  • the timing starting point of the time period is located at a quarter of any cycle of the first clock signal; wherein, the level of the first half
  • FIG. 2 exemplarily shows that when the output of the generation module in the first time period t01 is the first clock signal, and when the output in the second time period t12 is the second clock signal, the first clock signal, the second clock signal and The timing diagram of the generated signal, where the timing start point of the first time period t01 is time t0, the timing end point of the first time period t01 and the timing start point of the second time period are time t1, and the timing end point of the second time period t12 is t2 time, since the timing end point of the second time period in any cycle is also the timing starting point of the first time period in the next cycle, so the time t2 in any cycle is also the time t0 in the next cycle;
  • the corresponding relationship between the timing and the generated signal is explained:
  • the generation module starts to output the first clock signal, that is, the generated signal includes a high-level first clock signal; after a quarter of the first cycle, the generated signal changes from high to The first clock signal of the level is converted into the first clock signal of the low level; after a quarter of the preset cycle, it reaches the timing end point of the first time period t01 and the timing starting point t1 of the second time period t12 , the generation module starts to output the second clock signal and stops outputting the first clock signal, that is, the generated signal includes a high-level second clock signal, so that the generated signal is converted from a low-level first clock signal to a high-level second clock signal Clock signal; after a quarter of a preset period, the generated signal is converted from a high-level second clock signal to a low-level second clock signal; after a quarter of a preset period, it reaches At the timing end point t2 of the second time period t12, a cycle
  • a gate driver can be connected between the output module and the display panel, and the output signal of the output module can be output to the driving gate driver to control the gate driver to output the row driving signal, and to control the pixel gate of the display panel step by step Line scanning, thereby controlling the pixel charging cycle of the display panel, and then controlling the refresh rate of the display panel. Therefore, by changing the period of the output signal of the output module, the refresh rate of the display panel can be changed; the output module can have two types of output signals, the first type of output signal can be the first clock signal or the second clock signal, and the second type The output signal type may be a generated signal.
  • the output signal of the output module is the first clock signal or the second clock signal
  • the period of the first clock signal and the second clock signal is a preset period
  • the display panel is controlled to work at the first refresh rate
  • the period of the generated signal is half of the preset period
  • the display panel is controlled to work at the second refresh rate.
  • the switch control module can be used to switch the output signal type of the output module, so as to control the change of the refresh rate of the display panel.
  • the switch control module when the third control signal is at the first preset level, the switch control module outputs the switch control Signal to the output module, the output signal type can be switched to the generated signal; when the third control signal is at the second preset level, the switch control signal is output to the output module through the switch control module, and the output signal type can be switched to the first clock signal or the second clock signal, to realize the seamless switching of the output module between outputting the first clock signal or the second clock signal and outputting the generated signal, so that the output signal can include the first clock signal and the generated signal, or include the second Clock signals and generated signals.
  • the first preset level can be low level or high level, when the first preset level is low level, the second preset level is high level; When the level is a high level, the second preset level is a low level.
  • the output signal of the output module can be continuous and uninterrupted, so that when the refresh rate of the traditional display panel is changed, the phenomenon of black screen and flickering caused by the interval between outputting two gate drive signals with different periods can be avoided.
  • black screen and flickering screen it is necessary to re-drive the pixels of the display panel, which will affect the life of the display panel every time the refresh rate is switched. Therefore, while reducing the power consumption of the high refresh rate display panel, the display effect can be improved and the Extend the life of the display panel.
  • Fig. 3 exemplarily shows that when the first preset level is low level, the first clock signal, the second clock signal, the third control signal, the generated signal and the output signal including the first clock signal and the generated signal timing diagram.
  • the display state of the display panel is obtained through the switch control module, and the level of the third control signal is adjusted according to the display state of the display panel.
  • the switch control module when the display screen refresh rate of the display panel is lower than the preset threshold, can control the third control signal to switch to a high level; when the display screen refresh rate of the display panel is higher than the preset threshold, the switch control module The module can control the third control signal to switch to a low level, wherein the above-mentioned preset threshold can be the second refresh rate, specifically 60 Hz, 120 Hz, 144 Hz or 240 Hz, etc., so that the adaptive refresh rate can be realized
  • the adjustment improves the flexibility and controllability of changing the refresh rate of the display panel, and can minimize the power consumption of the high refresh rate display panel.
  • the generation module 10 includes a first generation unit 110 and a second generation unit 120 ;
  • the first generating unit 110 and the second generating unit 120 are respectively electrically connected to the output module 30;
  • the first generation unit 110 is used to process the first clock signal within the first time period to obtain the first generated signal, and output the first generated signal to the output module 30; the first generation unit 110 is also used to process the first clock signal during the second time period Internally process the second clock signal to obtain the first generated signal, and output the first generated signal to the output module 30;
  • the second generating unit 120 is used to process the second clock signal within the first time period to obtain a second generated signal, and output the second generated signal to the output module 30; the second generating unit 120 is also used to process the second clock signal during the second time period Internally process the first clock signal to obtain a second generated signal, and output the second generated signal to the output module 30;
  • the first control signal is at high level and the second control signal is at low level during the first time period, and the first control signal is at low level and the second control signal is at high level during the second time period.
  • the generating module may include a plurality of generating units, and the generated signals output by any two generating units have a phase difference.
  • the generating module may include a first generating unit and a second generating unit, and the input of the first generating unit
  • the output of the first generation unit can be controlled by the first control signal and the second control signal, so that the first generation unit can output the first generation signal
  • the above-mentioned first generated signal is the first clock signal in the first time period, and is the second clock signal in the second time period
  • the input of the second generation unit is also the first clock signal and the second clock signal, the first control signal and the second control signal, through the first control signal and the second control signal to control the output of the second generation unit
  • the second generation unit can generate the second generation signal
  • the second generation signal is the second generation signal in the first time period clock signal, and the first clock signal during the second time period.
  • the first control signal can be obtained by phase-shifting the first clock signal or the second clock signal through TCON or SOC.
  • the second control signal can also be obtained by shifting the phase of the first clock signal or the second clock signal through TCON or SOC. Obtained by phase shifting; the phase difference between the first control signal and the first clock signal can be 45 degrees or 135 degrees, and the phase difference between the second control signal and the first control signal can be 90 degrees.
  • the first control signal is at a high level
  • the second control signal is at low level.
  • Fig. 5 exemplarily shows the timing diagram of the first clock signal, the second clock signal, the first control signal, the second control signal, the third control signal, the first generated signal and the second generated signal, the following is combined with Fig. 5
  • Fig. 5 explain in detail the functions of the first control signal and the second control signal:
  • the first control signal is switched to a high level and the second control signal is switched to a low level to control the first generating unit to output the first A clock signal, and control the second generation unit to output the second clock signal; at the timing end point of the first time period t01 and the timing start point t1 of the second time period t12, the first control signal switches to low level and the second control signal
  • the signal is switched to a high level, controlling the first generating unit to output the second clock signal, and controlling the second generating unit to output the first clock signal; in this way, the cycle is continued, so that the first generating signal includes the first clock signal and the second clock signal, And the second generated signal includes the first clock signal and the second clock signal, the periods of the first generated signal and the second generated signal are equal to half of the preset period, and the phase difference is 90 degrees.
  • the first generating unit and the second generating unit can be controlled simply and effectively through the cooperation of the first control signal and the second control signal, thereby improving the stability and reliability of the first generating signal and the second generating signal.
  • the first generation unit 110 includes a first electronic switch 111 and a second electronic switch 112 ;
  • the drain of the first electronic switch 111 is electrically connected to the drain of the second electronic switch 112, the source of the first electronic switch 111 is used to receive the first clock signal, and the gate of the first electronic switch 111 is used to receive the first control signal. signal, the drain of the first electronic switch 111 is used to output the first clock signal to the output module 30 within the first time period;
  • the source of the second electronic switch 112 is used to receive the second clock signal, the gate of the second electronic switch 112 is used to receive the second control signal, and the drain of the second electronic switch 112 is used to output The second clock signal is sent to the output module 30;
  • the first generated signal includes a first clock signal and a second clock signal.
  • the first electronic switch and the second electronic switch can be any device or circuit with electronic switch function, for example, triode or metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), specifically, may be a thin film field effect transistor (Thin Film Transistor, TFT).
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • TFT Thin Film Transistor
  • the first control signal is switched to high level and the second control signal is switched to low level, the gate of the first electronic switch is at high level, and the first electronic switch turn on, the drain of the first electronic switch starts to output the first clock signal; the gate of the second electronic switch is at low level, the second electronic switch is turned off, and the second electronic switch stops outputting the second clock signal, thereby realizing the first
  • the generating unit outputs a first clock signal in a first time period.
  • the first control signal is switched to low level and the second control signal is switched to high level, the gate of the first electronic switch Very low level, the first electronic switch is turned off, the first electronic switch stops outputting the first clock signal; the gate of the second electronic switch is high level, the second electronic switch is turned on, and the drain of the second electronic switch starts to output The second clock signal, so that the first generation unit can output the second clock signal in the second time period, and then the first generation unit can output the first generation signal.
  • the first generation unit composed of the first electronic switch and the second electronic switch has the advantages of simple structure, easy control, stable output and low cost, which can improve the stability of the driving circuit and reduce the production cost of the display panel.
  • the second generating unit 120 includes a third electronic switch 121 and a fourth electronic switch 122;
  • the drain of the third electronic switch 121 is electrically connected to the drain of the fourth electronic switch 122, the source of the third electronic switch 121 is used to receive the second clock signal, and the gate of the third electronic switch 121 is used to receive the first control signal. signal, the drain of the third electronic switch 121 is used to output a second clock signal to the output module within the first time period;
  • the source of the fourth electronic switch 122 is used to receive the first clock signal
  • the gate of the fourth electronic switch 122 is used to receive the second control signal
  • the drain of the fourth electronic switch 122 is used to , outputting the first clock signal to the output module.
  • the second generated signal includes a first clock signal and a second clock signal.
  • the selection of the third electronic switch and the fourth electronic switch is consistent with the selection of the above-mentioned first electronic switch and the second electronic switch, and will not be repeated here.
  • the first control signal is switched to high level and the second control signal is switched to low level, the gate of the third electronic switch is at high level, and the third electronic switch is turned on, the drain of the third electronic switch starts to output the second clock signal; the gate of the fourth electronic switch is at low level, the fourth electronic switch is turned off, and the fourth electronic switch stops outputting the first clock signal, thereby realizing the second
  • the generating unit outputs the second clock signal during the first time period.
  • the first control signal is switched to low level and the second control signal is switched to high level, the gate of the third electronic switch Very low level, the third electronic switch is turned off, the third electronic switch stops outputting the second clock signal; the gate of the fourth electronic switch is high level, the fourth electronic switch is turned on, and the drain of the fourth electronic switch starts to output The first clock signal, so that the second generation unit can output the first clock signal in the second time period, and then the second generation unit can output the second generation signal.
  • the second generation unit composed of the third electronic switch and the fourth electronic switch has the advantages of simple structure, easy control, stable output and low cost, which can improve the stability of the driving circuit and reduce the production cost of the display panel.
  • the output module 30 includes a first output unit 310 and a second output unit 320 ;
  • the first output unit 310 is electrically connected to the first generation unit 110 and the switch control module 20 respectively, and the second output unit 320 is electrically connected to the second generation unit 120 and the switch control module 20 respectively;
  • the first output unit 310 is used to receive the first generated signal when the third control signal is at a low level, and output the first generated signal to the source driver 2; it is also used to receive the first generated signal when the third control signal is at a high level. a clock signal, and output the first clock signal to the source driver 2;
  • the second output unit 320 is used to receive the second generated signal when the third control signal is at low level, and output the second generated signal to the source driver 2; it is also used to receive the second generated signal when the third control signal is at high level. second clock signal, and output the second clock signal to the source driver 2 .
  • the output module can include multiple output units, and the number of output units can be determined according to the number of generation units. Specifically, the number of output units can be consistent with the number of generation units, and multiple output units and multiple generation units One-to-one correspondence, each output unit is used to receive the generated signal output by the corresponding generating unit, and receive the first clock signal or the second clock signal, the output signal of each output unit may include the first clock signal and the corresponding generating unit The output generation signal may alternatively include the second clock signal and the generation signal output by the corresponding generation unit.
  • the output module may include a first output unit and a second output unit, and the input of the first output unit is the first generation signal, the first clock signal and the switch
  • the control signal controls the output of the first output unit through the switch control signal, so that the first output unit can output the first output signal.
  • the first output signal includes two types of output signals, the first clock signal and the first generated signal, and according to The third control signal switches the output signal type of the first output signal.
  • the first output unit when the third control signal is at a low level, receives the first generated signal and stops receiving the first clock signal, so the first output signal includes The first generated signal outputs the above-mentioned first output signal to the gate driver; when the third control signal is at a high level, the first output unit receives the first clock signal and stops receiving the first generated signal, so the first output signal includes the first output signal A clock signal, outputting the above-mentioned first output signal to the gate driver.
  • the input of the second output unit is the second generation signal, the second clock signal and the switch control signal, and the output of the second output unit can be controlled by the switch control signal, so that the second output unit can output the second output signal, the above
  • the second output signal includes two types of output signals, the second generated signal and the second clock signal, and the output signal type of the second output signal is switched according to the third control signal.
  • the second The second output unit receives the second generated signal and stops receiving the second clock signal, so the second output signal includes the second generated signal, and outputs the above-mentioned second output signal to the display panel or the gate driver; when the third control signal is at a high level , the second output unit receives the second clock signal and stops receiving the second generated signal, so the second output signal includes the second clock signal, and outputs the above-mentioned second output signal to the display panel or the gate driver.
  • the first output signal may also include the second clock signal and the first generated signal.
  • the second output signal may also include the first clock signal and the second generated signal.
  • the output signal types included in the output signal may be Free collocation according to actual needs.
  • Fig. 5 exemplarily shows the first clock signal, the second clock signal, the first control signal, the second control signal, the third control signal, the first generated signal, the second generated signal, the first output signal and the second Timing diagram of the output signal.
  • the phase difference between the first generated signal included in the first output signal and the second generated signal included in the second output signal is 90 degrees, and when the third control signal is at high level Usually, the phase difference between the first clock signal included in the first output signal and the second generated signal included in the second output signal is also 90 degrees.
  • the output module The multiple output units included can provide two or more output signals with different phases for the source driver.
  • a single output signal can reduce the number of gate drive circuits that need to be input to reduce
  • the load of each output signal can also reduce the number of clock generators of the display panel, thereby improving the display stability of the display panel and reducing the production cost of the display panel.
  • the first output unit 310 includes a fifth electronic switch 311 and a sixth electronic switch 312;
  • the drain of the fifth electronic switch 311 is electrically connected to the drain of the sixth electronic switch 312, the source of the fifth electronic switch 311 is used to receive the first clock signal, and the gate of the fifth electronic switch 311 is used to receive the switch control signal , the drain of the fifth electronic switch 311 is used to output the first clock signal to the gate driver 2 when the third control signal is at a high level;
  • the source of the sixth electronic switch 312 is used to receive the first generated signal
  • the gate of the sixth electronic switch 312 is used to receive the switch control signal
  • the drain of the sixth electronic switch 312 is used to receive the first generated signal when the third control signal is low. , outputting the first generated signal to the gate driver 2 .
  • the selection of the fifth electronic switch and the sixth electronic switch is consistent with the selection of the above-mentioned first electronic switch and the second electronic switch, and will not be repeated here.
  • the switch control signal is input to the sixth electronic switch and stops inputting to the fifth electronic switch, and the switch control signal is at high level, then the gate of the sixth electronic switch is at high level. level, the sixth electronic switch is turned on and the fifth electronic switch is turned off, and the drain of the sixth electronic switch outputs the first generated signal, so that the first output unit outputs the first generated signal.
  • the switch control signal when the third control signal is at a high level, the switch control signal is input to the fifth electronic switch and stops being input to the sixth electronic switch. If the switch control signal is at a high level, the gate of the fifth electronic switch is at a high level. level, the fifth electronic switch is turned on and the sixth electronic switch is turned off, the drain of the fifth electronic switch outputs the first clock signal, so that the first output unit outputs the first clock signal, and the first output unit outputs the first output signal.
  • the first output unit composed of the fifth electronic switch and the sixth electronic switch has the advantages of simple structure, easy control, stable output and low cost.
  • the driving circuit can be greatly improved. stability and reduce the production cost of the display panel.
  • the second output unit 320 includes a seventh electronic switch 321 and an eighth electronic switch 322;
  • the drain of the seventh electronic switch 321 is electrically connected to the drain of the eighth electronic switch 322, the source of the seventh electronic switch 321 is used to receive the second clock signal, and the gate of the seventh electronic switch 321 is used to receive the switch control signal , the drain of the seventh electronic switch 321 is used to output the second clock signal to the gate driver 2 when the third control signal is at a high level;
  • the source of the eighth electronic switch 322 is used to receive the second generated signal
  • the gate of the eighth electronic switch 322 is used to receive the switch control signal
  • the drain of the eighth electronic switch 322 is used to , and output the second generated signal to the gate driver 2 .
  • the selection of the seventh electronic switch and the eighth electronic switch is consistent with the selection of the above-mentioned first electronic switch and the second electronic switch, and will not be repeated here.
  • the switch control signal is input to the eighth electronic switch and stops inputting to the seventh electronic switch, and the switch control signal is at high level, then the gate of the eighth electronic switch is at high level. level, the eighth electronic switch is turned on and the seventh electronic switch is turned off, and the drain of the eighth electronic switch outputs the second generated signal, so that the second output unit outputs the second generated signal.
  • the switch control signal is input to the seventh electronic switch and stops inputting to the eighth electronic switch, and the switch control signal is at high level, then the gate of the seventh electronic switch is at high level. level, the seventh electronic switch is turned on and the eighth electronic switch is turned off, the drain of the seventh electronic switch outputs the second clock signal, so that the second output unit can output the second clock signal, and then the second output unit can output the second output signal.
  • the second output unit composed of the seventh electronic switch and the eighth electronic switch has the advantages of simple structure, easy control, stable output and low cost.
  • the driving circuit can be greatly improved. stability and reduce the production cost of the display panel.
  • the switch control module 20 includes a first switch unit 210 and a second switch unit 220 ;
  • the first switch unit 210 is electrically connected to the second switch unit 220, the first output unit 310 and the second output unit 320 respectively, and the second switch unit 220 is electrically connected to the first output unit 310 and the second output unit 320 respectively;
  • the first switch unit 210 is used to receive the first level signal, and output the first switch control signal to the first output unit 310 and the second output unit 320 when the third control signal is low level, and the first switch control signal is high level;
  • the second switch unit 220 is used to receive the second level signal and the third control signal, and output the second switch control signal to the first output unit 310 and the second output unit 320 when the third control signal is at a high level.
  • the switch control signal is high level.
  • the first level signal may be a high level signal
  • the second level may be a low level signal
  • the third control signal may be a pulse signal with adjustable high and low levels.
  • the switch control module may include two switch units, specifically a first switch unit and a second switch unit, the first switch unit is used to output the first switch control signal to all output units, so as to control all output units to output the corresponding generation unit Output generation signal; the second switch unit is used to output a second switch control signal to the output unit, so as to control all output units to output the first clock signal or the second clock signal.
  • the input of the first switch unit is the first level signal
  • the third control signal is at low level
  • the first switch control signal is output to the first output unit and the second output unit
  • the second switch unit stops Outputting the second switch control signal
  • the first switch control signal is a high-level first level signal, thereby controlling the first output unit to output the first generated signal, and controlling the second output unit to output the second generated signal, thereby controlling the display
  • the panel operates at the second refresh rate.
  • the input of the second switch unit is the second level signal and the third control signal
  • the third control signal is high level
  • the second switch control signal is output to the first output unit and the second output unit
  • the first switch unit stops outputting the first switch control signal
  • the second switch control signal is a third control signal of high level, thereby controlling the first output unit to output the first clock signal, and controlling the second output unit to output the second clock signal , and then control the display panel to work at the first refresh rate.
  • the output signal type of the output module can be switched by switching the level of the third control signal.
  • the advantage of this setting is that the refresh rate of the display panel can be changed through an independent signal, thereby improving the request for changing the refresh rate. Response speed provides users with better visual effects and experience.
  • the first switch unit includes a ninth electronic switch 211
  • the second switch unit includes a tenth electronic switch 221 ;
  • the source and gate of the ninth electronic switch 211 are used to receive the first level signal, and the drain of the ninth electronic switch 211 is used to output the first switch control signal to the first output when the third control signal is at low level.
  • the source of the tenth electronic switch 221 is used to receive the second level signal
  • the gate of the tenth electronic switch 221 is used to receive the third control signal
  • the drain of the tenth electronic switch 221 is used to receive the third control signal when the third control signal is high. level
  • the second switch control signal is output to the fifth electronic switch of the first output unit 310 and the seventh electronic switch of the second output unit 320 .
  • the selection of the ninth electronic switch and the tenth electronic switch is consistent with the selection of the above-mentioned first electronic switch and the second electronic switch, and will not be repeated here.
  • the gate of the tenth electronic switch is at low level, and the tenth electronic switch is turned off; the source and gate of the ninth electronic switch receive the first level signal, and the tenth electronic switch
  • the drain of the ninth electronic switch outputs the first switch control signal to the sixth electronic switch of the first output unit, and the eighth electronic switch of the second output unit, so that the sixth electronic switch and the above-mentioned
  • the eighth electronic switch is turned on, thereby controlling the first output unit to output the first generated signal, and controlling the second output unit to output the second generated signal.
  • the gate of the tenth electronic switch is at high level, and the tenth electronic switch is turned on; the source and gate of the ninth electronic switch receive the first level signal, and the tenth electronic switch
  • the ninth electronic switch is turned on, the drain of the ninth electronic switch is at a high level, the source of the tenth electronic switch is at a low level, and the voltages at the drains of the ninth electronic switch and the tenth electronic switch will be neutralized.
  • the third control signal can be output to the fifth electronic switch of the first output unit, and the second output
  • the seventh electronic switch of the unit turns on the fifth electronic switch and the seventh electronic switch, thereby controlling the first output unit to output the first clock signal, and controlling the second output unit to output the second clock signal.
  • the ninth electronic switch and the tenth electronic switch can respond synchronously according to the level of the third control signal, can change the refresh rate of the display panel in real time, and greatly improve the response speed to the request for changing the refresh rate.
  • the driving circuit of the display panel includes a generation module, an output module and a switch control module; the output module is electrically connected to the generation module and the switch control module respectively; the generation module is used to receive the first clock signal, The second clock signal, the first control signal and the second control signal output the generated signal to the output module; wherein the generated signal includes the first clock signal and the second clock signal; the switch control module is used to receive the first level signal according to , the second level signal and the third control signal output the switch control signal to the output module; when the third control signal is low level, the output module is used to generate a signal to the display panel according to the switch control signal output; when the third control signal is When the level is high, the output module is also used to output the first clock signal and the second clock signal to the display panel according to the switch control signal, which can change the refresh rate of the display panel in real time and reduce the power consumption of the high refresh rate display panel. At the same time, the output module outputs The signal can be continuous and uninterrupted to improve the display effect of
  • the tenth embodiment of the present application also provides a display device 3 , including a display panel 31 , a control unit 32 , a source driver 33 , and a gate driver 34 ;
  • the display panel 31 is connected to the source driver 33 and the gate driver 34 respectively, and the control unit 32 is connected to the source driver 33 and the gate driver 34 respectively;
  • the control unit 32 includes the drive circuit provided by any one of the first embodiment to the ninth embodiment of the present application;
  • the drive circuit 35 of the control unit 32 is connected to the gate driver 34 .
  • the functions of the display device include the functions of the driving circuits provided in the above-mentioned first to ninth embodiments, which will not be repeated here.
  • the display device may include, but not limited to, a display panel, a control unit, a source driver, a gate driver, and a driving circuit for controlling a power supply.
  • FIG. 11 is only an example of a display device, and does not constitute a limitation to the display device. It may include more or less components than shown in the figure, or combine certain components, or different components, such as It may also include input and output devices, network access devices, etc.

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Abstract

一种显示面板(31)的驱动电路(1)和显示装置(3)，显示面板(31)的驱动电路(1)包括生成模块(10)、输出模块(30)和开关控制模块(20)；输出模块(30)分别与生成模块(10)和开关控制模块(20)电连接；输出模块(30)用于根据开关控制信号输出生成信号至栅极驱动器(2)；输出模块(30)还用于根据开关控制信号输出第一时钟信号和第二时钟信号至栅极驱动器(2)，可以实时改变显示面板(31)的刷新率，降低高刷新率显示面板(31)的功耗，同时输出模块(30)输出的信号可以连续不间断，以提升显示面板(31)的显示效果并延长显示面板(31)的寿命。

Description

显示面板的驱动电路和显示装置
本申请要求于2021年07月30日在中国专利局提交的、申请号为202110874017.X、发明名称为“显示面板的驱动电路和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，具体涉及一种显示面板的驱动电路和显示装置。
 背景技术
随着显示技术的快速发展，显示面板在娱乐、教育、安防等各种领域得到广泛应用，用户对显示面板的显示效果要求也逐渐提高。刷新率（Frames Per Second，FPS）是衡量显示面板的显示效果的一项重要指标，刷新率决定了画面每秒传输帧数，刷新率越高，每一帧的画面时间间隔越短，可以提高显示画面的清晰度和流畅度，有效提升显示效果。
目前，高刷新率显示面板在中高端市场已经被广泛推广，而高刷新率显示面板的功耗较高，如何降低高刷新率显示面板的功耗成为当前亟需解决的问题。
 技术问题
本申请实施例的目的之一在于：提供一种显示面板的驱动电路和显示装置，旨在解决现有的高刷新率显示面板的功耗较高的问题。
 技术解决方案
本申请实施例采用的技术方案是：
第一方面，提供了一种显示面板的驱动电路，包括生成模块、输出模块和开关控制模块；
所述输出模块分别与所述生成模块和所述开关控制模块电连接；
所述生成模块用于接收第一时钟信号、第二时钟信号、第一控制信号和第二控制信号，根据所述第一控制信号和所述第二控制信号，对所述第一时钟信号和所述第二时钟信号进行处理得到生成信号，并输出所述生成信号至所述输出模块；所述第一时钟信号和所述第二时钟信号具有预设相位差；
所述开关控制模块用于根据接收到的第一电平信号、第二电平信号和第三控制信号输出开关控制信号至所述输出模块；
在所述第三控制信号为低电平时，所述输出模块用于根据所述开关控制信号输出所述生成信号至栅极驱动器；在所述第三控制信号为高电平时，所述输出模块还用于根据所述开关控制信号输出所述第一时钟信号或所述第二时钟信号至栅极驱动器。
第二方面，提供了一种显示装置，包括显示面板、控制单元、源极驱动器、栅极驱动器；
所述显示面板分别与所述源极驱动器和所述栅极驱动器连接，所述控制单元分别与所述源极驱动器和所述栅极驱动器连接；
所述控制单元包括上述第一方面所述的驱动电路；
所述控制单元的驱动电路与所述栅极驱动器连接。
 有益效果
本申请实施例的第一方面提供一种显示面板的驱动电路，包括生成模块、输出模块和开关控制模块；输出模块分别与生成模块和开关控制模块电连接；输出模块用于根据开关控制信号输出生成信号至栅极驱动器；输出模块还用于根据开关控制信号输出第一时钟信号和第二时钟信号至栅极驱动器，可以实时改变显示面板的刷新率，降低高刷新率显示面板的功耗，同时输出模块输出的信号可以连续不间断，以提升显示面板的显示效果并延长显示面板的寿命。
可以理解的是，上述第二方面的有益效果可以参见上述第一方面中的相关描述，在此不再赘述。
 附图说明
图1是本申请实施例提供的显示面板的驱动电路的第一种结构示意图；
图2是本申请实施例提供的第一时钟信号、第二时钟信号和生成信号的时序示意图；
图3是本申请实施例提供的第一时钟信号、第二时钟信号、第三控制信号、生成信号以及包括第一时钟信号和生成信号的输出信号的时序示意图；
图4是本申请实施例提供的显示面板的驱动电路的第二种结构示意图；
图5是本申请实施例提供的第一时钟信号、第二时钟信号、第一控制信号、第二控制信号、第三控制信号、第一生成信号、第二生成信号、第一输出信号和第二输出信号的时序示意图；
图6是本申请实施例提供的显示面板的驱动电路的第三种结构示意图；
图7是本申请实施例提供的显示面板的驱动电路的第四种结构示意图；
图8是本申请实施例提供的显示面板的驱动电路的第五种结构示意图；
图9是本申请实施例提供的显示面板的驱动电路的第六种结构示意图；
图10是本申请实施例提供的显示面板的驱动电路的第七种结构示意图；
图11是本申请实施例提供的显示装置的结构示意图。
 本发明的实施方式
本申请实施例提供一种显示面板的驱动电路，可以应用于显示面板，通过上述驱动电路可以实时改变显示面板的刷新率，使显示面板可以在保证显示效果的同时在高刷新率和低刷新率之间切换，以降低高刷新率显示面板的功耗并延长显示面板的寿命。
在应用中，显示面板可以是基于TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器）技术的液晶显示面板、基于LCD（Liquid Crystal Display，液晶显示器）技术的液晶显示面板、基于OLED（Organic Light-Emitting Diode，有机发光二极管）技术的有机电激光显示面板、基于QLED（Quantum Dot Light Emitting Diodes，量子点发光二极管）技术的量子点发光二极管显示面板或曲面显示面板等。
如图1所示，本申请第一实施例提供的显示面板的驱动电路1，包括生成模块10、开关控制模块20和输出模块30；
输出模块30分别与生成模块10和开关控制模块20电连接；
生成模块10用于接收第一时钟信号、第二时钟信号、第一控制信号和第二控制信号，根据第一控制信号和第二控制信号，对第一时钟信号和第二时钟信号进行处理得到生成信号，并输出生成信号至输出模块30；第一时钟信号和第二时钟信号具有预设相位差；
开关控制模块20用于根据接收到的第一电平信号、第二电平信号和第三控制信号输出开关控制信号至输出模块30；
在第三控制信号为低电平时，输出模块30用于根据开关控制信号输出生成信号至栅极驱动器2；在第三控制信号为高电平时，输出模块30还用于根据开关控制信号输出第一时钟信号或第二时钟信号至栅极驱动器2。
在应用中，驱动电路可以包括多个晶体管、比较器、逻辑门、电阻、电容或电感等电子元器件；第一时钟信号、第二时钟信号、第一电平信号、第二电平信号、第一控制信号、第二控制信号和第三控制信号可以是由时序控制器（Timer Control Register，TCON）或片上芯片（System on Chip，SOC）输入至驱动电路的；第二时钟信号可以是通过TCON或SOC对第一时钟信号移相得到的，移相得到的第二时钟信号和第一时钟信号的预设相位差的范围可以是0度至180度。
在应用中，下面对生成模块的一种驱动方式作详细说明：第一时钟信号的周期和第二时钟信号的周期可以具有相同的预设周期，且第一时钟信号与第二时钟信号的预设相位差具体可以是90度，则当第一时钟信号为高电平时，第二时钟信号为低电平，同理，当第二时钟信号为高电平时，第一时钟信号为低电平；
生成模块的输入为第一时钟信号和第二时钟信号，通过第一控制信号和第二控制信号，可以使生成信号在第一时间段包括第一时钟信号，并在第二时间段包括第二时钟信号；第一时间段和第二时间段的长度可以相同并等于预设周期的一半，且第一时间段和第二时间段不断交替循环，第一时间段的时序起点和第二时间段的时序终点可以位于，第一时钟信号的任意一个周期的四分之一处，则第一时间段的时序终点和第二时间段的时序起点位于，第一时钟信号的任意一个周期的四分之三处；或者，第一时间段的时序起点和第二时间段的时序终点可以位于，第一时钟信号的任意一个周期的四分之三处，则第一时间段的时序终点和第二时间段的时序起点位于，第一时钟信号的任意一个周期的四分之一处；其中，第一时钟信号的前二分之一周期电平不变，则后二分之一周期电平也不变，上述第一时钟信号的前二分之一周期可以是高电平，也可以是低电平；
图2示例性的示出了生成模块在第一时间段t01的输出为第一时钟信号，并在第二时间段t12的输出为第二时钟信号时，第一时钟信号、第二时钟信号和生成信号的时序图，其中，第一时间段t01的时序起点为t0时刻，第一时间段t01的时序终点和第二时间段的时序起点为t1时刻，第二时间段t12的时序终点为t2时刻，由于任意一次循环中第二时间段的时序终点，也是下一次循环中第一时间段的时序起点，因此任意一次循环中的t2时刻也是下一次循环中的t0时刻；下面结合图2对时序和生成信号的对应关系进行说明：
在第一时间段t01的时序起点t0时刻，生成模块开始输出第一时钟信号，即生成信号包括高电平的第一时钟信号；经过四分之一个第一个周期后，生成信号由高电平的第一时钟信号转换为低电平的第一时钟信号；再经过四分之一个预设周期后，到达第一时间段t01的时序终点和第二时间段t12的时序起点t1时刻，生成模块开始输出第二时钟信号并停止输出第一时钟信号，即生成信号包括高电平的第二时钟信号，从而生成信号由低电平的第一时钟信号转换为高电平的第二时钟信号；再经过四分之一个预设周期后，生成信号由高电平的第二时钟信号转换为低电平的第二时钟信号；再经过四分之一个预设周期后，到达第二时间段t12的时序终点t2时刻，完成一次循环，同时也到达下次循环的第一时间段t01的时序起点t0时刻，并开始下一次循环，在上述下一次循环中时序变化和生成信号的变化关系跟上述一次循环一致，以此生成信号在第一时间段t01和第二时间段t12不断循环，使输出模块输出稳定的生成信号，生成信号的周期等于预设周期的一半。
在应用中，输出模块和显示面板之间可以连接栅极驱动器，输出模块的输出信号可以输出至驱动栅极驱动器，以控制栅极驱动器输出行驱动信号，并对显示面板的像素栅极进行逐行扫描，从而控制显示面板的像素充电周期，进而控制显示面板的刷新率。因此，通过改变输出模块输出信号的周期，可以改变显示面板的刷新率；输出模块可以具有两种输出信号种类，第一种输出信号种类可以是第一时钟信号或第二时钟信号，第二种输出信号种类可以是生成信号。
在应用中，当输出模块的输出信号是第一时钟信号或第二时钟信号时，第一时钟信号和第二时钟信号的周期为预设周期，控制显示面板以第一刷新率工作；当输出模块的输出信号是生成信号时，生成信号的周期为预设周期的一半，控制显示面板以第二刷新率工作。容易理解的是，在输出模块的输出信号的周期减半时，显示面板的刷新率翻一倍，从而通过切换输出模块输出的信号，可以实时改变显示面板的刷新率，降低高刷新率显示面板的功耗。
在应用中，开关控制模块可以用于切换输出模块的输出信号种类，从而控制显示面板的刷新率改变，具体的，当第三控制信号为第一预设电平时，通过开关控制模块输出开关控制信号至输出模块，可以将输出信号种类切换至生成信号；当第三控制信号为第二预设电平时，通过开关控制模块输出开关控制信号至输出模块，可以将输出信号种类切换至第一时钟信号或第二时钟信号，实现输出模块在输出第一时钟信号或第二时钟信号与输出生成信号之间的无缝切换，使输出信号可以包括第一时钟信号和生成信号，或者，包括第二时钟信号和生成信号。其中，第一预设电平可以是低电平也可以是高电平，当第一预设电平为低电平时，第二预设电平为高电平；同理当第一预设电平为高电平时，第二预设电平为低电平。
在应用中，输出模块的输出信号可以是连续不间断的，从而可以避免传统显示面板在改变刷新率时，输出两种周期不同的栅极驱动信号期间的间隔导致的黑屏、闪屏等现象，而在黑屏、闪屏的过程中需要重新驱动显示面板的像素，导致每次切换刷新率都会影响显示面板的寿命，因此，在降低了高刷新率显示面板的功耗同时，可以提升显示效果并延长显示面板的寿命。
图3示例性的示出了当第一预设电平为低电平，第一时钟信号、第二时钟信号、第三控制信号、生成信号以及包括第一时钟信号和生成信号的输出信号的时序图。
在一个实施例中，通过开关控制模块获取显示面板的显示状态，并根据显示面板的显示状态调整第三控制信号的电平。
在应用中，当显示面板的显示画面刷新率低于预设阈值时，开关控制模块可以控制第三控制信号切换至高电平；当显示面板的显示画面刷新率高于预设阈值时，开关控制模块可以控制第三控制信号切换至低电平，其中，上述预设阈值可以是第二刷新率，具体可以是60赫兹、120赫兹、144赫兹或240赫兹等，从而可以实现刷新率的自适应调节，提高改变显示面板的刷新率的灵活性和可控性，并可以最大限度地降低高刷新率显示面板的功耗。
如图4所示，基于图1所对应的第一实施例，本申请第二实施例提供的显示面板的驱动电路1，生成模块10包括第一生成单元110和第二生成单元120；
第一生成单元110和第二生成单元120分别与输出模块30电连接；
第一生成单元110用于在第一时间段内对第一时钟信号进行处理得到第一生成信号，并输出第一生成信号至输出模块30；第一生成单元110还用于在第二时间段内对第二时钟信号进行处理得到第一生成信号，并输出第一生成信号至输出模块30；
第二生成单元120用于在第一时间段内对第二时钟信号进行处理得到第二生成信号，并输出第二生成信号至输出模块30；第二生成单元120还用于在第二时间段内对第一时钟信号进行处理得到第二生成信号，并输出第二生成信号至输出模块30；
其中，第一时间段内第一控制信号为高电平且第二控制信号为低电平，第二时间段内第一控制信号为低电平且第二控制信号为高电平。
在应用中，生成模块可以包括多个生成单元，任意两个生成单元输出的生成信号均具有相位差，具体的，生成模块可以包括第一生成单元和第二生成单元，第一生成单元的输入为第一时钟信号、第二时钟信号、第一控制信号和第二控制信号，通过第一控制信号和第二控制信号控制第一生成单元的输出，可以使第一生成单元输出第一生成信号，上述第一生成信号在第一时间段为第一时钟信号，并在第二时间段为第二时钟信号；第二生成单元的输入也为第一时钟信号和第二时钟信号、第一控制信号和第二控制信号，通过第一控制信号和第二控制信号控制第二生成单元的输出，可以使第二生成单元生成第二生成信号，上述第二生成信号在第一时间段为第二时钟信号，并在第二时间段为第一时钟信号。
在应用中，第一控制信号可以通过TCON或SOC对第一时钟信号或第二时钟信号移相得到，同理，第二控制信号也可以通过TCON或SOC对第一时钟信号或第二时钟信号移相得到；第一控制信号与第一时钟信号的相位差可以是45度或135度，第二控制信号与第一控制信号的相位差可以是90度，在第一控制信号为高电平时，第二控制信号为低电平。
图5示例性的示出了第一时钟信号、第二时钟信号、第一控制信号、第二控制信号、第三控制信号、第一生成信号和第二生成信号的时序图，下面结合图5对第一控制信号和第二控制信号的作用作详细说明：
在第一时间段t01的时序起点t0时刻（第二时间段t12的时序终点t2时刻），第一控制信号切换至高电平且第二控制信号切换至低电平，控制第一生成单元输出第一时钟信号，以及控制第二生成单元输出第二时钟信号；在第一时间段t01的时序终点和第二时间段t12的时序起点t1时刻，第一控制信号切换至低电平且第二控制信号切换至高电平，控制第一生成单元输出第二时钟信号，以及控制第二生成单元输出第一时钟信号；以此不断循环，使第一生成信号包括第一时钟信号和第二时钟信号，以及使第二生成信号包括第一时钟信号和第二时钟信号，第一生成信号和第二生成信号的周期均等于预设周期的一半，且相位差为90度。
在应用中，通过第一控制信号和第二控制信号的配合可以简单有效的控制第一生成单元和第二生成单元，从而提高第一生成信号和第二生成信号的稳定性和可靠性。
如图6所示，基于图4所对应的第二实施例，本申请第三实施例提供的驱动电路1，第一生成单元110包括第一电子开关111和第二电子开关112；
第一电子开关111的漏极与第二电子开关112的漏极电连接，第一电子开关111的源极用于接收第一时钟信号，第一电子开关111的栅极用于接收第一控制信号，第一电子开关111的漏极用于在第一时间段内，输出第一时钟信号至输出模块30；
第二电子开关112的源极用于接收第二时钟信号，第二电子开关112的栅极用于接收第二控制信号，第二电子开关112的漏极用于在第二时间段内，输出第二时钟信号至输出模块30；
其中，第一生成信号包括第一时钟信号和第二时钟信号。
在应用中，第一电子开关和第二电子开关可以是任意的具有电子开关功能的器件或电路，例如，三极管或金属氧化物半导体场效应晶体管（Metal Oxide Semiconductor Field Effect Transistor，MOSFET），具体的，可以是薄膜场效应晶体管（Thin Film Transistor，TFT）。
在应用中，在第一时间段t01的时序起点t0时刻，第一控制信号切换至高电平且第二控制信号切换至低电平，第一电子开关的栅极为高电平，第一电子开关导通，第一电子开关的漏极开始输出第一时钟信号；第二电子开关的栅极为低电平，第二电子开关关断，第二电子开关停止输出第二时钟信号，从而实现第一生成单元在第一时间段输出第一时钟信号。
在应用中，在第一时间段t01的时序终点和第二时间段t12的时序起点t1时刻，第一控制信号切换至低电平且第二控制信号切换至高电平，第一电子开关的栅极为低电平，第一电子开关关断，第一电子开关停止输出第一时钟信号；第二电子开关的栅极为高电平，第二电子开关导通，第二电子开关的漏极开始输出第二时钟信号，从而实现第一生成单元在第二时间段输出第二时钟信号，进而实现第一生成单元输出第一生成信号。
在应用中，第一电子开关和第二电子开关组成的第一生成单元，具有结构简单、容易控制、输出稳定和低成本的优点，可以提高驱动电路的稳定性并降低显示面板的生产成本。
如图6所示，基于图4所对应的第二实施例，本申请第四实施例提供的驱动电路1，第二生成单元120包括第三电子开关121和第四电子开关122；
第三电子开关121的漏极与第四电子开关122的漏极电连接，第三电子开关121的源极用于接收第二时钟信号，第三电子开关121的栅极用于接收第一控制信号，第三电子开关121的漏极用于在所述第一时间段内，输出第二时钟信号至输出模块；
第四电子开关122的源极用于接收第一时钟信号，第四电子开关122的栅极用于接收第二控制信号，第四电子开关122的漏极用于在所述第二时间段内，输出第一时钟信号至输出模块。
其中，第二生成信号包括第一时钟信号和第二时钟信号。
在应用中，第三电子开关和第四电子开关的选型与上述第一电子开关和第二电子开关的选型一致，在此不再赘述。
在应用中，在第一时间段t01的时序起点t0时刻，第一控制信号切换至高电平且第二控制信号切换至低电平，第三电子开关的栅极为高电平，第三电子开关导通，第三电子开关的漏极开始输出第二时钟信号；第四电子开关的栅极为低电平，第四电子开关关断，第四电子开关停止输出第一时钟信号，从而实现第二生成单元在第一时间段输出第二时钟信号。
在应用中，在第一时间段t01的时序终点和第二时间段t12的时序起点t1时刻，第一控制信号切换至低电平且第二控制信号切换至高电平，第三电子开关的栅极为低电平，第三电子开关关断，第三电子开关停止输出第二时钟信号；第四电子开关的栅极为高电平，第四电子开关导通，第四电子开关的漏极开始输出第一时钟信号，从而实现第二生成单元在第二时间段输出第一时钟信号，进而实现第二生成单元输出第二生成信号。
在应用中，第三电子开关和第四电子开关组成的第二生成单元，具有结构简单、容易控制、输出稳定和低成本的优点，可以提高驱动电路的稳定性并降低显示面板的生产成本。
如图7所示，基于图6对应的第三实施例和第四实施例，本申请第五实施例提供的驱动电路1，输出模块30包括第一输出单元310和第二输出单元320；
第一输出单元310分别与第一生成单元110和开关控制模块20电连接，第二输出单元320分别与第二生成单元120和开关控制模块20电连接；
第一输出单元310用于在第三控制信号为低电平时，接收第一生成信号，并输出第一生成信号至源极驱动器2；还用于在第三控制信号为高电平时，接收第一时钟信号，并输出第一时钟信号至源极驱动器2；
第二输出单元320用于在第三控制信号为低电平时，接收第二生成信号，并输出第二生成信号至源极驱动器2；还用于在第三控制信号为高电平时，接收第二时钟信号，并输出第二时钟信号至源极驱动器2。
在应用中，输出模块可以包括多个输出单元，输出单元的数量可以根据生成单元的数量确定，具体的，输出单元的数量可以跟生成单元的数量一致，且多个输出单元和多个生成单元一一对应，每个输出单元用于接收对应的生成单元输出的生成信号，以及接收第一时钟信号或第二时钟信号，每个输出单元的输出信号可以包括第一时钟信号和对应的生成单元输出的生成信号，或者，可以包括第二时钟信号和对应的生成单元输出的生成信号。
在应用中，生成模块包括第一生成单元和第二生成单元时，输出模块可以包括第一输出单元和第二输出单元，第一输出单元的输入为第一生成信号、第一时钟信号和开关控制信号，通过开关控制信号控制第一输出单元的输出，可以使第一输出单元输出第一输出信号，上述第一输出信号包括第一时钟信号和第一生成信号两种输出信号种类，并根据第三控制信号切换第一输出信号的输出信号种类，具体的，当第三控制信号为低电平时，第一输出单元接收第一生成信号并停止接收第一时钟信号，因此第一输出信号包括第一生成信号，输出上述第一输出信号至栅极驱动器；当第三控制信号为高电平时，第一输出单元接收第一时钟信号并停止接收第一生成信号，因此第一输出信号包括第一时钟信号，输出上述第一输出信号至栅极驱动器。
在应用中，第二输出单元的输入为第二生成信号、第二时钟信号和开关控制信号，通过开关控制信号控制第二输出单元的输出，可以使第二输出单元输出第二输出信号，上述第二输出信号包括第二生成信号和第二时钟信号两种输出信号种类，并根据第三控制信号切换第二输出信号的输出信号种类，具体的，当第三控制信号为低电平时，第二输出单元接收第二生成信号并停止接收第二时钟信号，因此第二输出信号包括第二生成信号，输出上述第二输出信号至显示面板或栅极驱动器；当第三控制信号为高电平时，第二输出单元接收第二时钟信号并停止接收第二生成信号，因此第二输出信号包括第二时钟信号，输出上述第二输出信号至显示面板或栅极驱动器。需要说明的是，第一输出信号也可以包括第二时钟信号与第一生成信号，同理，第二输出信号也可以包括第一时钟信号与第二生成信号，输出信号包括的输出信号种类可以根据实际需要自由搭配。
图5示例性的示出了第一时钟信号、第二时钟信号、第一控制信号、第二控制信号、第三控制信号、第一生成信号、第二生成信号、第一输出信号和第二输出信号的时序图。
在应用中，当第三控制信号为低电平时，第一输出信号包括的第一生成信号与第二输出信号包括的第二生成信号的相位差为90度，当第三控制信号为高电平时，第一输出信号包括的第一时钟信号与第二输出信号包括的第二生成信号的相位差也为90度，在用于生成时钟信号的时钟发生器数量不变的情况下，输出模块包括的多个输出单元，可以为源极驱动器提供两个或更多的相位不同的输出信号，当输出信号的数量增加后，单个输出信号可以减少需要输入的栅极驱动电路的数量，以降低每个输出信号的负载，还可以减少显示面板的时钟发生器的数量，实现提高显示面板的显示稳定性和降低显示面板的生产成本。
如图8所示，基于图7对应的第五实施例，本申请第六实施例提供的驱动电路1，第一输出单元310包括第五电子开关311和第六电子开关312；
第五电子开关311的漏极和第六电子开关312的漏极电连接，第五电子开关311的源极用于接收第一时钟信号，第五电子开关311的栅极用于接收开关控制信号，第五电子开关311的漏极用于在第三控制信号为高电平时，输出第一时钟信号至栅极驱动器2；
第六电子开关312的源极用于接收第一生成信号，第六电子开关312的栅极用于接收开关控制信号，第六电子开关312的漏极用于在第三控制信号为低电平时，输出第一生成信号至栅极驱动器2。
在应用中，第五电子开关和第六电子开关的选型与上述第一电子开关和第二电子开关的选型一致，在此不再赘述。
在应用中，在第三控制信号为低电平时，开关控制信号输入至第六电子开关并停止输入至第五电子开关，开关控制信号为高电平，则第六电子开关的栅极为高电平，第六电子开关导通且第五电子开关关断，第六电子开关的漏极输出第一生成信号，从而实现第一输出单元输出第一生成信号。
在应用中，在第三控制信号为高电平时，开关控制信号输入至第五电子开关并停止输入至第六电子开关，开关控制信号为高电平，则第五电子开关的栅极为高电平，第五电子开关导通且第六电子开关关断，第五电子开关的漏极输出第一时钟信号，从而实现第一输出单元输出第一时钟信号，进而实现第一输出单元输出第一输出信号。
在应用中，第五电子开关和第六电子开关组成的第一输出单元，具有结构简单、容易控制、输出稳定和低成本的优点，配合具有相同优点的第一生成单元，可以大幅提高驱动电路的稳定性并降低显示面板的生产成本。
如图8所示，基于图7对应的第五实施例，本申请第七实施例提供的驱动电路1，第二输出单元320包括第七电子开关321和第八电子开关322；
第七电子开关321的漏极和第八电子开关322的漏极电连接，第七电子开关321的源极用于接收第二时钟信号，第七电子开关321的栅极用于接收开关控制信号，第七电子开关321的漏极用于在第三控制信号为高电平时，输出第二时钟信号至栅极驱动器2；
第八电子开关322的源极用于接收第二生成信号，第八电子开关322的栅极用于接收开关控制信号，第八电子开关322的漏极用于在第三控制信号为低电平时，输出第二生成信号至栅极驱动器2。
在应用中，第七电子开关和第八电子开关的选型与上述第一电子开关和第二电子开关的选型一致，在此不再赘述。
在应用中，在第三控制信号为低电平时，开关控制信号输入至第八电子开关并停止输入至第七电子开关，开关控制信号为高电平，则第八电子开关的栅极为高电平，第八电子开关导通且第七电子开关关断，第八电子开关的漏极输出第二生成信号，从而实现第二输出单元输出第二生成信号。
在应用中，在第三控制信号为高电平时，开关控制信号输入至第七电子开关并停止输入至第八电子开关，开关控制信号为高电平，则第七电子开关的栅极为高电平，第七电子开关导通且第八电子开关关断，第七电子开关的漏极输出第二时钟信号，从而实现第二输出单元输出第二时钟信号，进而实现第二输出单元输出第二输出信号。
在应用中，第七电子开关和第八电子开关组成的第二输出单元，具有结构简单、容易控制、输出稳定和低成本的优点，配合具有相同优点的第二生成单元，可以大幅提高驱动电路的稳定性并降低显示面板的生产成本。
如图9所示，基于图7对应的第六实施例和第七实施例，本申请第八实施例提供的驱动电路1，开关控制模块20包括第一开关单元210和第二开关单元220；
第一开关单元210分别与第二开关单元220、第一输出单元310及第二输出单元320电连接，第二开关单元220分别与第一输出单元310和第二输出单元320电连接；
第一开关单元210用于接收第一电平信号，在第三控制信号为低电平时，输出第一开关控制信号至第一输出单元310和第二输出单元320，第一开关控制信号为高电平；
第二开关单元220用于接收第二电平信号和第三控制信号，在第三控制信号为高电平时，输出第二开关控制信号至第一输出单元310和第二输出单元320，第二开关控制信号为高电平。
在应用中，第一电平信号可以是高电平信号，第二电平可以是低电平信号，第三控制信号可以是高低电平可调的脉冲信号。开关控制模块可以包括两个开关单元，具体可以是第一开关单元和第二开关单元，第一开关单元用于输出第一开关控制信号至所有输出单元，以控制所有输出单元输出对应的生成单元输出的生成信号；第二开关单元用于输出第二开关控制信号至所述输出单元，以控制所有输出单元输出第一时钟信号或第二时钟信号。
在应用中，第一开关单元的输入为第一电平信号，在第三控制信号为低电平时，输出第一开关控制信号至第一输出单元和第二输出单元，且第二开关单元停止输出第二开关控制信号，第一开关控制信号为高电平的第一电平信号，从而控制第一输出单元输出第一生成信号，以及控制第二输出单元输出第二生成信号，进而控制显示面板以第二刷新率工作。
在应用中，第二开关单元的输入为第二电平信号和第三控制信号，在第三控制信号为高电平时，输出第二开关控制信号至第一输出单元和第二输出单元，且第一开关单元停止输出第一开关控制信号，第二开关控制信号为高电平的第三控制信号，从而控制第一输出单元输出第一时钟信号，以及控制第二输出单元输出第二时钟信号，进而控制显示面板以第一刷新率工作。
在应用中，通过切换第三控制信号的电平高低可以实现切换输出模块的输出信号种类，这样设置的好处是可以通过一个独立信号完成改变显示面板的刷新率，从而提高对改变刷新率请求的响应速度，为用户提供更好的视觉效果和体验。
如图10所示，基于图9对应的第八实施例，本申请第九实施例提供的驱动电路1，第一开关单元包括第九电子开关211，第二开关单元包括第十电子开关221；
第九电子开关211的源极和栅极用于接收第一电平信号，第九电子开关211的漏极用于当第三控制信号为低电平时，输出第一开关控制信号至第一输出单元310的第六电子开关和第二输出单元320的第八电子开关；
第十电子开关221的源极用于接收第二电平信号，第十电子开关221的栅极用于接收第三控制信号，第十电子开关221的漏极用于当第三控制信号为高电平时，输出第二开关控制信号至第一输出单元310的第五电子开关和第二输出单元320的第七电子开关。
在应用中，第九电子开关和第十电子开关的选型与上述第一电子开关和第二电子开关的选型一致，在此不再赘述。
在应用中，在第三控制信号为低电平时，第十电子开关的栅极为低电平，第十电子开关关断；第九电子开关的源极和栅极接收第一电平信号，第九电子开关导通，则第九电子开关的漏极输出第一开关控制信号至第一输出单元的第六电子开关，以及第二输出单元的第八电子开关，使上述第六电子开关和上述第八电子开关导通，从而控制第一输出单元输出第一生成信号，以及控制第二输出单元输出第二生成信号。
在应用中，在第三控制信号为高电平时，第十电子开关的栅极为高电平，第十电子开关导通；第九电子开关的源极和栅极接收第一电平信号，第九电子开关导通，则第九电子开关的漏极为高电平，第十电子开关的源极为低电平，第九电子开关的漏极和第十电子开关的漏极处的电压会中和并为低电平，使第一输出单元的第六电子开关和第二输出单元的第八电子开关关断；第三控制信号可以输出至第一输出单元的第五电子开关，以及第二输出单元的第七电子开关，使上述第五电子开关和上述第七电子开关导通，从而控制第一输出单元输出第一时钟信号，以及控制第二输出单元输出第二时钟信号。
在应用中，第九电子开关和第十电子开关可以根据第三控制信号的电平高低进行同步响应，可以实时改变显示面板的刷新率，大幅提高对改变刷新率请求的响应速度。
本申请实施例的提供的显示面板的驱动电路，包括生成模块、输出模块和开关控制模块；输出模块分别与生成模块和开关控制模块电连接；生成模块用于根据接收到的第一时钟信号、第二时钟信号、第一控制信号和第二控制信号输出生成信号至输出模块；其中，生成信号包括第一时钟信号和第二时钟信号；开关控制模块用于根据接收到的第一电平信号、第二电平信号和第三控制信号输出开关控制信号至输出模块；在第三控制信号为低电平时，输出模块用于根据开关控制信号输出生成信号至显示面板；在第三控制信号为高电平时，输出模块还用于根据开关控制信号输出第一时钟信号和第二时钟信号至显示面板，可以实时改变显示面板的刷新率，降低高刷新率显示面板的功耗，同时输出模块输出的信号可以连续不间断，以提升显示面板的显示效果并延长显示面板的寿命。
如图11所示，本申请第十实施例还提供一种显示装置3，包括显示面板31、控制单元32、源极驱动器33、栅极驱动器34；
显示面板31分别与源极驱动器33和栅极驱动器34连接，控制单元32分别与源极驱动器33和栅极驱动器34连接；
控制单元32包括本申请第一实施例至第九实施例任意一个实施例提供的驱动电路；
控制单元32的驱动电路35与栅极驱动器34连接。
在应用中，显示装置的功能包括上述第一实施例至第九实施例提供的驱动电路的功能，在此不再赘述。
在应用中，该显示装置可包括，但不仅限于，显示面板、控制单元、源极驱动器、栅极驱动器和控制电源的驱动电路。本领域技术人员可以理解，图11仅仅是显示装置的举例，并不构成对显示装置的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件，例如还可以包括输入输出设备、网络接入设备等。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种显示面板的驱动电路，其中，包括生成模块、输出模块和开关控制模块；
    所述输出模块分别与所述生成模块和所述开关控制模块电连接；
    所述生成模块用于接收第一时钟信号、第二时钟信号、第一控制信号和第二控制信号，根据所述第一控制信号和所述第二控制信号，对所述第一时钟信号和所述第二时钟信号进行处理得到生成信号，并输出所述生成信号至所述输出模块；所述第一时钟信号和所述第二时钟信号具有预设相位差；
    所述开关控制模块用于根据接收到的第一电平信号、第二电平信号和第三控制信号输出开关控制信号至所述输出模块；
    在所述第三控制信号为低电平时，所述输出模块用于根据所述开关控制信号输出所述生成信号至栅极驱动器；在所述第三控制信号为高电平时，所述输出模块还用于根据所述开关控制信号输出所述第一时钟信号或所述第二时钟信号至栅极驱动器。
  2. 如权利要求1所述的驱动电路，其中，所述生成模块包括第一生成单元和第二生成单元；
    所述第一生成单元和第二生成单元分别与所述输出模块电连接；
    所述第一生成单元用于在第一时间段内对所述第一时钟信号进行处理得到第一生成信号，并输出所述第一生成信号至所述输出模块；所述第一生成单元还用于在所述第二时间段内对所述第二时钟信号进行处理得到第一生成信号，并输出所述第一生成信号至所述输出模块；
    所述第二生成单元用于在第一时间段内对所述第二时钟信号进行处理得到第二生成信号，并输出所述第二生成信号至所述输出模块；所述第二生成单元还用于在所述第二时间段内对所述第一时钟信号进行处理得到第二生成信号，并输出所述第二生成信号至所述输出模块；
    其中，所述第一时间段内所述第一控制信号为高电平且所述第二控制信号为低电平，所述第二时间段内所述第一控制信号为低电平且所述第二控制信号为高电平。
  3. 如权利要求2所述的驱动电路，其中，所述第一生成单元包括第一电子开关和第二电子开关；
    所述第一电子开关的漏极与所述第二电子开关的漏极电连接，所述第一电子开关的源极用于接收所述第一时钟信号，所述第一电子开关的栅极用于接收所述第一控制信号，所述第一电子开关的漏极用于在所述第一时间段内，输出所述第一时钟信号至所述输出模块；
    所述第二电子开关的源极用于接收所述第二时钟信号，所述第二电子开关的栅极用于接收所述第二控制信号，所述第二电子开关的漏极用于在所述第二时间段内，输出所述第二时钟信号至所述输出模块。
  4. 如权利要求2所述的驱动电路，其中，所述第二生成单元包括第三电子开关和第四电子开关；
    所述第三电子开关的漏极与所述第四电子开关的漏极电连接，所述第三电子开关的源极用于接收所述第二时钟信号，所述第三电子开关的栅极用于接收所述第一控制信号，所述第三电子开关的漏极用于在所述第一时间段内，输出所述第二时钟信号至所述输出模块；
    所述第四电子开关的源极用于接收所述第一时钟信号，所述第四电子开关的栅极用于接收所述第二控制信号，所述第四电子开关的漏极用于在所述第二时间段内，输出所述第一时钟信号至所述输出模块。
  5. 如权利要求1所述的驱动电路，其中，所述输出模块包括第一输出单元和第二输出单元；
    所述第一输出单元分别与第一生成单元和所述开关控制模块电连接，所述第二输出单元分别与第二生成单元和所述开关控制模块电连接；
    所述第一输出单元用于在所述第三控制信号为低电平时，接收第一生成信号，并输出所述第一生成信号至所述栅极驱动器；还用于在所述第三控制信号为高电平时，接收所述第一时钟信号，并输出所述第一时钟信号至所述栅极驱动器；
    所述第二输出单元用于在所述第三控制信号为低电平时，接收第二生成信号，并输出所述第二生成信号至所述栅极驱动器；还用于在所述第三控制信号为高电平时，接收所述第二时钟信号，并输出所述第二时钟信号至所述栅极驱动器。
  6. 如权利要求5所述的驱动电路，其中，所述第一输出单元包括第五电子开关和第六电子开关；
    所述第五电子开关的漏极和所述第六电子开关的漏极电连接，所述第五电子开关的源极用于接收所述第一时钟信号，所述第五电子开关的栅极用于接收所述开关控制信号，所述第五电子开关的漏极用于在所述第三控制信号为高电平时，输出所述第一时钟信号至所述栅极驱动器；
    所述第六电子开关的源极用于接收所述第一生成信号，所述第六电子开关的栅极用于接收所述开关控制信号，所述第六电子开关的漏极用于在所述第三控制信号为低电平时，输出所述第一生成信号至所述栅极驱动器。
  7. 如权利要求5所述的驱动电路，其中，所述第二输出单元包括第七电子开关和第八电子开关；
    所述第七电子开关的漏极和所述第八电子开关的漏极电连接，所述第七电子开关的源极用于接收所述第二时钟信号，所述第七电子开关的栅极用于接收所述开关控制信号，所述第七电子开关的漏极用于在所述第三控制信号为高电平时，输出所述第二时钟信号至所述栅极驱动器；
    所述第八电子开关的源极用于接收所述第二生成信号，所述第八电子开关的栅极用于接收所述开关控制信号，所述第八电子开关的漏极用于在所述第三控制信号为低电平时，输出所述第二生成信号至所述栅极驱动器。
  8. 如权利要求1所述的驱动电路，其中，所述开关控制模块包括第一开关单元和第二开关单元；
    所述第一开关单元分别与所述第二开关单元、第一输出单元及第二输出单元电连接，所述第二开关单元分别与所述第一输出单元和第二输出单元电连接；
    所述第一开关单元用于接收第一电平信号，在所述第三控制信号为低电平时，输出第一开关控制信号至所述第一输出单元和第二输出单元，所述第一开关控制信号为高电平；
    所述第二开关单元用于接收第二电平信号和第三控制信号，在所述第三控制信号为高电平时，输出第二开关控制信号至所述第一输出单元和第二输出单元，所述第二开关控制信号为高电平。
  9. 如权利要求8所述的驱动电路，其中，所述第一开关单元包括第九电子开关，所述第二开关单元包括第十电子开关；
    所述第九电子开关的源极和栅极用于接收所述第一电平信号，所述第九电子开关的漏极用于当所述第三控制信号为低电平时，输出所述第一开关控制信号至第一输出单元的第六电子开关和第二输出单元的第八电子开关；
    所述第十电子开关的源极用于接收所述第二电平信号，所述第十电子开关的栅极用于接收所述第三控制信号，所述第十电子开关的漏极用于当所述第三控制信号为高电平时，输出所述第二开关控制信号至第一输出单元的第五电子开关和第二输出单元的第七电子开关。
  10. 如权利要求1所述的驱动电路，其中，所述开关控制模块用于获取显示面板的显示状态，并根据所述显示面板的显示状态调整所述第三控制信号的电平。
  11. 如权利要求10所述的驱动电路，其中，所述开关控制模块用于：
    当显示面板的显示画面刷新率低于预设阈值时，调整所述第三控制信号切换至高电平；
    当显示面板的显示画面刷新率高于预设阈值时，调整所述第三控制信号切换至低电平。
  12. 如权利要求1所述的驱动电路，其中，所述预设相位差的范围为0度至180度。
  13. 如权利要求1所述的驱动电路，其中，所述第一控制信号和所述第二控制信号的相位差为90度。
  14. 如权利要求1所述的驱动电路，其中，所述第一电平信号为高电平信号，所述第二电平信号为低电平信号，所述第三控制信号为高低电平可调的脉冲信号。
  15. 一种显示装置，其中，包括显示面板、控制单元、源极驱动器、栅极驱动器；
    所述显示面板分别与所述源极驱动器和所述栅极驱动器连接，所述控制单元分别与所述源极驱动器和所述栅极驱动器连接；
    所述控制单元包括如权利要求1所述的驱动电路；
    所述控制单元的驱动电路与所述栅极驱动器连接。
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