WO2023019854A1 - 时间数字转换装置及其时间数字转换方法 - Google Patents

时间数字转换装置及其时间数字转换方法 Download PDF

Info

Publication number
WO2023019854A1
WO2023019854A1 PCT/CN2021/141900 CN2021141900W WO2023019854A1 WO 2023019854 A1 WO2023019854 A1 WO 2023019854A1 CN 2021141900 W CN2021141900 W CN 2021141900W WO 2023019854 A1 WO2023019854 A1 WO 2023019854A1
Authority
WO
WIPO (PCT)
Prior art keywords
time
digital conversion
signal
count value
digital
Prior art date
Application number
PCT/CN2021/141900
Other languages
English (en)
French (fr)
Inventor
程韦盛
白順尹
孙伯伟
Original Assignee
神盾股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 神盾股份有限公司 filed Critical 神盾股份有限公司
Publication of WO2023019854A1 publication Critical patent/WO2023019854A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Definitions

  • the invention relates to a conversion device, in particular to a time-to-digital conversion device and a time-to-digital conversion method thereof.
  • the time-to-digital converter can represent the sensing information through the time width, and count the time width through the oscillator, so as to convert the sensing information into a digital output.
  • the time-to-digital converter generally converts the time information into a digital signal by counting the clock signal provided by the oscillator.
  • the pulse width of the clock signal provided by the oscillator is not stable at the initial stage of startup, this will The digital signal cannot correctly reflect the time information.
  • the invention provides a time-to-digital conversion device and a time-to-digital conversion method thereof, which can ensure that the digital signal output by the time-to-digital conversion device provides correct time information.
  • the time-to-digital conversion device of the present invention includes a clock generation circuit and a time-to-digital converter.
  • the clock generation circuit generates n clock signals with different phases, where n is a positive integer.
  • the time-to-digital converter is coupled to the clock generating circuit, and starts counting rising edges or falling edges of the n clock signals to generate digital signals after a predetermined period of time has elapsed since the clock generating circuit starts generating n clock signals.
  • the present invention also provides a time-to-digital conversion method of the time-to-digital conversion device, which includes the following steps.
  • the enabling clock generating circuit generates n clock signals, wherein n is a positive integer. After a predetermined period of time has elapsed since the clock generating circuit starts to generate n clock signals, it starts to count the rising edges or falling edges of the n clock signals to generate digital signals.
  • the time-to-digital converter of the embodiment of the present invention can start to count the rising edge or falling edge of the clock signal to generate the digital signal after a preset period of time has elapsed since the clock generating circuit starts to generate the clock signal. Waiting for the clock signal output by the clock generating circuit to be stable in this way, and then counting the rising edge or falling edge, can ensure that the correctness of the digital signal generated by the time-to-digital conversion device will not be affected by the unstable clock signal of the clock generating circuit.
  • FIG. 1 is a schematic block diagram of a time-to-digital conversion device according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of an operation sequence of a time-to-digital conversion device according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of an operation sequence of a time-to-digital conversion device according to another embodiment of the present invention.
  • FIG. 4 is a flowchart of a time-to-digital conversion method of the time-to-digital conversion device according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a time-to-digital conversion method of a time-to-digital conversion device according to another embodiment of the present invention.
  • FIG. 1 is a schematic block diagram of a time-to-digital conversion device according to an embodiment of the present invention.
  • the time-to-digital conversion device includes a clock generation circuit 102 and a time-to-digital converter 104 , and the clock generation circuit 102 is coupled to the time-to-digital converter 104 .
  • the clock generating circuit 102 can generate n clock signals CK0 ⁇ CKn ⁇ 1 with different phases, wherein n is a positive integer, and the clock generating circuit 102 can be implemented by, for example, a ring oscillator, but not limited thereto.
  • the time-to-digital converter 104 can start counting the rising or falling edges of the clock signals CK0-CKn-1 after the clock generation circuit 102 starts to generate the clock signals CK0-CKn-1 for a preset period of time to generate the digital signal D1 . After waiting for the clock signals CK0 ⁇ CKn-1 output by the clock generating circuit 102 to be stable in this way, counting the rising or falling edges of the clock signals CK0 ⁇ CKn-1 can ensure the correctness of the digital signal D1 generated by the time-to-digital conversion device It is not affected by instability of the clock signals CK0 to CKn-1 of the clock generation circuit 102 .
  • the clock generation circuit 102 is enabled by the received enable signal EN1 and starts to generate the clock signals CK0 - CK3 .
  • the time-to-digital converter 104 can start counting the rising edges of the clock signals CK0 - CK3 according to the received enable signal EN2 after a predetermined period of time T1 has elapsed since the clock generating circuit 102 starts to generate the clock signal. As shown in FIG. 2 , the clock generation circuit 102 is enabled by the received enable signal EN1 and starts to generate the clock signals CK0 - CK3 .
  • the time-to-digital converter 104 can start counting the rising edges of the clock signals CK0 - CK3 according to the received enable signal EN2 after a predetermined period of time T1 has elapsed since the clock generating circuit 102 starts to generate the clock signal. As shown in FIG.
  • the clock signals CK0 ⁇ CK3 are not yet stable and have a relatively large pulse width, and after the preset time T1, the clock signals CK0 ⁇ CK3 become stable and have a smaller and fixed pulse width, so counting the clock signals CK0 - CK3 at this time can reflect the time information more accurately.
  • the time-to-digital converter 104 can determine the signal value of the output digital signal D1 according to the received stop signal SP1, for example.
  • the stop signal SP1 is a pulse signal
  • the time-to-digital converter 104 can determine the signal value of the output digital signal D1 according to the rising edge of the stop signal SP1 (in the embodiment of FIG. 2, the rising edge of the stop signal SP1 The corresponding signal value is 8).
  • the number of clock signals generated by the clock generation circuit 102 is not limited to the embodiment shown in FIG. 2 , and in other embodiments, the clock generation circuit 102 can also generate more or fewer clock signals.
  • the preset time T1 can be determined, for example, according to the time required for the change of the pulse width of the clock signal to be smaller than the preset value within a period of observation time, that is, the time required for the clock signal generated by the clock generating circuit 102 to stabilize Decide.
  • the time-to-digital converter 104 can also count according to the falling edges of the clock signals CK0-CK3 instead of the rising edges. Similarly, the time-to-digital converter 104 can also count according to the falling edges of the stop signal SP1. Determine the signal value of the output digital signal D1.
  • the enable signals EN1 , EN2 and the stop signal SP1 can be provided, for example, by a control circuit (not shown) coupled to the clock generation circuit 102 and the time-to-digital converter 104 .
  • a control circuit (not shown) coupled to the clock generation circuit 102 and the time-to-digital converter 104 .
  • the enable signal EN2 is generated to enable the time-to-digital converter 104 to start counting the rising or falling edges of the stop signal SP1 to ensure that the time-to-digital converter 104 can generate the correct digital signal D1.
  • the time-to-digital conversion device may, for example, be applied to a distance sensing device, such as a time-of-flight distance sensor or an ultrasonic sensor, but is not limited thereto.
  • a distance sensing device such as a time-of-flight distance sensor or an ultrasonic sensor
  • the time point at which the time-to-digital converter 104 starts counting the rising edge of the stop signal SP1 according to the enable signal EN2 may be the time point when the time-of-flight distance sensor emits light beams or the time point when the ultrasonic sensor emits sound waves, and the stop signal SP1 generates
  • the time point of the rising edge can be, for example, the time point when the time-of-flight distance sensor receives the reflected light beam or the time point when the ultrasonic sensor receives the reflected sound wave, so that accurate time information can be obtained through the digital signal D1 generated by the time-to-digital conversion device, which can also make The calculated distance sensing result is correct.
  • the signal value of the digital signal D1 can also be determined by, for example, two count values. For example, as shown in FIG. 3, different from the embodiment in FIG. 2, in the embodiment in FIG. Count value 2) in FIG. 3, and determine a second count value (such as count value 8 in FIG. 3) according to the rising edge of the received stop signal SP1, and generate a digital signal D1 according to the first count value and the second count value.
  • the difference (6) obtained by subtracting the first count value (2) from the second count value (8) can be used as a digital signal D1, which represents the rise from the rising edge of the start signal ST1 to the rising edge of the stop signal SP1 During the period of appearance, the time of 6 accumulated count values has elapsed.
  • the digital signal D1 can be sent to a subsequent signal processing circuit for application processing of the signal.
  • the signal processing circuit can perform application processing related to distance estimation.
  • the time when the rising edge of the start signal ST1 occurs can be the time point when the time-of-flight distance sensor emits a light beam or the time point when the ultrasonic sensor emits sound waves, and the time point when the stop signal SP1 generates a rising edge can be, for example, when the time-of-flight distance sensor receives a reflection The point in time of the beam of light or the point in time at which the ultrasonic sensor receives the reflected sound wave.
  • time-to-digital converter 104 can also count according to the falling edges of the counting clock signals CK0 - CK3 , and determine the first count value and the second count value according to the falling edges of the start signal ST1 and the stop signal SP1 .
  • FIG. 4 is a flowchart of a time-to-digital conversion method of the time-to-digital conversion device according to an embodiment of the present invention. It can be known from the above embodiments that the time-to-digital conversion method of the time-to-digital conversion device may at least include the following steps. First, enable the clock generating circuit to generate n clock signals (step S402 ), wherein n is a positive integer, for example, a first enabling signal may be provided to the clock generating circuit to enable the clock generating circuit to generate n clock signals.
  • the clock generating circuit starts counting the rising or falling edges of the n clock signals to generate a digital signal (step S404), for example, according to the second enabling signal
  • the preset time can be determined, for example, according to the time required for the change of the pulse width of the n clock signals to be smaller than the preset value within a period of observation. Waiting for the clock signal output by the clock generating circuit to be stable before counting the rising edge or falling edge can ensure that the correctness of the digital signal generated by the time-to-digital conversion device will not be affected by the unstable clock signal of the clock generating circuit.
  • FIG. 5 is a flowchart of a time-to-digital conversion method of a time-to-digital conversion device according to another embodiment of the present invention.
  • the time-to-digital conversion method of this embodiment generates a digital signal representing time information based on two count values.
  • the corresponding first count value and second count value can be determined according to the time of the start signal and stop signal received in sequence (step S502), and then according to the first count value and the second count value Generate a digital signal (step S504 ).
  • a digital signal can be generated according to the difference between the first count value and the second count value.
  • the start signal and the stop signal may be, for example, pulse signals, and the first count value and the second count value may be determined according to the count values corresponding to the rising or falling edge generation times of the start signal and the stop signal.
  • the time-to-digital converter of the embodiment of the present invention can start counting the rising or falling edges of the clock signal to generate a digital signal after a predetermined period of time has elapsed since the clock generating circuit starts to generate the clock signal. Waiting for the clock signal output by the clock generating circuit to be stable before counting the rising edge or falling edge can ensure that the correctness of the digital signal generated by the time-to-digital conversion device will not be affected by the unstable clock signal of the clock generating circuit.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Television Systems (AREA)
  • Carbon Steel Or Casting Steel Manufacturing (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

一种时间数字转换装置及其时间数字转换方法。时钟产生电路，产生具有不同相位的n个时钟信号。时间数字转换器于时钟产生电路开始产生n个时钟信号起经过一段预设时间后，开始计数n个时钟信号的上升缘或下降缘，以产生数字信号。

Description

时间数字转换装置及其时间数字转换方法 技术领域
本发明涉及一种转换装置，尤其涉及一种时间数字转换装置及其时间数字转换方法。
背景技术
随着集成电路的发展，将传感器所获得的感测信息转换为数字码的形式，可以实现更加广泛的运用。其中，对于时间量测系统而言，时间数字转换器可通过时间宽度来表示感测信息，并透过振荡器对时间宽度进行计数，从而将感测信息转换为数字形式的输出。
在现有技术中，时间数字转换器一般透过计数振荡器提供的时钟信号来将时间信息转换为数字信号，然由于振荡器启动初期所提供的时钟信号的脉波宽度并不稳定，如此将使数字信号无法正确地反映出时间信息。
发明内容
本发明提供一种时间数字转换装置及其时间数字转换方法，可确保时间数字转换装置输出的数字信号提供正确的时间信息。
本发明的时间数字转换装置包括时钟产生电路以及时间数字转换器。时钟产生电路产生具有不同相位的n个时钟信号，其中n为正整数。时间数字转换器耦接时钟产生电路，于时钟产生电路开始产生n个时钟信号起经过一段预设时间后，开始计数n个时钟信号的上升缘或下降缘，以产生数字信号。
本发明还提供一种时间数字转换装置的时间数字转换方法，包括下列步骤。致能时钟产生电路产生n个时钟信号，其中n为正整数。于时钟产生电路开始产生n个时钟信号起经过一段预设时间后，开始计数n个时钟信号的上升缘或下降缘，以产生数字信号。
基于上述，本发明实施例的时间数字转换器可于时钟产生电路开始产生时钟信号起经过一段预设时间后，开始计数时钟信号的上升缘或下降缘，以产生数字信号。如此等待时钟产生电路输出的时钟信号稳定后，再进行上升 缘或下降缘的计数，可确保时间数字转换装置产生的数字信号的正确性不因时钟产生电路的时钟信号不稳定而受到影响。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1是依照本发明一实施例所绘示的时间数字转换装置的方块示意图。
图2是依照本发明一实施例所绘示的时间数字转换装置的运作时序示意图。
图3是依照本发明另一实施例所绘示的时间数字转换装置的运作时序示意图。
图4是依照本发明一实施例所绘示的时间数字转换装置的时间数字转换方法流程图。
图5是依照本发明另一实施例所绘示的时间数字转换装置的时间数字转换方法流程图。
具体实施方式
为了使本发明之内容可以被更容易明了，以下特举实施例做为本发明确实能够据以实施的范例。另外，凡可能之处，在附图及实施方式中使用相同标号的组件/构件，系代表相同或类似部件。
以下请参照图1，图1是依照本发明一实施例所绘示的时间数字转换装置的方块示意图。时间数字转换装置包括时钟产生电路102以及时间数字转换器104，时钟产生电路102耦接时间数字转换器104。时钟产生电路102可产生具有不同相位的n个时钟信号CK0～CKn-1，其中n为正整数，时钟产生电路102可例如以环型振荡器来实施，然不以此为限。时间数字转换器104则可于时钟产生电路102开始产生时钟信号CK0～CKn-1起经过一段预设时间后，开始计数时钟信号CK0～CKn-1的上升缘或下降缘，以产生数字信号D1。如此等待时钟产生电路102输出的时钟信号CK0～CKn-1稳定后，再进行时钟信号CK0～CKn-1的上升缘或下降缘的计数，可确保时间数字转换装置产生的数字信号D1的正确性不因时钟产生电路102的时钟信号CK0～CKn-1 不稳定而受到影响。
举例来说，如图2所示，时钟产生电路102被所接收到的致能信号EN1致能，而开始产生时钟信号CK0～CK3。时间数字转换器104可在时钟产生电路102开始产生时钟信号起经过一段预设时间T1后，依据接收到的致能信号EN2开始计数时钟信号CK0～CK3的上升缘。如图2所示，在时钟产生电路102产生时钟信号CK0～CK3的初期，时钟信号CK0～CK3尚未稳定而具有较大的脉波宽度，而在经过预设时间T1后，时钟信号CK0～CK3变得稳定而具有较小且固定的脉波宽度，因此此时对时钟信号CK0～CK3进行计数可较正确地反映出时间信息。
时间数字转换器104可例如依据接收到的停止信号SP1来决定输出的数字信号D1的信号值。例如在图2中，停止信号SP1为脉冲信号，时间数字转换器104可依据停止信号SP1的上升缘来决定输出的数字信号D1的信号值(在图2实施例中，停止信号SP1的上升缘所对应的信号值为8)。
值得注意的是，时钟产生电路102所产生的时钟信号的数量并不以图2实施例为限，在其它实施例中，时钟产生电路102也可产生更多或更少的时钟信号。此外，预设时间T1可例如为依据时钟信号的脉波宽度的变化在一段观察时间内小于预设值所需的时间决定，亦即由时钟产生电路102所产生的时钟信号稳定所需的时间决定。在其它实施例中，时间数字转换器104也可例如依据时钟信号CK0～CK3的下降缘进行计数而非依据上升缘，类似地，时间数字转换器104也可例如依据停止信号SP1的下降缘来决定输出的数字信号D1的信号值。
致能信号EN1、EN2以及停止信号SP1可例如由与时钟产生电路102以及时间数字转换器104耦接的控制电路(未绘示)提供。在其它实施例中，也可通过控制电路侦测时钟产生电路102所产生的时钟信号的脉波宽度的变化在最近的一段观察时间内是否小于预设值，并在判断出时钟信号的脉波宽度的变化小于预设值时产生致能信号EN2致能时间数字转换器104开始计数停止信号SP1的上升缘或下降缘，以确保时间数字转换器104可产生正确的数字信号D1。
时间数字转换装置可例如应用于距离感测装置，例如飞行时间距离传感器或超声波传感器，然不以此为限。举例来说，时间数字转换器104依据致 能信号EN2开始计数停止信号SP1的上升缘的时间点可为飞行时间距离传感器发射光束的时间点或超声波传感器发射声波的时间点，而停止信号SP1产生上升缘的时间点可例如为飞行时间距离传感器接收到反射光束的时间点或超声波传感器接收到反射声波的时间点，如此通过时间数字转换装置产生的数字信号D1获得精确的时间信息，也可使计算出的距离感测结果正确。
此外，在部份实施例中，数字信号D1的信号值也可例如由两个计数值来决定。举例来说，如图3所示，与图2实施例不同的是，在图3实施例中，时间数字转换器104可依据接收的起始信号ST1的上升缘来决定第一计数值(例如图3的计数值2)，并依据接收的停止信号SP1的上升缘决定第二计数值(例如图3的计数值8)，并依据第一计数值与第二计数值来产生数字信号D1。例如可将第二计数值(8)减去第一计数值(2)所得到的差值(6)作为数字信号D1，其代表从起始信号ST1的上升缘出现至停止信号SP1的上升缘出现的期间，经过了6次累积计数值的时间。
数字信号D1可被传送给后级的信号处理电路进行信号的应用处理。举例来说，当时间数字转换装置应用于距离感测装置时，例如飞行时间距离传感器或超声波传感器，信号处理电路可进行与距离估算相关的应用处理。起始信号ST1的上升缘出现的时间可为飞行时间距离传感器发射光束的时间点或超声波传感器发射声波的时间点，而停止信号SP1产生上升缘的时间点可例如为飞行时间距离传感器接收到反射光束的时间点或超声波传感器接收到反射声波的时间点。此外，时间数字转换器104也可例如依据计数时钟信号CK0～CK3的下降缘进行计数，并依据起始信号ST1与停止信号SP1的下降缘来决定第一计数值与第二计数值。
图4是依照本发明一实施例所绘示的时间数字转换装置的时间数字转换方法流程图。由上述实施例可知，时间数字转换装置的时间数字转换方法可至少包括下列步骤。首先，致能时钟产生电路产生n个时钟信号(步骤S402)，其中n为正整数，例如可提供第一致能信号给时钟产生电路以致能时钟产生电路产生n个时钟信号。然后，于时钟产生电路开始产生n个时钟信号起经过一段预设时间后，开始计数n个时钟信号的上升缘或下降缘，以产生数字信号(步骤S404)，例如可依据第二致能信号于时钟产生电路开始产生n个时钟信号起经过预设时间后，开始计数n个时钟信号的上升缘或下降缘，以产 生数字信号。其中预设时间可例如为依据n个时钟信号的脉波宽度的变化在一段观察时间内小于预设值所需的时间决定。如此等待时钟产生电路输出的时钟信号稳定后，再进行上升缘或下降缘的计数，可确保时间数字转换装置产生的数字信号的正确性不因时钟产生电路的时钟信号不稳定而受到影响。
图5是依照本发明另一实施例所绘示的时间数字转换装置的时间数字转换方法流程图。相较于图4实施例，本实施例的时间数字转换方法为依据两个计数值来产生代表时间信息的数字信号。如图5所示，可依据依序接收到的起始信号与停止信号的时间决定对应的第一计数值与第二计数值(步骤S502)，然后再依据第一计数值与第二计数值产生数字信号(步骤S504)，举例来说，可依据第一计数值与第二计数值的差值产生数字信号。其中起始信号与停止信号可例如为脉冲信号，第一计数值与第二计数值可为依据起始信号与停止信号的上升缘或下降缘的产生时间所对应的计数值决定。
综上所述，本发明实施例的时间数字转换器可于时钟产生电路开始产生时钟信号起经过一段预设时间后，开始计数时钟信号的上升缘或下降缘，以产生数字信号。如此等待时钟产生电路输出的时钟信号稳定后，再进行上升缘或下降缘的计数，可确保时间数字转换装置产生的数字信号的正确性不因时钟产生电路的时钟信号不稳定而受到影响。
虽然本发明已以实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的精神和范围内，当可作些许的更改与润饰，故本发明的保护范围当视权利要求所界定的为准。

Claims (12)

  1. 一种时间数字转换装置，其特征在于，包括：
    时钟产生电路，产生具有不同相位的n个时钟信号，其中n为正整数；以及
    时间数字转换器，耦接所述时钟产生电路，于所述时钟产生电路开始产生所述n个时钟信号起经过一段预设时间后，开始计数所述n个时钟信号的上升缘或下降缘，以产生数字信号。
  2. 根据权利要求1所述的时间数字转换装置，其特征在于，所述时间数字转换器依据起始信号与停止信号决定第一计数值与第二计数值，并依据所述第一计数值与所述第二计数值产生所述数字信号。
  3. 根据权利要求2所述的时间数字转换装置，其特征在于，所述时间数字转换器依据所述第一计数值与所述第二计数值的差值产生所述数字信号。
  4. 根据权利要求2所述的时间数字转换装置，其特征在于，所述起始信号与所述停止信号为脉冲信号，所述时间数字转换器依据所述起始信号与所述停止信号的上升缘或下降缘的产生时间决定对应的所述第一计数值与所述第二计数值。
  5. 根据权利要求1所述的时间数字转换装置，其特征在于，所述预设时间为依据所述n个时钟信号的脉波宽度的变化在一段观察时间内小于预设值所需的时间决定。
  6. 根据权利要求1所述的时间数字转换装置，其特征在于，所述时钟产生电路依据第一致能信号产生所述n个时钟信号，所述时间数字转换器依据第二致能信号于所述时钟产生电路开始产生所述n个时钟信号起经过所述预设时间后，开始计数所述n个时钟信号的上升缘或下降缘，以产生所述数字信号。
  7. 一种时间数字转换装置的时间数字转换方法，其特征在于，包括：
    致能时钟产生电路产生n个时钟信号，其中n为正整数；以及
    于所述时钟产生电路开始产生所述n个时钟信号起经过一段预设时间后，开始计数所述n个时钟信号的上升缘或下降缘，以产生数字信号。
  8. 根据权利要求7所述的时间数字转换装置的时间数字转换方法，其特征在于，包括：
    依据依序接收到的起始信号与停止信号的时间决定对应的第一计数值与第二计数值；以及
    依据所述第一计数值与所述第二计数值产生所述数字信号。
  9. 根据权利要求8所述的时间数字转换装置的时间数字转换方法，其特征在于，包括：
    依据所述第一计数值与所述第二计数值的差值产生所述数字信号。
  10. 根据权利要求8所述的时间数字转换装置的时间数字转换方法，其特征在于，所述起始信号与所述停止信号为脉冲信号，所述第一计数值与所述第二计数值为依据所述起始信号与所述停止信号的上升缘或下降缘的产生时间所对应的计数值决定。
  11. 根据权利要求8所述的时间数字转换装置的时间数字转换方法，其特征在于，所述预设时间为依据所述n个时钟信号的脉波宽度的变化在一段观察时间内小于预设值所需的时间决定。
  12. 根据权利要求7所述的时间数字转换装置的时间数字转换方法，其特征在于，包括：
    提供第一致能信号致能所述时钟产生电路产生n个时钟信号；以及
    依据第二致能信号于所述时钟产生电路开始产生所述n个时钟信号起经过所述预设时间后，开始计数所述n个时钟信号的上升缘或下降缘，以产生所述数字信号。
PCT/CN2021/141900 2021-08-18 2021-12-28 时间数字转换装置及其时间数字转换方法 WO2023019854A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163234250P 2021-08-18 2021-08-18
US63/234,250 2021-08-18

Publications (1)

Publication Number Publication Date
WO2023019854A1 true WO2023019854A1 (zh) 2023-02-23

Family

ID=81015201

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/141900 WO2023019854A1 (zh) 2021-08-18 2021-12-28 时间数字转换装置及其时间数字转换方法

Country Status (3)

Country Link
CN (2) CN216748450U (zh)
TW (2) TWM625317U (zh)
WO (1) WO2023019854A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN216748450U (zh) * 2021-08-18 2022-06-14 神盾股份有限公司 时间数字转换装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1274200A (zh) * 1999-05-15 2000-11-22 三星电子株式会社 时间数字转换器以及利用该转换器的锁定电路和方法
CN1416116A (zh) * 2002-12-12 2003-05-07 威盛电子股份有限公司 数字波产生装置与方法
US20090296532A1 (en) * 2008-05-29 2009-12-03 Hong-Yean Hsieh High-Resolution Circular Interpolation Time-To-Digital Converter
CN104639159A (zh) * 2015-01-31 2015-05-20 复旦大学 一种超低功耗且无亚稳态的频率数字转换器
CN107094015A (zh) * 2011-10-17 2017-08-25 联发科技股份有限公司 时间数字转换系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4030598A1 (de) * 1990-09-27 1992-04-02 Siemens Ag Schaltungsanordnung zum umwandeln einer analogsignalfolge in eine digitale impulsfolge
US20070002994A1 (en) * 2005-06-30 2007-01-04 Ofir Kanter Clock jitter estimation apparatus, systems, and methods
JP2009005288A (ja) * 2007-06-25 2009-01-08 Sanyo Electric Co Ltd クロック生成回路
TWI620419B (zh) * 2016-04-26 2018-04-01 華邦電子股份有限公司 具有高解析度的時間數位轉換器
EP3339985B1 (en) * 2016-12-22 2019-05-08 ams AG Time-to-digital converter and conversion method
US10725433B2 (en) * 2018-12-04 2020-07-28 Sharp Kabushiki Kaisha Time-to-digital conversion circuitry
CN110376872B (zh) * 2019-05-29 2020-10-23 西安电子科技大学 一种基于异步复位的应用于tadc的时间数字转换器
KR102317072B1 (ko) * 2019-12-17 2021-10-25 현대모비스 주식회사 라이다 시스템에서의 시간-디지털 변환 방법 및 장치
CN216748450U (zh) * 2021-08-18 2022-06-14 神盾股份有限公司 时间数字转换装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1274200A (zh) * 1999-05-15 2000-11-22 三星电子株式会社 时间数字转换器以及利用该转换器的锁定电路和方法
CN1416116A (zh) * 2002-12-12 2003-05-07 威盛电子股份有限公司 数字波产生装置与方法
US20090296532A1 (en) * 2008-05-29 2009-12-03 Hong-Yean Hsieh High-Resolution Circular Interpolation Time-To-Digital Converter
CN107094015A (zh) * 2011-10-17 2017-08-25 联发科技股份有限公司 时间数字转换系统
CN104639159A (zh) * 2015-01-31 2015-05-20 复旦大学 一种超低功耗且无亚稳态的频率数字转换器

Also Published As

Publication number Publication date
CN114326359A (zh) 2022-04-12
TWM625317U (zh) 2022-04-01
CN216748450U (zh) 2022-06-14
TW202309696A (zh) 2023-03-01
TWI792807B (zh) 2023-02-11

Similar Documents

Publication Publication Date Title
CN109387776B (zh) 测量时钟抖动的方法、时钟抖动测量电路和半导体装置
TWI696842B (zh) 飛時測距感測器以及飛時測距方法
WO2023019854A1 (zh) 时间数字转换装置及其时间数字转换方法
JP4771795B2 (ja) 光測距装置
KR101017590B1 (ko) 거리 기만 재밍 측정 방법 및 장치
CN108988832B (zh) 用于检测与电子装置相关联的延迟的方法和相应的电子装置
TWI700507B (zh) 飛行時間測距裝置以及飛行時間測距方法
JPH07160406A (ja) 距離測定装置、およびそれを用いた座標入力装置
US7501861B2 (en) Phase-difference detecting apparatus and method
Amin et al. FPGA based processing of speckle affected self-mixing interferometric signals
JPH0886870A (ja) レーザ測距装置
JP4199589B2 (ja) 距離測定装置
JP7170953B2 (ja) 時間演算装置及び時間演算方法
JP2000284002A (ja) ピーク検出装置、および、ピーク検出方法
JPH09102779A (ja) 伝送線路伝搬遅延時間測定システムにおける伝搬遅延時間補正方法
JPH10197578A (ja) パルス検出方法およびその方法を用いた装置
JPS5997069A (ja) 超音波式車高測定装置
JPH1028110A (ja) 位相差測定回路
JPS62197776A (ja) 目標信号検出回路
JP2007295315A (ja) 信号送信回路
CN117811502A (zh) 一种放大级电路、信号放大方法及晶体振荡器
TW201335606A (zh) 訊號轉態偵測電路及方法
JPS5856157B2 (ja) 位相差測定による硬貨選別装置
JPH0448288A (ja) レーザ警報装置
JPH10332652A (ja) 超音波ビーム路程カウンタ回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21954089

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE