WO2023019757A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2023019757A1
WO2023019757A1 PCT/CN2021/129340 CN2021129340W WO2023019757A1 WO 2023019757 A1 WO2023019757 A1 WO 2023019757A1 CN 2021129340 W CN2021129340 W CN 2021129340W WO 2023019757 A1 WO2023019757 A1 WO 2023019757A1
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Prior art keywords
trench
layer
conductive layer
gate
insulating layer
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PCT/CN2021/129340
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English (en)
French (fr)
Inventor
邵光速
肖德元
邱云松
吴敏敏
Original Assignee
长鑫存储技术有限公司
北京超弦存储器研究院
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Priority to US17/934,489 priority Critical patent/US20230200045A1/en
Publication of WO2023019757A1 publication Critical patent/WO2023019757A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

Definitions

  • the present invention is based on a Chinese patent application with the application number 202110955136.8, the filing date is August 19, 2021, and the title of the invention is "semiconductor device and its manufacturing method", and claims the priority of the Chinese patent application. The entire contents of which are incorporated herein by reference.
  • Embodiments of the present disclosure relate to the field of semiconductor technology, and relate to but not limited to a semiconductor device and a manufacturing method thereof.
  • the requirements for integration in the semiconductor manufacturing process are getting higher and higher.
  • semiconductor devices with a vertical channel structure are gradually being applied.
  • the transistor channel of the vertical channel structure is perpendicular to the surface of the substrate, so it can be conveniently arranged in an array.
  • the layout and process of its wiring need to be further optimized and improved.
  • embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the semiconductor device includes a substrate, and the method includes:
  • a plurality of second grooves extending along a second direction are formed on the substrate on which the first grooves are formed; the first direction is perpendicular to the second direction; the second grooves of the first grooves a depth equal to a second depth of the second trench;
  • bit line separating the conductive layer in the first trench on the cross-section in the second direction to form two strips connected to the sidewalls on both sides of the first trench and extending along the first direction.
  • a word line extending along the second direction is formed in the first trench and the second trench and on the conductive layer.
  • the separating the conductive layer in the first trench on the cross-section in the second direction includes:
  • a first slot having a third depth is formed on the first insulating layer, the conductive layer, and the second insulating layer in the first trench along the first direction; the third depth less than the total thickness of the first insulating layer, conductive layer and second insulating layer, and the third depth is greater than the sum of the thicknesses of the first insulating layer and conductive layer;
  • the first insulating material includes oxide
  • the method further includes:
  • forming a word line extending along the second direction in the first trench and the second trench and on the conductive layer includes:
  • the word line is formed.
  • forming the word line in the recessed region includes:
  • the gate conductive layer in the recessed region is separated into two word lines extending along the second direction on a cross section in the first direction.
  • the forming a gate conductive layer between the gate oxide layers in the recessed region includes:
  • a conductive material is deposited between the gate oxide layers in the recessed region to form a gate conduction layer; the thickness of the gate conduction layer is less than or equal to the height of the gate oxide layer.
  • the separating the gate conductive layer in the recessed region into two word lines extending along the second direction on a cross-section in the first direction includes:
  • a second slit having a fourth depth is formed on the gate conductive layer; the fourth depth is greater than or equal to the thickness of the gate conductive layer; the second slit is formed on the gate conductive layer.
  • each of the gate conductive layers connected to the conductive material on both sides of the second isolation layer constitutes the word line.
  • the second insulating material includes nitride.
  • the thickness of the gate conductive layer is smaller than the height of the gate oxide layer, after the gate conductive layer in the recessed region is separated on the cross section in the first direction, the The method also includes:
  • a third insulating material is filled between the gate oxide layers in the recessed region to form a third isolation layer; wherein, the bottom of the third isolation layer is connected to the top of the second isolation layer and the gate conductive layer.
  • an embodiment of the present disclosure provides a semiconductor device, including:
  • a first insulating layer located at the bottom of the first trench and the second trench;
  • word lines extending along the second direction in the first trench and the second trench and on the conductive layer.
  • the semiconductor device also includes:
  • the first isolation layer is located on the first insulating layer in the first trench; wherein, the conductive layer in the first trench is covered by the first The isolation layer is separated.
  • the semiconductor device also includes:
  • the second insulating layer is located between the conductive layer and the word line; wherein, the second insulating layer in the first trench is separated by the first isolation layer on a cross-section in the second direction.
  • the semiconductor device also includes:
  • a gate oxide layer located on part of sidewalls of the first trench and the second trench on the second insulating layer
  • the word line includes: a gate conductive layer corresponding to each semiconductor column located between adjacent gate oxide layers; and the gate conductive layer is connected in the second direction.
  • the semiconductor device also includes:
  • the second isolation layer is located on the second insulating layer in the second trench; wherein, the gate conductive layer in the second trench is covered by the The second isolation layer separates.
  • a trench is formed on a substrate during the manufacturing process of a semiconductor device, a first insulating layer, a conductive layer, and a second insulating layer are formed in the trench, and then the first insulating layer is placed in the first trench.
  • the conductive layer is separated on a cross-section in the second direction to form a bit line structure buried in the substrate.
  • the bit lines formed by depositing conductive materials used in the embodiments of the present disclosure have higher conductivity, and thus can improve the overall performance of the semiconductor device.
  • the double bit line structure parallel to each other and separated in the second direction formed on the sidewalls on both sides of the first trench can improve the integration of the semiconductor device and reduce the parasitic capacitance between the bit lines.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure
  • FIGS. 2A to 2E are top views and cross-sectional views of the first groove formed in the manufacturing method provided by the embodiment of the present disclosure
  • 3A to 3B are top views and partial cross-sectional views of the second groove formed in the manufacturing method provided by the embodiment of the present disclosure.
  • FIGS. 4A to 4C are top views and partial cross-sectional views of forming a first insulating layer, a conductive layer, and a second insulating layer in the manufacturing method provided by an embodiment of the present disclosure
  • 5A to 5C are top views and partial cross-sectional views of forming a first slit in the manufacturing method provided by an embodiment of the present disclosure
  • 6A to 6C are top views and partial cross-sectional views of forming the first isolation layer in the manufacturing method provided by the embodiment of the present disclosure
  • 7A to 7D are cross-sectional views of the recessed region formed in the manufacturing method provided by the embodiment of the present disclosure.
  • FIGS. 8A to 8D are cross-sectional views of a partial cross-section of a gate oxide layer and a gate conductive layer formed in the manufacturing method provided by an embodiment of the present disclosure
  • 9A to 9B are cross-sectional views of forming a second isolation layer and partial cross-sections in the manufacturing method provided by an embodiment of the present disclosure
  • 10A to 10G are schematic structural diagrams of a semiconductor device provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the semiconductor device includes a substrate, and the method includes:
  • Step S101 forming a plurality of first trenches extending along a first direction on the substrate;
  • Step S102 forming a plurality of second grooves extending along a second direction on the substrate formed with the first grooves; the first direction is perpendicular to the second direction; the first grooves the first depth of the groove is equal to the second depth of the second trench;
  • Step S103 sequentially forming a first insulating layer, a conductive layer, and a second insulating layer in the first trench and the second trench;
  • Step S104 separating the conductive layer in the first trench on the cross-section in the second direction, forming a connection with the sidewalls on both sides in the first trench and extending along the first direction
  • Step S105 forming a word line extending along the second direction in the first trench and the second trench and on the conductive layer.
  • grooves with patterns may be formed on the surface of the substrate by etching.
  • the first direction is a direction extending parallel to the surface of the substrate, and a plurality of first grooves may be formed in this direction, and these first grooves are parallel to each other.
  • the plurality of first grooves are parallel to each other and may have equal spacing, depth and width. Therefore, these first trenches can be formed simultaneously by etching.
  • the above etching can be one etching or multiple etchings.
  • FIG. 2A it is a top view after forming the first groove
  • FIG. 2B, FIG. 2C, FIG. 2D and FIG. 2E are the aa' section, bb' section, cc' section and dd' section in FIG. 2A respectively.
  • a plurality of parallel first grooves 110 are formed on the substrate 100 .
  • second trenches distributed perpendicular to the first trenches may be formed again by means of etching.
  • the extending direction of the second trench is also parallel to the substrate surface, but perpendicular to the first direction.
  • a network structure can be formed on the surface of the substrate, that is, a plurality of first grooves and second grooves interlaced with each other.
  • the unetched regions form semiconductor pillars perpendicular to the substrate surface one by one, and these semiconductor pillars can be used as vertical channels of transistors, thereby forming transistor arrays.
  • FIG. 3A it is a top view after forming the second trench 120.
  • FIG. 3B is a cross-sectional view on the cc' section in FIG. Column 130.
  • FIG. 4B and FIG. 4C are cross-sectional views on the bb' section and the cc' section in FIG. 4A, respectively.
  • the first insulating layer is a layer covering the bottoms of the first trench and the second trench, and is made of insulating materials, such as oxides, nitrides or other insulating materials.
  • the conductive layer is a layer deposited on the first insulating layer, and is made of conductive materials, such as metallic copper, metallic materials such as metal docks, doped semiconductor materials, or other conductive materials.
  • the second insulating layer is a layer filled on the conductive layer and is made of insulating materials, such as oxides, nitrides or other insulating materials.
  • the insulating material forming the first insulating layer can be combined with the insulating material forming the second insulating layer Insulation materials are the same or different.
  • the sum of the thicknesses of the first insulating layer, the conductive layer and the second insulating layer is equal to the height of the semiconductor column, that is, the first groove and the second groove are filled.
  • the conductive layer in the first trench is continuous and extends in the first direction.
  • the conductive layer connects the sidewalls on both sides of the first trench, and an isolation structure can be formed in the middle of the conductive layer to separate the conductive layer on the cross section in the second direction, for example, forming a slit and filling it with an insulating material .
  • the conductive layer in the first trench extends along the sidewalls on both sides of the first trench to form two bit lines, which are parallel to each other and separated on the cross-section in the second direction. There are two bit lines on the first insulating layer of each first trench, forming a double bit line structure of the semiconductor device.
  • word lines can be formed on the conductive layer of the first trench and in the second trench. In fact, the word lines extend along the second trench, that is, extend along the second direction. However, since a part of the material constituting the word line may be located in the first trench, it needs to be formed in the first trench and the second trench. Of course, two adjacent word lines can be separated by an insulating material.
  • the embodiments of the present disclosure provide a way to form buried word lines and bit lines in the substrate, and each transistor channel has a double bit line structure, that is, two Each side has a conductive layer formed by depositing a conductive material.
  • the bit lines formed by depositing conductive materials used in the embodiments of the present disclosure have higher electrical conductivity, so the overall performance of the semiconductor device can be improved.
  • the double bit line structures parallel to each other and separated in the second direction formed in the first gaps on the side walls on both sides of the first trench the integration of semiconductor devices can be improved and the parasitic between bit lines can be reduced. capacitance.
  • the separating the conductive layer in the first trench on the cross-section in the second direction includes:
  • a first gap having a third depth is formed on the first insulating layer, the conductive layer, and the second insulating layer in the first trench; the third depth is smaller than the The total thickness of the first insulating layer, the conductive layer and the second insulating layer, and the third depth is greater than the sum of the thicknesses of the conductive layer of the first insulating layer;
  • FIG. 5A it is a top view of forming the first slit 330
  • FIG. 5B and FIG. 5C are cross-sectional views on the bb' section and cc' section in FIG. 5A, respectively
  • FIG. 6A is a top view of forming the first isolation layer 340
  • 6B and 6C are cross-sectional views of FIG. 6A on the bb' section and the cc' section, respectively.
  • the above-mentioned first gap can be formed on the first insulating layer, the conductive layer and the second insulating layer in the first trench by etching, where the depth of the first gap is greater than that of the first insulating layer.
  • the first slits in each first groove may have equal pitch, depth and width. Therefore, these first gaps can also be formed simultaneously by etching.
  • a layer of the first insulating material can be filled in the first gap by means of epitaxial growth or deposition, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD) or Physical Vapor Deposition (Physical Vapor Deposition, PVD) and other methods to form the above-mentioned first isolation layer.
  • the first insulating material may be oxide, nitride or other insulating materials.
  • the first insulating material may be filled on the entire inner wall of the first slit, including the bottom and sidewalls of the first slit. In this way, the conductive layer in the first trench is separated by the first insulating material, ie, the above-mentioned first isolation layer, on the cross-section in the second direction.
  • the process of forming the first isolation layer can be performed simultaneously, which can reduce process steps and improve manufacturing efficiency.
  • the first insulating material includes oxide
  • Oxide can be used as the first insulating material in the embodiment of the present disclosure because it can have good insulating properties and the cost is not high.
  • the first insulating material may include silicon oxide, nitrogen oxide, or other oxides.
  • the method further includes:
  • part of the redundant insulating material may cover the semiconductor pillar, thereby affecting the performance of the semiconductor device. Therefore, planarization can be performed by chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • forming a word line extending along the second direction in the first trench and the second trench and on the conductive layer includes:
  • the word line is formed.
  • part of the second insulating layer may be removed by etching to form a concave region with a pattern.
  • FIGS. 7A to 7D they are schematic diagrams corresponding to the aa' section, the bb' section, the cc' section and the dd' section in FIG. 6A after forming the concave region.
  • the recessed area is a network structure formed by the first groove and the second groove, and the depth is smaller than the thickness of the second insulating layer. Therefore, part of the second insulating layer is exposed at the bottom of the recessed region, and part of the sidewall of the semiconductor pillar is exposed on the sidewall.
  • the recessed area is spaced apart from the aforementioned bit line by the second insulating layer.
  • the word line can be formed by deposition in the recessed area, therefore, the bit line and the word line can also be separated by the second insulating layer.
  • the bit line buried in the substrate is formed first, and then the word line is formed, which can reduce the size of the semiconductor device and improve the integration degree.
  • forming the word line in the recessed region includes:
  • the gate conductive layer in the recessed region is separated into two word lines extending along the second direction on a cross section in the first direction.
  • FIGS. 8A to 8D are schematic diagrams of forming a gate oxide layer 440 on the basis of FIG. 7B and FIG. 7C respectively;
  • FIG. 8C and FIG. 8D are respectively based on FIGS. 8A and 8B
  • a schematic diagram of forming the conductive layer 450 is shown in FIGS. 8A to 8D, among them, FIG. 8A and FIG. 8B are schematic diagrams of forming a gate oxide layer 440 on the basis of FIG. 7B and FIG. 7C respectively;
  • FIG. 8C and FIG. 8D are respectively based on FIGS. 8A and 8B
  • a schematic diagram of forming the conductive layer 450 are schematic diagram of forming the conductive layer 450 .
  • part of the sidewall of the semiconductor pillar is exposed in the above-mentioned recessed region.
  • each sidewall in the recessed region is in contact with the corresponding semiconductor pillar, therefore, the sidewall of the semiconductor pillar is also the sidewall of the recessed region.
  • the sidewall of the semiconductor pillar can be oxidized to form a gate oxide layer on the sidewall in the recessed area, where the gate oxide layer is part of the gate and is used to electrically isolate the semiconductor pillar, that is, the conductive channel .
  • the height of the gate oxide layer is the same as the depth of the recessed region, and its thickness is smaller than the width of the recessed region. Therefore, the gate oxide layers of the semiconductor pillars in the recessed region are separated from each other, and the bottom of the remaining recessed region is still partially exposed. second insulating layer,.
  • a conductive material may be deposited in the remaining recessed area to form a gate conductive layer, and the gate conductive layer is located between the gate oxide layers and connects the semiconductor pillars in the recessed area.
  • the gate conductive layer surrounding each semiconductor and the above-mentioned gate oxide layer constitute the corresponding gate of each semiconductor, and the method of depositing the conductive material may be CVD, ALD or PVD.
  • the above-mentioned gate conductive layer is continuous in the recessed region, and a double bit line structure extending along the first direction has been formed in the first trench, therefore, a double bit line structure along the first direction can be formed in the second trench A word line structure extending in two directions.
  • the gate conductive layer is connected to the gate oxide layer on both sides of the recessed region in the second trench on the cross section in the first direction, and an isolation structure can be formed in the middle of the gate conductive layer to separate the gate on the cross section in the first direction.
  • Conductive layers are separated, for example, by forming slits and filling with insulating material. In this way, the separated gate conductive layer in the second trench and the corresponding gate conductive layer in the first trench form a word line extending along the second direction, and connect a plurality of semiconductor columns in the second direction and corresponding gate oxide layer.
  • the forming a gate conductive layer between the gate oxide layers in the recessed region includes:
  • a conductive material is deposited between the gate oxide layers in the recessed region to form a gate conduction layer; the thickness of the gate conduction layer is less than or equal to the height of the gate oxide layer.
  • the deposited conductive material may be a metal material, a doped semiconductor material, or other conductive materials.
  • the depth of the recessed region is equal to the height of the exposed part of the semiconductor pillars, and the height of the gate oxide layer is equal to the depth of the recessed region. Therefore, when the thickness of the gate conductive layer is less than the height of the gate oxide layer, the remaining part of the bottom of the recessed region is in contact with the gate conductive layer, and the sidewall is in contact with part of the gate oxide layer; when the thickness of the gate conductive layer is equal to When the height of the gate oxide layer is greater than the height of the gate oxide layer, the above-mentioned recessed area is completely filled.
  • the separating the gate conductive layer in the recessed region into two word lines extending along the second direction on a cross-section in the first direction includes:
  • a second slit having a fourth depth is formed on the gate conductive layer; the fourth depth is greater than or equal to the thickness of the gate conductive layer; the second slit is formed on the gate conductive layer.
  • each of the gate conductive layers connected to the conductive material on both sides of the second isolation layer constitutes the word line.
  • the above-mentioned second gap may be formed on the gate conductive layer in the second groove by an etching method.
  • FIG. 9A it is a schematic diagram of forming the second slit 550 on the basis of FIG. 8D;
  • FIG. 9B is a schematic diagram of forming the second isolation layer 560 on the basis of FIG. The gap, therefore, is unchanged from the cross-sectional view in Figure 8C.
  • the depth of the second slit is greater than or equal to the thickness of the gate conductive layer, so that the gate conductive layer can be separated by the second slit on the cross section in the first direction.
  • the second slits in each second groove may have equal pitch, depth and width. Therefore, these second gaps can also be formed simultaneously by etching.
  • the second insulating material may be filled in the second gap by deposition, for example, CVD, ALD or PVD.
  • the second insulating material may be oxide, nitride or other insulating materials.
  • the conductive layer in the second trench is separated by the second insulating material, ie, the above-mentioned second isolation layer, on the cross-section in the first direction.
  • the second isolation layer is formed, in the intersection region of each first trench and the second trench, the second isolation layer is in contact with the above-mentioned first isolation layer.
  • the second insulating material includes nitride.
  • the second insulating material may include silicon nitride, titanium nitride or other nitrides and the like.
  • the thickness of the gate conductive layer is smaller than the height of the gate oxide layer, after the gate conductive layer in the recessed region is separated on the cross section in the first direction, the The method also includes:
  • a third insulating material is filled between the gate oxide layers in the recessed region to form a third isolation layer; wherein, the bottom of the third isolation layer is connected to the top of the second isolation layer and the gate conductive layer.
  • a third insulating material may be filled between the gate oxide layers by deposition, where the third insulating material may be oxide, nitride or other insulating materials.
  • the third insulating material may be the same as or different from the second insulating material, and the deposition process may be performed simultaneously to form the third isolation layer.
  • FIG. 10A is a top view of a semiconductor device 1100
  • FIG. 10B and FIG. 10C are cross-sectional views of the bb' section and the cc' section in FIG. 10A respectively.
  • the semiconductor device 1100 includes:
  • a first insulating layer 1030 located at the bottom of the first trench 1010 and the second trench 1020;
  • the sidewalls of the two bit lines 1200 are respectively connected and extend along the first direction D1;
  • word lines 1300 extending along the second direction D2 in the first trench 1010 and the second trench 1020 and on the conductive layer 1040 .
  • the first direction in the embodiments of the present disclosure is a direction extending parallel to the surface of the substrate.
  • Each first groove is a strip structure.
  • the plurality of first grooves are parallel to each other and may have equal spacing, depth and width.
  • each second groove is a strip structure extending in the second direction.
  • the plurality of second grooves are parallel to each other and may have equal spacing, depth and width.
  • the second groove has the same depth as the first groove described above. In this way, the second grooves and the above-mentioned first grooves form a network structure on the surface of the substrate.
  • the first insulating layer is used to electrically isolate the conductive layer from the substrate, and is composed of insulating materials, such as oxides, nitrides or other insulating materials.
  • the conductive layer here is made of conductive materials, such as metallic copper, metal docks and other metal materials, doped semiconductor materials or other conductive materials.
  • the conductive layer in the second trench is directly connected to the sidewalls on both sides of the second trench and extends in the second direction; the conductive layer in the first trench is separated into two mutually
  • the parallel bit lines are respectively connected to the sidewalls on both sides of the second groove and extend in the first direction, thus constituting the double bit line structure of the embodiment of the present disclosure.
  • the word lines are located on the double bit line structure, and the two can be electrically isolated by an insulating material.
  • the above word lines extend in the second direction.
  • Figure 10D is a cross-sectional view on the bb' section in Figure 10A, and the semiconductor device 1100 further includes:
  • the first isolation layer 1050 is located on the first insulating layer in the first trench; wherein, the conductive layer in the first trench is separated by the first isolation layer 1050 .
  • the conductive layer in the first trench may be separated into two mutually parallel bit lines by the first isolation layer on a cross section in the second direction.
  • the first isolation layer may be made of oxide material and extend in a first direction.
  • FIG. 10E is a cross-sectional view on the bb' section in FIG. 10A, and the semiconductor device 1100 further includes:
  • the second insulating layer 1060 is located between the conductive layer and the word line; wherein, the second insulating layer 1060 in the first trench is surrounded by the first insulating layer on the cross section in the second direction 1050 separation.
  • the electrical isolation between the conductive layer and the word line can be realized through the second insulating layer, and the second insulating layer can be made of nitride, oxide or other insulating materials. Since the double bit line structure is formed in the first trench, the two bit lines are separated by the first isolation layer. Correspondingly, the second insulating layer in the first trench can also be separated by the above-mentioned first isolation layer.
  • FIG. 10F is a cross-sectional view on the cc' section in FIG. 10A, and the semiconductor device 1100 further includes:
  • a gate oxide layer 1070 located on part of sidewalls of the first trench and the second trench on the second insulating layer;
  • the word line includes: a gate conductive layer 1080 corresponding to each semiconductor column located between adjacent gate oxide layers 1070; the gate conductive layer is connected in the second direction.
  • the gate includes a gate oxide layer and a gate conductive layer, and the gate is located on the second insulating layer.
  • the gate oxide layer covers the side walls of the first trench and the remaining part of the second trench; the gate conductive layer is located between the gate oxide layers.
  • the gate conductive layers in the second trench are connected to each other and separated in a cross-section in the first direction to form a word line extending in the second direction.
  • FIG. 10G is a cross-sectional view on the cc' section in FIG. 10A, and the semiconductor device 1100 further includes:
  • the second isolation layer 1090 is located on the second insulating layer in the second trench; wherein, the gate conductive layer in the second trench is covered by the cross section in the first direction The second isolation layer 1090 is separated.
  • the cross section of the gate conductive layer in the second trench in the first direction may be separated by the second isolation layer into two parallel word lines.
  • the second isolation layer may be made of nitride material and extend in the second direction.
  • the material constituting the second isolation layer may be the same as the material constituting the above-mentioned second insulating layer.
  • a trench is formed on a substrate during the manufacturing process of a semiconductor device, a first insulating layer, a conductive layer, and a second insulating layer are formed in the trench, and then the first insulating layer is placed in the first trench.
  • the conductive layer is separated on a cross-section in the second direction to form a bit line structure buried in the substrate.
  • the bit lines formed by depositing conductive materials used in the embodiments of the present disclosure have higher conductivity, and thus can improve the overall performance of the semiconductor device.
  • the double bit line structure parallel to each other and separated in the second direction formed on the sidewalls on both sides of the first trench can improve the integration of the semiconductor device and reduce the parasitic capacitance between the bit lines.

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Abstract

本公开实施例提供一种半导体器件及其制造方法，所述半导体器件，包括衬底，所述方法包括：在所述衬底中形成沿第一方向延伸的多条第一沟槽；在形成有所述第一沟槽的所述衬底上形成沿第二方向延伸的多条第二沟槽；所述第一方向与所述第二方向垂直；所述第一沟槽的第一深度等于所述第二沟槽的第二深度；在所述第一沟槽与所述第二沟槽内依次形成第一绝缘层、导电层和第二绝缘层；将所述第一沟槽中的所述导电层在所述第二方向的截面上分离，形成与所述第一沟槽内两侧的侧壁连接且沿所述第一方向延伸的两条位线；在所述第一沟槽和第二沟槽内、所述导电层上，形成沿所述第二方向延伸的字线。

Description

半导体器件及其制造方法
相关申请的交叉引用
本发明基于申请号为202110955136.8、申请日为2021年8月19日、发明名称为“半导体器件及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本发明作为参考。
技术领域
本公开实施例涉及半导体技术领域，涉及但不限于一种半导体器件及其制造方法。
背景技术
随着芯片及存储器的技术发展，半导体制造工艺中对于集成度的要求越来越高。为了提升半导体衬底的利用率，提升集成度，垂直沟道结构的半导体器件开始逐渐被应用。垂直沟道结构的晶体管沟道垂直于衬底的表面，因而可以方便地排列成阵列。然而，针对垂直沟道结构的半导体器件，对于其走线的布局和工艺过程还有待进一步地优化和改善。
发明内容
有鉴于此，本公开实施例提供了一种半导体器件及其制造方法。
第一方面，本公开实施例提供了一种半导体器件的制造方法，所述半导体器件，包括衬底，所述方法包括：
在所述衬底上形成沿第一方向延伸的多条第一沟槽；
在形成有所述第一沟槽的所述衬底上形成沿第二方向延伸的多条第二沟槽；所述第一方向与所述第二方向垂直；所述第一沟槽的第一深度等于所述第二沟槽的第二深度；
在所述第一沟槽与所述第二沟槽内依次形成第一绝缘层、导电层和第二绝缘层；
将所述第一沟槽中的所述导电层在所述第二方向的截面上分离，形成与所述第一沟槽内两侧的侧壁连接且沿所述第一方向延伸的两条位线；
在所述第一沟槽和第二沟槽内、所述导电层上，形成沿所述第二方向延伸的字线。
在一些实施例中，所述将所述第一沟槽中的导电层在所述第二方向的截面上分离，包括：
沿所述第一方向，在所述第一沟槽内的所述第一绝缘层、所述导电层和所述第二绝缘层上形成具有第三深度的第一缝隙；所述第三深度小于所述第一绝缘层、导电层和第二绝缘层的总厚度，且所述第三深度大于所述第一绝缘层和导电层的厚度之和；
在所述第一缝隙内填充第一绝缘材料，形成第一隔离层；其中，所述第一沟槽中的导电层在所述第二方向的截面上被所述第一隔离层分离。
在一些实施例中，所述第一绝缘材料包括氧化物。
在一些实施例中，所述在所述第一沟槽与所述第二沟槽内依次形成第一绝缘层、导电层和第二绝缘层之后，所述方法还包括：
对所述第二绝缘层和所述衬底表面进行平坦化处理，使所述第一沟槽和所述第二沟槽以外区域的衬底表面显露。
在一些实施例中，所述在所述第一沟槽和第二沟槽内、所述导电层上，形成沿所述第二方向延伸的字线，包括：
去除所述第一沟槽和所述第二沟槽内、所述导电层上方部分的所述第二绝缘层，形成凹陷区域；
在所述凹陷区域内，形成所述字线。
在一些实施例中，所述在所述凹陷区域内，形成所述字线，包括：
在所述凹陷区域内的侧壁形成栅极氧化层；
在所述凹陷区域内的所述栅极氧化层之间形成栅极导电层；
将所述凹陷区域内的所述栅极导电层在所述第一方向的截面上分离为两条沿所述第二方向延伸的所述字线。
在一些实施例中，所述在所述凹陷区域内的所述栅极氧化层之间形成栅极导电层，包括：
在所述凹陷区域的所述栅极氧化层之间沉积导电材料，形成栅极导电层；所述栅极导电层的厚度小于或等于所述栅极氧化层的高度。
在一些实施例中，所述将所述凹陷区域内的所述栅极导电层在所述第一方向的截面上分离为两条沿所述第二方向延伸的所述字线，包括：
沿所述第二方向，在所述栅极导电层上形成具有第四深度的第二缝隙；所述第四深度大于或等于所述栅极导电层的厚度；所述第二缝隙在所述第一方向的截面上分离所述栅极导电层；
在所述第二缝隙内填充第二绝缘材料，形成第二隔离层；其中，所述第二隔离层两侧的所述导电材料连通的各所述栅极导电层构成所述字线。
在一些实施例中，所述第二绝缘材料包括氮化物。
在一些实施例中，所述栅极导电层的厚度小于所述栅极氧化层的高度，所述将所述凹陷区域内的栅极导电层在所述第一方向的截面上分离之后，所述方法还包括：
在所述凹陷区域内的栅极氧化层之间填充第三绝缘材料形成第三隔离层；其中，第三隔离层的底部与所述第二隔离层的顶部和所述栅极导电层连接。
另一方面，本公开实施例提供了一种半导体器件，包括：
衬底；
在所述衬底上沿第一方向延伸的多条第一沟槽以及沿第二方向延伸的多条第二沟槽；其中，所述第一方向与所述第二方向垂直；所述第一沟槽的第一深度等于所述第二沟槽的第二深度；
位于所述第一沟槽与所述第二沟槽底部的第一绝缘层；
位于所述第一绝缘层上的导电层；所述导电层在所述第二方向的截面上分离，所述分离的导电层构成与所述第一沟槽内两侧的侧壁分别连接且沿所述第一方向延伸的两条位线；
所述第一沟槽和第二沟槽内、所述导电层上具有沿所述第二方向延伸的字线。
在一些实施例中，所述半导体器件还包括：
第一隔离层，位于所述第一沟槽内的所述第一绝缘层上；其中，所述第一沟槽中的所述导电层在所述第二方向的截面上被所述第一隔离层分离。
在一些实施例中，所述半导体器件还包括：
第二绝缘层，位于所述导电层与所述字线之间；其中，所述第一沟槽中的第二绝缘层在所述第二方向的截面上被所述第一隔离层分离。
在一些实施例中，所述半导体器件还包括：
栅极氧化层，位于所述第二绝缘层上的所述第一沟槽和所述第二沟槽的部分侧壁上；
所述字线，包括：位于相邻的所述栅极氧化层之间的各半导体柱对应的栅极导电层；所述栅极导电层在所述第二方向上连通。
在一些实施例中，所述半导体器件还包括：
第二隔离层，位于所述第二沟槽内的所述第二绝缘层上；其中，所述第二沟槽中的所述栅极导电层在所述第一方向的截面上被所述第二隔离层分离。
本公开实施例提供的技术方案，在半导体器件的制造过程中通过在衬底上形成沟槽，在沟槽中形成第一绝缘层、导电层和第二绝缘层，然后将第一沟槽中的导电层在第二方向的截面上分离，形成掩埋于衬底内的位线结构。如此，一方面相比于对半导体衬底掺杂形成的位线，本公开实施例采用的沉积导电材料形成的位线具有更高的导电性能，因此能够提升半导体器件的整体性能。另一方面，通过在第一沟槽两侧侧壁形成的相互平行且在第二方向分离的双位线结构，可以提升半导体器件的集成度，减少位线之间的寄生电容。
附图说明
图1为本公开实施例提供的一种半导体器件的制造方法的流程图；
图2A至图2E为本公开实施例提供的制造方法中形成第一沟槽的俯视图及各截面图；
图3A至图3B为本公开实施例提供的制造方法中形成第二沟槽的俯视图及部分截面的截面图；
图4A至图4C为本公开实施例提供的制造方法中形成第一绝缘层、导电层和第二绝缘层的俯视图及部分截面的截面图；
图5A至图5C为本公开实施例提供的制造方法中形成第一缝隙的俯视图及部分截面的截面图；
图6A至图6C为本公开实施例提供的制造方法中形成第一隔离层的俯视图及部分截面的截面图；
图7A至图7D为本公开实施例提供的制造方法中形成凹陷区域的各截面图；
图8A至图8D为本公开实施例提供的制造方法中形成栅极氧化层和栅极导电层的部分截面的截面图；
图9A至图9B为本公开实施例提供的制造方法中形成第二隔离层及部分截面的截面图；
图10A至图10G为本公开实施例提供的一种半导体器件的结构示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1所示，本公开实施例提供了一种半导体器件的制造方法，所述半导体器件，包括衬底，所述方法包括：
步骤S101、在所述衬底上形成沿第一方向延伸的多条第一沟槽；
步骤S102、在形成有所述第一沟槽的所述衬底上形成沿第二方向延伸的多条第二沟槽；所述第一方向与所述第二方向垂直；所述第一沟槽的第一深度等于所述第二沟槽的第二深度；
步骤S103、在所述第一沟槽与所述第二沟槽内依次形成第一绝缘层、导电层和第二绝缘层；
步骤S104、将所述第一沟槽中的所述导电层在所述第二方向的截面上分离，形成与所述第一沟槽内两侧的侧壁连接且沿所述第一方向延伸的两条位线；
步骤S105、在所述第一沟槽和第二沟槽内、所述导电层上，形成沿所述第二方向延伸的字线。
在本公开实施例中，可以通过刻蚀的方法在衬底表面形成具有图形的沟槽。这里，第一方向是平行于衬底表面延伸的方向，在此方向上可以形成多条第一沟槽，这些第一沟槽之间相互平行。示例性地，多条第一沟槽之间相互平行且可以具有相等的间距、深度以及宽度。因此，这些第一沟槽可以通过刻蚀同步形成。当然，上述刻蚀可以是一次刻蚀，也可以是多重刻蚀。
如图2A所示，为形成第一沟槽后的俯视图，图2B、图2C、图2D以及图2E分别为图2A中在aa’截面、bb’截面、cc’截面以及dd’截面上的截面图，衬 底100上形成有多条平行分布的第一沟槽110。
在形成第一沟槽后，可以再次利用刻蚀的方法形成垂直于第一沟槽分布的第二沟槽。第二沟槽的延伸方向同样平行于衬底表面，但与第一方向相互垂直。这样，就可以在衬底表面形成网状的结构，即相互交错的多条第一沟槽和第二沟槽。未被刻蚀的区域则形成了一个个垂直于衬底表面的半导体柱，这些半导体柱可以用于作为晶体管的垂直沟道，进而可以形成晶体管阵列。
如图3A所示，为形成第二沟槽120后的俯视图，图3B为图3A中在cc’截面上的截面图，在第一沟槽和第二沟槽以外的区域形成有多个半导体柱130。
本公开实施例中，在形成第一沟槽和第二沟槽之后，如图4A所示，为在第一沟槽110和第二沟槽120内依次形成第一绝缘层220、导电层230和第二绝缘层240的俯视图；图4B和图4C分别为图4A中在bb’截面和cc’截面上的截面图。
这里，该第一绝缘层是覆盖在第一沟槽和第二沟槽底部的一层，由绝缘材料构成，例如氧化物、氮化物或者其他绝缘材料等。该导电层是沉积在第一绝缘层上的一层，由导电材料构成，例如金属铜、金属坞等金属材料、掺杂的半导体材料或其他导电材料。该第二绝缘层是填充在导电层上的一层，由绝缘材料构成，例如氧化物、氮化物或者其他绝缘材料等，这里，构成第一绝缘层的绝缘材料可以与构成第二绝缘层的绝缘材料相同或不同。上述第一绝缘层、导电层和第二绝缘层的厚度之和等于半导体柱的高度，即填充满第一凹槽和第二凹槽。
在第一沟槽内的导电层连续，且在第一方向上延伸。在第二方向的截面上导电层连接第一沟槽两侧的侧壁，可以在导电层中间形成隔离结构将第二方向的截面上的导电层实现分离，例如，形成狭缝并填充绝缘材料。这样，第一沟槽内的导电层就会沿第一沟槽的两侧的侧壁延伸，形成两条位线，两条位线相互平行，且在第二方向的截面上分离。每条第一沟槽的第一绝缘层上都具有两条位线，就形成了半导体器件的双位线结构。
由于第一沟槽内的隔离结构没有延伸至第二沟槽内，因此，在上述第一沟槽的导电层上，以及第二沟槽内可以形成字线。事实上，字线会沿着第二沟槽延伸，即沿着第二方向延伸。但是由于构成字线的材料可能会有一部分位于第一沟槽内，因此需要在第一沟槽以及第二沟槽内形成。当然，相邻的两条字线之间可以通过绝缘材料隔离开来。
如此，针对垂直沟道的半导体器件，本公开实施例中提供了在衬底内形成掩埋的字线和位线的方式，并且对于每个晶体管的沟道都具有双位线的结构，即两侧均具有通过沉积导电材料形成的导电层。这样，一方面相比于对半导体衬底掺杂形成的位线，本公开实施例采用的沉积导电材料形成的位线具有更高的导电性能，因此能够提升半导体器件的整体性能。另一方面，通过在第一沟槽两侧侧壁的第一缝隙内形成的相互平行且在第二方向分离的双位线结构，可以提升半导体器件的集成度，减少位线之间的寄生电容。
在一些实施例中，所述将所述第一沟槽中的导电层在所述第二方向的截面上分离，包括：
沿所述第一方向，在所述第一沟槽内的所述第一绝缘层、导电层和所述第二绝缘层上形成具有第三深度的第一缝隙；所述第三深度小于所述第一绝缘层、导电层和第二绝缘层的总厚度，且所述第三深度大于所述第一绝缘层导电层的厚度之和；
在所述第一缝隙内填充第一绝缘材料，形成第一隔离层；其中，所述第一沟槽中的导电层在所述第二方向的截面上被所述第一隔离层分离。
如图5A所示，为形成第一缝隙330的俯视图，图5B和图5C分别为图5A中在bb’截面和cc’截面上的截面图；图6A为形成第一隔离层340的俯视图，图6B和图6C分别为图6A中在bb’截面和cc’截面上的截面图。
在本公开实施例中，可以通过刻蚀的方法在第一沟槽内的第一绝缘层、导电层和第二绝缘层上形成上述第一缝隙，这里，第一缝隙的深度大于第一绝缘层和导电层的厚度之和，这样可以使得导电层在第二方向的截面上被第一缝隙分离。示例性地，每条第一沟槽内的第一缝隙可以具有相等的间距、深度以及宽度。因此，这些第一缝隙也可以通过刻蚀同步形成。
在形成第一缝隙后，可以通过外延生长或者沉积等方式在第一缝隙中填充一层第一绝缘材料，例如，采用化学气相沉积(Chemical Vapor Deposition，CVD)、原子层沉积(Atomic Layer Deposition，ALD)或物理气相沉积(Physical Vapor Deposition，PVD)等方式形成上述第一隔离层。这里，第一绝缘材料可以是氧化物、氮化物或者其他绝缘材料等。第一绝缘材料可以填充在第一缝隙的整个内壁上，包括第一缝隙的底部和侧壁。如此，第一沟槽内的导电层在第二方向的截面上被第一绝缘材料，即上述第一隔离层分离。
本公开实施例形成第一隔离层的过程可以同步进行，能够减少工艺步骤，提高制造效率。
在一些实施例中，所述第一绝缘材料包括氧化物。
由于氧化物可以具有良好的绝缘性，并且成本不高，可以用作本公开实施例中的第一绝缘材料。示例性地，第一绝缘材料可以包括氧化硅、氧化氮或其他氧化物等。
在一些实施例中，所述在所述第一沟槽与所述第二沟槽内依次形成第一绝缘层、导电层和第二绝缘层之后，所述方法还包括：
对所述第二绝缘层和所述衬底表面进行平坦化处理，使所述第一沟槽和所述第二沟槽以外区域的衬底表面显露。
在本公开实施例中，在第一沟槽与第二沟槽内填充绝缘材料形成第二绝缘层后，部分多余的绝缘材料可能覆盖在半导体柱上方，从而影响半导体器件的性能。因此，可以通过化学机械抛光(Chemical Mechanical Polishing，CMP)进行平坦化处理。
在一些实施例中，所述在所述第一沟槽和第二沟槽内、所述导电层上，形成沿所述第二方向延伸的字线，包括：
去除所述第一沟槽和所述第二沟槽内、所述导电层上方部分的所述第二绝缘层，形成凹陷区域；
在所述凹陷区域内，形成所述字线。
在本公开实施例中，可以通过刻蚀的方法去除部分的第二绝缘层，形成具有图形的凹陷区域。如图7A至7D所示，分别为图6A中aa’截面、bb’截面、cc’截面以及dd’截面在形成凹陷区域后对应的示意图。
该凹陷区域为第一凹槽和第二凹槽构成的网状的结构，深度小于第二绝缘层的厚度。因此，凹陷区域的底部暴露出部分第二绝缘层，侧壁暴露出半导体柱的部分侧壁。这里，凹陷区域与上述位线通过第二绝缘层间隔开。在凹陷区域内可以通过沉积的方式形成字线，因此，位线和字线也可以通过第二绝缘层间隔开。
本公开实施例中的先形成掩埋在衬底内的位线，再形成字线，可以减小半导体器件的尺寸，提高集成度。
在一些实施例中，所述在所述凹陷区域内，形成所述字线，包括：
在所述凹陷区域内的侧壁形成栅极氧化层；
在所述凹陷区域内的所述栅极氧化层之间形成栅极导电层；
将所述凹陷区域内的所述栅极导电层在所述第一方向的截面上分离为两条沿所述第二方向延伸的所述字线。
如图8A至8D所示，其中，图8A和图8B分别为在图7B和图7C的基础上形成栅极氧化层440的示意图；图8C和图8D分别为在图8A和8B的基础上形成导电层450的示意图。
在本公开实施例中，部分半导体柱的侧壁暴露在上述凹陷区域内。需要说明的是，凹陷区域内的每个侧壁都与对应的半导体柱接触，因此，半导体柱的侧壁也即凹陷区域的侧壁。可以对半导体柱的侧壁进行氧化处理，从而在凹陷区域内的侧壁形成栅极氧化层，这里的栅极氧化层是栅极的一部分，用于与半导体柱，即导电沟道实现电隔离。示例性地，栅极氧化层的高度与凹陷区域的深度相同，厚度小于凹陷区域的宽度，因此，凹陷区域内的各半导体柱的栅极氧化层互相分离，剩余凹陷区域的底部仍然暴露出部分第二绝缘层，。
可以在剩余凹陷区域内沉积导电材料形成栅极导电层，该栅极导电层位于栅极氧化层之间，并连接凹陷区域内的各半导体柱。这里，环绕各半导体的栅极导电层和上述栅极氧化层构成了各半导体出对应的栅极，沉积导电材料的方法可以是CVD、ALD或者PVD等。
在本公开实施例中，上述栅极导电层在凹陷区域内连续，且在第一沟槽内已形成沿第一方向延伸的双位线结构，因此，可以在第二沟槽内形成沿第二方向延伸的字线结构。相应地，栅极导电层在第一方向的截面上连接第二沟槽内凹陷区域两侧的栅极氧化层，可以在栅极导电层中间形成隔离结构将第一方向的截面上的栅极导电层实现分离，例如，形成狭缝并填充绝缘材料。这样，在第二沟槽内被分离的栅极导电层与第一沟槽内的对应的栅极导电层形成了沿第二方向延伸的字线，并连接多个第二方向的半导体柱和对应的栅极氧化层。
在一些实施例中，所述在所述凹陷区域内的所述栅极氧化层之间形成栅极导电层，包括：
在所述凹陷区域的所述栅极氧化层之间沉积导电材料，形成栅极导电层；所述栅极导电层的厚度小于或等于所述栅极氧化层的高度。
在本公开实施例中，沉积的导电材料可以是金属材料、掺杂的半导体材料或者其他导电材料等。需要说明的是，凹陷区域的深度等于暴露出的部分半导体柱的高度，栅极氧化层的高度等于凹陷区域的深度。因此，当栅极导电层的厚度小于栅极氧化层的高度时，上述凹陷区域剩余的部分底部与栅极导电层接触，侧壁与部分栅极氧化层接触；当栅极导电层的厚度等于栅极氧化层的高度时，上述凹陷区域被填充完全。
在一些实施例中，所述将所述凹陷区域内的所述栅极导电层在所述第一方向的截面上分离为两条沿所述第二方向延伸的所述字线，包括：
沿所述第二方向，在所述栅极导电层上形成具有第四深度的第二缝隙；所述第四深度大于或等于所述栅极导电层的厚度；所述第二缝隙在所述第一方向的截面上分离所述栅极导电层；
在所述第二缝隙内填充第二绝缘材料，形成第二隔离层；其中，所述第二隔离层两侧的所述导电材料连通的各所述栅极导电层构成所述字线。
在本公开实施例中，可以通过刻蚀的方法在第二凹槽内的栅极导电层上形成上述第二缝隙。如图9A所示，为在图8D的基础上形成第二缝隙550的示意图；图9B为在图9A的基础上形成第二隔离层560的示意图，由于是在第二沟槽中形成第二缝隙，因此，图8C中的截面图没有变化。
这里第二缝隙的深度大于或等于栅极导电层的厚度，这样可以使得栅极导电层在第一方向的截面上被第二缝隙分离。示例性地，每条第二沟槽内的第二缝隙可以具有相等的间距、深度以及宽度。因此，这些第二缝隙也可以通过刻蚀同步形成。
在形成第二缝隙后，可以通过沉积的方式在第二缝隙中填充第二绝缘材料，例如，CVD、ALD或PVD等。这里，第二绝缘材料可以是氧化物、氮化物或者其他绝缘材料等。如此，第二沟槽内的导电层在第一方向的截面上被第二绝缘材料，即上述第二隔离层分离。
需要说明的是，在形成第二隔离层后，在每个第一沟槽与第二沟槽的相交的区域内，第二隔离层与上述第一隔离层接触。
在一些实施例中，所述第二绝缘材料包括氮化物。
由于氮化物可以具有良好的绝缘性，并且成本不高，可以用作本公开实施例中的第二绝缘材料。示例性地，第二绝缘材料可以包括氮化硅、氮化钛或其他氮化物等。
在一些实施例中，所述栅极导电层的厚度小于所述栅极氧化层的高度，所述将所述凹陷区域内的栅极导电层在所述第一方向的截面上分离之后，所述方法还包括：
在所述凹陷区域内的栅极氧化层之间填充第三绝缘材料形成第三隔离层；其中，第三隔离层的底部与所述第二隔离层的顶部和所述栅极导电层连接。
在本公开实施例中，当栅极导电层的厚度小于栅极氧化层的高度时，上述凹陷区域剩余的部分底部与栅极导电层接触，侧壁与部分栅极氧化层接触。可以在栅极氧化层之间通过沉积的方式填充第三绝缘材料，这里的第三绝缘材料可以是氧化物、氮化物或者其他绝缘材料等。示例性地，第三绝缘材料可以与 第二绝缘材料相同或不同，在沉积的过程中可以同步进行，形成第三隔离层。
本公开实施例还提供了一种半导体器件，如图10A所示为半导体器件1100的俯视图，图10B和图10C分别为图10A中bb’截面和cc’截面的截面图。该半导体器件1100包括：
衬底1000；
在所述衬底1000上沿第一方向D1延伸的多条第一沟槽1010以及沿第二方向D2延伸的多条第二沟槽1020；其中，所述第一方向D1与所述第二方向D2垂直；所述第一沟槽1010的第一深度等于所述第二沟槽1020的第二深度；
位于所述第一沟槽1010与所述第二沟槽1020底部的第一绝缘层1030；
位于所述第一绝缘层1030上的导电层1040；所述导电层1040在所述第二方向D2的截面上分离，所述分离的导电层1040构成与所述第一沟槽1010内两侧的侧壁分别连接且沿所述第一方向D1延伸的两条位线1200；
所述第一沟槽1010和第二沟槽1020内、所述导电层1040上具有沿所述第二方向D2延伸的字线1300。
本公开实施例中的第一方向是平行于衬底表面延伸的方向，在第一方向上有多条相互平行的第一沟槽，每条第一沟槽都是条状结构，在第一方向上延伸。示例性地，多条第一沟槽之间相互平行且可以具有相等的间距、深度以及宽度。
相应地，在与第一方向垂直的第二方向上有多条相互平行的第二沟槽，每条第二沟槽都是条状结构，在第二方向上延伸。示例性地，多条第二沟槽之间相互平行且可以具有相等的间距、深度以及宽度。这里，第二沟槽具有与上述第一沟槽相同的深度。如此，第二沟槽与上述第一沟槽在衬底表面构成了网状的结构。
第一绝缘层用于将导电层与衬底电隔离，由绝缘材料组成，例如氧化物、氮化物或者其他绝缘材料等。这里的导电层则由导电材料构成，例如金属铜、金属坞等金属材料、掺杂的半导体材料或其他导电材料。在第二沟槽内的导电层直接连接第二沟槽两侧的侧壁，并且在第二方向上延伸；在第一沟槽内的导电在第二方向的截面上层被分离为两条相互平行的位线，分别连接第二凹槽两侧的侧壁，并且在第一方向上延伸，如此，构成了本公开实施例的双位线结构。
本公开实施例中的字线位于双位线结构之上，两者之间可以通过绝缘材料实现电隔离，相应地，上述字线在第二方向上延伸。
在一些实施例中，如图10D所示，图10D为图10A中在bb’截面上的截面图，所述半导体器件1100还包括：
第一隔离层1050，位于所述第一沟槽内的所述第一绝缘层上；其中，所述第一沟槽中的所述导电层被所述第一隔离层1050分离。
在本公开实施例中，第一沟槽中的导电层在第二方向的截面上可以被第一隔离层分离为两条相互平行的位线。该第一隔离层可以由氧化物材料构成，并在第一方向上延伸。
在一些实施例中，如图10E所示，图10E为图10A中在bb’截面上的截面图，所述半导体器件1100还包括：
第二绝缘层1060，位于所述导电层与所述字线之间；其中，所述第一沟槽 中的第二绝缘层1060在所述第二方向的截面上被所述第一隔离层1050分离。
在本公开实施例中，导电层与字线之间可以通过第二绝缘层实现电隔离，该第二绝缘层可以由氮化物、氧化物或者其他绝缘材料构成。由于在第一沟槽中形成双位线结构，两条位线之间被第一隔离层分离。相应地，在第一沟槽中的第二绝缘层也可以被上述第一隔离层分离。
在一些实施例中，如图10F所示，图10F为图10A中在cc’截面上的截面图，所述半导体器件1100还包括：
栅极氧化层1070，位于所述第二绝缘层上的所述第一沟槽和所述第二沟槽的部分侧壁上；
所述字线，包括：位于相邻的所述栅极氧化层1070之间的各半导体柱对应的栅极导电层1080；所述栅极导电层在所述第二方向上连通。
在本公开实施例中，栅极包括栅极氧化层和栅极导电层，且栅极位于第二绝缘层上。其中，栅极氧化层覆盖在第一沟槽和第二沟槽剩余部分的侧壁上；栅极导电层位于栅极氧化层之间。这里，在第二沟槽内的栅极导电层相互连通，并在第一方向的截面上被分离，构成人沿第二方向延伸的字线。
在一些实施例中，如图10G所示，图10G为图10A中在cc’截面上的截面图，所述半导体器件1100还包括：
第二隔离层1090，位于所述第二沟槽内的所述第二绝缘层上；其中，所述第二沟槽中的所述栅极导电层在所述第一方向的截面上被所述第二隔离层1090分离。
在本公开实施例中，第二沟槽中的栅极导电层在第一方向的截面上可以被第二隔离层分离为两条相互平行的字线。该第二隔离层可以由氮化物材料构成，并在第二方向上延伸。这里，构成第二隔离层的材料可以和构成上述第二绝缘层的材料相同。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例提供的技术方案，在半导体器件的制造过程中通过在衬底上形成沟槽，在沟槽中形成第一绝缘层、导电层和第二绝缘层，然后将第一沟槽中的导电层在第二方向的截面上分离，形成掩埋于衬底内的位线结构。如此，一方面相比于对半导体衬底掺杂形成的位线，本公开实施例采用的沉积导电材料形成的位线具有更高的导电性能，因此能够提升半导体器件的整体性能。另一方面，通过在第一沟槽两侧侧壁形成的相互平行且在第二方向分离的双位线结构，可以提升半导体器件的集成度，减少位线之间的寄生电容。

Claims (15)

  1. 一种半导体器件的制造方法，所述半导体器件，包括衬底，所述方法包括：
    在所述衬底上形成沿第一方向延伸的多条第一沟槽；
    在形成有所述第一沟槽的所述衬底上形成沿第二方向延伸的多条第二沟槽；所述第一方向与所述第二方向垂直；所述第一沟槽的第一深度等于所述第二沟槽的第二深度；
    在所述第一沟槽与所述第二沟槽内依次形成第一绝缘层、导电层和第二绝缘层；
    将所述第一沟槽中的所述导电层在所述第二方向的截面上分离，形成与所述第一沟槽内两侧的侧壁连接且沿所述第一方向延伸的两条位线；
    在所述第一沟槽和第二沟槽内、所述导电层上，形成沿所述第二方向延伸的字线。
  2. 根据权利要求1所述的方法，其中，所述将所述第一沟槽中的导电层在所述第二方向上的截面上分离，包括：
    沿所述第一方向，在所述第一沟槽内的所述第一绝缘层、所述导电层和所述第二绝缘层上形成具有第三深度的第一缝隙；所述第三深度小于所述第一绝缘层、导电层和第二绝缘层的总厚度，且所述第三深度大于所述第一绝缘层和导电层的厚度之和；
    在所述第一缝隙内填充第一绝缘材料，形成第一隔离层；其中，所述第一沟槽中的导电层在所述第二方向的截面上被所述第一隔离层分离。
  3. 根据权利要求2所述的方法，其中，所述第一绝缘材料包括氧化物。
  4. 根据权利要求1所述的方法，其中，所述在所述第一沟槽与所述第二沟槽内依次形成第一绝缘层、导电层和第二绝缘层之后，所述方法还包括：
    对所述第二绝缘层和所述衬底表面进行平坦化处理，使所述第一沟槽和所述第二沟槽以外区域的衬底表面显露。
  5. 根据权利要求1所述的方法，其中，所述在所述第一沟槽和第二沟槽内、所述导电层上，形成沿所述第二方向延伸的字线，包括：
    去除所述第一沟槽和所述第二沟槽内、所述导电层上方部分的所述第二绝缘层，形成凹陷区域；
    在所述凹陷区域内，形成所述字线。
  6. 根据权利要求5所述的方法，其中，所述在所述凹陷区域内，形成所述字线，包括：
    在所述凹陷区域内的侧壁形成栅极氧化层；
    在所述凹陷区域内的所述栅极氧化层之间形成栅极导电层；
    将所述凹陷区域内的所述栅极导电层在所述第一方向的截面上分离为两条沿所述第二方向延伸的所述字线。
  7. 根据权利要求6所述的方法，其中，所述在所述凹陷区域内的所述栅极氧化层之间形成栅极导电层，包括：
    在所述凹陷区域的所述栅极氧化层之间沉积导电材料，形成栅极导电层；所述栅极导电层的厚度小于或等于所述栅极氧化层的高度。
  8. 根据权利要求6所述的方法，其中，所述将所述凹陷区域内的所述栅极导电层在所述第一方向的截面上分离为两条沿所述第二方向延伸的所述字线，包括：
    沿所述第二方向，在所述栅极导电层上形成具有第四深度的第二缝隙；所述第四深度大于或等于所述栅极导电层的厚度；所述第二缝隙在所述第一方向的截面上分离所述栅极导电层；
    在所述第二缝隙内填充第二绝缘材料，形成第二隔离层；其中，所述第二隔离层两侧的所述导电材料连通的各所述栅极导电层构成所述字线。
  9. 根据权利要求8所述的方法，其中，所述第二绝缘材料包括氮化物。
  10. 根据权利要求9所述的方法，其中，所述栅极导电层的厚度小于所述栅极氧化层的高度，所述将所述凹陷区域内的栅极导电层在所述第一方向的截面上分离之后，所述方法还包括：
    在所述凹陷区域内的栅极氧化层之间填充第三绝缘材料形成第三隔离层；其中，第三隔离层的底部与所述第二隔离层的顶部和所述栅极导电层连接。
  11. 一种半导体器件，包括：
    衬底；
    在所述衬底上沿第一方向延伸的多条第一沟槽以及沿第二方向延伸的多条第二沟槽；其中，所述第一方向与所述第二方向垂直；所述第一沟槽的第一深度等于所述第二沟槽的第二深度；
    位于所述第一沟槽与所述第二沟槽底部的第一绝缘层；
    位于所述第一绝缘层上的导电层；所述导电层在所述第二方向的截面上分离，所述分离的导电层构成与所述第一沟槽内两侧的侧壁分别连接且沿所述第一方向延伸的两条位线；
    所述第一沟槽和第二沟槽内、所述导电层上具有沿所述第二方向延伸的字线。
  12. 根据权利要求11所述的半导体器件，其中，所述半导体器件还包括：
    第一隔离层，位于所述第一沟槽内的所述第一绝缘层上；其中，所述第一沟槽中的所述导电层在所述第二方向的截面上被所述第一隔离层分离。
  13. 根据权利要求12所述的半导体器件，其中，所述半导体器件还包括：
    第二绝缘层，位于所述导电层与所述字线之间；其中，所述第一沟槽中的第二绝缘层在所述第二方向的截面上被所述第一隔离层分离。
  14. 根据权利要求13所述的半导体器件，其中，所述半导体器件还包括：
    栅极氧化层，位于所述第二绝缘层上的所述第一沟槽和所述第二沟槽的部分侧壁上；
    所述字线，包括：位于相邻的所述栅极氧化层之间的各半导体柱对应的栅极导电层；所述栅极导电层在所述第二方向上连通。
  15. 根据权利要求14所述的半导体器件，其中，所述半导体器件还包括：
    第二隔离层，位于所述第二沟槽内的所述第二绝缘层上；其中，所述第二 沟槽中的所述栅极导电层在所述第一方向的截面上被所述第二隔离层分离。
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