WO2023008054A1 - 炭化珪素基板 - Google Patents

炭化珪素基板 Download PDF

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Publication number
WO2023008054A1
WO2023008054A1 PCT/JP2022/025747 JP2022025747W WO2023008054A1 WO 2023008054 A1 WO2023008054 A1 WO 2023008054A1 JP 2022025747 W JP2022025747 W JP 2022025747W WO 2023008054 A1 WO2023008054 A1 WO 2023008054A1
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Prior art keywords
silicon carbide
carbide substrate
resistivity
center
downstream side
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Ceased
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PCT/JP2022/025747
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English (en)
French (fr)
Japanese (ja)
Inventor
宏樹 高岡
俊策 上田
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority to JP2023538356A priority Critical patent/JPWO2023008054A1/ja
Priority to US18/291,816 priority patent/US12116696B2/en
Publication of WO2023008054A1 publication Critical patent/WO2023008054A1/ja
Anticipated expiration legal-status Critical
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    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/90—Carbides
    • C01B32/914—Carbides of single elements
    • C01B32/956—Silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C30B23/06—Heating of the deposition chamber, the substrate or the materials to be evaporated
    • C30B23/063—Heating of the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides

Definitions

  • Patent Document 1 Japanese Patent Application Laid-Open No. 2015-93810 describes a SiC single crystal.
  • the SiC single crystal described in Patent Document 1 is formed from a seed crystal using a sublimation recrystallization method.
  • the temperature is low in the central portion of the crystal growth surface of the seed crystal, and the temperature is high in the peripheral portion of the crystal growth surface of the seed crystal.
  • the speed of crystal growth in the central portion of the crystal growth surface of the seed crystal increases, and the speed of crystal growth in the peripheral portion of the crystal growth surface of the seed crystal decreases.
  • the crystal growth surface of the seed crystal is a convex curved surface.
  • a silicon carbide substrate of the present disclosure contains a dopant.
  • the silicon carbide substrate has a portion having a lower resistivity than the center on the off-downstream side of the center of the silicon carbide substrate in plan view.
  • a value obtained by dividing the difference between the resistivity of the silicon carbide substrate at the center and the minimum value of the resistivity of the silicon carbide substrate at the OFF downstream side of the center by the resistivity of the silicon carbide substrate at the center is 0.015 or less.
  • the resistivity of the silicon carbide substrate increases toward the OFF downstream side from the position where the resistivity of the silicon carbide substrate has a minimum value.
  • FIG. 1 is a plan view of silicon carbide substrate 100 .
  • FIG. 2 is a cross-sectional view of silicon carbide substrate 100 .
  • FIG. 3 is a schematic cross-sectional view of step flow growth of a seed crystal 220 whose crystal growth surface is inclined at an off angle ⁇ .
  • FIG. 4 is a schematic graph showing the resistivity of silicon carbide substrate 100 on the OFF downstream side of center C.
  • FIG. 5 is a schematic diagram showing a method of measuring resistivity of silicon carbide substrate 100 using a measuring device.
  • FIG. 6 is a process diagram showing a method of manufacturing silicon carbide substrate 100 .
  • FIG. 7 is a schematic cross-sectional view of the manufacturing apparatus 300. As shown in FIG. FIG. FIG.
  • FIG. 8 is a schematic diagram showing the temperature distribution in the vicinity of the seed crystal 220. As shown in FIG. FIG. 9 is a graph showing the relationship between the thickness of ingot 200 and the resistivity of ingot 200 .
  • FIG. 10 is a plan view of silicon carbide substrate 100A.
  • FIG. 11 is a cross-sectional view of silicon carbide substrate 100A.
  • FIG. 12 is a schematic graph showing the resistivity of silicon carbide substrate 100A on the off downstream side of center C. As shown in FIG.
  • the thermal expansion coefficient of the central portion is smaller than the thermal expansion coefficient of the peripheral portion, and due to this difference in thermal expansion coefficient, tensile stress remains in the peripheral portion. .
  • This tensile residual stress may cause cracks in the substrate cut out from the SiC single crystal described in Patent Document 1.
  • the crystal growth surface is a convex curved surface
  • the inclination with respect to the (0001) plane is off at the peripheral edge portion of the crystal growth surface on the off downstream side. It becomes larger than the angle, and stacking faults are likely to occur.
  • the present disclosure has been made in view of the problems of the prior art as described above. More specifically, the present disclosure provides a silicon carbide substrate capable of suppressing crack generation, stacking fault generation, and heterogeneous crystal generation. [Effect of the present disclosure] According to the silicon carbide substrate of the present disclosure, crack generation can be suppressed, stacking fault generation can be suppressed, and heterogeneous crystal generation can be suppressed.
  • a silicon carbide substrate according to an embodiment contains a dopant.
  • the silicon carbide substrate has a portion having a lower resistivity than the center on the off-downstream side of the center of the silicon carbide substrate in plan view.
  • a value obtained by dividing the difference between the resistivity of the silicon carbide substrate at the center and the minimum value of the resistivity of the silicon carbide substrate at the OFF downstream side of the center by the resistivity of the silicon carbide substrate at the center is 0.015 or less.
  • the resistivity of the silicon carbide substrate increases toward the OFF downstream side from the position where the resistivity of the silicon carbide substrate has a minimum value.
  • the silicon carbide substrate of (1) above it is possible to suppress the occurrence of cracks, stacking faults, and heterogeneous crystals.
  • a silicon carbide substrate according to another embodiment contains a dopant.
  • the silicon carbide substrate has a portion having a lower resistivity than the center at the periphery of the silicon carbide substrate located on the off-downstream side of the center of the silicon carbide substrate in plan view.
  • the silicon carbide substrate has a minimum resistivity at the outer periphery. A value obtained by dividing the difference between the resistivity of the silicon carbide substrate at the center and the minimum resistivity of the silicon carbide substrate at the periphery by the resistivity of the silicon carbide substrate at the center is 0.015 or less.
  • the silicon carbide substrate of (2) above it is possible to suppress the occurrence of cracks, stacking faults, and heterogeneous crystals.
  • the silicon carbide substrate of (1) or (2) above may have an outer diameter of 150 mm or more.
  • the silicon carbide substrate of (3) above it is possible to suppress the occurrence of cracks and the occurrence of stacking faults even when the outer diameter is large.
  • the dopant may be nitrogen.
  • a difference between the resistivity of the silicon carbide substrate at the center of the silicon carbide substrate and the minimum value of the resistivity of the silicon carbide substrate on the off downstream side of the center may be 0.22 m ⁇ cm or less.
  • the area ratio of stacking faults may be 20% or less.
  • a silicon carbide substrate according to the embodiment is referred to as a silicon carbide substrate 100 .
  • FIG. 1 is a plan view of a silicon carbide substrate 100.
  • FIG. FIG. 2 is a cross-sectional view of silicon carbide substrate 100 .
  • silicon carbide substrate 100 has a first main surface 100a and a second main surface 100b.
  • First main surface 100a and second main surface 100b are end surfaces in the thickness direction of silicon carbide substrate 100 .
  • the second principal surface 100b is the opposite surface of the first principal surface 100a.
  • the outer periphery of silicon carbide substrate 100 is referred to as outer periphery 100c.
  • Silicon carbide substrate 100 is formed of a single crystal of silicon carbide.
  • the polytype of silicon carbide forming silicon carbide substrate 100 is, for example, 4H.
  • the polytype of silicon carbide forming silicon carbide substrate 100 is not limited to this.
  • the polytype of silicon carbide forming silicon carbide substrate 100 may be, for example, 6H.
  • the silicon carbide substrate 100 contains dopants.
  • a dopant contained in silicon carbide substrate 100 is an n-type dopant or a p-type dopant. Specific examples of n-type dopants include nitrogen and phosphorus. Specific examples of p-type dopants include aluminum and boron.
  • the dopant contained in silicon carbide substrate 100 is preferably nitrogen.
  • first main surface 100a is inclined at an off angle ⁇ in the off direction.
  • the off direction is, for example, the ⁇ 11-20> direction.
  • the off direction may be the ⁇ 1-100> direction.
  • the ⁇ 0001 ⁇ plane of silicon carbide forming silicon carbide substrate 100 is indicated by a dotted line.
  • FIG. 3 is a schematic cross-sectional view during step flow growth of a seed crystal 220 whose crystal growth surface is inclined at an off angle ⁇ .
  • the seed crystal 220 is crystal-grown by step flow growth along the direction of the arrow in FIG.
  • the downstream side of this step-flow growth is referred to as the off-downstream side.
  • the right side is OFF downstream and the left side is OFF upstream.
  • the center of silicon carbide substrate 100 in plan view is defined as center C.
  • FIG. 4 is a schematic graph showing the resistivity of silicon carbide substrate 100 on the OFF downstream side of center C.
  • silicon carbide substrate 100 has a portion with lower resistivity than center C on the OFF downstream side of center C. As shown in FIG. This portion is radially outward of the center C.
  • the resistivity of silicon carbide substrate 100 is the minimum value. The resistivity of silicon carbide substrate 100 increases from position P toward the OFF downstream side (radial direction outer side).
  • the difference between the resistivity of silicon carbide substrate 100 at center C and the resistivity of silicon carbide substrate 100 at position P is divided by the resistivity of silicon carbide substrate 100 at center C.
  • the value is 0.015 or less.
  • the difference between the resistivity of silicon carbide substrate 100 at center C and the resistivity of silicon carbide substrate 100 at position P is 0.22 m ⁇ cm or less.
  • FIG. 5 is a schematic diagram showing a method of measuring resistivity of silicon carbide substrate 100 using a measuring device.
  • silicon carbide substrate 100 to be measured is placed in the measuring device.
  • Silicon carbide substrate 100 is arranged between a pair of probe cores PC.
  • the diameter of the probe core PC is set to 25 mm.
  • a high frequency is applied between the probe cores PC.
  • a magnetic flux (indicated by dotted lines in FIG. 5) is generated between the probe cores PC.
  • This magnetic flux also causes an eddy current in silicon carbide substrate 100 . Eddy currents in the silicon carbide substrate 100 cause power loss and reduce the current flowing through the circuitry of the measurement device.
  • the amount of decrease in current and the sheet resistance of silicon carbide substrate 100 are in an inversely proportional relationship. Therefore, the measuring device measures the silicon carbide substrate 100 based on the detected current decrease amount, the sheet resistance calibration curve (calculation formula showing the relationship between the current decrease amount and the sheet resistance), and the thickness of the silicon carbide substrate 100. A resistivity of 100 can be measured.
  • the area ratio of stacking faults is preferably 20% or less.
  • the area ratio of stacking faults is calculated by photoluminescence measurement. More specifically, first, silicon carbide substrate 100 is divided into a plurality of measurement regions. Each measurement area is 2.7 mm x 2.7 mm in size. Second, photoluminescence measurement is performed on silicon carbide substrate 100 . Light emission is observed from the measurement region where the stacking fault exists. Third, the number of measurement areas where luminescence was observed divided by the total number of measurement areas is multiplied by 100. As a result, the area ratio of stacking faults is obtained.
  • An outer diameter D is the outer diameter of the silicon carbide substrate 100 .
  • the outer diameter D is, for example, 100 mm (4 inches) or more.
  • Outer diameter D is preferably 150 mm (6 inches) or greater. However, the outer diameter D may be less than 100 mm.
  • FIG. 6A to 6D are process diagrams showing a method for manufacturing the silicon carbide substrate 100.
  • the method for manufacturing silicon carbide substrate 100 includes a crystal growth step S1 and a slicing step S2.
  • FIG. 7 is a schematic cross-sectional view of the manufacturing apparatus 300. As shown in FIG. As shown in FIG. 7, manufacturing apparatus 300 has crucible 310 and heater 320 .
  • the crucible 310 is made of a heat resistant material.
  • the crucible 310 is made of graphite, for example.
  • Crucible 310 has a tubular portion 311 and a lid 312 . One end of the tubular portion 311 is closed by a bottom wall 313 .
  • a raw material 210 is placed inside the tubular portion 311 .
  • Raw material 210 is silicon carbide powder.
  • seed crystal 220 is attached to the inner wall surface of the lid 312 .
  • seed crystal 220 is arranged inside crucible 310 .
  • Seed crystal 220 has a first main surface 220a and a second main surface 220b.
  • the first main surface 220a faces the raw material 210 side. From another point of view, the first main surface 220 a is the crystal growth surface of the seed crystal 220 .
  • the second major surface 220 b is the opposite surface of the first major surface 220 a and is attached to the lid 312 .
  • Seed crystal 220 is formed of a single crystal of silicon carbide.
  • First main surface 220a is inclined at an off angle ⁇ in the off direction with respect to the ⁇ 0001 ⁇ plane of silicon carbide forming seed crystal 220 .
  • the heater 320 sublimates the raw material 210 by heating the crucible 310 from the outside.
  • Heater 320 is, for example, a resistance heater.
  • the sublimated raw material 210 faces the seed crystal 220 and is recrystallized on the first major surface 220a. By repeating this process, the seed crystal 220 grows and becomes an ingot 200 (indicated by the dotted line in FIG. 7).
  • FIG. 8 is a schematic diagram showing the temperature distribution in the vicinity of the seed crystal 220.
  • FIG. A solid curve in FIG. 8 indicates the relationship between the position on the seed crystal 220 and the temperature at that position.
  • the temperature in the vicinity of seed crystal 220 decreases from the center of seed crystal 220 toward the outside in the radial direction and reaches a minimum value.
  • the temperature in the vicinity of the seed crystal 220 becomes higher toward the outside in the radial direction after reaching the minimum value.
  • Such a temperature distribution in the vicinity of the seed crystal 220 can be obtained, for example, by adjusting the output of the heater 320 and/or the placement of heat insulating material arranged around the crucible 310 .
  • the thickness of the ingot 200 at the central portion of the tip surface of the ingot 200 is defined as the first thickness.
  • the maximum thickness of ingot 200 is defined as a second thickness.
  • the temperature distribution is preferably selected such that the value obtained by subtracting the first thickness from the second thickness is 2 mm or less.
  • silicon carbide substrate 100 is cut out from ingot 200 formed in crystal growth step S1. Cutting of silicon carbide substrate 100 from ingot 200 is performed using, for example, a wire saw.
  • the amount of dopant incorporated is small, and the coefficient of thermal expansion and resistivity are large.
  • the amount of dopant incorporated is high and the coefficient of thermal expansion and resistivity are low.
  • FIG. 9 is a graph showing the relationship between the thickness of the ingot 200 and the resistivity of the ingot 200.
  • the horizontal axis represents the thickness (unit: mm) of ingot 200 , which is calculated from the distance from first main surface 220 a of seed crystal 220 .
  • the vertical axis is the resistivity of the ingot 200 (unit: m ⁇ cm). Note that FIG. 9 shows the relationship between the thickness of ingot 200 and the resistivity of ingot 200 when the dopant is nitrogen.
  • the resistivity of ingot 200 increases as the thickness of ingot 200 increases. This is because the crystal growth surface of the seed crystal 220 is located closer to the raw material 210 as the crystal growth progresses, so the temperature of the crystal growth surface of the seed crystal 220 is increased and the resistance tends to be increased.
  • the temperature near the seed crystal 220 once becomes the minimum value, and then increases further toward the outside in the radial direction. Therefore, the dopant content in ingot 200 decreases from the position where the thickness of ingot 200 reaches the second thickness toward the outside in the radial direction. As a result, the resistivity of silicon carbide substrate 100 cut out from ingot 200 increases from position P toward the OFF downstream side.
  • the silicon carbide substrate 100 has a portion having a lower resistivity than the center C on the off downstream side of the center C. That is, silicon carbide substrate 100 has a smaller coefficient of thermal expansion in a region radially outside center C. As shown in FIG. Therefore, in silicon carbide substrate 100, tensile residual stress is less likely to occur in a region located radially outside center C, and crack generation is suppressed.
  • the temperature distribution during crystal growth is controlled so that the value obtained by subtracting the first thickness of the ingot 200 from the second thickness of the ingot 200 is small (specifically, 2 mm or less). Therefore, during the crystal growth process, a portion of the crystal growth surface where the angle of inclination with respect to the ⁇ 0001 ⁇ plane is larger than the off angle ⁇ is less likely to occur. As a result, in silicon carbide substrate 100 cut out from ingot 200, the occurrence of stacking faults is suppressed.
  • sample 1 and sample 2 were prepared as samples of silicon carbide substrate 100 .
  • (A) silicon carbide substrate 100 has a portion where the resistivity of silicon carbide substrate 100 is lower than center C on the off-downstream side of center C, and (B) silicon carbide substrate.
  • Table 1 shows the crack occurrence rate, stacking fault area ratio, and heterogeneous crystal occurrence rate for Samples 1 and 2. Five samples of each type were prepared, and the rate of occurrence of cracks was evaluated based on how many of the five samples had cracks. For the heterogeneous crystal occurrence rate, five samples were prepared, and the number of heterogeneous crystals among the five samples was evaluated. The presence or absence of heterogeneous crystals was visually confirmed.
  • Silicon carbide substrate 100 according to a modification will be described below. Silicon carbide substrate 100 according to the modification is referred to as silicon carbide substrate 100A. Here, points different from silicon carbide substrate 100 will be mainly described, and redundant description will not be repeated.
  • FIG. 10 is a plan view of silicon carbide substrate 100A.
  • FIG. 11 is a cross-sectional view of silicon carbide substrate 100A.
  • silicon carbide substrate 100A has a first main surface 100a and a second main surface 100b.
  • the outer diameter is outer diameter D.
  • first main surface 100a is inclined at an off angle ⁇ in the off direction (eg, ⁇ 11-20> direction) with respect to the ⁇ 0001 ⁇ plane of silicon carbide forming silicon carbide substrate 100A. are doing.
  • the configuration of silicon carbide substrate 100A is common to the configuration of silicon carbide substrate 100 .
  • the silicon carbide substrate 100A has a portion having a lower resistivity than the center C at the outer periphery 100c located on the off downstream side of the center C.
  • FIG. 12 is a schematic graph showing the resistivity of silicon carbide substrate 100A on the off downstream side of center C. As shown in FIG. As shown in FIG. 12 , the resistivity of silicon carbide substrate 100A has a minimum value at outer periphery 100c located downstream of center C. As shown in FIG.
  • the value obtained by dividing the difference between the resistivity at center C of silicon carbide substrate 100A and the resistivity at outer periphery 100c of silicon carbide substrate 100A by the resistivity at center C of silicon carbide substrate 100A is 0.015 or less.
  • the difference between the resistivity at center C of silicon carbide substrate 100A and the resistivity at outer periphery 100c of silicon carbide substrate 100A is 0.22 m ⁇ cm or less. .
  • the configuration of silicon carbide substrate 100A is different from the configuration of silicon carbide substrate 100 .
  • silicon carbide substrate 100A In the manufacturing process of silicon carbide substrate 100A, ingot 200 is formed such that the outer diameter of ingot 200 is larger than outer diameter D. Then, the ingot 200 is ground so that the outer diameter of the ingot 200 becomes the outer diameter D before the slicing step S2 is performed. That is, silicon carbide substrate 100 from which outer periphery 100c side is removed by processing is silicon carbide substrate 100A. Therefore, like silicon carbide substrate 100, silicon carbide substrate 100A can suppress the occurrence of cracks, stacking faults, and dissimilar crystals.

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  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Inorganic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
PCT/JP2022/025747 2021-07-30 2022-06-28 炭化珪素基板 Ceased WO2023008054A1 (ja)

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AT524251B1 (de) * 2020-09-28 2023-04-15 Ebner Ind Ofenbau Vorrichtung zum Züchten von Einkristallen
CN119041030B (zh) * 2024-11-01 2025-04-18 山东天岳先进科技股份有限公司 一种大尺寸、低电阻4h碳化硅晶棒、低电阻4h碳化硅晶片及制备方法

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CN103614779A (zh) * 2013-11-28 2014-03-05 中国电子科技集团公司第五十五研究所 一种提高碳化硅外延片片内n型掺杂浓度均匀性的方法
JP2017055086A (ja) * 2015-09-11 2017-03-16 昭和電工株式会社 ＳｉＣエピタキシャルウェハの製造方法及びＳｉＣエピタキシャルウェハの製造装置
JP2017065955A (ja) * 2015-09-29 2017-04-06 新日鐵住金株式会社 ｐ型低抵抗率炭化珪素単結晶基板
JP2017095319A (ja) * 2015-11-26 2017-06-01 新日鐵住金株式会社 ＳｉＣ単結晶インゴットの製造方法及びＳｉＣ単結晶インゴット並びにＳｉＣ単結晶ウェハ
JP2019021694A (ja) * 2017-07-13 2019-02-07 日立金属株式会社 炭化ケイ素積層基板およびその製造方法

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JP6235875B2 (ja) 2013-11-12 2017-11-22 一般財団法人電力中央研究所 炭化珪素単結晶の製造方法及び炭化珪素単結晶の製造装置
JP7185087B1 (ja) * 2022-06-02 2022-12-06 昭和電工株式会社 ＳｉＣ基板及びＳｉＣインゴット

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CN103614779A (zh) * 2013-11-28 2014-03-05 中国电子科技集团公司第五十五研究所 一种提高碳化硅外延片片内n型掺杂浓度均匀性的方法
JP2017055086A (ja) * 2015-09-11 2017-03-16 昭和電工株式会社 ＳｉＣエピタキシャルウェハの製造方法及びＳｉＣエピタキシャルウェハの製造装置
JP2017065955A (ja) * 2015-09-29 2017-04-06 新日鐵住金株式会社 ｐ型低抵抗率炭化珪素単結晶基板
JP2017095319A (ja) * 2015-11-26 2017-06-01 新日鐵住金株式会社 ＳｉＣ単結晶インゴットの製造方法及びＳｉＣ単結晶インゴット並びにＳｉＣ単結晶ウェハ
JP2019021694A (ja) * 2017-07-13 2019-02-07 日立金属株式会社 炭化ケイ素積層基板およびその製造方法

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