WO2023005162A1 - 位线结构、半导体结构及位线结构的制作方法 - Google Patents

位线结构、半导体结构及位线结构的制作方法 Download PDF

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Publication number
WO2023005162A1
WO2023005162A1 PCT/CN2022/071821 CN2022071821W WO2023005162A1 WO 2023005162 A1 WO2023005162 A1 WO 2023005162A1 CN 2022071821 W CN2022071821 W CN 2022071821W WO 2023005162 A1 WO2023005162 A1 WO 2023005162A1
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Prior art keywords
initial
dielectric layer
layer
substrate
bit line
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PCT/CN2022/071821
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English (en)
French (fr)
Inventor
金星
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长鑫存储技术有限公司
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Priority to US18/150,899 priority Critical patent/US20230148354A1/en
Publication of WO2023005162A1 publication Critical patent/WO2023005162A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present disclosure relates to but not limited to a bit line structure, a semiconductor structure and a manufacturing method of the bit line structure.
  • bit line In a DRAM (Dynamic Random Access Memory) device, the bit line (Bitline) is connected to a transistor (Transistor) and a capacitor (Capacitor).
  • Transistor Transistor
  • Capacitor Capacitor
  • the contact resistance of the bit line affects the conductivity of the bit line, affects the current of the device, and then affects the conduction capability of the device. As the size of integrated circuits shrinks, the requirements for the contact conductive structure of bit lines are getting higher and higher.
  • the disclosure provides a bit line structure, a semiconductor structure and a manufacturing method of the bit line structure.
  • a first aspect of the present disclosure provides a bit line structure, the bit line structure is disposed on a substrate, and the bit line structure includes:
  • a barrier layer comprising an extension covering a top surface and an outer side wall surface of the contact portion
  • the conductive layer covers part of the barrier layer.
  • the contact portion includes a first portion and a second portion, the first portion is located inside the substrate, and the second portion is located above the substrate;
  • the barrier layer further includes a main body portion, and a second portion of the contact portion passes through the main body portion and extends into the conductive layer;
  • the conductive layer covers the main body and part of the surface of the extension.
  • the main body part is integrated with the extension part.
  • the main body part covers the first dielectric layer above the substrate
  • a second portion of the contact portion penetrates the first dielectric layer.
  • a first part of the outer wall of the extension is in contact with the substrate, and an insulating part is provided on the second part of the outer wall of the extension.
  • the insulating part is integrated with the first dielectric layer.
  • a plurality of word lines arranged in parallel are buried in the substrate, and the contact portion is arranged between adjacent word lines.
  • the projection of the extension on the substrate is in a square shape, and a plane parallel to the word line and perpendicular to the substrate is taken as a first section, and the second section of the extension is The outer walls of the two parts are perpendicular to the first section.
  • the thickness of the outer sidewall of the first part of the extension part is greater than the thickness of the outer sidewall of the second part of the extension part.
  • a second aspect of the present disclosure provides a semiconductor structure including the bit line structure described in the present disclosure.
  • a third aspect of the present disclosure provides a manufacturing method of a bit line structure, the manufacturing method including the following steps:
  • the substrate comprising a substrate and a first initial dielectric layer covering the substrate;
  • a contact portion and a second initial dielectric unit covering the outer sidewall of the contact portion are formed in the initial contact hole, the bottom surface of the contact portion is connected to the substrate, and the side wall of the second initial dielectric unit is connected to the substrate.
  • the substrate is connected to the first initial dielectric layer;
  • the third initial dielectric layer covers the first dielectric layer and the sidewalls of the second initial dielectric unit, and the top surface of the contact portion and the second On the top surface of the initial dielectric unit, the third initial dielectric layer is integrated with the second initial dielectric unit, and the initial stacked structure covers the third initial dielectric layer;
  • Etching the initial stack structure, the third initial dielectric layer and the second initial dielectric unit, the retained initial stack structure forms a stack structure, the stack structure includes a conductive layer; the retained second initial The dielectric unit and the third initial dielectric layer are connected together to form a barrier layer, and the retained second initial dielectric unit and the third initial dielectric layer covering the contact portion form an extension of the barrier layer ;
  • a fourth dielectric layer is formed, and the fourth dielectric layer covers the stacked structure and part of the extension.
  • the formation of the second initial dielectric unit covering the outer sidewall of the contact portion in the initial contact hole includes:
  • forming a contact portion in the initial contact hole includes:
  • depositing the initial stack structure includes:
  • An initial isolation layer is deposited, the initial isolation layer covering the initial conductive layer.
  • the method further includes:
  • a mask layer is formed on the initial isolation layer.
  • the etching the initial stack structure, the third initial dielectric layer, and the second initial dielectric unit includes:
  • Etching the third initial dielectric layer, the reserved part of the third initial dielectric layer corresponding to the pattern is used as a part of the extension part, and the reserved third initial dielectric layer corresponding to the pattern Another part of the dielectric layer serves as the main body of the barrier layer;
  • the second initial dielectric unit is etched, and the second initial dielectric unit corresponding to the pattern is retained as another part of the extension portion.
  • the fourth dielectric layer is integrated with the first dielectric layer
  • a part of the fourth dielectric layer located between the second initial dielectric unit and the substrate forms an insulating part.
  • the barrier layer covers the top surface and the outer wall of the contact portion, and the barrier layer protects the sidewall of the contact portion from oxidation, thereby reducing the contact resistance of the bit line.
  • FIG. 1 is a schematic cross-sectional view of a bit line structure in a direction parallel to WL according to an exemplary embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional view of a bit line structure along the BL direction according to an exemplary embodiment of the present disclosure.
  • Fig. 3 is a projection view of a contact portion of a bit line structure on a substrate according to an exemplary embodiment.
  • Fig. 4 is a flow chart of a manufacturing method of a bit line structure according to an exemplary embodiment.
  • Fig. 5 is a flow chart of forming a second initial dielectric unit covering an outer sidewall of a contact portion in an initial contact hole in a method for manufacturing a bit line structure according to an exemplary embodiment.
  • Fig. 6 is a flow chart of forming a contact portion in an initial contact hole in a manufacturing method of a bit line structure according to an exemplary embodiment.
  • Fig. 7 is a flow chart of depositing an initial stacked structure in a method for manufacturing a bit line structure according to an exemplary embodiment.
  • Fig. 8 is a flow chart of a manufacturing method of a bit line structure according to an exemplary embodiment.
  • Fig. 9 is a flow chart of etching an initial stacked structure, a third initial dielectric layer and a second initial dielectric unit in a manufacturing method of a bit line structure according to an exemplary embodiment.
  • Fig. 10-a is a schematic cross-sectional view of a substrate along a direction parallel to WL according to an exemplary embodiment.
  • Fig. 10-b is a schematic cross-sectional view of the substrate along the BL direction according to an exemplary embodiment.
  • Fig. 11-a is a schematic cross-sectional view showing the formation of a photoresist mask layer in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 11-b is a schematic cross-sectional view showing the formation of a photoresist mask layer along the BL direction according to an exemplary embodiment.
  • Fig. 12-a is a schematic cross-sectional view of forming an initial contact hole in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 12-b is a schematic cross-sectional view along the BL direction of forming an initial contact hole in a substrate according to an exemplary embodiment.
  • Fig. 13-a is a schematic cross-sectional view of depositing a second initial dielectric layer in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 13-b is a schematic cross-sectional view of depositing a second initial dielectric layer along the BL direction according to an exemplary embodiment.
  • Fig. 14-a is a schematic cross-sectional view showing the formation of the second initial dielectric unit in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 14-b is a schematic cross-sectional view showing the formation of the second initial dielectric unit along the BL direction according to an exemplary embodiment.
  • Fig. 15-a is a schematic cross-sectional view of depositing a contact dielectric layer in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 15-b is a schematic cross-sectional view of a deposited contact dielectric layer along the BL direction according to an exemplary embodiment.
  • Fig. 16-a is a schematic cross-sectional view of forming a contact portion in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 16-b is a schematic cross-sectional view of forming a contact portion along the BL direction according to an exemplary embodiment.
  • Fig. 17-a is a schematic cross-sectional view showing the formation of the first dielectric layer along the direction parallel to WL according to an exemplary embodiment.
  • Fig. 17-b is a schematic cross-sectional view showing the formation of the first dielectric layer along the BL direction according to an exemplary embodiment.
  • Fig. 18-a is a schematic cross-sectional view of forming a third initial dielectric layer in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 18-b is a schematic cross-sectional view showing the formation of the third initial dielectric layer along the BL direction according to an exemplary embodiment.
  • Fig. 19-a is a schematic cross-sectional view showing the formation of an initial conductive layer in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 19-b is a schematic cross-sectional view showing the formation of an initial conductive layer along the BL direction according to an exemplary embodiment.
  • Fig. 20-a is a schematic cross-sectional view showing the formation of an initial isolation layer in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 20-b is a schematic cross-sectional view showing the formation of an initial isolation layer along the BL direction according to an exemplary embodiment.
  • Fig. 21-a is a schematic cross-sectional view of forming a mask layer in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 21-b is a schematic cross-sectional view of forming a mask layer along the BL direction according to an exemplary embodiment.
  • Fig. 22-a is a schematic cross-sectional view of forming a stacked structure in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 22-b is a schematic cross-sectional view of forming a stacked structure along the BL direction according to an exemplary embodiment.
  • Fig. 23-a is a schematic cross-sectional view of depositing a fourth dielectric layer in a direction parallel to WL according to an exemplary embodiment.
  • Fig. 23-b is a schematic cross-sectional view of depositing a fourth dielectric layer along the BL direction according to an exemplary embodiment.
  • Fig. 24 is a schematic cross-sectional view of a bit line structure in a direction parallel to WL' according to an exemplary comparative example.
  • Fig. 25 is a schematic cross-sectional view of a bit line structure along the BL' direction according to an exemplary comparative example.
  • Fig. 26 is a projection view of a contact portion of a bit line structure in a substrate according to an exemplary comparative example.
  • Photoresist mask layer 11. First pattern; 110. Substrate; 101. Initial contact hole; 102. Contact hole; 111. Active region; 120. First initial dielectric layer; 121. First dielectric layer; 130, second initial dielectric unit; 131, second initial dielectric layer; 140, third initial dielectric layer; 150, contact dielectric layer; 160, initial conductive layer; 170, initial isolation layer; 180, mask layer; 190, the fourth dielectric layer; 200, the bit line structure; 210, the contact part; 211, the first part; 212, the second part; 220, the barrier layer; 221, the extension part; 2211, the outer side wall of the first part; Part of the outer wall; 222, the main body; 230, the conductive layer; 240, the isolation layer; 300, the insulating structure; 310, the insulating part; 400, the word line; 500, the initial stacked structure; 600, the stacked structure;
  • the contact portion of the bit line structure is connected to the capacitor of the transistor through the conductive layer, wherein the resistance of the contact portion has the greatest influence on the conductivity of the bit line.
  • a barrier metal layer of metal or metal compound with high refractory property such as titanium nitride is provided on the top surface of the contact part to reduce the resistance thereof.
  • FIG. 24 shows a schematic cross-sectional view of the bit line structure in a direction parallel to the word line (that is, the WL' direction in FIG. 26 ).
  • FIG. 25 shows a schematic cross-sectional view of the bit line structure in the direction of the bit line structure (that is, the BL' direction in FIG. 26 ).
  • Fig. 26 shows a projected view of the contact portion 210' of the bit line structure on the substrate 110'.
  • the bit line structure 200' in the related art is disposed in the substrate 110', the bit line structure includes a contact portion 210', a barrier metal layer 220', a conductive layer 230' and an isolation layer 240', and the contact portion 210' is disposed on the substrate In 110', the bottom of the contact part 210' is connected to the substrate 110', the top surface of the contact part 210' is flush with the insulating layer 120' on the substrate 110', and the barrier metal layer 220' covers the top of the contact part 210'.
  • the conductive layer 230' is located on the substrate 110' and covers the barrier metal layer 220', and the isolation layer 240' covers the conductive layer 230'.
  • the bit line structure 200' covers the insulating structure 300'.
  • the top surface of the contact part 210' is electrically connected to the conductive layer 230' through the barrier metal layer 220', and the contact area between the contact part 210' and the conductive layer 230' is the top surface area of the contact part 210'.
  • the sidewall of the contact part 210' is easily oxidized, which increases the resistance of the contact part 210'.
  • FIGS. 1-3 An exemplary embodiment of the present disclosure, as shown in FIGS. 1-3 , provides a bit line structure disposed on a substrate 110.
  • FIG. 1 shows that the bit line structure of this embodiment is parallel to the WL direction in FIG. 3 (i.e. the extending direction of the word line);
  • FIG. 2 shows a schematic cross-sectional view of the bit line structure in FIG. 3 in the BL direction (i.e. the extending direction of the bit line structure);
  • FIG. 3 shows the present embodiment A projected view of the contact portion 210 of the bit line structure on the substrate 110 .
  • the bit line structure 200 includes: a contact portion 210 whose bottom surface is connected to the substrate 110 , a barrier layer 220 covering part of the contact portion 210 , and a conductive layer 230 covering part of the barrier layer 220 .
  • the barrier layer 220 includes an extension portion 221 covering the top surface and the outer wall surface of the contact portion 210 .
  • the substrate 110 includes active regions 111 arranged in an array, and the bottom surface of the contact portion 210 is in contact with the active regions 111 in the substrate.
  • the substrate 110 is a semiconductor substrate including a silicon-containing substance, for example, the semiconductor substrate may be a silicon substrate, a silicon germanium substrate, or an SOI (silicon on insulator, silicon on insulator) substrate.
  • the contact part 210 includes polysilicon.
  • the barrier layer 220 can be a single-layer or stacked structure, and the barrier layer 220 includes one or more of conductive metal, conductive metal nitride, and conductive alloy.
  • the conductive metal can be titanium (Titanium), tantalum (tantalum) , Tungsten (Tungsten).
  • the conductive layer 230 can be a single-layer or laminated structure, and the conductive layer 230 includes one or more of conductive metal, conductive metal nitride, and conductive alloy.
  • the conductive metal can be titanium (Titanium), tantalum (tantalum) , Tungsten (Tungsten).
  • both the top surface and the outer wall surface of the contact portion 210 are covered with a barrier layer 220 , so as to avoid the occurrence of a barrier layer 220 on the top surface of the contact portion 210 during the bit line manufacturing process.
  • the surface and the outer wall surface are oxidized, thereby increasing the problem of contact resistance. Adopting the bit line structure in this embodiment reduces the contact resistance of the contact portion 210 and improves the electrical performance of the bit line structure.
  • the contact part 210 includes a first portion 211 and a second portion 212 , the first portion 211 is located inside the substrate 110 , and the second portion 212 is located above the substrate 110 .
  • the barrier layer 220 further includes a main body portion 222 , the second portion 212 of the contact portion 210 penetrates the main body portion 222 and extends into the conductive layer 230 , and the conductive layer 230 covers the main body portion 222 and part of the extension portion 221 of the barrier layer 220 .
  • the bit line structure is improved, and the contact part 210 is set such that the first part 211 is buried in the substrate 110, the second part 212 of the contact part 210 extends to the outside of the substrate 110 and extends into the conductive layer 230, and the contact part 210
  • the contact area of the contact portion 210 with the conductive layer 230 is the sum of the area of the top wall of the contact portion 210 and the area of the side wall of the second portion 212 of the contact portion 210 extending into the conductive layer 230, increasing the contact area of the contact portion 210 with the conductive layer 230 .
  • the contact resistance between the contact portion 210 and the conductive layer 230 is reduced, the electrical connection performance between the contact portion 210 of the bit line and the conductive layer 230 is higher, and the current conduction Faster pass speed can improve the electrical performance of the device.
  • bit line structure of this embodiment is the same as the above embodiment, the difference between this embodiment and the above embodiment is that, as shown in Figures 1 and 2, the main body part 222 Covering the first dielectric layer 121 above the substrate 110 , the second portion 112 of the contact portion 210 penetrates through the first dielectric layer 121 .
  • the material of the first dielectric layer 121 may include materials with good insulating properties such as silicon nitride or silicon oxynitride.
  • the first dielectric layer 121 covers the surface of the substrate 110 and insulates and isolates structures inside the substrate 110 .
  • bit line structure of this embodiment is the same as the above-mentioned embodiment, the difference between this embodiment and the above-mentioned embodiment is that, as shown in Figures 1 and 2, along the extension In the circumferential direction of 221 , the outer wall 2211 of the first part of the extension part 221 is in contact with the substrate 110 , and the outer wall 2212 of the second part of the extension part 221 is provided with the insulating part 310 .
  • the first part of the outer wall 2211 of the extension part 221 covers the extension part 221 in the first circumferential direction of the contact part 210
  • the second part of the outer wall 2212 of the extension part 222 covers the contact part 210.
  • the second direction is the extending direction of the bit line structure 200 (ie, the BL direction in FIG. 3 ).
  • the outer wall 2212 of the second part where the insulating part 310 covers the extension part 221 plays a good role in protection and protection for the contact part 210 in the extension part 221 .
  • the insulating part 310 is integrated with the first dielectric layer 121 on the surface of the substrate, so as to better protect the outer wall 2212 of the second part of the extension part 221 .
  • most of the content of the bit line structure of this embodiment is the same as that of the above-mentioned embodiment, wherein, as shown in FIG. There are a plurality of word lines 400 , and the contact portion 210 is disposed between adjacent word lines 400 .
  • the word line 400 is a buried word line, the word line 400 is embedded in the substrate 110, the word line 400 intersects the active region 111, and the top surface of the word line 400 is not higher than the substrate 110. surface.
  • the active regions 111 in the substrate 110 are arranged in an array, and a plurality of word lines 400 in the substrate 110 are also arranged in parallel in an array, and each word line 400 intersects at least one active region 111 .
  • the contact portion 210 is disposed in the substrate 110 between adjacent word lines 400 , and the bottom surface of the contact portion 210 is in contact with the active region 111 , making full use of the limited space of the substrate 110 .
  • the projection of the extension portion 221 on the substrate 110 is a square shape, the plane parallel to the word line 400 and perpendicular to the substrate 110 is taken as the first section, and the second part of the outer wall 2212 of the extension portion 221 perpendicular to the first section.
  • the second part of the outer wall 2212 of the extension 221 is perpendicular to the first section, and the direction of the second part of the outer wall 2212 of the extension 221 is the extending direction of the bit line structure 200 (that is, the direction shown in FIG. 3 BL direction), the extending direction of the bit line 200 (ie, the BL direction shown in FIG. 3 ) is perpendicular to the extending direction of the word line 400 (ie, the WL direction shown in FIG. 3 ).
  • the projection of the extension part 221 on the substrate 110 is square, that is, the first direction where the outer wall 2211 of the first part of the extension part 221 is located is perpendicular to the second direction.
  • the first direction is the direction shown in FIG. 3 WL direction.
  • the limited space of the substrate 110 is fully utilized, and more bit line structures 200 and word lines 400 are provided.
  • most of the content of the bit line structure 200 of this embodiment is the same as that of the above embodiment, the difference between this embodiment and the above embodiment is that, as shown in Figures 1 and 2, the extension The thickness of the first part of the outer wall 2211 of the extension part 221 is greater than the thickness of the second part of the outer wall 2212 of the extension part 221 .
  • the projection of the extension portion 221 on the substrate 110 is in a square shape, and the second direction where the second part of the outer wall 2212 of the extension portion 221 is located is the extension direction of the bit line structure 200 (ie, BL shown in FIG. 3 ). direction), the first direction in which the outer wall 2211 of the first portion of the extension portion 221 is located is parallel to the extending direction of the word line 400 (ie, the WL direction shown in FIG. 3 ).
  • the linear shape of the bit line structure 200 is maintained by reducing the thickness of the second portion of the outer wall 2212 of the extension portion 221 .
  • the bit line structure 200 of this embodiment is disposed in a substrate 110 covered with a first dielectric layer 121, and an array is disposed in the substrate 110.
  • active region 111 the bit line structure 200 includes: a contact portion 210 whose bottom surface is in contact with the active region 111, a barrier layer 220 covering part of the contact portion 210, a conductive layer 230 covering part of the barrier layer 220, and a top layer of the conductive layer 230.
  • the isolation layer 240 on the surface.
  • the material of the isolation layer 240 may include materials with good insulation properties such as silicon nitride or silicon oxynitride, and the isolation layer 240 covers the conductive layer 230 to protect the bit line structure 200 .
  • the contact portion 210 includes a first portion 211 embedded in the substrate 110 and a second portion 212 protruding from the substrate 110 .
  • the barrier layer 220 includes an extension portion 221 covering the side wall surface and the top surface of the contact portion 210, and a main body portion 222 covering the first dielectric layer 121, and the second portion 212 of the contact portion 210 extends through the main body portion 222 into the conductive layer.
  • the extension 221 covering the side wall of the first part 211 of the contact part 210 is also buried in the substrate 110, the extension 221 covering the side wall of the second part 212 of the contact part 210 and the second part of the contact part 210 Portions 212 protrude together into conductive layer 230 .
  • the conductive layer 230 covers the main body portion 222 of the barrier layer 220 and the surface of the extension portion 221 protruding into the conductive layer 230 .
  • the outside of the bit line structure 200 is covered with an insulating structure 300 , and the insulating structure 300 covers the sidewalls on both sides of the bit line structure 200 above the substrate 110 , the top surface of the isolation layer 240 , and the top surface of the isolation layer 240 located in the substrate 110 The second portion of the outer side wall 2212 of the contact portion.
  • the contact area between the contact portion 210 and the conductive layer 230 is increased, the contact resistance between the contact portion 210 and the conductive layer 230 is reduced, and the electrical connection efficiency between the contact portion 210 and the conductive layer 230 is higher.
  • the current conduction speed of the bit line structure is faster, which improves the electrical performance of the device.
  • the bit line structure in this embodiment is further provided with an isolation layer 240 and an insulating structure 300 to protect the bit line structure, so that the bit line structure is stronger and more stable.
  • a semiconductor structure is provided, and the semiconductor structure includes the bit line structure 200 in the above-mentioned embodiments of the present disclosure.
  • the semiconductor structure according to an embodiment of the present disclosure may be included in a memory cell and a memory cell array, and a read operation or a write operation is performed through the bit line structure 200 in the above-described embodiment of the present disclosure.
  • the contact resistance of the contact part of the bit line structure is small, the current conduction speed is fast, the speed of reading and writing data in the semiconductor structure is faster, and the electrical performance and storage performance of the semiconductor structure are improved. .
  • the memory cell and the memory cell array may be included in a memory device, and the memory device may be used in a Dynamic Random Access Memory (DRAM).
  • DRAM Dynamic Random Access Memory
  • SRAM static random-access memory
  • flash memory flash EPROM
  • ferroelectric random-access memory FeRAM
  • magnetic random-access memory Magnetic Random-Access Memory, MRAM
  • phase change random-access memory Phase change Random-Access Memory, PRAM
  • FIG. 4 shows a flow chart of a method for manufacturing a bit line structure according to an exemplary embodiment of the present disclosure.
  • 10-a to FIG. 23-b are schematic diagrams of various stages of the manufacturing method of the bit line structure. The manufacturing method of the bit line structure will be introduced below with reference to FIG. 10-a to FIG. 23-b.
  • a manufacturing method of a bit line structure provided by an exemplary embodiment of the present disclosure includes the following steps:
  • Step S110 providing a base, the base includes a substrate and a first initial dielectric layer covering the substrate.
  • Fig. 10-a is a schematic cross-sectional view of the substrate provided by this embodiment in the direction parallel to WL (see Fig. 3)
  • Fig. 10-b is a schematic cross-sectional view of the substrate provided by this embodiment in the BL direction (refer to Fig. 3).
  • the substrate 110 is provided first, and then the first initial dielectric layer 120 is deposited on the substrate 110, and the first initial dielectric layer 120 covers the substrate 110 The top surface of the substrate 100 is formed.
  • the substrate 110 is a semiconductor substrate including a silicon-containing substance, for example, the semiconductor substrate may be a silicon substrate, a silicon germanium substrate, or an SOI (silicon on insulator, silicon on insulator) substrate.
  • the substrate 110 includes active regions 111 arranged in an array (refer to FIG. 3 ).
  • a plurality of word lines 400 (refer to Figure 3) arranged in parallel are also arranged in the substrate 100, and the word lines 400 are buried word lines, which are embedded in the substrate Bottom 100 middle.
  • the word lines 400 extend along a first direction (refer to the WL direction in FIG. 3 ), and each word line 400 intersects with the active region 111 at a predetermined angle, but is not perpendicular to each other (refer to FIG. 3 ).
  • the material of the first initial dielectric layer 120 includes materials with good insulating properties such as silicon nitride or silicon oxynitride. In this embodiment, the material of the first initial dielectric layer 120 is silicon nitride.
  • Step S120 forming an initial contact hole in the substrate, the bottom wall of the initial contact hole exposes the substrate, and the initial contact hole penetrates the first initial dielectric layer.
  • Figure 11-a is a schematic cross-sectional view of a photoresist mask layer formed in this embodiment parallel to the WL direction (see Figure 3)
  • Figure 11-b is a photoresist mask layer formed in a BL direction in this embodiment (see Figure 3).
  • Figure 3) for a schematic cross-sectional view.
  • Figure 12-a is a schematic cross-sectional view of forming an initial contact hole in this embodiment parallel to the WL direction (refer to Figure 3)
  • Figure 12-b is a schematic view of forming an initial contact hole in a BL direction (refer to Figure 3) in this embodiment .
  • a photoresist mask layer 10 is formed on the first initial dielectric layer 120, and the photoresist mask layer 10 defines There is a first pattern 11, the projection of the first pattern 11 on the substrate 100 is located between two adjacent word lines 400, and the projection of the first pattern 11 on the substrate 100 and the active region 111 (refer to FIG. 3 ) on the substrate 100 have overlapping regions. According to the first pattern 11 , the first initial dielectric layer 120 and part of the substrate 110 are sequentially removed to expose the active region 111 and form the initial contact hole 101 .
  • Step S130 forming a contact portion and a second initial dielectric unit covering the outer sidewall of the contact portion in the initial contact hole, the bottom surface of the contact portion is connected to the substrate, and the side wall of the second initial dielectric unit is connected to the substrate and the first initial dielectric unit Layers are connected.
  • Figure 14-a is a schematic cross-sectional view of forming the second initial dielectric unit in the direction parallel to WL (refer to Figure 3) in this embodiment
  • Figure 14-b is a schematic cross-sectional view of forming the second initial dielectric unit in the BL direction in this embodiment (refer to Figure 3 ) schematic diagram.
  • a second initial dielectric unit 130 is formed in the initial contact hole 101, and the second initial dielectric unit 130 covers the sidewall of the initial contact hole 101.
  • Fig. 16-a is a schematic diagram of forming the contact portion in the second direction, that is, parallel to the WL direction (refer to Fig. 3) shown in Fig. 3 in this embodiment
  • Fig. 16-b is a schematic diagram of forming the contact portion in the BL direction in this embodiment (Refer to Figure 3) schematic diagram.
  • the second initial dielectric unit 130 is filled to form a contact portion 210, the bottom surface of the contact portion 210 is in contact with the substrate 110, the second initial dielectric unit, the top surface of the contact portion 210 It is flush with the top surface of the first initial dielectric layer 120 , and the outer sidewall of the contact portion 210 is covered by the second initial dielectric unit 130 .
  • the second initial dielectric unit 130 can be deposited by atomic layer deposition (Atomic Layer Deposition, ALD), and the material of the second initial dielectric unit 130 includes one or more than two kinds of conductive metal, conductive metal nitride, and conductive alloy.
  • the conductive metal may be titanium (Titanium), tantalum (tantalum), or tungsten (Tungsten).
  • the material of the second initial dielectric unit 130 is titanium nitride.
  • the contact portion 210 may be deposited by an atomic layer deposition process (Atomic Layer Deposition, ALD), and the material of the contact portion 210 may be polysilicon.
  • ALD atomic layer deposition
  • Step S140 Etching part of the first initial dielectric layer to form a first dielectric layer, the first dielectric layer exposing part of the sidewall of the second initial dielectric unit.
  • Figure 17-a is a schematic cross-sectional view of the formation of the first dielectric layer in this embodiment parallel to the WL direction (refer to Figure 3)
  • Figure 17-b is a schematic cross-sectional view of the formation of the first dielectric layer in the BL direction in this embodiment (refer to Figure 3) cross-sectional schematic diagram.
  • the first initial dielectric layer 120 with a predetermined thickness can be etched back and removed by a dry etching process or a wet etching process , forming the first dielectric layer 121 .
  • the thickness of the first dielectric layer 121 is reduced by a predetermined thickness compared with the first initial dielectric layer 120, and the top of the contact portion 210 that is originally flush with the top surface of the first initial dielectric layer 120 forms a top that protrudes from the top surface of the first dielectric layer 121 by a predetermined predetermined thickness.
  • the height of the protrusion, the second initial dielectric unit 130 of the side wall of the protrusion is exposed.
  • Step S150 Depositing a third initial dielectric layer and an initial stacked structure, the third initial dielectric layer covers the first dielectric layer and the sidewalls of the second initial dielectric unit, and the top surface of the contact portion and the top surface of the second initial dielectric unit, The third initial dielectric layer is integrated with the second initial dielectric unit, and the initial lamination structure covers the third initial dielectric layer.
  • Figure 18-a is a schematic cross-sectional view of the formation of the third initial dielectric layer in this embodiment parallel to the WL direction (refer to Figure 3)
  • Figure 18-b is a schematic cross-sectional view of the formation of the third initial dielectric layer in the BL direction in this embodiment (refer to Figure 3).
  • the third initial dielectric layer 140 can be deposited by atomic layer deposition (Atomic Layer Deposition, ALD), the material of the third initial dielectric layer 140 includes conductive metal, conductive metal nitride , one or more than two kinds of conductive alloys, for example, the conductive metal can be titanium (Titanium), tantalum (tantalum), tungsten (Tungsten).
  • ALD atomic layer deposition
  • the material of the third initial dielectric layer 140 may be the same as or different from that of the second initial dielectric unit.
  • the material of the third initial dielectric layer 140 and the material of the second initial dielectric unit 130 are titanium nitride.
  • the third initial dielectric layer 140 covers the protrusion formed by the contact portion 210 protruding from the first dielectric layer 121, and is connected with the second initial dielectric unit 130, so that all the side walls and the top surface of the contact portion 210 are covered. cover.
  • Figure 19-a is a schematic cross-sectional view of the initial conductive layer formed in this embodiment parallel to the WL direction (refer to Figure 3), and Figure 19-b is a cross-sectional view of the initial conductive layer formed in the BL direction (refer to Figure 3) in this embodiment schematic diagram.
  • the thickness of the third initial dielectric layer 140 is smaller than the height of the convex part of the contact part 210, and the third initial dielectric layer After 140, the top surface of the convex portion is still higher than the top surface of the third initial dielectric layer 140 formed on the first dielectric layer 121.
  • the top of the contact portion 210 and the third The initial dielectric layer 140 extends into the initial stack structure 500 , and the sum of the area of the top surface of the contact portion 210 and the sidewall extending into the initial stack structure 500 is the contact area of the contact portion 210 and the initial stack structure 500 .
  • Step S160 Etching the initial stacked structure, the third initial dielectric layer and the second initial dielectric unit, the retained initial stacked structure forms a stacked structure, and the stacked structure includes a conductive layer; the retained second initial dielectric unit and the third initial dielectric unit The layers are joined together to form a barrier layer, and the retained second initial dielectric unit and the third initial dielectric layer covering the contact portion form an extension of the barrier layer.
  • the material of the conductive layer 230 includes one or more of conductive metal, conductive metal nitride, and conductive alloy.
  • the conductive metal can be titanium (Titanium), tantalum (tantalum), or tungsten (Tungsten).
  • the material of the conductive layer 230 is tungsten.
  • Figure 22-a is a schematic cross-sectional view of the stacked structure formed in this embodiment parallel to the WL direction (see Figure 3), and Figure 22-b is a cross-sectional view of the stacked structure formed in this embodiment in the BL direction (see Figure 3) schematic diagram.
  • the stacked structure 600 is a linear structure extending along the second direction (the extension direction of the bit line structure 200, that is, the BL direction shown in FIG. One direction (ie, the WL direction shown in FIG. 3 ) is vertical.
  • any sections of the stacked structure 600 in the first direction are equal.
  • the width of the laminated structure 600 is greater than the width of the contact portion 210 and less than or equal to the width of the initial contact hole 101, so as to ensure that both sides of the contact portion 210 are covered.
  • Step S170 forming a fourth dielectric layer, the fourth dielectric layer covers the stacked structure and part of the extension.
  • Figure 23-a is a schematic cross-sectional view of depositing the fourth dielectric layer in this embodiment parallel to the WL direction (refer to Figure 3)
  • Figure 23-b is a schematic cross-sectional view of depositing the fourth dielectric layer in the BL direction in this embodiment (refer to Figure 3) cross-sectional schematic diagram.
  • the fourth dielectric layer 190 can be deposited by atomic layer deposition (Atomic Layer Deposition, ALD).
  • ALD atomic layer deposition
  • the material of the fourth dielectric layer 190 includes materials with good insulating properties such as silicon nitride or silicon oxynitride. In this embodiment, the material of the fourth dielectric layer 190 is silicon nitride.
  • the second initial dielectric unit is covered on the side wall of the initial contact hole, and then the contact portion is formed.
  • the outer wall of the formed contact portion is covered by the second initial dielectric unit, and then the third initial dielectric unit covering the top surface of the contact portion is formed.
  • the initial dielectric layer is used to cover both the outer sidewall and the top surface of the contact part, so as to prevent the contact resistance from increasing due to oxidation of the outer sidewall and top surface of the contact part in contact with air during the bit line process.
  • the first initial dielectric layer is etched back to become the first dielectric layer, the top of the contact portion protrudes from the first dielectric layer, so that the top of the contact portion extends into the conductive layer of the stacked structure, and the contact area of the contact portion and the conductive layer is the sum of the area of the top wall of the contact part and the side wall area of the contact part extending into the conductive layer.
  • the manufacturing method of this embodiment increases the contact area between the contact part and the conductive layer by preventing the oxidation resistance of the contact part from increasing during the manufacturing process, reducing The contact resistance between the contact portion and the conductive layer is small, the electrical connection efficiency between the contact portion of the bit line structure and the conductive layer is higher, the conduction speed of the current is faster, and the electrical performance of the device can be improved.
  • this embodiment is an illustration of the implementation of step S120 in the above embodiment.
  • FIG. 5 shows a flow chart of forming a second initial dielectric unit covering the outer sidewall of the contact portion in the initial contact hole in step S120 in the manufacturing method of the bit line structure provided by this embodiment.
  • Forming a second initial dielectric unit covering the outer sidewall of the contact portion in the initial contact hole includes the following steps:
  • S121 depositing a second initial dielectric layer, where the second initial dielectric layer covers the first initial dielectric layer and the sidewalls and bottom walls of the initial contact holes.
  • Figure 13-a is a schematic cross-sectional view of depositing a second initial dielectric layer in this embodiment in a direction parallel to WL (refer to Figure 3)
  • Figure 13-b is a schematic cross-sectional view of depositing a second initial dielectric layer in a direction BL in this embodiment (refer to Figure 3 ).
  • the second initial dielectric layer 131 can be deposited by atomic layer deposition (Atomic Layer Deposition, ALD), in this embodiment , the material of the second initial dielectric layer 131 is titanium nitride.
  • ALD atomic layer deposition
  • the second initial dielectric layer covering the top surface of the first initial dielectric layer 120 is removed by dry or wet etching 131 , removing the second initial dielectric layer 131 covering the bottom wall of the initial contact hole 101 until the substrate 110 is exposed, and retaining the second initial dielectric layer 131 covering the sidewall of the initial contact hole 101 as the second initial dielectric unit 130 .
  • the exposed bottom wall of the second initial dielectric unit 130 and the initial contact hole 101 encloses the contact hole 102 .
  • the side wall surface of the contact hole 102 formed in this embodiment is surrounded by the second initial dielectric unit 130, so that the bottom surface of the formed contact portion 210 is in contact with the substrate 101, and the side wall of the contact portion 210 is in contact with the second initial dielectric unit. 130 connection, to prevent the sidewall of the contact portion 210 from being directly exposed to the air, to prevent the sidewall of the contact portion 210 from being oxidized by air during the manufacturing process of the bit line, and to avoid the resistance increase caused by the oxidation of the contact portion 210 .
  • this embodiment is an illustration of the implementation of step S130 in the foregoing embodiment.
  • FIG. 6 shows a flow chart of forming a contact portion in an initial contact hole in step S130 in the manufacturing method of the bit line structure according to this embodiment.
  • Forming a contact portion in an initial contact hole includes the following steps:
  • Figure 15-a is a schematic cross-sectional view of the medium-deposited contact dielectric layer shown in this embodiment parallel to the WL direction (refer to Figure 3)
  • Figure 15-b is a schematic cross-sectional view of the medium-deposited contact medium layer shown in this embodiment in the BL direction (refer to Figure 3).
  • Figure 3) schematic cross-sectional view.
  • an atomic layer deposition process Atomic Layer Deposition, ALD
  • ALD atomic layer deposition
  • the contact dielectric layer 150 fills the contact hole 102 and cover the top surface of the first initial dielectric layer 120.
  • the material of the contact dielectric layer 150 is titanium nitride.
  • the contact dielectric layer 150 on the first initial dielectric layer 120 is removed by dry or wet etching until the exposed The top surface of the first initial dielectric layer 120 forms a contact portion 210 , and the top surface of the contact portion 210 is flush with the top surface of the first initial dielectric layer 120 .
  • the contact portion is formed by removing the contact dielectric layer on the top surface of the first initial dielectric layer. During this process, the top contact dielectric layer oxidized by air can be removed, and the formed contact portion has lower resistance and better conductivity. good.
  • this embodiment is an illustration of the implementation of step S150 in the above embodiment.
  • FIG. 7 shows a flow chart of depositing an initial stacked structure in step S150 in the manufacturing method of the bit line structure according to this embodiment.
  • Depositing an initial stack structure includes the following steps:
  • an initial conductive layer 160 can be deposited by atomic layer deposition (Atomic Layer Deposition, ALD), and the initial conductive layer 160 covers the first The top surface of the initial dielectric layer 120 , the sidewall of the second initial dielectric unit 130 , the top surface of the contact portion 210 and the top surface of the third initial dielectric layer 140 , for example, the material of the initial conductive layer 160 is tungsten.
  • ALD atomic layer deposition
  • Figure 20-a is a schematic cross-sectional view of the initial isolation layer formed in this embodiment parallel to the WL direction (see Figure 3), and Figure 20-b is a cross-sectional view of the initial isolation layer in the BL direction (refer to Figure 3) in this embodiment schematic diagram.
  • the initial isolation layer 170 can be deposited by atomic layer deposition (Atomic Layer Deposition, ALD), and the initial isolation layer 170 covers the initial conductive layer 160, in this embodiment, the material of the initial isolation layer 170 is titanium nitride.
  • ALD atomic layer deposition
  • the initial stacked structure 500 includes a contact portion 210 above the substrate, a second initial dielectric unit 130 , a third dielectric layer 140 , an initial conductive layer 160 and an initial isolation layer 170 .
  • the deposited initial stacked structure includes an initial conductive layer and an initial isolation layer, and the manufactured bit line structure is stronger and lower in temperature.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a bit line structure, as shown in FIG. 8 , which shows a flowchart of a method for manufacturing a bit line structure according to an exemplary embodiment of the present disclosure.
  • Step S210-step S250 in this embodiment is the same as step S110-step S150 in the above-mentioned embodiment
  • step S270 in this embodiment is the same as step S160 in the above-mentioned embodiment
  • step S280 in this embodiment is the same as step S170 in the above-mentioned embodiment same.
  • the difference between this embodiment and the above-mentioned embodiments is that, in the manufacturing method of the bit line structure of this embodiment, after the third initial dielectric layer and the initial stacked structure are deposited in step S250, the initial layer is etched in step S270. Before the stacked structure, the third initial dielectric layer and the second initial dielectric unit, a step S260 is further included: forming a mask layer on the initial isolation layer.
  • Figure 21-a is a schematic cross-sectional view of the mask layer formed in this embodiment parallel to the WL direction (see Figure 3)
  • Figure 21-b is a cross-sectional view of the mask layer formed in the BL direction (see Figure 3) in this embodiment schematic diagram.
  • the mask layer 180 is correspondingly arranged on the initial isolation layer 170 above the contact portion 210, and the mask layer 180 is along the second direction (the extension direction of the bit line structure 200, that is, the BL direction shown in FIG. 3 ), and in the first direction (that is, the WL direction shown in FIG.
  • the width of the mask layer 180 Greater than the width of the contact portion 210 , less than or equal to the width of the initial contact hole 101 , the projection of the contact portion 210 on the substrate 110 is located within the projection of the mask layer 180 on the substrate 100 .
  • the width of the mask layer 180 is smaller than the width of the initial contact hole 101, and the two side edges of the projection of the initial contact hole 101 on the substrate 100 are two sides of the projection formed by the mask layer 180 on the substrate 100. side out.
  • the width of the mask layer is limited to a range larger than the width of the contact portion and smaller than the width of the initial contact hole, and both sides of the initial contact hole are reserved beyond the mask layer, ensuring that according to this embodiment
  • the bit line structure obtained by etching the mask layer has a good linear shape, and can expose part of the side wall surface of the extension part of the barrier layer, so that the subsequently deposited fourth dielectric layer can cover the exposed part of the extension part. On the side wall surface, the protection of the contact part is strengthened.
  • this embodiment is an illustration of the implementation of step S270 in the above embodiment.
  • FIG. 9 shows a flow chart of etching the initial stacked structure, the third initial dielectric layer and the second initial dielectric unit in step S270 in the manufacturing method of the bit line structure according to this embodiment.
  • Etching the initial stack structure, the third initial dielectric layer and the second initial dielectric unit includes the following steps:
  • the mask layer 180 is disposed on the initial isolation layer 170, and the unmasked layer is removed by dry or wet etching
  • the initial conductive layer 160 is covered by the pattern defined by the film layer 180, and the remaining part of the initial conductive layer 160 forms the conductive layer 230; the pattern defined by the mask layer 180 is transferred to the third initial dielectric layer 140, through dry or wet etching Remove the third initial dielectric layer 140 that is not covered by the pattern defined by the mask layer 180, and the remaining third initial dielectric layer 140 is used as a part of the main body portion 222 and the extension portion 221 of the barrier layer 220; the pattern defined by the mask layer 180 is transferred On the second initial dielectric unit 130, the second initial dielectric unit 130 not covered by the pattern defined by the mask layer 180 is removed by dry or wet etching until the substrate 110 is exposed, and the retained second initial dielectric unit The unit 130 serves as another part of the extension 221 of the barrier layer 220 .
  • step S280 when the width of the formed laminated structure is smaller than the width of the initial contact hole 101, after part of the second initial dielectric unit 130 is removed, the sidewalls on both sides of the initial contact hole 101 are exposed. As shown in FIG. 22-a and FIG. 22-b , a protective space is formed on both sides of the extension portion 221 of the barrier layer 220 .
  • the fourth dielectric layer 190 is subsequently deposited, part of the fourth dielectric layer 190 covers the stacked structure 600 above the substrate 100 (see FIGS. 1 and 2 ), and part of the fourth dielectric layer 190 fills the protective space on both sides of the extension portion 221.
  • the insulating part 310 is formed in the middle, the fourth dielectric layer 190 covering the laminated structure 600 above the substrate 100 and the insulating parts 310 on both sides of the extension part 221 together serve as the insulating structure 300, and the insulating structure 300 is integrated with the first dielectric layer 121, Provide good protection for the bit line structure.
  • the barrier layer covers the top surface and the outer wall of the contact portion, and the barrier layer protects the sidewall of the contact portion from oxidation, thereby reducing the contact resistance of the bit line.

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Abstract

本公开提供一种位线结构、半导体结构及位线结构的制作方法，所述位线结构设置于衬底，所述位线结构包括：接触部，其底面与衬底连接；阻挡层，其包括延伸部，延伸部覆盖接触部的顶面和外侧壁面；导电层，覆盖部分阻挡层。

Description

位线结构、半导体结构及位线结构的制作方法
本公开基于申请号为202110844690.9，申请日为2021年07月26日，申请名称为“位线结构、半导体结构及位线结构的制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种位线结构、半导体结构及位线结构的制作方法。
背景技术
在DRAM(Dynamic Random Access Memory，动态随机存取存储器)器件中，位线(Bitline)和晶体管(Transistor)、电容器(Capacitor)连接，在DRAM的制造过程中，需要沉积多晶硅(polysilicon，简称poly)以形成位线接触(Bit line contact)导电结构，位线的接触电阻影响位线的导电性能，影响器件的电流大小，进而影响器件导通能力。随着集成电路的尺寸微缩，对位线的接触导电结构的要求越来越高。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种位线结构、半导体结构及位线结构的制作方法。
本公开的第一方面提供一种位线结构，所述位线结构设置于衬底，所述位线结构包括：
接触部，其底面与所述衬底连接；
阻挡层，其包括延伸部，所述延伸部覆盖所述接触部的顶面和外侧壁面；
导电层，覆盖部分所述阻挡层。
根据本公开的一些实施例，所述接触部包括第一部分和第二部分，所述第一部分位于所述衬底内部，所述第二部分位于所述衬底的上方；
所述阻挡层还包括主体部，所述接触部的第二部分贯穿所述主体部并延伸至所述导电层内；
所述导电层覆盖所述主体部，以及所述延伸部的部分表面。
根据本公开的一些实施例，所述主体部与所述延伸部连为一体。
根据本公开的一些实施例，所述主体部覆盖所述衬底上方的第一介质层；
所述接触部的第二部分贯穿所述第一介质层。
根据本公开的一些实施例，沿所述延伸部的周向方向，所述延伸部的第一部分外侧壁与所述衬底接触连接，所述延伸部的第二部分外侧壁设置绝缘部。
根据本公开的一些实施例，所述绝缘部与所述第一介质层连为一体。
根据本公开的一些实施例，所述衬底中埋设有平行设置的多条字线，所述接触部设置在相邻的所述字线之间。
根据本公开的一些实施例，所述延伸部在所述衬底上的投影呈方形，以平行于所述字线且垂直于所述衬底的平面为第一截面，所述延伸部的第二部分外侧壁与所述第一截面相互垂直。
根据本公开的一些实施例，所述延伸部的第一部分外侧壁的厚度大于所述延伸部的第二部分外侧壁的厚度。
本公开的第二方面提供一种半导体结构，所述半导体结构包括本公开所述的位线结构。
本公开的第三方面提供一种位线结构的制作方法，所述制作方法包括以下步骤：
提供基底，所述基底包括衬底和覆盖在所述衬底上的第一初始介质层；
在所述基底内形成初始接触孔，所述初始接触孔的底壁暴露所述衬底，所述初始接触孔贯穿所述第一初始介质层；
在所述初始接触孔中形成接触部和覆盖所述接触部的外侧壁的第二初始介质单元，所述接触部的底面与所述衬底相连，所述第二初始介质单元的侧壁与所述衬底和所述第一初始介质层相连；
刻蚀部分所述第一初始介质层，形成第一介质层，所述第一介质层暴露所述第二初始介质单元的部分侧壁；
沉积第三初始介质层和初始层叠结构，所述第三初始介质层覆盖所述第一介质层和所述第二初始介质单元的侧壁，以及所述接触部的顶面和所述第二初始介质单元的顶面，所述第三初始介质层与所述第二初始介质单元连为一体，所述初始层叠结构覆盖所述第三初始介质层；
刻蚀所述初始层叠结构、所述第三初始介质层和所述第二初始介质单元，被保留的初始层叠结构形成层叠结构，所述层叠结构包括导电层；被保留的所述第二初始介质单元和所述第三初始介质层连为一体形成阻挡层，包覆所述接触部的被保留的所述第二初始介质单元和所述第三初始介质层形成所述阻挡层的延伸部；
形成第四介质层，所述第四介质层覆盖所述层叠结构和部分所述延伸部。
根据本公开的一些实施例，所述在所述初始接触孔中形成覆盖所述接触部的外侧壁的第二初始介质单元，包括：
沉积第二初始介质层，所述第二初始介质层覆盖所述第一初始介质层和所述初始接触孔的侧壁和底壁；
刻蚀覆盖在所述第一初始介质层上的所述第二初始介质层，包括所述第一初始介质层，刻蚀覆盖在所述初始接触孔的底壁的所述第二初始介质层，暴露所述衬底，形成所述第二初始介质单元。
根据本公开的一些实施例，在所述初始接触孔中形成接触部，包括：
沉积接触介质层，所述接触介质层覆盖所述第二初始介质单元的内壁面和所述第一初始介质层，以及所述初始接触孔暴露的所述衬底；
去除部分所述接触介质层，保留所述接触介质层在所述初始接触孔中的部分，形成所述接触部，所述接触部的顶面与所述第一初始介质层的顶面平齐。
根据本公开的一些实施例，沉积所述初始层叠结构包括：
沉积初始导电层，所述初始导电层覆盖所述第三初始介质层；
沉积初始隔离层，所述初始隔离层覆盖所述初始导电层。
根据本公开的一些实施例，所述方法还包括：
在所述初始隔离层上形成掩膜层。
根据本公开的一些实施例，所述刻蚀所述初始层叠结构、所述第三初始介质层和所述第二初始介质单元，包括：
刻蚀所述初始隔离层，被保留的与所述掩膜层定义的图形对应的所述初始隔离层形成所述隔离层；
刻蚀所述初始导电层，被保留的与所述图形对应的所处初始导电层形成所述导电层；
刻蚀所述第三初始介质层，被保留的与所述图形对应的所述第三初始介质层的一部分作为所述延伸部的一部分，被保留的与所述图形对应的所述第三初始介质层的另一部分作为所述阻挡层的主体部；
刻蚀所述第二初始介质单元，被保留的与所述图形对应的所述第二初始介质单元作为所述延伸部的另一部分。
根据本公开的一些实施例，所述第四介质层与所述第一介质层连为一体；
位于所述第二初始介质单元与所述衬底之间的部分所述第四介质层形成绝缘部。
本公开实施例所提供的位线结构，阻挡层覆盖接触部的顶面和外侧壁面，阻挡层保护接触部的侧壁不被氧化，减小了位线的接触电阻。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是本公开一个示例性实施例示出的位线结构在平行于WL方向上的截面示意图。
图2是本公开一个示例性实施例示出的位线结构在BL方向上的截面示意图。
图3是根据一示例性实施例示出的一种位线结构的接触部在衬底上的投影图。
图4是根据一示例性实施例示出的一种位线结构的制作方法的流程图。
图5是根据一示例性实施例示出的一种位线结构的制作方法中在初始接触孔中形成覆盖接触部的外侧壁的第二初始介质单元的流程图。
图6是根据一示例性实施例示出的一种位线结构的制作方法中在初始接触孔中形成接触部的流程图。
图7是根据一示例性实施例示出的一种位线结构的制作方法中沉积初始层叠结构的流程图。
图8是根据一示例性实施例示出的一种位线结构的制作方法的流程图。
图9是根据一示例性实施例示出的一种位线结构的制作方法中刻蚀初始层叠结构、第三初始介质层和第二初始介质单元的流程图。
图10-a是根据一示例性实施例示出的基底在平行于WL方向的截面示意图。
图10-b是根据一示例性实施例示出的基底在BL方向的截面示意图。
图11-a是根据一示例性实施例示出的形成光刻胶掩膜层在平行于WL方向的截面示意图。
图11-b是根据一示例性实施例示出的形成光刻胶掩膜层在BL方向的截面示意图。
图12-a是根据一示例性实施例示出的形成初始接触孔在平行于WL方向的截面示意图。
图12-b是根据一示例性实施例示出的在基底内形成初始接触孔在BL方向的截面示意图。
图13-a是根据一示例性实施例示出的沉积第二初始介质层在平行于WL方向的截面示意图。
图13-b是根据一示例性实施例示出的沉积第二初始介质层在BL方向的截面示意图。
图14-a是根据一示例性实施例示出的形成第二初始介质单元在平行于WL方向的截面示意图。
图14-b是根据一示例性实施例示出的形成第二初始介质单元在BL方向的截面示意图。
图15-a是根据一示例性实施例示出的沉积接触介质层在平行于WL方向的截面示意图。
图15-b是根据一示例性实施例示出的沉积接触介质层在BL方向的截面示意图。
图16-a是根据一示例性实施例示出的形成接触部在平行于WL方向的截面示意图。
图16-b是根据一示例性实施例示出的形成接触部在BL方向的截面示意图。
图17-a是根据一示例性实施例示出的形成第一介质层在平行于WL方向的截面示意图。
图17-b是根据一示例性实施例示出的形成第一介质层在BL方向的截面示意图。
图18-a是根据一示例性实施例示出的形成第三初始介质层在平行于WL方向的截面示意图。
图18-b是根据一示例性实施例示出的形成第三初始介质层在BL方向的截面示意图。
图19-a是根据一示例性实施例示出的形成初始导电层在平行于WL方向的截面示意图。
图19-b是根据一示例性实施例示出的形成初始导电层在BL方向的截面示意图。
图20-a是根据一示例性实施例示出的形成初始隔离层在平行于WL方向的截面示意图。
图20-b是根据一示例性实施例示出的形成初始隔离层在BL方向的截面示意图。
图21-a是根据一示例性实施例示出的形成掩膜层在平行于WL方向的截面示意图。
图21-b是根据一示例性实施例示出的形成掩膜层在BL方向的截面示意图。
图22-a是根据一示例性实施例示出的形成层叠结构在平行于WL方向的截面示意图。
图22-b是根据一示例性实施例示出的形成层叠结构在BL方向的截面示意图。
图23-a是根据一示例性实施例示出的沉积第四介质层在平行于WL方向的截面示意图。
图23-b是根据一示例性实施例示出的沉积第四介质层在BL方向的截面示意图。
图24是根据一示例性对比例示出的位线结构在平行于WL’方向上的截面示意图。
图25是根据一示例性对比例示出的位线结构在BL’方向上的截面示意图。
图26是根据一示例性对比例示出的一种位线结构的接触部在衬底中的投影图。
附图标记：
10、光刻胶掩膜层；11、第一图案；110、衬底；101、初始接触孔；102、接触孔；111、有源区；120、第一初始介质层；121、第一介质层；130、第二初始介质单元；131、第二初始介质层；140、第三初始介质层；150、接触介质层；160、初始导电层；170、初始隔离层；180、掩膜层；190、第四介质层；200、位线结构；210、接触部；211、第一部分；212、第二部分；220、阻挡层；221、延伸部；2211、第一部分外侧壁；2212、第二部分外侧壁；222、主体部；230、导电层；240、隔离层；300、绝缘结构；310、绝缘部；400、字线；500、初始层叠结构；600、层叠结构；
110’、120’、绝缘层；200’、位线结构；衬底；210’、接触部；220’、阻挡金属层；230’、导电层；240’、隔离层；300’、绝缘结构。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
位线结构的接触部通过导电层和晶体管电容器连接，其中，接触部的电阻对位线的导电性影响最大。目前，为了减小位线的接触电阻，在接触部顶面还设置有氮化钛等具有高耐熔性的金属或金属化合物的阻挡金属层以减小其电阻。
如图24-26所示，参照图26中示出的方位，如图24示出了位线结构在平行于字线方向(即图26中WL’方向)的截面示意图。图25示出了位线结构在位线结构方向(即图26中BL’方向)的截面示意图。图26示出了位线结构的接触部210’在衬底110’上的投影图。相关技术中的位线结构200’设置在衬底110’中，位线结构包括接触部210’、阻挡金属层220’、导电层230’以及隔离层240’，接触部210’设置在衬底110’中，接触部210’的底部与衬底110’连接、接触部210’的顶面与衬底110’上的绝缘层120’平齐，阻挡金属层220’覆盖接触部210’的顶面，导电层230’位于衬底110’上并覆盖阻挡金属层220’，隔离层240’覆盖导电层230’。位线结构200’外覆盖绝缘结构300’。
接触部210’的顶面通过阻挡金属层220’与导电层230’电连接，接触部210’和导电层230’的接触面积为接触部210’的顶面面积。但是，该位线结构200’在制程过程中，在接触部210’的侧壁面形成绝缘部时，接触部210’的侧壁容易被氧化，增加接触部210’的电阻。
而且，集成电路向高集成度及高密度方向发展，集成电路的尺寸缩小，集成电路中的字线(Wordline)间距缩小，位线的尺寸缩小，接触部的接触面积缩小，位线电阻值可能大幅增加。
本公开示例性的实施例，如图1-3所示，提供了一种位线结构，设置于衬底110，图1示出了本实施例的位线结构平行于图3中WL方向上(即字线的延伸方向)的截面示意图；图2示出了本实施例的位线结构在图3中BL方向(即位线结构的延伸方向)的截面示意图；图3示出了本实施例的位线 结构的接触部210在衬底110上的投影图。
如图1、图2所示，位线结构200包括：底面与衬底110连接的接触部210、覆盖部分接触部210的阻挡层220以及覆盖部分阻挡层220的导电层230。其中，阻挡层220包括覆盖接触部210的顶面和外侧壁面的延伸部221。
如图3所示，衬底110包括阵列形式排布的有源区111，接触部210的底面和衬底中的有源区111接触连接。其中，衬底110为包括含硅物质的半导体衬底，例如，半导体衬底可以为硅衬底、硅锗衬底或SOI(silicon on insulator，绝缘体上硅)衬底。接触部210包括多晶硅。
阻挡层220可以为单层或叠层结构，阻挡层220包括导电金属、导电金属氮化物、导电合金中的一种或二种以上，例如，导电金属可以为钛(Titanium)、钽(tantalum)、钨(Tungsten)。
导电层230可以为单层或叠层结构，导电层230包括导电金属、导电金属氮化物、导电合金中的一种或二种以上，例如，导电金属可以为钛(Titanium)、钽(tantalum)、钨(Tungsten)。
如图1、图2和图3所示，本实施例的位线结构200，在接触部210的顶面和外侧壁面均覆盖阻挡层220，避免出现在位线制程中，接触部210的顶面和外侧壁面被氧化，进而增加接触电阻的问题。采用本实施例中的位线结构降低了接触部210的接触电阻，提高位线结构的电性能。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图1、图2所示，接触部210包括第一部分211和第二部分212，第一部分211位于衬底110内部，第二部分212位于衬底110的上方。阻挡层220还包括主体部222，接触部210的第二部分212贯穿主体部222并延伸至导电层230内，导电层230覆盖阻挡层220的主体部222以及延伸部221的部分表面。
本实施例改进了位线结构，将接触部210设置为第一部分211埋入在衬底110中，接触部210的第二部分212延伸至衬底110外部并延伸到导电层230内，接触部210与导电层230接触的面积为接触部210的顶壁与接触部210延伸到导电层230内的第二部分212的侧壁的面积的总和，增加了接触部210与导电层230的接触面积。
本实施例通过增加了接触部210与导电层230的接触面积，减小接触部210与导电层230的接触电阻，位线的接触部210和导电层230的电连接性能更高，电流的导通速度更快，能够提高器件的电性能。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图1、2所示，主体部222覆盖衬底110上方的第一介质层121，接触部210的第二部分112贯穿第一介质层121。
示例性的，第一介质层121的材料可以包括氮化硅或氮氧化硅等绝缘性能良好的材料。第一介质层121覆盖在衬底110的表面，对衬底110内部的结构进行绝缘和隔离。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图1、2所示，沿延伸部221的周向方向，延伸部221的第一部分外侧壁2211与衬底110接触连接，延伸部221的第二部分外侧壁2212设置绝缘部310。
其中，沿延伸部221的周向方向，延伸部221的第一部分外侧壁2211为覆盖在接触部210周向第一方向的延伸部221，延伸部222的第二部分外侧壁2212为覆盖在接触部210周向第二方向的延伸部221。其中，第二方向为位线结构200的延伸方向(即图3中BL方向)。
设置绝缘部310覆盖延伸部221的第二部分外侧壁2212对延伸部221内的接触部210起到了良好的防护和保护作用。在本实施例中，绝缘部310与衬底表面上的第一介质层121连为一体，以对延伸部221的第二部分外侧壁2212起到更好的保护作用。
根据一个示例性实施例，本实施例的位线结构的大部分内容和上述实施例相同，其中，如图3所 示，实施例的位线结构200，在衬底110中埋设有平行设置的多条字线400，接触部210设置在相邻的字线400之间。
如图3所示，字线400为掩埋字线，字线400埋入式设置在衬底110中，字线400和有源区111相交，字线400的顶面不高于衬底110的表面。在本实施例中，衬底110中的有源区111阵列排布，衬底110内的多条字线400也呈阵列平行排布，每条字线400均与至少一个有源区111相交。
接触部210设置在相邻的字线400之间的衬底110中，接触部210的底面与有源区111接触连接，充分利用了衬底110有限的空间。
在本公开部分实施例中，延伸部221在衬底110上的投影呈方形，以平行于字线400且垂直于衬底110的平面为第一截面，延伸部221的第二部分外侧壁2212与第一截面相互垂直。
本实施例中，延伸部221的第二部分外侧壁2212与第一截面相互垂直，延伸部221的第二部分外侧壁2212的方向为位线结构200的延伸方向(即图3中示出的BL方向)，位线200的延伸方向(即图3中示出的BL方向)和字线400的延伸方向(即图3中示出的WL方向)垂直。
延伸部221在衬底110上的投影呈方形，也即延伸部221的第一部分外侧壁2211所在第一方向和第二方向垂直，在本实施例中，第一方向为图3中示出的WL方向。
本实施例充分的利用衬底110有限的空间，设置更多的位线结构200和字线400。
根据一个示例性实施例，本实施例的位线结构200的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图1、2所述，延伸部221的第一部分外侧壁2211的厚度大于延伸部221的第二部分外侧壁2212的厚度。
根据上述实施例可知，延伸部221在衬底110上的投影呈方形，延伸部221的第二部分外侧壁2212所在第二方向为位线结构200的延伸方向(即图3中示出的BL方向)，延伸部221的第一部分外侧壁2211所在第一方向平行于字线400的延伸方向(即图3中示出的WL方向)。
本实施例通过减薄延伸部221的第二部分外侧壁2212的厚度，保持位线结构200的线型形状。
根据一个示例性实施例，如图1-3所示，本实施例的位线结构200，设置在衬底110中，衬底110上覆盖有第一介质层121，衬底110中设置有阵列式有源区111，位线结构200包括：底面与有源区111接触连接的接触部210、覆盖部分接触部210的阻挡层220、覆盖部分阻挡层220的导电层230以及覆盖导电层230顶面的隔离层240。
隔离层240的材料可以包括氮化硅或氮氧化硅等绝缘性能良好的材料，隔离层240覆盖在导电层230上，起到保护位线结构200的作用。
如图1、图2所示，接触部210包括埋入设置在衬底110中的第一部分211和从衬底110中向外伸出的第二部分212。阻挡层220包括覆盖接触部210的侧壁面和顶面的延伸部221，以及覆盖在第一介质层121上的主体部222，接触部210的第二部分212贯穿主体部222伸入到导电层230中，覆盖在接触部210的第一部分211侧壁的延伸部221也埋入在衬底110中，覆盖在接触部210的第二部分212侧壁的延伸部221和接触部210的第二部分212一起伸入到导电层230中。导电层230覆盖阻挡层220的主体部222以及伸入到导电层230中的延伸部221的表面。
在本实施例中，位线结构200外侧还覆盖有绝缘结构300，绝缘结构300覆盖在位线结构200位于衬底110上方的两侧侧壁、隔离层240的顶面以及位于衬底110中接触部的第二部分外侧壁2212。
本实施例的位线结构200，增加了接触部210与导电层230的接触面积，减小接触部210与导电层230的接触电阻，接触部210和导电层230的电连接效率更高，在集成电路中，位线结构的电流的导通速度更快，提高了器件的电性能。并且，本实施例中的位线结构还设置隔离层240和绝缘结构300保护位线结构，使位线结构更加坚固、稳定。
根据本公开示例性的实施例，提供了一种半导体结构，半导体结构包括本公开上述实施例中的位 线结构200。
根据本公开实施例的半导体结构可以被包括在存储器单元和存储器单元阵列中，通过本公开上述实施例中的位线结构200执行读取操作或写入操作。本公开实施例的半导体结构，位线结构的接触部的接触电阻小，电流导通速度快，半导体结构的读取和写入数据的速度更快，半导体结构的电性能和存储性能均得到提高。
存储器单元和存储器单元阵列可以被包括在存储器件中，存储器件可以用在动态随机存储器DRAM(Dynamic Random Access Memory，DRAM)中。然而，也可以应用于静态随机存储器(Static Random-Access Memory，SRAM)、快闪存储器(flash EPROM)、铁电随机存储器(Ferroelectric Random-Access Memory，FeRAM)、磁性随机存储器(Magnetic Random Access Memory，MRAM)、相变随机存储器(Phase change Random-Access Memory，PRAM)等。
本公开示例性的实施例中提供了一种位线结构的制作方法，如图4所示，图4示出了根据本公开一示例性的实施例提供的位线结构的制作方法的流程图，图10-a至图23-b为位线结构的制作方法的各个阶段的示意图，下面结合图10-a至图23-b对位线结构的制作方法进行介绍。
如图4所示，本公开一示例性的实施例提供的一种位线结构的制作方法，包括如下的步骤：
步骤S110：提供基底，基底包括衬底和覆盖在衬底上的第一初始介质层。
图10-a是本实施例提供的基底在平行于WL方向(参照图3)的截面示意图，图10-b是本实施例提供的基底在BL方向(参照图3)的截面示意图。如图10-a和图10-b所示，提供基底100的过程中，首先提供衬底110，接着在衬底110上沉积第一初始介质层120，第一初始介质层120覆盖衬底110的顶面，形成基底100。
其中，衬底110为包括含硅物质的半导体衬底，例如，半导体衬底可以为硅衬底、硅锗衬底或SOI(silicon on insulator，绝缘体上硅)衬底。衬底110包括阵列形式排布的有源区111(参照图3)。如图10-a和图10-b所示所示，衬底100中还设置有多个平行排列的字线400(参照图3)，字线400为掩埋字线，埋入式设置在衬底100中。其中，字线400沿第一方向(参照图3的WL方向)延伸，每条字线400和有源区111呈预定角度相交，但非垂直正交(参照图3)。
第一初始介质层120的材料包括氮化硅或氮氧化硅等绝缘性能良好的材料。在本实施例中，第一初始介质层120的材料为氮化硅。
步骤S120：在基底内形成初始接触孔，初始接触孔的底壁暴露衬底，初始接触孔贯穿第一初始介质层。
图11-a是本实施例中形成光刻胶掩膜层在平行于WL方向(参照图3)的截面示意图，图11-b是本实施例中形成光刻胶掩膜层在BL方向(参照图3)的截面示意图。图12-a是本实施例中形成初始接触孔在平行于WL方向(参照图3)的截面示意图，图12-b是本实施例中形成初始接触孔在BL方向(参照图3)的示意图。
如图12-a和图12-b所示，参照图11-a和图11-b，在第一初始介质层120上形成光刻胶掩膜层10，光刻胶掩膜层10上定义有第一图案11，第一图案11在衬底100上的投影位于相邻的两条字线400之间，并且第一图案11在衬底100上的投影和有源区111(参照图3)在衬底100上的投影存在重合区域。根据第一图案11依次去除第一初始介质层120、去除部分衬底110，暴露出有源区111，形成初始接触孔101。
步骤S130：在初始接触孔中形成接触部和覆盖接触部的外侧壁的第二初始介质单元，接触部的底面与衬底相连，第二初始介质单元的侧壁与衬底和第一初始介质层相连。
图14-a是本实施例中形成第二初始介质单元在平行于WL方向(参照图3)的截面示意图，图14-b本实施例中形成第二初始介质单元在BL方向(参照图3)的示意图。如图14-a和图14-b所示，在初 始接触孔101中形成第二初始介质单元130，第二初始介质单元130覆盖初始接触孔101的侧壁。
图16-a是本实施例中形成接触部在第二方向即图3中示出的平行于WL方向(参照图3)的示意图，图16-b是本实施例中形成接触部在BL方向(参照图3)的示意图。如图16-a和图16-b所示，在第二初始介质单元130中填充形成接触部210，接触部210的底面和衬底110接触，第二初始介质单元、接触部210的顶面和第一初始介质层120的顶面平齐，接触部210的外侧壁被第二初始介质单元130覆盖。
其中，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积第二初始介质单元130，第二初始介质单元130的材料包括导电金属、导电金属氮化物、导电合金中的一种或二种以上，例如，导电金属可以为钛(Titanium)、钽(tantalum)、钨(Tungsten)。在本实施例中，第二初始介质单元130的材料为氮化钛。
可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积接触部210，接触部210的材料可以为多晶硅。
步骤S140：刻蚀部分第一初始介质层，形成第一介质层，第一介质层暴露第二初始介质单元的部分侧壁。
图17-a是本实施例中形成第一介质层在平行于WL方向(参照图3)的截面示意图，图17-b是本实施例中形成第一介质层在BL方向(参照图3)的截面示意图。如图17-a和图17-b所示，参照图16-a和图16-b，可以通过干法刻蚀工艺或湿法刻蚀工艺，回刻去除预定厚度的第一初始介质层120，形成第一介质层121。第一介质层121的厚度相比第一初始介质层120减小预定厚度，原本和第一初始介质层120顶面平齐的接触部210的顶端形成凸出第一介质层121的顶面预定高度的凸部，凸部侧壁的第二初始介质单元130被暴露出来。
步骤S150：沉积第三初始介质层和初始层叠结构，第三初始介质层覆盖第一介质层和第二初始介质单元的侧壁，以及接触部的顶面和第二初始介质单元的顶面，第三初始介质层与第二初始介质单元连为一体，初始层叠结构覆盖第三初始介质层。
图18-a是本实施例中形成第三初始介质层在平行于WL方向(参照图3)的截面示意图，图18-b是本实施例中形成第三初始介质层在BL方向(参照图3)的截面示意图。
如图18-a和图18-b所示，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积第三初始介质层140，第三初始介质层140的材料包括导电金属、导电金属氮化物、导电合金中的一种或二种以上，例如，导电金属可以为钛(Titanium)、钽(tantalum)、钨(Tungsten)。第三初始介质层140的材料可以和第二初始介质单元的材料相同或不同。在本实施例中，第三初始介质层140的材料和第二初始介质单元130的材料均为氮化钛。
第三初始介质层140覆盖在接触部210凸出于第一介质层121形成的凸部上、和第二初始介质单元130连接在一起，以使接触部210的全部侧壁和顶面均被覆盖。
图19-a是本实施例中形成初始导电层在平行于WL方向(参照图3)的截面示意图，图19-b是本实施例中形成初始导电层在BL方向(参照图3)的截面示意图。如图19-a和图19-b所示，并参照图18-a和图18-b，第三初始介质层140的厚度小于接触部210的凸部的高度，在形成第三初始介质层140之后，凸部的顶面仍高于形成在第一介质层121上的第三初始介质层140的顶面，在形成初始层叠结构500后，接触部210的顶部及其上覆盖的第三初始介质层140共同延伸至初始层叠结构500中，接触部210的顶面及其延伸到初始层叠结构500中的侧壁的面积的总和，为接触部210和初始层叠结构500的接触面积。
步骤S160：刻蚀初始层叠结构、第三初始介质层和第二初始介质单元，被保留的初始层叠结构形成层叠结构，层叠结构包括导电层；被保留的第二初始介质单元和第三初始介质层连为一体形成阻挡 层，包覆接触部的被保留的第二初始介质单元和第三初始介质层形成阻挡层的延伸部。
导电层230的材料包括导电金属、导电金属氮化物、导电合金中的一种或二种以上，例如，导电金属可以为钛(Titanium)、钽(tantalum)、钨(Tungsten)。在本实施例中，导电层230的材料为钨。
图22-a是本实施例中形成的层叠结构在平行于WL方向(参照图3)的截面示意图，图22-b是本实施例中形成的层叠结构在BL方向(参照图3)的截面示意图。
如图22-a和图22-b所示，刻蚀去除部分初始层叠结构500、第三初始介质层140和第二初始介质单元130，直至暴露出第一介质层121或暴露出衬底110，形成层叠结构600，层叠结构600为沿第二方向(位线结构200的延伸方向，即图3中示出的BL方向)延伸的线性结构，其中，第二方向与字线400延伸的第一方向(即图3中示出的WL方向)垂直。
层叠结构600在第一方向(即图3中示出的WL方向)的任意截面的宽度是相等的。并且，在第一方向(即图3中示出的WL方向)上，层叠结构600的宽度大于接触部210的宽度、小于或等于初始接触孔101的宽度，以保证接触部210的两侧覆盖有阻挡层220。
步骤S170：形成第四介质层，第四介质层覆盖层叠结构和部分延伸部。
图23-a是本实施例中沉积第四介质层在平行于WL方向(参照图3)的截面示意图，图23-b是本实施例中沉积第四介质层在BL方向(参照图3)的截面示意图。如图23-a和图23-b所示，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积第四介质层190。第四介质层190的材料包括氮化硅或氮氧化硅等绝缘性能良好的材料。在本实施例中，第四介质层190的材料为氮化硅。
本实施例的制作方法，在初始接触孔侧壁覆盖第二初始介质单元，再形成接触部，形成的接触部的外侧壁被第二初始介质单元覆盖，然后形成覆盖接触部顶面的第三初始介质层，以将接触部的外侧壁和顶面均被覆盖，避免在位线制程中，接触部的外侧壁和顶面与空气接触氧化导致接触电阻增大。而且，回刻第一初始介质层成为第一介质层，接触部的顶部凸出于第一介质层，以使接触部的顶部延伸到层叠结构的导电层中，接触部与导电层接触的面积为接触部的顶壁与接触部延伸到导电层内的侧壁面积的总和，本实施例的制作方法，通过防止制程中接触部氧化电阻增加，增加了接触部与导电层的接触面积，减小接触部与导电层的接触电阻，位线结构的接触部和导电层的电连接效率更高，电流的导通速度更快，能够提高器件的电性能。
根据一个示例性实施例，本实施例是对上述实施例步骤S120的实施方式的说明。如图5所示，图5示出了根据本实施例提供的位线结构的制作方法中步骤S120中在初始接触孔中形成覆盖接触部的外侧壁的第二初始介质单元的流程图。
在初始接触孔中形成覆盖接触部的外侧壁的第二初始介质单元，包括以下步骤：
S121：沉积第二初始介质层，第二初始介质层覆盖第一初始介质层和初始接触孔的侧壁和底壁。
图13-a是本实施例中沉积第二初始介质层在平行于WL方向(参照图3)的截面示意图，图13-b是本实施例中沉积第二初始介质层在BL方向(参照图3)的截面示意图。如图13-a和图13-b所示，参照图12-a、图12-b，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积第二初始介质层131，在本实施例中，第二初始介质层131的材料为氮化钛。
S122：刻蚀覆盖在第一初始介质层上的第二初始介质层，包括第一初始介质层，刻蚀覆盖在初始接触孔的底壁的第二初始介质层，暴露衬底，形成第二初始介质单元。
如图14-a和图14-b所示，参照图13-a、图13-b，通过干法或湿法刻蚀，去除覆盖在第一初始介质层120顶面的第二初始介质层131，去除覆盖在初始接触孔101的底壁的第二初始介质层131直至暴露出衬底110，保留覆盖在初始接触孔101侧壁的第二初始介质层131作为第二初始介质单元130。第二初始介质单元130和初始接触孔101暴露出的底壁围成接触孔102。
本实施例中形成的接触孔102的侧壁面由第二初始介质单元130围成，以使形成的接触部210的底面与衬底101接触，而接触部210的侧壁与第二初始介质单元130连接，避免接触部210的侧壁直接暴露在空气中，避免在位线制造过程中接触部210的侧壁被空气氧化，避免接触部210氧化导致的电阻增加。
根据一个示例性实施例，本实施例是对上述实施例步骤S130的实施方式的说明。如图6所示，图6示出了根据本实施例提供的位线结构的制作方法中步骤S130中在初始接触孔中形成接触部的流程图。
在初始接触孔中形成接触部，包括以下步骤：
S131：沉积接触介质层，接触介质层覆盖第二初始介质单元的内壁面和第一初始介质层，以及初始接触孔暴露的衬底；
图15-a是本实施例示出的中沉积接触介质层在平行于WL方向(参照图3)的截面示意图，图15-b是是本实施例示出的中沉积接触介质层在BL方向(参照图3)的截面示意图。如图15-a和图15-b所示，参照图14-a、图14-b，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积接触介质层150，接触介质层150填充接触孔102并覆盖第一初始介质层120的顶面，在本实施例中，接触介质层150的材料为氮化钛。
S132：去除部分接触介质层，保留接触介质层在初始接触孔中的部分，形成接触部，接触部的顶面与第一初始介质层的顶面平齐。
如图16-a和图16-b所示，参照图15-a、图15-b，通过干法或湿法刻蚀，去除第一初始介质层120上的接触介质层150，直至暴露出第一初始介质层120的顶面，形成接触部210，接触部210的顶面与第一初始介质层120的顶面平齐。
本示例性实施例，通过去除第一初始介质层顶面上的接触介质层形成接触部，在此过程中能够去除被空气氧化的顶层接触介质层，形成的接触部电阻更小，导电性能更好。
根据一个示例性实施例，本实施例是对上述实施例步骤S150的实施方式的说明。如图7所示，图7示出了根据本实施例提供的位线结构的制作方法中步骤S150中沉积初始层叠结构的流程图。
沉积初始层叠结构，包括以下步骤：
S151沉积初始导电层，初始导电层覆盖第三初始介质层。
如图19-a、图19-b所示，参照图18-a、图18-b，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积初始导电层160，初始导电层160覆盖第一初始介质层120的顶面、和第二初始介质单元130的侧壁，以及接触部210的顶面和第三初始介质层140的顶面，示例性的，初始导电层160的材料为钨。
S152沉积初始隔离层，初始隔离层覆盖初始导电层。
图20-a是本实施例中形成初始隔离层在平行于WL方向(参照图3)的截面示意图，图20-b是本实施例中形成初始隔离层在BL方向(参照图3)的截面示意图。如图20-a、图20-b所示，参照图19-a、图19-b，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积初始隔离层170，初始隔离层170覆盖初始导电层160，在本实施例中，初始隔离层170的材料为氮化钛。
如图20-a、图20-b所示，初始层叠结构500包括位于衬底上方的接触部210、第二初始介质单元130、第三介质层140、初始导电层160以及初始隔离层170。
本实施例中，沉积的初始层叠结构包括初始导电层和初始隔离层，制作得到的位线结构更加坚固、温度。
本公开示例性的实施例中提供一种位线结构的制备方法，如图8所示，图8示出了根据本公开一示例性的实施例提供的位线结构的制作方法的流程图，本实施例的步骤S210-步骤S250和上述实施例 的步骤S110-步骤S150均相同，本实施例的步骤S270和上述实施例的步骤S160相同，本实施例的步骤S280和上述实施例的步骤S170相同。
如图8所示，本实施例和上述实施例的区别之处在于，本实施例的位线结构的制作方法，在步骤S250沉积第三初始介质层和初始层叠结构之后，步骤S270刻蚀初始层叠结构、第三初始介质层和第二初始介质单元之前，还包括步骤S260：在初始隔离层上形成掩膜层。
图21-a是本实施例中形成掩膜层在平行于WL方向(参照图3)的截面示意图，图21-b是本实施例中形成掩膜层在BL方向(参照图3)的截面示意图。如图21-a、图21-b所示，参照图20-a、图20-b，掩膜层180对应设置在接触部210上方的初始隔离层170上，掩膜层180为沿第二方向(位线结构200的延伸方向，即图3中示出的BL方向)延伸的条形结构，且在第一方向(即图3中示出的WL方向)上，掩膜层180的宽度大于接触部210的宽度，小于或等于初始接触孔101的宽度，接触部210在衬底110上形成的投影位于掩膜层180在衬底100上形成的投影内。
在本实施例中，掩膜层180的宽度小于初始接触孔101的宽度，初始接触孔101在衬底100上形成的投影的两侧边缘从掩膜层180在衬底100上形成的投影两侧伸出。
本实施例中，将掩膜层的宽度限制在大于接触部的宽度、小于初始接触孔的宽度的范围中，初始接触孔的两侧均保留有超出掩膜层部分，保证根据本实施例的掩膜层刻蚀得到的位线结构具有良好的线型形状，并且，能够暴露出阻挡层的延伸部的部分侧壁面，以便于后续沉积的第四介质层能够覆盖在延伸部的暴露出的侧壁面上，对接触部加强防护。
根据一个示例性实施例，本实施例是对上述实施例步骤S270的实施方式的说明。如图9所示，图9示出了根据本实施例提供的位线结构的制作方法中步骤S270中刻蚀初始层叠结构、第三初始介质层和第二初始介质单元的流程图。
刻蚀初始层叠结构、第三初始介质层和第二初始介质单元，包括以下步骤：
S271：刻蚀初始隔离层，被保留的与掩膜层定义的图形对应的初始隔离层形成隔离层。
S272：刻蚀初始导电层，被保留的与图形对应的所处初始导电层形成导电层。
S273：刻蚀第三初始介质层，被保留的与图形对应的第三初始介质层的一部分作为延伸部的一部分，被保留的与图形对应的第三初始介质层的另一部分作为阻挡层的主体部。
S274：刻蚀第二初始介质单元，被保留的与图形对应的第二初始介质单元作为延伸部的另一部分。
如图22-a和图22-b所示，参照图21-a和图21-b，掩膜层180设置在初始隔离层170上，通过干法或湿法刻蚀去除未被掩膜层180定义的图形覆盖的初始隔离层170，保留的部分初始隔离层170形成隔离层240；掩膜层180定义的图形转移到初始导电层160上，通过干法或湿法刻蚀去除未被掩膜层180定义的图形覆盖的初始导电层160，保留的部分初始导电层160形成导电层230；掩膜层180定义的图形转移到第三初始介质层140上，通过干法或湿法刻蚀去除未被掩膜层180定义的图形覆盖的第三初始介质层140，保留的第三初始介质层140作为阻挡层220的主体部222以及延伸部221的一部分；掩膜层180定义的图形转移到第二初始介质单元130上，通过干法或湿法刻蚀去除未被掩膜层180定义的图形覆盖的第二初始介质单元130，直至暴露出衬底110，被保留的第二初始介质单元130作为阻挡层220的延伸部221的另一部分。
在本示例性实施例中，在步骤S280中，形成的层叠结构的宽度小于初始接触孔101的宽度时，部分第二初始介质单元130被去除之后，暴露出初始接触孔101的两侧侧壁，如图22-a、图22-b所示，在阻挡层220的延伸部221的两侧形成防护空间。在后续沉积第四介质层190时，部分第四介质层190覆盖衬底100上方的层叠结构600(参照图1、图2)，部分第四介质层190填充到延伸部221两侧的防护空间中形成绝缘部310，覆盖衬底100上方的层叠结构600的第四介质层190和延伸部221两侧的绝缘部310共同作为绝缘结构300，绝缘结构300与第一介质层121连为一体，为位线结构提供良好的 防护作用。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的位线结构，阻挡层覆盖接触部的顶面和外侧壁面，阻挡层保护接触部的侧壁不被氧化，减小了位线的接触电阻。

Claims (17)

  1. 一种位线结构，设置于衬底，所述位线结构包括：
    接触部，其底面与所述衬底连接；
    阻挡层，其包括延伸部，所述延伸部覆盖所述接触部的顶面和外侧壁面；
    导电层，覆盖部分所述阻挡层。
  2. 根据权利要求1所述的位线结构，其中，所述接触部包括第一部分和第二部分，所述第一部分位于所述衬底内部，所述第二部分位于所述衬底的上方；
    所述阻挡层还包括主体部，所述接触部的第二部分贯穿所述主体部并延伸至所述导电层内；
    所述导电层覆盖所述主体部，以及所述延伸部的部分表面。
  3. 根据权利要求2所述的位线结构，其中，所述主体部与所述延伸部连为一体。
  4. 根据权利要求2所述的位线结构，其中，所述主体部覆盖所述衬底上方的第一介质层；
    所述接触部的第二部分贯穿所述第一介质层。
  5. 根据权利要求4所述的位线结构，其中，沿所述延伸部的周向方向，所述延伸部的第一部分外侧壁与所述衬底接触连接，所述延伸部的第二部分外侧壁设置绝缘部。
  6. 根据权利要求5所述的位线结构，其中，所述绝缘部与所述第一介质层连为一体。
  7. 根据权利要求5所述的位线结构，其中，所述衬底中埋设有平行设置的多条字线，所述接触部设置在相邻的所述字线之间。
  8. 根据权利要求7所述的位线结构，其中，所述延伸部在所述衬底上的投影呈方形，以平行于所述字线且垂直于所述衬底的平面为第一截面，所述延伸部的第二部分外侧壁与所述第一截面相互垂直。
  9. 根据权利要求5所述的位线结构，其中，所述延伸部的第一部分外侧壁的厚度大于所述延伸部的第二部分外侧壁的厚度。
  10. 一种半导体结构，所述半导体结构包括如权利要求1至9任一项所述的位线结构。
  11. 一种位线结构的制作方法，其中，所述制作方法包括以下步骤：
    提供基底，所述基底包括衬底和覆盖在所述衬底上的第一初始介质层；
    在所述基底内形成初始接触孔，所述初始接触孔的底壁暴露所述衬底，所述初始接触孔贯穿所述第一初始介质层；
    在所述初始接触孔中形成接触部和覆盖所述接触部的外侧壁的第二初始介质单元，所述接触部的底面与所述衬底相连，所述第二初始介质单元的侧壁与所述衬底和所述第一初始介质层相连；
    刻蚀部分所述第一初始介质层，形成第一介质层，所述第一介质层暴露所述第二初始介质单元的部分侧壁；
    沉积第三初始介质层和初始层叠结构，所述第三初始介质层覆盖所述第一介质层和所述第二初始介质单元的侧壁，以及所述接触部的顶面和所述第二初始介质单元的顶面，所述第三初始介质层与所 述第二初始介质单元连为一体，所述初始层叠结构覆盖所述第三初始介质层；
    刻蚀所述初始层叠结构、所述第三初始介质层和所述第二初始介质单元，被保留的初始层叠结构形成层叠结构，所述层叠结构包括导电层；被保留的所述第二初始介质单元和所述第三初始介质层连为一体形成阻挡层，包覆所述接触部的被保留的所述第二初始介质单元和所述第三初始介质层形成所述阻挡层的延伸部；
    形成第四介质层，所述第四介质层覆盖所述层叠结构和部分所述延伸部。
  12. 根据权利要求11所述的位线结构的制作方法，其中，所述在所述初始接触孔中形成覆盖所述接触部的外侧壁的第二初始介质单元，包括：
    沉积第二初始介质层，所述第二初始介质层覆盖所述第一初始介质层和所述初始接触孔的侧壁和底壁；
    刻蚀覆盖在所述第一初始介质层上的所述第二初始介质层，包括所述第一初始介质层，刻蚀覆盖在所述初始接触孔的底壁的所述第二初始介质层，暴露所述衬底，形成所述第二初始介质单元。
  13. 根据权利要求12所述的位线结构的制作方法，其中，在所述初始接触孔中形成接触部，包括：
    沉积接触介质层，所述接触介质层覆盖所述第二初始介质单元的内壁面和所述第一初始介质层，以及所述初始接触孔暴露的所述衬底；
    去除部分所述接触介质层，保留所述接触介质层在所述初始接触孔中的部分，形成所述接触部，所述接触部的顶面与所述第一初始介质层的顶面平齐。
  14. 根据权利要求11所述的位线结构的制作方法，其中，沉积所述初始层叠结构包括：
    沉积初始导电层，所述初始导电层覆盖所述第三初始介质层；
    沉积初始隔离层，所述初始隔离层覆盖所述初始导电层。
  15. 根据权利要求14所述的位线结构的制作方法，其中，所述制作方法还包括：
    在所述初始隔离层上形成掩膜层。
  16. 根据权利要求15所述的位线结构的制作方法，其中，所述刻蚀所述初始层叠结构、所述第三初始介质层和所述第二初始介质单元，包括：
    刻蚀所述初始隔离层，被保留的与所述掩膜层定义的图形对应的所述初始隔离层形成所述隔离层；
    刻蚀所述初始导电层，被保留的与所述图形对应的所处初始导电层形成所述导电层；
    刻蚀所述第三初始介质层，被保留的与所述图形对应的所述第三初始介质层的一部分作为所述延伸部的一部分，被保留的与所述图形对应的所述第三初始介质层的另一部分作为所述阻挡层的主体部；
    刻蚀所述第二初始介质单元，被保留的与所述图形对应的所述第二初始介质单元作为所述延伸部的另一部分。
  17. 根据权利要求11所述的位线结构的制作方法，其中，所述第四介质层与所述第一介质层连为一体；
    位于所述第二初始介质单元与所述衬底之间的部分所述第四介质层形成绝缘部。
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