WO2023004841A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023004841A1
WO2023004841A1 PCT/CN2021/110232 CN2021110232W WO2023004841A1 WO 2023004841 A1 WO2023004841 A1 WO 2023004841A1 CN 2021110232 W CN2021110232 W CN 2021110232W WO 2023004841 A1 WO2023004841 A1 WO 2023004841A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
light
pixel
display panel
pixel electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/110232
Other languages
English (en)
French (fr)
Inventor
董成才
李玎
刘毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
TCL China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TCL China Star Optoelectronics Technology Co Ltd filed Critical TCL China Star Optoelectronics Technology Co Ltd
Priority to US17/600,171 priority Critical patent/US11899323B2/en
Publication of WO2023004841A1 publication Critical patent/WO2023004841A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present application relates to the field of display technology, in particular to a display panel.
  • some of the pixel electrodes controlled by the voltage control the overall brightness of the pixel, while elements such as metal traces and vias that are not controlled are usually blocked by black light-absorbing materials, that is, black matrix (Black matrix) , BM) shaded.
  • black matrix Black matrix
  • the topography after the BM process will restrict the flow of the alignment film.
  • the thickness of the BM is much greater than the thickness of the alignment film, so the topography of the inner area of the main frame formed by the outer channel area around the BM is relatively low, forming a concave structure. If the size of the main frame surrounded by BM is too small, and the nozzle array spacing for spraying the alignment film material is larger than the size of the main frame, then during the spraying process, some areas in the main frame will miss the spraying of the alignment film material , and lose the ability of alignment.
  • the inventors of the present application found that in a pixel electrode with at least two sub-pixel regions, the region between the main pixel region and the sub-pixel region is the region where the liquid crystal is not controlled. In the prior art, this area is correspondingly provided with a BM, but after partitioning, the size of the main frame body of the BM corresponding to the main pixel area and the sub-pixel is too small, resulting in the risk that the alignment film cannot cover the inner area of the main frame of the BM .
  • the embodiment of the present application provides a display panel, which can reduce the risk that the alignment film cannot cover the area inside the frame due to the too small size of the main frame surrounded by the BM.
  • An embodiment of the present application provides a display panel, including scan lines and data lines, the scan lines and the data lines intersect to form a plurality of pixel areas, the pixel areas include a main pixel area and are separated from the main pixel area The sub-pixel area provided, the display panel includes:
  • the pixel electrodes include a main pixel electrode and a sub-pixel electrode, the main pixel electrode is arranged in the main pixel area, and the sub-pixel electrode is arranged in the sub-pixel area;
  • the black matrix layer includes first light-shielding strips, second light-shielding strips and third light-shielding strips, the first light-shielding strips and the second light-shielding strips intersect to form a plurality of main frames, one main frame
  • the frame body is correspondingly arranged around one of the pixel regions;
  • the third shading strip is arranged in the main frame, and is correspondingly arranged between the main pixel region and the sub-pixel region;
  • the three shading strips are bounded by the main frame to form two sub-frames, the third shading strip is provided with a channel connecting the two sub-frames, and
  • a first alignment layer where the first alignment layer covers the black matrix layer.
  • At least one channel is disposed in the middle area of the third light-shielding strip.
  • the channel is an opening.
  • the channel in the thickness direction of the third light-shielding strip, is in a structure that is wide at the top and narrow at the bottom.
  • the channel in the orthographic projection of the third shading strip on the plane where the black matrix layer is located, in the direction from the middle area to the end surface of the channel, the channel The width increases.
  • the channel are equal in width.
  • the channel has a width greater than or equal to 10 microns.
  • the third light-shielding strip covers the entire area between the main pixel electrode and the sub-pixel electrode; the third light-shielding strip includes a hole structure and a light-shielding layer The light-shielding body layer is covered on the hole structure, and the holes of the hole structure form the channel connecting the two sub-frames.
  • the main pixel electrode and the sub-pixel electrode partially overlap with the third light-shielding strip respectively.
  • the main pixel electrode and the sub-pixel electrode of a pixel electrode are both arranged in a pixel region;
  • the main pixel electrode of one pixel electrode is disposed in the main pixel area, and the sub-pixel electrode of the other pixel electrode is disposed in the sub-pixel area.
  • the display panel includes an array substrate and a color filter substrate disposed opposite to the array substrate;
  • the array substrate includes a first substrate and a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, the plurality of pixel electrodes and a second alignment layer disposed on the first substrate;
  • the scan lines are formed on the first metal layer, and the data lines are formed on the second metal layer;
  • the color filter substrate includes a second substrate and the black matrix layer and the first alignment layer disposed on the surface of the second substrate close to the array substrate.
  • the display panel includes an array substrate and a color filter substrate disposed opposite to the array substrate;
  • the array substrate includes a first substrate and a first metal layer disposed on the first substrate, a first insulating layer, a second metal layer, a second insulating layer, the black matrix layer, the plurality of pixel electrodes and The first alignment layer; the scan lines are formed on the first metal layer, and the data lines are formed on the second metal layer;
  • the color filter substrate includes a second substrate and a second alignment layer disposed on a surface of the second substrate close to the array substrate.
  • the embodiment of the present application also provides a display panel, including scanning lines and data lines, the scanning lines and the data lines are intersected to form a plurality of pixel areas, and the pixel areas include main pixel areas and the main pixel areas Sub-pixel regions arranged at intervals, wherein the display panel includes:
  • the pixel electrodes include a main pixel electrode and a sub-pixel electrode, the main pixel electrode is arranged in the main pixel area, and the sub-pixel electrode is arranged in the sub-pixel area;
  • the black matrix layer includes first light-shielding strips, second light-shielding strips and third light-shielding strips, the first light-shielding strips and the second light-shielding strips intersect to form a plurality of main frames, one main frame
  • the frame body is correspondingly arranged around one of the pixel regions
  • the third shading strip is arranged in the main frame, and is correspondingly arranged between the main pixel region and the sub-pixel region
  • the three shading strips are bounded by the main frame to form two sub-frames, and the third shading strip is provided with a channel connecting the two sub-frames;
  • first alignment layer covering the black matrix layer
  • At least one channel is disposed in the middle area of the third light-shielding strip; the main pixel electrode and the sub-pixel electrode partially overlap with the third light-shielding strip respectively.
  • the channel is an opening.
  • the channel in the thickness direction of the third light-shielding strip, is in a structure that is wide at the top and narrow at the bottom.
  • the channel in the orthographic projection of the third shading strip on the plane where the black matrix layer is located, in the direction from the middle area to the end surface of the channel, the channel The width increases.
  • the channel are equal in width.
  • the third light-shielding strip covers the entire area between the main pixel electrode and the sub-pixel electrode; the third light-shielding strip includes a hole structure and a light-shielding layer The light-shielding body layer is covered on the hole structure, and the holes of the hole structure form the channel connecting the two sub-frames.
  • the pixel electrode includes a main pixel electrode and a sub-pixel electrode, the main pixel electrode is arranged in the main pixel area, and the sub-pixel electrode is arranged in the sub-pixel area;
  • the black matrix layer is arranged on the pixel electrode;
  • the black matrix The layer includes a first shading strip, a second shading strip and a third shading strip, the first shading strip and the second shading strip intersect to form a plurality of main frames, and one main frame is correspondingly arranged around a pixel area;
  • the second Three light-shielding strips are arranged in the main frame, and are correspondingly arranged between the main pixel area and the sub-pixel area;
  • the third light-shielding strip is bounded by the main frame to form two sub-frames, and the third light-shielding strip is provided with
  • FIG. 1 is a schematic top view of a first structure of a display panel provided by an embodiment of the present application
  • Fig. 2 is a schematic structural diagram of removing the black matrix layer in Fig. 1;
  • FIG. 3 is a schematic cross-sectional view of a first structure of a display panel provided in an embodiment of the present application
  • FIG. 4 is a schematic diagram of a black matrix layer of the first structure of the display panel provided by the embodiment of the present application.
  • FIG 5 is another schematic diagram of the black matrix layer of the first structure of the display panel provided by the embodiment of the present application.
  • FIG. 6 is a schematic cross-sectional view of a third light-shielding strip of the first structure of the display panel provided by the embodiment of the present application;
  • FIG. 7 is a schematic top view of the black matrix layer of the second structure of the display panel provided by the embodiment of the present application.
  • Fig. 8 is a schematic cross-sectional view of a third light-shielding strip of the second structure of the display panel provided by the embodiment of the present application;
  • FIG. 9 is a schematic top view of the third structure of the display panel provided by the embodiment of the present application with the black matrix layer removed;
  • FIG. 10 is a schematic cross-sectional view of a fourth structure of a display panel provided by an embodiment of the present application.
  • An embodiment of the present application provides a display panel, which will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • the embodiment of the present application provides a display panel 100 , which includes a plurality of scan lines SCAN, a plurality of data lines DATA, a plurality of pixel electrodes PX, a black matrix layer BM and a first alignment layer R1.
  • Scanning lines SCAN and data lines DATA are intersected to form a plurality of pixel regions SX.
  • the pixel area SX includes a main pixel area S1 and a sub-pixel area S2 spaced apart from the main pixel area S1.
  • the pixel electrode PX includes a main pixel electrode P1 and a sub-pixel electrode P2.
  • the main pixel electrode P1 is disposed in the main pixel area S1.
  • the sub-pixel electrode P2 is disposed in the sub-pixel region S2.
  • the black matrix layer BM includes first shading bars B1 , second shading bars B2 and third shading bars B3 .
  • the first shading strip B1 and the second shading strip B2 intersect to form a plurality of main frames M.
  • a main frame M is correspondingly arranged around a pixel area SX.
  • the third light-shielding bar B3 is disposed in the main frame M, and correspondingly disposed between the main pixel area S1 and the sub-pixel area S2.
  • the third shading strip B3 is bounded by the main frame M to form two sub-frames M1.
  • the third shading strip B3 is provided with a channel OP connecting the two sub-frames M1.
  • the first alignment layer R1 covers the black matrix layer BM.
  • the third light-shielding bar B3 divides the main frame M into two sub-frames M1.
  • the inner spaces of the two sub-frames M1 are connected, so that when spraying the alignment liquid, as long as The alignment liquid sprayed in the inner space of one sub-frame M1 can flow to the inner space of another sub-frame M1 through the channel OP, thereby reducing or even avoiding the risk that the inner space of the sub-frame M1 is not covered with the alignment layer.
  • the inner space of the sub-frame M1 is defined by the outer surface of the third shading strip B3 and the inner surface of the frame M.
  • the area between the main pixel electrode P1 and the sub-pixel electrode P2 is an uncontrolled area of the liquid crystal
  • the third light-shielding bar B3 is arranged between the main pixel area S1 and the sub-pixel area S2, that is, the third light-shielding bar B3 is arranged in the area where the liquid crystal is not controlled.
  • the controlled area is beneficial to reduce the dark state brightness of the uncontrolled area of the liquid crystal, improve the contrast ratio, and improve the dark state viewing angle.
  • the material of the black matrix layer BM is black, which may be a photoresist material, an inorganic material or a metal material layer.
  • the material of the pixel electrode PX may be a metal oxide material such as indium tin oxide.
  • the extending direction of the first light-shielding bar B1 is parallel to the extending direction of the scanning line SCAN, and the first light-shielding bar B1 blocks the scanning line SCAN.
  • the extending direction of the second light-shielding bar B2 is parallel to the extending direction of the data line DATA, and the second light-shielding bar B2 shields the data line DATA.
  • the main pixel electrode P1 and the sub-pixel electrode P2 partially overlap with the third light-shielding bar B3 respectively.
  • the overlapping width of the third light-shielding bar B3 and the main pixel electrode P1 is between 1 micron and 5 microns, such as 1 micron, 2 microns, 3 microns, 4 microns or 5 microns.
  • the overlapping width of the third light-shielding bar B3 and the sub-pixel electrode P2 is between 1 micron and 5 microns, such as 1 micron, 2 microns, 3 microns, 4 microns or 5 microns.
  • the main pixel electrode P1 and the sub-pixel electrode P2 are respectively partially overlapped with the third light-shielding bar B3, that is, the width of the third light-shielding bar B3 is set to be larger than the width of the liquid crystal uncontrolled area, so as to deal with the black matrix layer BM and the pixel electrode PX. To address the problem of misalignment, ensure that the third light-shielding bar B3 can shield the uncontrolled area of the liquid crystal in the width direction.
  • the main pixel electrode P1 and the sub-pixel electrode P2 of a pixel electrode PX are both disposed in a pixel region SX.
  • the display panel 100 further includes a first thin film transistor T1 and a second thin film transistor T2, the first thin film transistor T1 is connected to the main pixel electrode P1, and the second thin film transistor T2 is connected to the sub-pixel electrode P2.
  • the display panel 100 includes an array substrate 10 and a color filter substrate 20 disposed opposite to the array substrate 10 .
  • the array substrate 10 includes a first substrate 11, a first metal layer 12, a first insulating layer 13, a second metal layer 14, a second insulating layer 15, a plurality of pixel electrodes PX and a second Alignment layer R2.
  • the scan lines SCAN are formed on the first metal layer 12 .
  • the data line DATA is formed on the second metal layer 14 .
  • the color filter substrate 20 includes a second substrate 21 and a black matrix layer BM and a first alignment layer R1 disposed on the surface of the second substrate 21 close to the array substrate 10 .
  • the first metal layer 12 not only includes the scan line SCAN, but also includes a gate and a first common electrode.
  • the second metal layer 14 also includes a common electrode, a source and a drain.
  • the color filter substrate 20 also includes a common electrode disposed between the black matrix layer BM and the first alignment layer R1.
  • At least one channel OP is disposed in the middle area of the third light-shielding bar B3.
  • one channel OP is taken as an example for description, but it is not limited thereto.
  • the channel OP is an opening, which disconnects the third light-shielding strip B3. Such an arrangement facilitates the simplification of the process of forming the channel OP.
  • the channel OP is arranged in the middle area of the third light-shielding strip B3, so as to facilitate the rapid and uniform flow of the alignment liquid from the inner space of one sub-frame M1 to the inner space of the other sub-frame M1.
  • the width K of the channel OP is greater than or equal to 10 microns, such as 10 microns, 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns or 100 microns.
  • the width K of the channel OP may also be equal to the length of the third light-shielding strip B3, that is, the third light-shielding strip B3 is not provided.
  • the width K of the channel OP increases from the middle area to the end surface of the channel OP in the direction of the channel OP.
  • the channel OP faces from the end of the channel OP to the direction of the middle area, and the side wall Cb of the channel OP has a continuously changing taper angle.
  • such an arrangement facilitates the alignment liquid to pass through the channel OP.
  • the smooth design of the side wall of the channel OP can increase the shading area in the direction of the orthographic projection and increase the light absorption of the side wall.
  • the light absorption of the entire side wall The area is uniformized to better improve the brightness of the dark state.
  • the channel OP in the orthographic projection of the third light-shielding bar B3 on the plane where the black matrix layer BM is located, the channel OP is in the direction from the middle area to the end face of the channel OP, and the width K of the channel OP is equal, as shown in Figure 5 .
  • the multiple channel OPs are set at intervals.
  • the way of setting the interval of multiple channels OP has a better effect of reducing the brightness of the dark state than the setting of a single channel OP; because the way of setting the interval of multiple channels OP can absorb more much light.
  • the total width of the channel OP refers to the sum of the widths of all the channels OP on the third shading bar B3.
  • the channel OP in the thickness direction of the third light-shielding strip B3 , has a structure that is wide at the top and narrow at the bottom. That is to say, the width K of the channel OP gradually decreases from the end close to the first alignment layer R1 to the end far away from the first alignment layer R1 of the third light-shielding bar B3 . Such an arrangement facilitates the passage of the alignment liquid through the channel OP.
  • the third light-shielding bar B3 covers the main pixel electrode P1 and the sub-pixel electrode P2 the entire area in between.
  • the third light-shielding bar B3 includes at least one hole structure B31 and a light-shielding layer B32.
  • the light-shielding layer B32 covers the hole structure B31.
  • the holes in the hole structure B31 form a channel OP connecting the two sub-frames M1.
  • the hole structure B31 is formed by thermally decomposing a mixed material, and the mixed material includes a thermally decomposed material and a light-shielding material.
  • Such an arrangement makes the two sub-frames M1 communicate, and also enables the third light-shielding bar B3 to cover the entire liquid crystal uncontrolled area between the main pixel electrode P1 and the sub-pixel electrode P2, so that the dark-state brightness of this area is minimized.
  • the hole structure B31 is used to form the channel OP, which can better connect and support the light-shielding body layer B32 while connecting the two sub-frames M1, and avoid unstable connection of the light-shielding body layer B32.
  • the hole structure can also be replaced by a through hole, that is, the through hole is used as the channel OP.
  • the thermal decomposition material can be formed in the uncontrolled area of the liquid crystal first, and then the black matrix layer BM covering the thermal decomposition material is formed on the uncontrolled area of the liquid crystal, and then the thermal decomposition material is heated, and the thermal decomposition material is decomposed to form through hole.
  • the difference between this embodiment and the above-mentioned embodiments is that: in a pixel area SX, the main pixel electrode P1 of a pixel electrode PX is arranged on the main In the pixel area S1, the sub-pixel electrode P2 of the other pixel electrode PX is disposed in the sub-pixel area S2.
  • the black matrix layer BM is disposed on the color filter substrate 20 .
  • the black matrix layer BM can be disposed on the array substrate 10 .
  • the difference between this embodiment and the above-mentioned embodiment is that:
  • the display panel 100 includes an array substrate 10 and a color filter substrate 20 disposed opposite to the array substrate 10 .
  • the array substrate 10 includes a first substrate 11 and a first metal layer 12, a first insulating layer 13, a second metal layer 14, a second insulating layer 15, a black matrix layer BM, and a plurality of pixels arranged on the first substrate 11.
  • the scan line SCAN is formed on the first metal layer 12
  • the data line DATA is formed on the second metal layer 14 .
  • the color filter substrate 20 includes a second substrate 21 and a second alignment layer R2 disposed on a surface of the second substrate 21 close to the array substrate 10 .
  • the color filter substrate 20 further includes a common electrode disposed between the second substrate 21 and the second alignment layer R2.
  • the pixel electrode PX includes a main pixel electrode P1 and a sub-pixel electrode P2, the main pixel electrode P1 is arranged in the main pixel region S1, and the sub-pixel electrode P2 is arranged in the sub-pixel region S2;
  • the black matrix layer BM Including the first shading strip B1, the second shading strip B2 and the third shading strip B3, the first shading strip B1 and the second shading strip B2 intersect to form a plurality of main frames M, and one main frame M is correspondingly arranged around a pixel
  • the third light-shielding bar B3 is arranged in the main frame M, and is correspondingly arranged between the main pixel area S1 and the sub-pixel area S2.
  • the third shading strip B3 is bounded by the main frame M to form two sub-frames M1, and the third shading strip B3 is provided with a channel OP connecting the two sub-frames M1.
  • the third shading bar B3 divides the main frame M into two sub-frames M1, and by setting the channel OP on the third shading bar B3, the inner spaces of the two sub-frames M1 are connected, so that When spraying the alignment liquid, as long as the alignment liquid is sprayed in the inner space of one sub-frame M1, it can flow to the inner space of another sub-frame M1 through the channel OP, so as to reduce or even avoid the lack of space in the inner space of the sub-frame M. Risk of covering the alignment layer.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
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  • Spectroscopy & Molecular Physics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板(100)，其中，主像素电极(P1)设置在主像素区(S1)内，子像素电极(P2)设置在子像素区(S2)内；第一遮光条(B1)和第二遮光条(B2)交叉形成多个主框体(M)，一主框体(M)对应围设在一像素区(SX)周侧；第三遮光条(B3)设置在主框体(M)内，且对应设置在主像素区(S1)和子像素区(S2)之间。第三遮光条(B3)与主框体(M)界定形成两个子框体(M1)，第三遮光条(B3)上设置有连通两个子框体(M1)的通道(OP)。

Description

显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板。
 背景技术
对于液晶像素而言，受到电压控制的部分像素电极控制着像素整体的亮暗，而未受控制的金属走线，过孔等要素，通常会被黑色吸光材料遮挡，即被黑矩阵（Black matrix，BM）遮蔽。
由于BM较厚，BM制程完成后的地形会对配向膜的流动造成一定的限制。其中BM的厚度远大于配向膜的厚度，因此被BM围外通道区形成的主框体的内区域地形较低，形成凹陷结构。如果BM围成的主框体尺寸过小，而喷涂配向膜材料的喷嘴阵列的间距大于主框体尺寸，那么在喷涂的过程中，就会有一些主框体内的区域错过配向膜材料的喷涂，而失去配向的能力。
在对现有技术的研究和实践过程中，本申请的发明人发现，在具有至少两个子像素区的像素电极中，主像素区和子像素区之间的区域是液晶不受控的区域，在现有技术中该区域对应设置有BM，但是由于进行分区后，使得主像素区和子像素各自对应的BM的主框体尺寸过小，导致配向膜存在不能覆盖该BM的主框体内区域的风险。
 技术问题
本申请实施例提供一种显示面板，可以降低因BM围成的主框体尺寸过小，导致配向膜不能覆盖框体内区域的风险。
 技术解决方案
本申请实施例提供一种显示面板，包括扫描线和数据线，所述扫描线和所述数据线交叉设置形成多个像素区，所述像素区包括主像素区和与所述主像素区间隔设置的子像素区，所述显示面板包括：
多个像素电极，所述像素电极包括主像素电极和子像素电极，所述主像素电极设置在所述主像素区内，所述子像素电极设置在所述子像素区内；
黑矩阵层，所述黑矩阵层包括第一遮光条、第二遮光条和第三遮光条，所述第一遮光条和所述第二遮光条交叉形成多个主框体，一所述主框体对应围设在一所述像素区的周侧；所述第三遮光条设置在所述主框体内，且对应设置在所述主像素区和所述子像素区之间；所述第三遮光条与所述主框体界定形成两个子框体，所述第三遮光条上设置有连通两个所述子框体的通道，以及
第一配向层，所述第一配向层覆盖所述黑矩阵层。
可选的，在本申请的一些实施例中，所述通道具有多个，多个所述通道间隔设置。
可选的，在本申请的一些实施例中，至少一所述通道设置在所述第三遮光条的中间区域。
可选的，在本申请的一些实施例中，所述通道为开口。
可选的，在本申请的一些实施例中，在所述第三遮光条的厚度方向，所述通道呈上宽下窄结构。
可选的，在本申请的一些实施例中，所述第三遮光条于所述黑矩阵层所在平面的正投影中，所述通道自中间区域向所述通道端面的方向上，所述通道的宽度递增。
可选的，在本申请的一些实施例中，所述第三遮光条于所述黑矩阵层所在平面的正投影中，所述通道自中间区域向所述通道端面的方向上，所述通道的宽度相等。
可选的，在本申请的一些实施例中，所述通道的宽度大于或等于10微米。
可选的，在本申请的一些实施例中，所述第三遮光条覆盖所述主像素电极和所述子像素电极之间的整个区域；所述第三遮光条包括孔洞结构和遮光体层，所述遮光体层覆盖在孔洞结构上，所述孔洞结构的孔洞形成连通两个所述子框体的所述通道。
可选的，在本申请的一些实施例中，所述主像素电极和所述子像素电极分别与所述第三遮光条部分重叠。
可选的，在本申请的一些实施例中，在一所述像素区中，一所述像素电极的所述主像素电极和所述子像素电极均设置在一所述像素区内；或
在一所述像素区中，一所述像素电极的所述主像素电极设置在所述主像素区内，另一所述像素电极的所述子像素电极设置在所述子像素区内。
可选的，在本申请的一些实施例中，所述显示面板包括阵列基板和与所述阵列基板相对设置的彩膜基板；
所述阵列基板包括第一基板和设置在是第一基板上的第一金属层、第一绝缘层、第二金属层、第二绝缘层、所述多个像素电极和第二配向层；所述扫描线形成于所述第一金属层，所述数据线形成于所述第二金属层；
所述彩膜基板包括第二基板和设置在所述第二基板靠近所述阵列基板的表面上的所述黑矩阵层和所述第一配向层。
可选的，在本申请的一些实施例中，所述显示面板包括阵列基板和与所述阵列基板相对设置的彩膜基板；
所述阵列基板包括第一基板和设置在是第一基板上的第一金属层、第一绝缘层、第二金属层、第二绝缘层、所述黑矩阵层、所述多个像素电极和所述第一配向层；所述扫描线形成于所述第一金属层，所述数据线形成于所述第二金属层；
所述彩膜基板包括第二基板和设置在所述第二基板靠近所述阵列基板的表面上的第二配向层。
本申请实施例还提供一种显示面板，包括扫描线和数据线，所述扫描线和所述数据线交叉设置形成多个像素区，所述像素区包括主像素区和与所述主像素区间隔设置的子像素区，其中，所述显示面板包括：
多个像素电极，所述像素电极包括主像素电极和子像素电极，所述主像素电极设置在所述主像素区内，所述子像素电极设置在所述子像素区内；
黑矩阵层，所述黑矩阵层包括第一遮光条、第二遮光条和第三遮光条，所述第一遮光条和所述第二遮光条交叉形成多个主框体，一所述主框体对应围设在一所述像素区的周侧；所述第三遮光条设置在所述主框体内，且对应设置在所述主像素区和所述子像素区之间；所述第三遮光条与所述主框体界定形成两个子框体，所述第三遮光条上设置有连通两个所述子框体的通道；以及
第一配向层，所述第一配向层覆盖所述黑矩阵层；
至少一所述通道设置在所述第三遮光条的中间区域；所述主像素电极和所述子像素电极分别与所述第三遮光条部分重叠。
可选的，在本申请的一些实施例中，所述通道具有多个，多个所述通道间隔设置。
可选的，在本申请的一些实施例中，所述通道为开口。
可选的，在本申请的一些实施例中，在所述第三遮光条的厚度方向，所述通道呈上宽下窄结构。
可选的，在本申请的一些实施例中，所述第三遮光条于所述黑矩阵层所在平面的正投影中，所述通道自中间区域向所述通道端面的方向上，所述通道的宽度递增。
可选的，在本申请的一些实施例中，所述第三遮光条于所述黑矩阵层所在平面的正投影中，所述通道自中间区域向所述通道端面的方向上，所述通道的宽度相等。
可选的，在本申请的一些实施例中，所述第三遮光条覆盖所述主像素电极和所述子像素电极之间的整个区域；所述第三遮光条包括孔洞结构和遮光体层，所述遮光体层覆盖在孔洞结构上，所述孔洞结构的孔洞形成连通两个所述子框体的所述通道。
 有益效果
本申请实施例的显示面板中，像素电极包括主像素电极和子像素电极，主像素电极设置在主像素区内，子像素电极设置在子像素区内；黑矩阵层设置在像素电极上；黑矩阵层包括第一遮光条、第二遮光条和第三遮光条，第一遮光条和第二遮光条交叉形成多个主框体，一主框体对应围设在一像素区的周侧；第三遮光条设置在主框体内，且对应设置在主像素区和子像素区之间；所述第三遮光条与所述主框体界定形成两个子框体，所述第三遮光条上设置有连通两个所述子框体的通道；本实施例中第三遮光条将所述主框体分成两个子框体，通过在第三遮光条上设置通道，使得两个子框体内的空间相连通，以使在喷涂配向液时，只要有一个子框体的内空间中喷涂有配向液，便能通过通道流向另一子框体的内空间，从而达到减低甚至避免子框体的内空间没有覆盖配向层的风险。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的显示面板的第一种结构的俯视示意图；
图2是图1中去除黑矩阵层的结构示意图；
图3是本申请实施例的提供的显示面板的第一种结构的剖视示意图；
图4是本申请实施例提供的显示面板的第一种结构的黑矩阵层的示意图；
图5是本申请实施例提供的显示面板的第一种结构的黑矩阵层的另一种示意图；
图6是本申请实施例提供的显示面板的第一种结构的第三遮光条的剖视示意图；
图7是本申请实施例提供的显示面板的第二种结构的黑矩阵层的俯视示意图；
图8是本申请实施例提供的显示面板的第二种结构的第三遮光条的剖视示意图；
图9是本申请实施例提供的显示面板的第三种结构去除黑矩阵层的俯视示意图；
图10是本申请实施例提供的显示面板的第四种结构的剖视示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供一种显示面板，下文进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参照图1-图3，本申请实施例提供一种显示面板100，其包括多条扫描线SCAN、多条数据线DATA、多个像素电极PX、黑矩阵层BM和第一配向层R1。
扫描线SCAN和数据线DATA交叉设置形成多个像素区SX。像素区SX包括主像素区S1和与主像素区S1间隔设置的子像素区S2。
像素电极PX包括主像素电极P1和子像素电极P2。主像素电极P1设置在主像素区S1内。子像素电极P2设置在子像素区S2内。
黑矩阵层BM包括第一遮光条B1、第二遮光条B2和第三遮光条B3。第一遮光条B1和第二遮光条B2交叉形成多个主框体M。一主框体M对应围设在一像素区SX的周侧。第三遮光条B3设置在主框体M内，且对应设置在主像素区S1和子像素区S2之间。第三遮光条B3与主框体M界定形成两个子框体M1。第三遮光条B3上设置有连通两个子框体M1的通道OP。
第一配向层R1覆盖黑矩阵层BM。
第三遮光条B3将主框体M分成两个子框体M1，通过在第三遮光条B3上设置通道OP，使得两个子框体M1的内空间相连通，以使在喷涂配向液时，只要有一个子框体M1的内空间中喷涂有配向液，便能通过通道OP流向另一子框体M1的内空间，从而达到减低甚至避免子框体M1的内空间没有覆盖配向层的风险。
需要说明的是，子框体M1的内空间是第三遮光条B3的外表面和框体M的内表面界定形成的空间。
其中，主像素电极P1和子像素电极P2之间的区域为液晶不受控区域，将第三遮光条B3设置在主像素区S1和子像素区S2之间，即将第三遮光条B3设置在液晶不受控区域，有利于减低液晶不受控区域的暗态亮度，提高对比度，改善暗态视角。
可选的，黑矩阵层BM的材料为黑色，其可以是光阻材料、无机材料或金属材料层。
可选的，像素电极PX的材料可以是氧化铟锡等金属氧化物材料。
其中，第一遮光条B1的延伸方向平行与扫描线SCAN的延伸方向，第一遮光条B1遮挡扫描线SCAN。第二遮光条B2的延伸方向平行与数据线DATA的延伸方向，第二遮光条B2遮挡数据线DATA。
可选的，请参照图1和图2，主像素电极P1和子像素电极P2分别与第三遮光条B3部分重叠。
可选的，第三遮光条B3与主像素电极P1的重叠宽度介于1微米-5微米之间，比如1微米、2微米、3微米、4微米或5微米。第三遮光条B3与子像素电极P2的重叠宽度介于1微米-5微米之间，比如1微米、2微米、3微米、4微米或5微米。
将主像素电极P1和子像素电极P2分别与第三遮光条B3部分重叠，也即将第三遮光条B3的宽度设置得大于上述液晶不受控区域的宽度，以应对黑矩阵层BM和像素电极PX对位偏差的问题，确保第三遮光条B3在宽度方向上能够遮挡液晶不受控区域。
可选的，请参照图1和图2，在一像素区SX中，一像素电极PX的主像素电极P1和子像素电极P2均设置在一像素区SX内。
其中，显示面板100还包括第一薄膜晶体管T1和第二薄膜晶体管T2，第一薄膜晶体管T1连接于主像素电极P1，第二薄膜晶体管T2连接于子像素电极P2。
可选的，请参照图3，显示面板100包括阵列基板10和与阵列基板10相对设置的彩膜基板20。
阵列基板10包括第一基板11和设置在是第一基板11上的第一金属层12、第一绝缘层13、第二金属层14、第二绝缘层15、多个像素电极PX和第二配向层R2。扫描线SCAN形成于第一金属层12。数据线DATA形成于第二金属层14。
彩膜基板20包括第二基板21和设置在第二基板21靠近阵列基板10的表面上的黑矩阵层BM和第一配向层R1。
其中，第一金属层12除了包括扫描线SCAN，还包括栅极和第一公共电极。第二金属层14除了包括数据线DATA，还包括共享电极、源极和漏极。
彩膜基板20还包括公共电极，公共电极设置在黑矩阵层BM和第一配向层R1之间。
请参照图4，可选的，至少一通道OP设置在第三遮光条B3的中间区域。本实施例以一个通道OP为例进行说明，但不限于此。
其中，通道OP为开口，其断开第三遮光条B3。这样的设置便于简化形成通道OP的工艺。
本申请实施例将通道OP设置在第三遮光条B3的中间区域，便于配向液快速和均匀地从一个子框体M1的内空间流向另一个子框体M1的内空间。
可选的，通道OP的宽度K大于或等于10微米，比如可以是10微米、20微米、30微米、40微米、50微米、60微米、70微米、80微米、90微米或100微米。
可选的，在一些实施例中，通道OP的宽度K也可以等于第三遮光条B3的长度，也即不设置第三遮光条B3。
可选的，请继续参照图4，第三遮光条B3于黑矩阵层BM所在平面的正投影中，通道OP自中间区域向通道OP端面的方向上，通道OP的宽度K递增。
这样的设置在保证通道OP宽度的前提下，尽可能多的保留第三遮光条B3，以减低液晶不受控区域的暗态亮度。
可选的，第三遮光条B3于黑矩阵层BM所在平面的正投影中，通道OP自通道OP端面向中间区域的方向上，通道OP的侧壁Cb具有连续变化的锥度角。这样的设置一方面便于配向液穿过通道OP，另一方面，通道OP侧壁的圆滑设计能提高正投影方向的遮挡面积，以及提高侧壁的吸光量，另一使得整个侧壁的吸光量区域均匀化，进而更好改善暗态亮度。
可选在一些实施例中，第三遮光条B3于黑矩阵层BM所在平面的正投影中，通道OP自中间区域向通道OP端面的方向上，通道OP的宽度K相等，如图5所示。
可选的，请参照图5，在一些实施例中，通道OP具有多个，多个通道OP间隔设置。其中在通道OP的总宽度一定的情况，多个通道OP的间隔设置的方式比单个通道OP的设置方式具有更好的减低暗态亮度的效果；因为多个通道OP间隔设置的方式能够吸收更多的光。
其中通道OP的总宽度是指第三遮光条B3上的所有的通道OP的宽度的总和。
可选的，请参照图6，在第三遮光条B3的厚度方向，通道OP呈上宽下窄结构。也就是说，第三遮光条B3自靠近第一配向层R1的一端向远离第一配向层R1的一端，通道OP的宽度K递减。这样的设置便于配向液通过通道OP。
在一些实施例中，请参照图7和图8，相较于上述的实施例，本实施例的与上述实施例的不同之处在于：第三遮光条B3覆盖主像素电极P1和子像素电极P2之间的整个区域。第三遮光条B3包括至少一孔洞结构B31和一遮光体层B32，遮光体层B32覆盖在孔洞结构B31上，孔洞结构B31的孔洞形成连通两个子框体M1的通道OP。
可选的，孔洞结构B31由混合材料受热分解形成，混合材料包括热分解材料和遮光材料。
这样的设置即使得两个子框体M1连通，也使得第三遮光条B3覆盖主像素电极P1和子像素电极P2之间整个液晶不受控区域，使得该区域的暗态亮度最小化。
另外，采用孔洞结构B31形成通道OP，可以在连通两个子框体M1的同时，更好连接和支撑遮光体层B32，避免遮光体层B32的连接不稳定。
在一些实施例中，还可以将孔洞结构替换为通孔，也即以通孔作为通道OP，这样的设置更有利于配向液通过通道OP。在制程上，可以先在液晶不受控区域形成热分解材料，随后在液晶不受控区域上形成覆盖热分解材料的黑矩阵层BM，接着对热分解材料进行加热，热分解材料被分解形成通孔。
在一些实施例中，请参照图9，相较于上述实施例，本实施例与上述实施例的不同之处在于：在一像素区SX中，一像素电极PX的主像素电极P1设置在主像素区S1内，另一像素电极PX的子像素电极P2设置在子像素区S2内。
也就是说，黑矩阵层BM设置于彩膜基板20上。
请参照图10，可选的，在一些实施例中，黑矩阵层BM可以设置于阵列基板10上。本实施例相较于上述的实施例的不同之处在于：
显示面板100包括阵列基板10和与阵列基板10相对设置的彩膜基板20。
阵列基板10包括第一基板11和设置在是第一基板11上的第一金属层12、第一绝缘层13、第二金属层14、第二绝缘层15、黑矩阵层BM、多个像素电极PX和第一配向层R1。扫描线SCAN形成于第一金属层12，数据线DATA形成于第二金属层14。
彩膜基板20包括第二基板21和设置在第二基板21靠近阵列基板10的表面上的第二配向层R2。
其中，彩膜基板20还包括公共电极，公共电极设置在第二基板21和第二配向层R2之间。
本申请实施例的显示面板中，像素电极PX包括主像素电极P1和子像素电极P2，主像素电极P1设置在主像素区S1内，子像素电极P2设置在子像素区S2内；黑矩阵层BM包括第一遮光条B1、第二遮光条B2和第三遮光条B3，第一遮光条B1和第二遮光条B2交叉形成多个主框体M，一主框体M对应围设在一像素区SX的周侧；第三遮光条B3设置在主框体M内，且对应设置在主像素区S1和子像素区S2之间。第三遮光条B3与所述主框体M界定形成两个子框体M1，所述第三遮光条B3上设置有连通两个所述子框体M1的通道OP。本实施例中第三遮光条B3将所述主框体M分成两个子框体M1，通过在第三遮光条B3上设置通道OP，使得两个子框体M1的内空间相连通，以使在喷涂配向液时，只要有一个子框体M1的内空间中喷涂有配向液，便能通过通道OP流向另一子框体M1的内空间，从而达到减低甚至避免子框体M的内空间没有覆盖配向层的风险。
以上对本申请实施例所提供的一种显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，包括扫描线和数据线，所述扫描线和所述数据线交叉设置形成多个像素区，所述像素区包括主像素区和与所述主像素区间隔设置的子像素区，其中，所述显示面板包括：
    多个像素电极，所述像素电极包括主像素电极和子像素电极，所述主像素电极设置在所述主像素区内，所述子像素电极设置在所述子像素区内；
    黑矩阵层，所述黑矩阵层包括第一遮光条、第二遮光条和第三遮光条，所述第一遮光条和所述第二遮光条交叉形成多个主框体，一所述主框体对应围设在一所述像素区的周侧；所述第三遮光条设置在所述主框体内，且对应设置在所述主像素区和所述子像素区之间；所述第三遮光条与所述主框体界定形成两个子框体，所述第三遮光条上设置有连通两个所述子框体的通道；以及
    第一配向层，所述第一配向层覆盖所述黑矩阵层。
  2. 根据权利要求1所述的显示面板，其中，至少一所述通道设置在所述第三遮光条的中间区域。
  3. 根据权利要求1所述的显示面板，其中，所述通道具有多个，多个所述通道间隔设置。
  4. 根据权利要求1所述的显示面板，其中，所述通道为开口。
  5. 根据权利要求4所述的显示面板，其中，在所述第三遮光条的厚度方向，所述通道呈上宽下窄结构。
  6. 根据权利要求4所述的显示面板，其中，所述第三遮光条于所述黑矩阵层所在平面的正投影中，所述通道自中间区域向所述通道端面的方向上，所述通道的宽度递增。
  7. 根据权利要求4所述的显示面板，其中，所述第三遮光条于所述黑矩阵层所在平面的正投影中，所述通道自中间区域向所述通道端面的方向上，所述通道的宽度相等。
  8. 根据权利要求4所述的显示面板，其中，所述通道的宽度大于或等于10微米。
  9. 根据权利要求1所述的显示面板，其中，所述第三遮光条覆盖所述主像素电极和所述子像素电极之间的整个区域；所述第三遮光条包括孔洞结构和遮光体层，所述遮光体层覆盖在孔洞结构上，所述孔洞结构的孔洞形成连通两个所述子框体的所述通道。
  10. 根据权利要求1所述的显示面板，其中，所述主像素电极和所述子像素电极分别与所述第三遮光条部分重叠。
  11. 根据权利要求1所述的显示面板，其中，在一所述像素区中，一所述像素电极的所述主像素电极和所述子像素电极均设置在一所述像素区内；或
    在一所述像素区中，一所述像素电极的所述主像素电极设置在所述主像素区内，另一所述像素电极的所述子像素电极设置在所述子像素区内。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板包括阵列基板和与所述阵列基板相对设置的彩膜基板；
    所述阵列基板包括第一基板和设置在是第一基板上的第一金属层、第一绝缘层、第二金属层、第二绝缘层、所述多个像素电极和第二配向层；所述扫描线形成于所述第一金属层，所述数据线形成于所述第二金属层；
    所述彩膜基板包括第二基板和设置在所述第二基板靠近所述阵列基板的表面上的所述黑矩阵层和所述第一配向层。
  13. 根据权利要求1所述的显示面板，其中，所述显示面板包括阵列基板和与所述阵列基板相对设置的彩膜基板；
    所述阵列基板包括第一基板和设置在是第一基板上的第一金属层、第一绝缘层、第二金属层、第二绝缘层、所述黑矩阵层、所述多个像素电极和所述第一配向层；所述扫描线形成于所述第一金属层，所述数据线形成于所述第二金属层；
    所述彩膜基板包括第二基板和设置在所述第二基板靠近所述阵列基板的表面上的第二配向层。
  14. 一种显示面板，包括扫描线和数据线，所述扫描线和所述数据线交叉设置形成多个像素区，所述像素区包括主像素区和与所述主像素区间隔设置的子像素区，其中，所述显示面板包括：
    多个像素电极，所述像素电极包括主像素电极和子像素电极，所述主像素电极设置在所述主像素区内，所述子像素电极设置在所述子像素区内；
    黑矩阵层，所述黑矩阵层包括第一遮光条、第二遮光条和第三遮光条，所述第一遮光条和所述第二遮光条交叉形成多个主框体，一所述主框体对应围设在一所述像素区的周侧；所述第三遮光条设置在所述主框体内，且对应设置在所述主像素区和所述子像素区之间；所述第三遮光条与所述主框体界定形成两个子框体，所述第三遮光条上设置有连通两个所述子框体的通道；以及
    第一配向层，所述第一配向层覆盖所述黑矩阵层；
    至少一所述通道设置在所述第三遮光条的中间区域；所述主像素电极和所述子像素电极分别与所述第三遮光条部分重叠。
  15. 根据权利要求14所述的显示面板，其中，所述通道具有多个，多个所述通道间隔设置。
  16. 根据权利要求14所述的显示面板，其中，所述通道为开口。
  17. 根据权利要求16所述的显示面板，其中，在所述第三遮光条的厚度方向，所述通道呈上宽下窄结构。
  18. 根据权利要求16所述的显示面板，其中，所述第三遮光条于所述黑矩阵层所在平面的正投影中，所述通道自中间区域向所述通道端面的方向上，所述通道的宽度递增。
  19. 根据权利要求16所述的显示面板，其中，所述第三遮光条于所述黑矩阵层所在平面的正投影中，所述通道自中间区域向所述通道端面的方向上，所述通道的宽度相等。
  20. 根据权利要求14所述的显示面板，其中，所述第三遮光条覆盖所述主像素电极和所述子像素电极之间的整个区域；所述第三遮光条包括孔洞结构和遮光体层，所述遮光体层覆盖在孔洞结构上，所述孔洞结构的孔洞形成连通两个所述子框体的所述通道。
PCT/CN2021/110232 2021-07-26 2021-08-03 显示面板 Ceased WO2023004841A1 (zh)

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