WO2023000377A1 - 晶圆形变的调整方法及半导体结构 - Google Patents

晶圆形变的调整方法及半导体结构 Download PDF

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Publication number
WO2023000377A1
WO2023000377A1 PCT/CN2021/110026 CN2021110026W WO2023000377A1 WO 2023000377 A1 WO2023000377 A1 WO 2023000377A1 CN 2021110026 W CN2021110026 W CN 2021110026W WO 2023000377 A1 WO2023000377 A1 WO 2023000377A1
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wafer
deformation
stress film
groove
degree
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PCT/CN2021/110026
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English (en)
French (fr)
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郭帅
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长鑫存储技术有限公司
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Priority to US17/520,791 priority Critical patent/US20230025264A1/en
Publication of WO2023000377A1 publication Critical patent/WO2023000377A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Definitions

  • Embodiments of the present application relate to but are not limited to a method for adjusting wafer deformation and a semiconductor structure.
  • Wafer is a single crystal silicon material used to make semiconductor devices. It is a silicon wafer formed by grinding, polishing and slicing cylindrical single crystal silicon. Wafers are the raw materials and substrates for making various semiconductor products. In the manufacturing process of semiconductor products, various methods including photolithography, ion implantation, coating and cleaning can be performed on the surface of the wafer to form complex device and circuit structures. However, the stress generated during these manufacturing processes will cause deformation of the wafer, which in turn will cause problems such as product failure and low yield.
  • Embodiments of the present application provide a wafer deformation adjustment method and a semiconductor structure.
  • the method for adjusting wafer deformation includes:
  • At least one groove is formed on the back surface of the wafer
  • a stress film having a stress effect on the deformation of the wafer is formed on the back of the wafer with the at least one groove; the stress film covers the inner wall of the at least one groove.
  • the semiconductor structure provided by the embodiment of the present application includes:
  • the backside of the wafer has at least one groove
  • the wafer backside of the at least one groove includes a stress film that exerts stress on the deformation of the wafer; wherein the stress film covers the inner wall of the at least one groove and is used to adjust the deformation of the wafer.
  • FIG. 1 is a flowchart of a method for adjusting wafer deformation according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of forming grooves and stress films in a wafer deformation adjustment method according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of filling trenches in a method for adjusting wafer deformation according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of the stress effect on the wafer when depositing a film on the surface of the wafer according to the embodiment of the present application;
  • FIG. 6 is a schematic diagram of the principle of forming a protective film on the surface of a wafer in a method for adjusting wafer deformation according to an embodiment of the present application;
  • FIG. 7 is a schematic diagram of the principle of forming grooves on the back of the wafer in a wafer deformation adjustment method according to an embodiment of the present application.
  • STO selective titanium titanate
  • FIG. 9 is a schematic diagram of the principle of forming a stress film on the back of the wafer by annealing in a method for adjusting wafer deformation according to an embodiment of the present application;
  • FIG. 10 is a schematic diagram of the principle of removing a protective film in a wafer deformation adjustment method according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of an STO thin film used as a stress film in a method for adjusting wafer deformation according to an embodiment of the present application.
  • the embodiment of the present application provides a method for adjusting wafer deformation, as shown in FIG. 1 , the method includes:
  • Step S101 determining the deformation position and deformation degree of the wafer
  • Step S102 forming at least one groove on the back of the wafer according to the deformation position and degree of deformation
  • Step S103 forming a stress film on the back of the wafer having the at least one groove; the stress film covers the inner wall of the at least one groove.
  • various methods including photolithography, ion implantation, coating and cleaning can be performed on the surface of the wafer to form complex device and circuit structures.
  • the stresses generated during these manufacturing processes can cause deformation of the wafer, also known as wafer warpage. If it is not controlled, the deformation of the wafer may cause the position deviation of the subsequent process, affect the manufacturing accuracy, and cause product failure.
  • the deformation of the wafer 20 can be adjusted by forming a groove 21 on the back surface of the wafer.
  • the groove here can be a groove in the shape of a slit, or a groove in a round hole or other shapes.
  • the shape and depth of the groove can be determined according to the degree of deformation mentioned above.
  • the groove can generate stress at the deformation position of the wafer, thereby adjusting the deformation of the wafer.
  • the embodiment of the present application further adjusts by forming a stress film 22 on the surface of the groove 21 wafer 20 stress.
  • the above-mentioned processes of forming trenches and forming stress films can be carried out at any time during the manufacturing process of semiconductor products, for example, when wafer deformation occurs, resulting in inability to perform positional alignment or easy occurrence of When there is a large deviation, measure the deformation of the wafer; or, after some processes where the wafer is prone to deformation, measure the deformation of the wafer, and further flip the wafer, and adjust the deformation by the above method on the back of the wafer .
  • the deformation of the wafer can be adjusted during the manufacturing process of semiconductor products, and the adjustment method is simple and easy to implement, and it is not easy to interfere with the manufacturing of semiconductor products, which can effectively improve product performance and production yield.
  • the material of the stress film may be a material with a thermal expansion coefficient greater than that of the wafer. In this way, the stress can be adjusted through the thermal expansion of the stress film, thereby improving the deformation of the wafer.
  • the material of the stress film may be STO, that is, strontium titanate with a chemical formula of SrTiO3, or a doped STO material.
  • STO is a widely used electroceramic material with high thermal expansion coefficient, high thermal stability, high dielectric constant, and low price.
  • the material of the stress film is a crystalline material; the formation of a stress film on the back of the wafer having the at least one groove that has a stress effect on the deformation of the wafer includes:
  • Annealing is performed on the material of the stress film to form the stress film through crystallization.
  • the above-mentioned stress film is a crystalline material, that is, a crystalline thin film can be formed on the surface of the groove on the back of the wafer.
  • the material of the stress film may be deposited first to form a liquid or solid film, and then a crystalline stress film is formed by annealing. During the crystallization process of the stress film, the crystal lattice will change, and then the stress can be adjusted.
  • performing annealing treatment on the material of the stress film to form the stress film through crystallization includes:
  • the material of the stress film is annealed at a corresponding temperature to crystallize to form the stress film.
  • the temperature during the annealing process may affect the stress of the stress film
  • different temperatures may be used for annealing according to the degree of deformation during the annealing process of the material of the stress film. For example, the larger the deformation, the higher the annealing temperature, and the smaller the deformation, the lower the annealing temperature.
  • the change of deformation can be monitored in real time during the annealing process, and the annealing temperature can be adjusted accordingly.
  • the back of the wafer has multiple deformation positions; according to the degree of deformation, annealing the material of the stress film at a corresponding temperature to form the stress film through crystallization includes:
  • the materials of the stress film covered by different deformation positions are annealed at different temperatures to crystallize and form the stress film.
  • the deformation positions can be annealed at different temperatures according to the degree of deformation of different deformation positions, so as to flexibly deform the wafer. Make adjustments.
  • annealing the material of the stress film at a corresponding temperature to form the stress film through crystallization includes:
  • the back of the wafer is annealed at a corresponding temperature to crystallize and form the stress film.
  • the material of the stress film covered after the trench is formed on the back of the wafer is a thin film, so it may only cover the inner wall of the trench, and not fill the entire trench.
  • a layer of amorphous silicon can be covered on the surface of the material of the stress film, so that the amorphous silicon fills the groove and covers the back of the wafer, so that the back of the wafer presents a smooth plane.
  • the amorphous silicon can be crystallized to form polycrystalline silicon, and at the same time, the material of the stress film covered under the amorphous silicon film can also be crystallized to form the above stress film, and in the crystallization process.
  • the adjustment of stress improves the deformation of the wafer.
  • the formation of at least one groove on the back of the wafer according to the deformation position and degree of deformation includes:
  • At least one groove of a corresponding depth is formed in the adjustment region.
  • each position where the wafer is deformed can be detected first, and the adjustment area can be determined at the position where the deformation occurs.
  • the range of the adjustment area can cover the entire deformation position, and the area corresponding to the deformation position can also be determined according to the effect of the stress.
  • the aforementioned grooves are then formed in each adjustment area.
  • forming at least one groove with a corresponding depth in the adjustment region includes:
  • At least one groove of the corresponding depth is formed by etching in the adjustment area.
  • the method of forming the groove on the backside of the wafer may be formed by etching, including dry etching, wet etching and other methods.
  • the silicon on the back side of the wafer is stripped from the wafer by corrosive solutions, reactive ions, or other gases, thereby forming trenches.
  • forming at least one groove with a corresponding depth in the adjustment region includes:
  • At least one groove of the corresponding depth is formed in the adjusted region by etching at a position not shielded by the mask layer;
  • the groove is formed by etching, and the mask layer can be used to block the region that does not need to be etched, and expose the region where the groove needs to be formed.
  • the mask layer can be a thin film of materials such as silicon nitride or silicon oxide.
  • a patterned area is formed by photolithography and other processes, and then etched to form a groove. Finally, the mask layer can be further removed by grinding or etching. Eventually trenches are formed on the backside of the wafer.
  • a semiconductor device is formed within a first thickness from the front side of the wafer to the inside of the wafer; the depth of the at least one groove is smaller than the thickness of the wafer and the first thickness Difference.
  • the back side of the wafer is used to form grooves and stress films to adjust the deformation of the wafer
  • the front side of the wafer is used to manufacture semiconductor devices. Since semiconductor devices need to perform ion implantation, etching and other processes on the surface of the wafer, that is, the area within a certain thickness (the above-mentioned first thickness) from the front of the wafer to the inside of the wafer is used to form semiconductor devices. Therefore, the trench formed on the back of the wafer cannot affect the area required by the semiconductor device, that is, the bottom of the trench does not exceed the bottom of the wafer thickness occupied by the semiconductor device. Therefore, the depth of the first groove needs to be smaller than the difference between the thickness of the wafer and the above-mentioned first thickness.
  • the grooves include at least two grooves each of which may be different in shape, depth or width.
  • the degree of deformation in different regions of the wafer may be different, different grooves can be used to adjust the degree of deformation in different positions. That is, the shape, depth or width of each groove can be different. Certainly, considering that further adjustments can be made through the stress film later, the shape, depth or width of each of the above grooves can also be the same.
  • the deformation of the wafer can be flexibly adjusted from multiple dimensions, reducing the failure of semiconductor devices caused by wafer deformation and improving product yield.
  • the method before forming at least one trench on the backside of the wafer, the method further includes:
  • a protective film can be formed on the surface of the semiconductor devices on the front of the wafer.
  • the protective film can be made of materials such as polycrystalline carbon, polycrystalline silicon, oxide or silicon nitride.
  • the method further includes:
  • the protective film on the front side of the wafer is removed.
  • the wafer After forming the trench and the stress film on the back of the wafer, the wafer needs to be turned back to face up, so as to facilitate the subsequent semiconductor device manufacturing process or form semiconductor device products. Therefore, after the wafer can be flipped back to face up, the protective film on the wafer surface can be removed by chemical or physical grinding.
  • the protective film may be thinned first by physical mechanical grinding, so as to quickly remove most of the material of the protective film and retain part of the protective film. Then, etching is carried out by using a chemical agent that corrodes the material of the protective film to remove the remaining protective film.
  • the determination of the deformation position and deformation degree of the wafer includes:
  • Deformation detection is performed on the back surface of the wafer to determine the deformation position and the deformation degree.
  • the wafer it is first possible to determine whether the wafer is deformed, as well as the position and degree of deformation through deformation detection. If the wafer is deformed, but the degree of deformation is small, for example, the degree of deformation is less than a predetermined adjustment threshold. Then it can be considered that there is no deformation of the wafer or no deformation adjustment is required. However, if the wafer is deformed and the degree of deformation is greater than a predetermined adjustment threshold, the deformation can be further adjusted through the methods in the above embodiments.
  • the deformation detection method can be realized by an optical detection method, a probe method, or other various methods.
  • the timing of deformation detection can be carried out at any stage of the semiconductor device manufacturing process. In practical applications, it can be determined according to the degree of impact of each process on wafer deformation or the precision of the product, or in the process of wafer flatness. Inspection is performed during more demanding process steps (for example, before wafer bonding). After the detection, the wafer deformation can be further adjusted through the adjustment method in the above embodiment according to the detection result.
  • the embodiment of the present application also provides a semiconductor structure 200, including:
  • the backside of the wafer 210 has at least one groove 220;
  • the back side of the wafer of the at least one groove 220 includes a stress film 230 that has a stress effect on the deformation of the wafer 210; wherein, the stress film 230 covers the inner wall of the at least one groove 220 for adjusting the deformation of the wafer 210.
  • various methods including photolithography, ion implantation, coating and cleaning can be performed on the surface of the wafer to form complex device and circuit structures.
  • the stresses generated during these manufacturing processes can cause deformation of the wafer, also known as wafer warpage. If it is not controlled, the deformation of the wafer may cause the position deviation of the subsequent process, affect the manufacturing accuracy, and cause product failure.
  • the semiconductor structure provided by the embodiment of the present application including the groove and the stress film, can be used to adjust the deformation of the wafer.
  • both the stress film and the grooves on the back of the wafer can provide stress, and the shape, depth, quantity of the grooves, the film thickness of the stress film, the crystallization degree of the stress film, and the annealing temperature during formation, etc. Different degrees and different directions of stress are produced on the wafer, so the complex wafer deformation can be precisely adjusted, thereby improving the performance of semiconductor products and improving the yield rate.
  • different deformation positions on the back of the wafer correspond to adjustment areas
  • the wafer can be divided into different adjustment areas, and different adjustment areas can be adjusted separately.
  • parameters such as the number, shape, depth, and thickness of the stress film of grooves in different adjustment regions can be different, so as to realize precise adjustment for different adjustment regions.
  • the depth of the at least one groove is related to the degree of deformation of the adjustment region.
  • different adjustment regions may have grooves with different depths, and the depth of the grooves is formed according to the degree of deformation.
  • different degrees of deformation adjustment can also be achieved by adopting different annealing temperatures and other means when forming the stress film.
  • the front side of the wafer has semiconductor devices.
  • the front side of the wafer is used to form various semiconductor devices, including large-scale integrated circuits such as memories and chips.
  • the groove and stress film on the back of the wafer can be formed after the semiconductor device is formed on the front of the wafer, so as to adjust the stress of the wafer and improve the life of the device; it can also be formed during the manufacturing process of the semiconductor device, for example, a certain part of the semiconductor device manufacturing If a process is relatively easy to cause deformation of the wafer, the wafer can be turned over after the process to form the structural adjustment deformation of the above-mentioned groove and stress film, so as to reduce the impact of deformation in the subsequent process; or during the semiconductor device manufacturing process If a certain process requires higher flatness of the wafer, the structure of the above-mentioned groove and stress film can be formed on the back of the wafer before that to improve the flatness of the wafer and reduce the defect rate of the process.
  • the size of the device will become smaller and smaller, so the precision requirement in the process will be higher.
  • the wafer After the wafer goes through different processes, the wafer will be deformed, which will affect the lithography accuracy.
  • the wafer since the wafer is a single crystal material, it has anisotropy, so the amount of deformation in different directions is different, so it is difficult to adjust and control.
  • stress adjustment can be achieved by depositing different films on the surface of the wafer.
  • thin film 52 can cause the wafer 50 to generate tensile stress, and deposit an oxide thin film and a silicon nitride thin film respectively to achieve stress balance.
  • STO or doped STO materials are used to deposit thin films in trenches. Crystallization is formed after annealing treatment, so as to realize the adjustment of wafer deformation in a specific direction. Moreover, through this solution, the precise adjustment of the wafer shape variable can be realized through the control of parameters such as groove depth and annealing temperature.
  • the method for adjusting the wafer distortion may include the following process: as shown in FIG. 6 , deposit amorphous carbon (A-C) on the surface of the wafer 600 after undergoing part of the process to form a part of the semiconductor device 601 to form a protective film 602, and then flip the wafer so that the back side of the wafer is facing upwards.
  • A-C amorphous carbon
  • a plurality of trenches 603 are formed on the backside of the wafer 600 by etching.
  • the depth, shape and number of grooves formed can be adjusted according to the actual requirements for deformation adjustment, and more efficient parameters can also be selected according to the requirements of equipment capacity or process duration.
  • STO can be deposited on the back of the wafer 600 so that the STO material covers the inner wall of the trench and the surface of the wafer 600 to form an STO film 604 .
  • an amorphous silicon material (A-Si) 605 may be filled in the trench and covered on the backside of the wafer 600 by the amorphous silicon material 605 .
  • an annealing treatment may be performed on the back of the wafer 600, for example, a spike annealing technique (Spike Anneal).
  • Spike Anneal a spike annealing technique
  • the STO material forms a crystalline film
  • the polysilicon material is further crystallized to form polysilicon
  • the crystallized STO and polysilicon are used as a stress film to adjust wafer deformation.
  • the wafer 600 can be turned over so that the front side of the wafer 600 faces upward.
  • the amorphous carbon protective film 602 on the front of the wafer 600 can be removed by grinding or etching, so that the semiconductor device 601 on the surface of the wafer 600 is exposed again, and the subsequent process is continued.
  • the STO film on the back of the wafer can achieve a wide range of stress adjustment.
  • an STO film with a thickness of 3nm (nanometer) can achieve a deformation adjustment of about 100 microns, and through the doping process and The annealing temperature and the like can further adjust the amount of deformation during the annealing process.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be used as a single unit, or two or more units can be integrated into one unit; the above-mentioned integration
  • the unit can be realized in the form of hardware or in the form of hardware plus software functional unit.
  • Embodiments of the present application provide a method for adjusting wafer deformation and a semiconductor structure.
  • the method can be applied to the production process of semiconductor products, and the semiconductor structure can be applied as part or all of the structures in the semiconductor products.
  • a groove is formed on the back of the wafer, and a stress film is covered on the inner wall of the groove, so as to realize the stress adjustment of the wafer and improve the performance of the wafer. deformation, improve product performance, and increase production yield.

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Abstract

本申请实施例公开了一种晶圆形变的调整方法及半导体结构，该方法包括：确定晶圆的形变位置和形变程度；根据所述形变位置和形变程度，在晶圆背面形成至少一个沟槽；在具有所述至少一个沟槽的晶圆背面形成对所述晶圆的形变具有应力作用的应力膜；所述应力膜覆盖所述至少一个沟槽的内壁。

Description

晶圆形变的调整方法及半导体结构
相关申请的交叉引用
本申请基于申请号为202110819709.4、申请日为2021年7月20日、申请名称为“晶圆形变的调整方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种晶圆形变的调整方法及半导体结构。
背景技术
晶圆是用于制作半导体器件单晶硅材料，是由圆柱形的单晶硅经过研磨、抛光以及切片等步骤后形成的硅晶圆片。晶圆是制作各种半导体产品的原材料以及基板。在半导体产品的制作过程中，可以在晶圆的表面进行包括光刻、离子注入、镀膜以及清洗等各种手法形成复杂的器件及电路结构。然而，在这些制造过程中产生的应力会造成晶圆的形变，进而造成产品失效、良率低等问题。
发明内容
本申请实施例提供一种晶圆形变的调整方法及半导体结构。
第一方面，本申请实施例提供的晶圆形变的调整方法，包括：
确定晶圆的形变位置和形变程度；
根据所述形变位置和形变程度，在晶圆背面形成至少一个沟槽；
在具有所述至少一个沟槽的晶圆背面形成对所述晶圆的形变具有应力作用的应力膜；所述应力膜覆盖所述至少一个沟槽的内壁。
第二方面，本申请实施例提供的半导体结构，包括：
晶圆；
所述晶圆的背面具有至少一个沟槽；
所述至少一个沟槽的晶圆背面包括对晶圆的形变具有应力作用的应力膜；其中，所述应力膜覆盖所述至少一个沟槽的内壁，用于调整所述晶圆的形变。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1为本申请实施例的一种晶圆形变的调整方法流程图；
图2为本申请实施例的一种晶圆形变的调整方法中形成沟槽和应力膜的示意图；
图3为本申请实施例的一种晶圆形变的调整方法中填充沟槽的示意图；
图4为本申请实施例的一种半导体结构的示意图；
图5为本申请实施例的在晶圆表面沉积薄膜时对晶圆的应力作用的原理图；
图6为本申请实施例的一种晶圆形变的调整方法中在晶圆表面形成保护膜的原理示意图；
图7为本申请实施例的一种晶圆形变的调整方法中在晶圆背面形成沟槽的原理示意图；
图8为本申请实施例的一种晶圆形变的调整方法中在晶圆背面形成STO(钛酸锶)薄膜的原理示意图；
图9为本申请实施例的一种晶圆形变的调整方法中在晶圆背面退火形成应力膜的原理示意图；
图10为本申请实施例的一种晶圆形变的调整方法中去除保护膜的原理示意图；
图11为本申请实施例的一种晶圆形变的调整方法中STO薄膜作为应力膜的示意图。
具体实施方式
目为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本申请实施例提供一种晶圆形变的调整方法，如图1所示，该方法包括：
步骤S101、确定晶圆的形变位置和形变程度；
步骤S102、根据所述形变位置和形变程度，在晶圆背面形成至少一个沟槽；
步骤S103、在具有所述至少一个沟槽的晶圆背面形成对所述晶圆的形变具有应力作用的应力膜；所述应力膜覆盖所述至少一个沟槽的内壁。
在半导体产品的制作过程中，可以在晶圆的表面进行包括光刻、离子注入、镀膜以及清洗等各种手法形成复杂的器件及电路结构。在这些制造过程中产生的应力会造成晶圆的形变，又称为晶圆翘曲。如果不进行控制，晶圆的形变可能会造成后续工艺的位置偏差，影响制造精度，从而造成产品失效。
因此，在本申请实施例中，如图2所示，可以通过在晶圆背面形成沟槽21来调整晶圆20的形变。这里的沟槽可以是窄缝形态的沟槽也可以是圆孔或者其他形状的沟槽。沟槽的形状、深度都可以根据上述形变程度来确定。通过沟槽可以在晶圆的形变位置产生应力作用，进而调整晶圆的形变。
此外，考虑到沟槽产生的应力作用的方向和强度有限，而晶圆的形变可能是不规则的，因此，本申请实施例还通过在沟槽21的表面形成应力膜22的方式来进一步调整晶圆20的应力。
需要说明的是，上述形成沟槽以及形成应力膜的过程可以在半导体产品的制造过程中的任意时段进行，例如，在产生晶圆形变，造成一些工艺过程中无法进行位置对准或 者容易产生较大偏差时，进行晶圆形变的测量；或者，在晶圆容易产生形变的一些工艺制程之后，进行晶圆形变的测量，并进一步翻转晶圆，在晶圆背面通过上述方法调整形变。
如此，可以在半导体产品的制造过程中对晶圆的形变进行调整，并且调整方法简单易于实现，且不易对半导体产品的制造产生干扰，可以有效提升产品性能和生产良率。
在一些实施例中，上述应力膜的材料，可以为热膨胀系数大于晶圆的热膨胀系数的材料，如此，可以通过应力膜的热膨胀作用调整应力，进而改善晶圆的形变。
示例性地，应力膜的材料可以为STO，即钛酸锶，化学式为SrTiO3，也可以为掺杂后的STO材料。STO是一种用途广泛的电陶瓷材料，具有较高的热膨胀系数，且热稳定性高、介电常数高，且价格低廉。
在一些实施例中，所述应力膜的材料为结晶材料；所述在具有所述至少一个沟槽的晶圆背面形成对所述晶圆的形变具有应力作用的应力膜，包括：
在具有所述至少一个沟槽的晶圆背面沉积所述应力膜的材料；
对所述应力膜的材料进行退火处理，结晶形成所述应力膜。
上述应力膜为结晶材料，即可以在晶圆背面的沟槽表面形成结晶薄膜。在本申请实施例中，可以先沉积应力膜的材料，形成液态或者固态的薄膜，然后通过退火形成结晶的应力膜。应力膜结晶的过程中，会发生晶格的变化，进而实现应力的调整。
在一些实施例中，所述对所述应力膜的材料进行退火处理，结晶形成所述应力膜，包括：
根据所述形变程度，对所述应力膜的材料进行相应温度的退火处理，结晶形成所述应力膜。
由于退火过程中的温度可能会影响应力膜的应力大小，因此，在对应力膜的材料进行退火处理的过程中，可以根据形变程度采用不同的温度进行退火处理。例如，形变越大，退火的温度越高，形变越小，退火的温度越低。又如，可以在退火的过程中实时监控形变的大小变化，并据此调整退火的温度。
在一些实施例中，所述晶圆背面具有多个形变位置；所述根据所述形变程度，对所述应力膜的材料进行相应温度的退火处理，结晶形成所述应力膜，包括：
根据不同的所述形变位置的所述形变程度，分别对不同形变位置覆盖的所述应力膜的材料进行不同温度的退火处理，结晶形成所述应力膜。
考虑到晶圆的不同位置可能存在不同程度的形变，因此，可以对晶圆背面的不同形变位置，分别基于形变程度进行调节。
由于上述形成应力膜的过程中，不同的退火温度会产生不同大小的应力，因此，可以根据不同形变位置的形变程度，分别对形变位置进行不同温度的退火处理，从而灵活地对晶圆形变进行调节。
在一些实施例中，所述根据所述形变程度，对所述应力膜的材料进行相应温度的退火处理，结晶形成所述应力膜，包括：
在覆盖有如图3所示的所述应力膜22的材料的晶圆20背面沉积非晶硅薄膜31，填充所述至少一个沟槽；
根据所述形变程度，对所述晶圆背面进行相应温度的退火处理，结晶形成所述应力膜。
在本申请实施例中，晶圆背面形成沟槽后覆盖的应力膜的材料是一层厚度较小的薄膜，因此可能仅覆盖在沟槽的内壁上，而不会填充整个沟槽。对应力膜进行退火处理时，可以先在应力膜的材料的表面覆盖一层非晶硅，使得非晶硅填充沟槽并覆盖在晶圆背面，使得晶圆背面呈现光滑的平面。
在非晶硅薄膜上进行退火处理时，可以使非晶硅结晶，形成多晶硅，同时可以使得非晶硅薄膜下覆盖的应力膜的材料也发生结晶，形成上述应力膜，并在结晶过程中实现应力的调节，改善晶圆的形变。
在一些实施例中，所述根据所述形变位置和形变程度，在晶圆背面形成至少一个沟槽，包括：
根据所述形变位置，在所述晶圆背面确定形成所述至少一个沟槽的调整区域；
根据所述形变程度，在所述调整区域内形成相应深度的至少一个沟槽。
在本申请实施例中，可以先检测晶圆发生形变的各个位置，并在发生形变的位置确定调整区域。调整区域的范围可以覆盖整个形变位置，也可以根据应力的作用，确定出与形变位置相对应的区域。然后在每个调整区域内形成上述沟槽。
由于不同区域的形变程度不同，因此，可以在不同的调整区域内，形成深度、宽度或者长度不同的沟槽，从而实现灵活调整。
在一些实施例中，所述根据所述形变程度，在所述调整区域内形成相应深度的至少一个沟槽，包括：
根据所述形变程度，在所述调整区域内通过刻蚀形成所述相应深度的至少一个沟槽。
在本申请实施例中，在晶圆背面形成沟槽的方法可以通过刻蚀来形成，包括干法刻蚀、湿法刻蚀等方式。通过具有腐蚀性的溶液、反应离子或者其他气体等使得晶圆背面部分的硅从晶圆剥离，从而形成沟槽。
在一些实施例中，所述根据所述形变程度，在所述调整区域内形成相应深度的至少一个沟槽，包括：
在所述调整区域的表面形成带有刻蚀图形的掩膜层；
所述根据所述形变程度，在所述调整区域内通过刻蚀在所述掩膜层未遮挡的位置形成所述相应深度的至少一个沟槽；
去除所述掩膜层。
通过刻蚀的方法形成沟槽，可以利用掩膜层遮挡不需要被刻蚀掉的区域，裸露需要形成沟槽的区域。掩膜层可以是氮化硅或者氧化硅等材料的薄膜，通过光刻等工艺形成图形化的区域，然后进行刻蚀形成沟槽，最后可以通过研磨或者刻蚀的方式进一步去除掩膜层，最终在晶圆背面形成沟槽。
在一些实施例中，晶圆正面和所述晶圆正面至晶圆内部的第一厚度内形成有半导体器件；所述至少一个沟槽的深度小于所述晶圆的厚度与所述第一厚度之差。
在本申请实施例中，晶圆背面用于形成沟槽和应力膜调整晶圆的形变，晶圆正面则 用于制造半导体器件。由于半导体器件需要在晶圆表面进行离子注入、刻蚀等工艺，即晶圆正面至晶圆内部的一定厚度内(上述第一厚度)的区域用于形成半导体器件。因此，晶圆背面形成的沟槽不能影响到半导体器件所需的区域，即沟槽的底部不超过半导体器件所占晶圆厚度的底部。因此，第一沟槽的深度需要小于晶圆厚度与上述第一厚度之差。
在一些实施例中，所述沟槽中包括每一所述沟槽的形状、深度或宽度可以不同的至少两个沟槽。
由于晶圆不同区域的形变程度可能存在差异，因此，针对不同位置的不同形变程度，可以利用不同的沟槽来进行调节。即每一沟槽的形状、深度或者宽度都可以不同。当然，考虑到后续还可以进一步通过应力膜进行调整，上述每一沟槽的形状、深度或者宽度也可相同。
如此，可以从多个维度灵活地对晶圆的形变进行调节，减少晶圆形变带来的半导体器件失效的情况，提升产品良率。
在一些实施例中，在所述晶圆背面形成至少一个沟槽之前，所述方法还包括：
在所述晶圆正面的半导体器件表面形成保护膜；
翻转所述晶圆，使所述晶圆背面朝向竖直上方。
在晶圆背面形成沟槽时，需要将晶圆翻转并将晶圆背面朝向上方，并且需要对晶圆进行刻蚀等处理。而晶圆正面可能已经经过了一段半导体器件的相关制程，形成了部分或者全部的半导体器件。为了保护晶圆正面的半导体器件不受损坏，且便于在晶圆背面形成沟槽时翻转并固定晶圆，这里，可以先在晶圆正面的半导体器件表面形成保护膜。保护膜可以由多晶碳、多晶硅、氧化物或者氮化硅等材料制作而成。
在一些实施例中，在所述晶圆背面形成所述应力膜之后，所述方法还包括：
翻转所述晶圆，使所述晶圆正面朝向竖直上方；
去除所述晶圆正面的保护膜。
在形成晶圆背面的沟槽以及应力膜后，需要将晶圆翻转回正面朝上，以便后续的半导体器件的制程，或者形成半导体器件产品。因此，可以翻转回晶圆正面朝上后，再通过化学或者物理研磨的方法去除晶圆表面的保护膜。
示例性地，为了防止去除保护膜时损伤半导体器件，可以先利用物理机械研磨的方法对保护膜进行减薄，快速去除大部分保护膜的材料，并保留部分保护膜。然后再利用对保护膜材料有腐蚀作用的化学制剂进行刻蚀，去除残留的保护膜。
在一些实施例中，所述确定晶圆的形变位置和形变程度，包括：
在所述晶圆背面进行形变检测，确定所述形变位置和所述形变程度。
在本申请实施例中，可以先通过形变检测确定晶圆是否存在形变，以及形变位置和形变程度。如果晶圆存在形变，但形变的程度较小，例如，形变程度小于预定的调整阈值。那么可以认为晶圆不存在形变或者不需要进行形变的调整。而如果晶圆存在形变且形变程度大于预定的调整阈值，则可以进一步通过上述实施例中的方法进行形变的调整。
形变检测的方法可以通过光学检测方法、探针法或者其他各种方法进行实现。进行形变检测的时机可以在半导体器件的制造工艺任意阶段中进行，在实际应用中，可以根 据各制程对晶圆形变产生影响的程度或者产品的精密度来确定，或者在对晶圆平整度要求较高的工艺步骤中(例如，进行晶圆键合之前)进行检测。在进行检测之后则可以根据检测结果通过上述实施例中的调整方法来进一步调整晶圆形变。
如图4所示，本申请实施例还提供一种半导体结构200，包括：
晶圆210；
所述晶圆210的背面具有至少一个沟槽220；
所述至少一个沟槽220的晶圆的背面包括对晶圆210的形变具有应力作用的应力膜230；其中，所述应力膜230覆盖所述至少一个沟槽220的内壁，用于调整所述晶圆210的形变。
在半导体产品的制作过程中，可以在晶圆的表面进行包括光刻、离子注入、镀膜以及清洗等各种手法形成复杂的器件及电路结构。在这些制造过程中产生的应力会造成晶圆的形变，又称为晶圆翘曲。如果不进行控制，晶圆的形变可能会造成后续工艺的位置偏差，影响制造精度，从而造成产品失效。
因此，本申请实施例提供的半导体结构，包括沟槽以及应力膜，可以用于调整晶圆的形变。
需要说明的是，晶圆背面的应力膜和沟槽都可以提供应力作用，并且沟槽的形状、深度、数量以及应力膜的膜厚、应力膜的结晶程度以及形成时的退火温度等等都会对晶圆产生不同程度和不同方向的应力作用，因而可以对复杂的晶圆形变进行精确地调整，进而提升半导体产品的性能，提升良率。
在一些实施例中，所述晶圆的背面不同的形变位置分别对应有调整区域；
在每一所述调整区域的范围内分别具有至少一个所述沟槽。
上述晶圆的背面不同位置可能存在不同的方向以及不同程度的形变，因此，可以将晶圆划分不同的调整区域，并对不同调整区域分别进行调整。
因此，不同调整区域内的沟槽数量、形状、深度以及应力膜的厚度等参数可以不同，从而实现对不同调整区域的精确调整。
在一些实施例中，所述至少一个沟槽的深度与所述调整区域的形变程度相关。
沟槽的不同深度对晶圆应力会产生不同强度的效果，因此，在不同调整区域可以具有不同深度的沟槽，并且沟槽深度是根据形变程度形成的。此外，也可以通过在形成应力膜时采用不同的退火温度等手段实现不同程度的形变调整。
在一些实施例中，所述晶圆的正面具有半导体器件。
在本申请实施例中，晶圆的正面用于形成各种半导体器件，包括存储器、芯片等大规模集成电路等结构。上述晶圆背面的沟槽以及应力膜可以在晶圆正面形成半导体器件后形成，从而调整晶圆应力，提升器件的寿命；也可以在半导体器件的制造过程中形成，比如，半导体器件制造的某一制程比较容易造成晶圆的形变，则可以在该制程后翻转晶圆并形成上述沟槽及应力膜的结构调整形变，减少在后续制程中形变带来的影响；或者半导体器件制造的过程中某一制程对于晶圆的平整度要求较高，则可以在此之前现在晶圆背面形成上述沟槽及应力膜的结构，提升晶圆平整度，降低该制程的不良率。
本申请实施例还提供如下示例：
由于半导体制造工艺的不断提升，器件尺寸会越来越小，因此，在制程上的精密度要求会更高。而晶圆经过不同制程后会使晶圆发生形变，从而对光刻精度产生影响。并且，由于晶圆为单晶材料，其存在各向异性，因此不同方向形变量不同，因而难以调整和控制。
在相关技术中，可以采用在晶圆表面沉积不同薄膜的方式实现应力调整，如图5所示，沉积氧化物(OX)薄膜51，可以使得晶圆50产生压应力，沉积氮化硅(SIN)薄膜52，可以使得晶圆50产生拉应力，分别沉积氧化物薄膜和氮化硅薄膜，则可以达到应力平衡。
在本申请实施例中，为了实现对晶圆的形变的精准控制，将晶圆形变对光刻精确度的影响降到最低，采用STO或者掺杂的STO材料在沟槽中进行薄膜沉积，经过退火处理后形成结晶，从而实现对晶圆形变在特定方向上的调节。并且，通过本方案可以通过沟槽深度、退火温度等参数的控制，实现对晶圆形变量的精确调节。
本申请实施例提供的晶圆形变的调整方法可以包括如下流程：如图6所示，在经历部分制程形成部分半导体器件601后的晶圆600表面沉积非晶碳(A-C)，形成保护膜602，然后翻转晶圆使得晶圆背面朝上。
如图7所示，在晶圆600背面通过刻蚀形成多个沟槽603。形成沟槽的深度、形状和数量都可以根据对形变调节的实际需求进行调整，也可以根据设备的能力或者工艺时长等需求选择较为高效的参数。
如图8所示，形成沟槽603后，可以晶圆600背面沉积STO，使得STO材料覆盖沟槽的内壁以及晶圆600表面，形成STO薄膜604。
然后，如图9所示，可以在沟槽内填充非晶硅材料(A-Si)605并使非晶硅材料605覆盖在晶圆600背面。此时，可以对晶圆600背面进行退火处理，例如，尖峰退火技术(Spike Anneal)。从而使STO材料形成结晶膜，并使得多晶硅材料进一步晶化形成多晶硅，结晶后的STO以及多晶硅则作为应力膜实现对晶圆形变的调整。
如图10所示，完成应力膜的制程后，可以翻转晶圆600，使晶圆600正面朝上。通过研磨或者刻蚀等方法可以去除晶圆600正面的非晶碳保护膜602，使得晶圆600表面的半导体器件601重新裸露出来，继续进行后续制程。
如图11所示，晶圆背面的STO薄膜可以实现大范围的应力调节，示例性地，厚度为3nm(纳米)的STO薄膜可以实现100微米左右的形变量的调节，并且通过掺杂工艺以及退火温度等可以进一步调节退火过程中的形变量。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非 排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本申请各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本申请的实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请实施例提供了一种晶圆形变的调整方法及半导体结构，该方法可以应用于半导体产品的生产过程，该半导体结构则可以应用为半导体产品中的部分或全部结构。通过本申请实施例的技术方案，根据晶圆的形变位置和形变程度，在晶圆背面形成沟槽，并在沟槽内壁上覆盖应力膜，从而实现对晶圆的应力调整，进而改善晶圆的形变，提升产品性能，提高生产良率。

Claims (19)

  1. 一种晶圆形变的调整方法，所述方法包括：
    确定晶圆的形变位置和形变程度；
    根据所述形变位置和形变程度，在晶圆背面形成至少一个沟槽；
    在具有所述至少一个沟槽的晶圆背面形成对所述晶圆的形变具有应力作用的应力膜；所述应力膜覆盖所述至少一个沟槽的内壁。
  2. 根据权利要求1所述的方法，其中，所述应力膜的材料为结晶材料；所述在具有所述至少一个沟槽的晶圆背面形成对所述晶圆的形变具有应力作用的应力膜，包括：
    在具有所述至少一个沟槽的晶圆背面沉积所述应力膜的材料；
    对所述应力膜的材料进行退火处理，结晶形成所述应力膜。
  3. 根据权利要求2所述的方法，其中，所述对所述应力膜的材料进行退火处理，结晶形成所述应力膜，包括：
    根据所述形变程度，对所述应力膜的材料进行相应温度的退火处理，结晶形成所述应力膜。
  4. 根据权利要求3所述的方法，其中，所述晶圆背面具有多个形变位置；所述根据所述形变程度，对所述应力膜的材料进行相应温度的退火处理，结晶形成所述应力膜，包括：
    根据不同的所述形变位置的所述形变程度，分别对不同形变位置覆盖的所述应力膜的材料进行不同温度的退火处理，结晶形成所述应力膜。
  5. 根据权利要求3所述的方法，其中，所述根据所述形变程度，对所述应力膜的材料进行相应温度的退火处理，结晶形成所述应力膜，包括：
    在覆盖有所述应力膜的材料的晶圆背面沉积非晶硅薄膜，填充所述至少一个沟槽；
    根据所述形变程度，对所述晶圆背面进行相应温度的退火处理，结晶形成所述应力膜。
  6. 根据权利要求1至5任一所述的方法，其中，所述根据所述形变位置和形变程度，在晶圆背面形成至少一个沟槽，包括：
    根据所述形变位置，在所述晶圆背面确定形成所述至少一个沟槽的调整区域；
    根据所述形变程度，在所述调整区域内形成相应深度的至少一个沟槽。
  7. 根据权利要求5所述的方法，其中，所述根据所述形变程度，在所述调整区域内形成相应深度的至少一个沟槽，包括：
    根据所述形变程度，在所述调整区域内通过刻蚀形成所述相应深度的至少一个沟槽。
  8. 根据权利要求7所述的方法，其中，所述根据所述形变程度，在所述调整区域内形成相应深度的至少一个沟槽，包括：
    在所述调整区域的表面形成带有刻蚀图形的掩膜层；
    所述根据所述形变程度，在所述调整区域内通过刻蚀在所述掩膜层未遮挡的位置形成所述相应深度的至少一个沟槽；
    去除所述掩膜层。
  9. 根据权利要求5所述的方法，其中，晶圆正面和所述晶圆正面至晶圆内部的第一厚度内形成有半导体器件；所述至少一个沟槽的深度小于所述晶圆的厚度与所述第一厚度之差。
  10. 根据权利要求1所述的方法，其中，所述沟槽中包括形状、深度或宽度不同的至少两个沟槽。
  11. 根据权利要求1所述的方法，其中，在所述晶圆背面形成至少一个沟槽之前，所述方法还包括：
    在所述晶圆正面的半导体器件表面形成保护膜；
    翻转所述晶圆，使所述晶圆背面朝向竖直上方。
  12. 根据权利要求11所述的方法，其中，在所述晶圆背面形成所述应力膜之后，所述方法还包括：
    翻转所述晶圆，使所述晶圆正面朝向竖直上方；
    去除所述晶圆正面的保护膜。
  13. 根据权利要求1所述的方法，其中，所述确定晶圆的形变位置和形变程度，包括：
    在所述晶圆背面进行形变检测，确定所述形变位置和所述形变程度。
  14. 根据权利要求1所述的方法，其中，所述应力膜的材料的热膨胀系数大于所述晶圆的热膨胀系数。
  15. 根据权利要求14所述的方法，其中，所述应力膜的材料为钛酸锶STO，或者掺杂STO材料。
  16. 一种半导体结构，包括：
    晶圆；
    所述晶圆的背面具有至少一个沟槽；
    所述至少一个沟槽的晶圆的背面包括对晶圆的形变具有应力作用的应力膜；其中，所述应力膜覆盖所述至少一个沟槽的内壁，用于调整所述晶圆的形变。
  17. 根据权利要求16所述的半导体结构，其中，所述晶圆的背面不同的形变位置分别对应有调整区域；
    在每一所述调整区域的范围内分别具有至少一个所述沟槽。
  18. 根据权利要求17所述的半导体结构，其中，所述至少一个沟槽的深度与所述调整区域的形变程度相关。
  19. 根据权利要求16所述的半导体结构，其中，所述晶圆的正面具有半导体器件。
PCT/CN2021/110026 2021-07-20 2021-08-02 晶圆形变的调整方法及半导体结构 WO2023000377A1 (zh)

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