WO2022270161A1 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- WO2022270161A1 WO2022270161A1 PCT/JP2022/019673 JP2022019673W WO2022270161A1 WO 2022270161 A1 WO2022270161 A1 WO 2022270161A1 JP 2022019673 W JP2022019673 W JP 2022019673W WO 2022270161 A1 WO2022270161 A1 WO 2022270161A1
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- WIPO (PCT)
- Prior art keywords
- lead frame
- insulating substrate
- wiring
- semiconductor module
- heat dissipation
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 230000017525 heat dissipation Effects 0.000 claims description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 10
- 238000001816 cooling Methods 0.000 description 9
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
Definitions
- the present invention relates to semiconductor modules.
- Patent Document 1 an insulating substrate 11 made of a ceramic material and having a wiring layer on which components are mounted is formed on one main surface;
- a semiconductor package 100 on which a wiring substrate 10 is mounted is disclosed, which includes a base plate 13 having a protruding portion 13c protruding outward from an outer peripheral edge and having a thickness greater than that of an insulating substrate 11.
- FIG. 1 The emitter wiring pattern 12a for connecting the emitter electrode of the semiconductor chip 20 and the collector wiring pattern 12b for connecting the collector electrode of the semiconductor chip 20 are connected to external electrodes by lead frames (emitter terminal 18a and collector terminal 18b).
- One aspect of the present invention for achieving the above object is a semiconductor module including an insulating substrate, wiring formed on the insulating substrate, a semiconductor chip, and a lead frame, wherein one surface of the semiconductor chip is the wiring. and the other surface is connected to the lead frame, the wiring has a floating wiring to which the lead frame is connected, and the connection point between the floating wiring and the lead frame is located at the corner of the insulating substrate.
- a semiconductor module characterized by:
- a semiconductor module having a semiconductor chip wiring formed on an insulating substrate, and a lead frame, it is possible to provide a semiconductor module having a higher heat dissipation effect than conventional semiconductor modules.
- FIG. 2 is a perspective view showing an example of the configuration of the power semiconductor module of the present invention
- Top view of the power semiconductor module viewed from direction A in FIG. The bottom view of the power semiconductor module seen from the B direction of FIG. 1 of FIG.
- Side view of the power semiconductor module seen from direction D in FIG. A simplified diagram of a part of the top view of FIG. Cross-sectional view of the power semiconductor module seen in the EE cross section of FIG.
- FIG. 1 is a perspective view showing an example of the configuration of the power semiconductor module of the present invention
- FIG. 2 is a top view of the power semiconductor module viewed from direction A in FIG. 1
- FIG. 3 is a power semiconductor module viewed from direction B in FIG. 4 is a side view of the power semiconductor module viewed from direction C in FIG. 1
- FIG. 5 is a side view of the power semiconductor module viewed from direction D in FIG.
- a semiconductor module 10 according to one embodiment of the present invention has wirings 2, semiconductor chips 3 and lead frames 4 laminated in this order on the surface of an insulating substrate 1.
- FIG. 1 is a perspective view showing an example of the configuration of the power semiconductor module of the present invention
- FIG. 2 is a top view of the power semiconductor module viewed from direction A in FIG. 1
- FIG. 3 is a power semiconductor module viewed from direction B in FIG. 4
- FIG. 5 is a side view of the power semiconductor module viewed from direction D in FIG.
- a semiconductor module 10 according to one embodiment of
- the semiconductor chip 3 has one surface connected to the wiring 2 formed on the insulating substrate 1 and the other surface connected to the lead frame 4 .
- the semiconductor chip 3 is not limited to this.
- a plurality of insulating substrates 1 (three insulating substrates 1 in FIGS. 1 and 2) are housed in a resin case 7. Although not shown, the surface of the insulating substrate 1 is sealed together with the wiring 2, the semiconductor chip 3 and the lead frame 4 with an insulating resin.
- Materials for the insulating substrate 1 and the wiring 2 are not particularly limited, but for example, ceramics can be used for the insulating substrate 1 and copper can be used for the wiring 2 .
- a heat dissipation member 6 having at least a base plate is provided on the surface of the insulating substrate 1 opposite to the surface on which the semiconductor chip 3 is provided.
- the heat radiating member 6 may further have heat radiating fins 6a.
- the configuration of the radiation fins 6a may be cylindrical as shown, or may be flat (not shown).
- the cooling method of the heat radiating member 6 may be air cooling or water cooling.
- air cooling for example, a fan can be provided to cool the heat radiating member 6 and the heat radiating fins 6a.
- a cooling passage may be provided so that water or a cooling medium contacts the heat radiating member or the heat radiating fins 6a.
- FIG. 6 is a diagram showing a simplified configuration of part of the top view of FIG. 1, and FIG. 7 is a cross-sectional view of the power semiconductor module as seen from the EE cross section of FIG.
- the shape of the lead frame 4 in FIG. 2 is simplified.
- the lead frame 4 is connected to the wiring 2 via a first connection point 4a.
- the terminals 5 are provided, for example, on both sides of the insulating substrate 1, and the current from the terminals 5 on one side passes through the wiring 2 and is conducted to the terminals 5 on the other side via the semiconductor chip 3 and the lead frame 4. be killed.
- the wiring 2 is a floating wiring that is not used as a circuit, in addition to the wiring that is used as a circuit, such as a current path between the terminals 5 on both sides. It is set as the structure which has the wiring 2a. Then, at the corner portion of the insulating substrate 1, the floating wiring 2a and the lead frame 4 are connected at the position of the second connection point 4b.
- the heat generated from the semiconductor chip 3 is led to the heat dissipation member 6 via the wiring 2 and the insulating substrate 1 immediately below the semiconductor chip 3, and is dissipated (heat dissipation path 11). Further, heat generated from the semiconductor chip 3 is guided to the first connection point 4a via the lead frame 4, is guided to the heat dissipation member 6 via the wiring 2 and the insulating substrate 1, and is dissipated (heat dissipation path 12).
- the heat generated from the semiconductor chip 3 is led to the second connection point 4b via the lead frame 4.
- the heat led to the second connection point 4b is led to the heat dissipation member 6 via the floating wiring 2a and the insulating substrate 1, and is radiated (heat dissipation path 13).
- the floating wiring 2a that does not function as a wiring among the wirings 2 to the lead frame 4 in this way, in addition to the heat radiation paths 11 and 12 of the conventional configuration, the floating wiring 2a and the insulating substrate 1 can be And the heat dissipation path 13 that transfers heat to the heat dissipation member 6 can enhance the heat dissipation effect.
- the heat dissipation path 13 can be added without interfering with the conventional heat dissipation paths 11 and 12, so that the heat dissipation effect can be enhanced.
- connection point 4b between the floating wiring 2a and the lead frame 4 is closer to the outer circumference of the insulating substrate 1 than the first connection point 4a, which is another connection point between the lead frame 4 and the wiring 2. is preferably located in order to enhance the heat radiation effect.
- the thickness of the lead frame 4 is preferably 1.0 mm or more and 1.2 mm or less. From the viewpoint of reducing thermal resistance, it is preferable that the thickness of the lead frame 4 is thick (the thicker the lead frame 4, the easier it is to conduct heat) (the heat dissipation effect through the heat dissipation paths 12 and 13 is enhanced). On the other hand, from the viewpoint of improving thermal fatigue resistance, it is preferable that the thickness of the lead frame 4 is thin (because the lead frame 4 made of copper has a larger thermal expansion coefficient than the insulating substrate 1 made of ceramics, the thinner one less stress).
- the thickness of the lead frame 4 is preferably 1.0 mm or more and 1.2 mm or less in order to balance low thermal resistance and thermal fatigue resistance.
- Thermal fatigue due to the difference in coefficient of thermal expansion between the insulating substrate 1 and the lead frame 4 increases at the corners of the insulating substrate 1 where the second connection points 4b are provided, but the thickness of the lead frame 4 is set within the above range.
- both reduction in thermal resistance and resistance to thermal fatigue can be achieved.
- the heat dissipation member 6 is preferably arranged so as to overlap the floating wiring 2a with the insulating substrate 1 interposed therebetween.
- the heat dissipation member 6 has heat dissipation fins 6a, it is preferable that the heat dissipation fins 6a are arranged so as to overlap the floating wirings 2a with the insulating substrate 1 interposed therebetween.
- the present invention it is possible to provide a semiconductor module having a semiconductor chip, wiring formed on an insulating substrate, and a lead frame, and having a higher heat dissipation effect than conventional semiconductor modules. .
- the present invention is not limited to the above-described embodiments, and includes various modifications.
- the above embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the described configurations.
- it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
例えば、上記した実施例は本発明を分かり易く説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、ある実施例の構成に他の実施例の構成を加えることも可能である。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることが可能である。
Claims (6)
- 絶縁基板と、前記絶縁基板に形成された配線と、半導体チップと、リードフレームと、を備える半導体モジュールにおいて、
前記半導体チップは、一方の面が前記配線に接続され、他方の面が前記リードフレームに接続され、
前記配線は、前記リードフレームが接続されたフローティング配線を有し、
前記フローティング配線と前記リードフレームとの接続点は、前記絶縁基板の角部に位置することを特徴とする半導体モジュール。 - 請求項1の半導体モジュールにおいて、前記フローティング配線と前記リードフレームとの接続点は、前記リードフレームと前記配線との他の接続点よりも前記絶縁基板の外周側に位置することを特徴とする半導体モジュール。
- 請求項1または2の半導体モジュールにおいて、前記絶縁基板はセラミックスで形成されており、前記リードフレームは銅で形成されていることを特徴とする半導体モジュール。
- 請求項3の半導体モジュールにおいて、前記リードフレームの厚さは、1.0mm以上1.2mm以下であることを特徴とする半導体モジュール。
- 請求項1または2の半導体モジュールにおいて、前記絶縁基板の前記半導体チップとは反対側の面に放熱部材を有し、前記放熱部材は、前記絶縁基板を介して前記フローティング配線と重なるように配置されていることを特徴とする半導体モジュール。
- 請求項5の半導体モジュールにおいて、前記放熱部材は放熱フィンを有し、前記放熱フィンは、前記絶縁基板を介して前記フローティング配線と重なるように配置されていることを特徴とする半導体モジュール。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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DE112022001960.3T DE112022001960T5 (de) | 2021-06-24 | 2022-05-09 | Halbleitermodul |
CN202280040728.XA CN117480602A (zh) | 2021-06-24 | 2022-05-09 | 半导体模块 |
US18/569,679 US20240274490A1 (en) | 2021-06-24 | 2022-05-09 | Semiconductor module |
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JP2021104723A JP7551571B2 (ja) | 2021-06-24 | 2021-06-24 | 半導体モジュール |
JP2021-104723 | 2021-06-24 |
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WO2022270161A1 true WO2022270161A1 (ja) | 2022-12-29 |
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PCT/JP2022/019673 WO2022270161A1 (ja) | 2021-06-24 | 2022-05-09 | 半導体モジュール |
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US (1) | US20240274490A1 (ja) |
JP (1) | JP7551571B2 (ja) |
CN (1) | CN117480602A (ja) |
DE (1) | DE112022001960T5 (ja) |
WO (1) | WO2022270161A1 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS63110693A (ja) * | 1986-10-28 | 1988-05-16 | 株式会社東芝 | 半導体素子実装用基板 |
JP2004221516A (ja) * | 2002-11-22 | 2004-08-05 | Toyota Industries Corp | 半導体モジュールおよび半導体モジュール用リード |
JP2008171963A (ja) * | 2007-01-11 | 2008-07-24 | Hitachi Ltd | 半導体チップ冷却構造 |
JP2014222788A (ja) * | 2012-03-30 | 2014-11-27 | 三菱マテリアル株式会社 | パワーモジュール用基板の製造方法、ヒートシンク付パワーモジュール用基板の製造方法及びパワーモジュールの製造方法 |
JP2016146450A (ja) * | 2015-02-09 | 2016-08-12 | 株式会社デンソー | 電子装置 |
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JP2017054842A (ja) | 2015-09-07 | 2017-03-16 | 株式会社東芝 | 配線基板、半導体装置、及び半導体パッケージ |
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JPS63110693A (ja) * | 1986-10-28 | 1988-05-16 | 株式会社東芝 | 半導体素子実装用基板 |
JP2004221516A (ja) * | 2002-11-22 | 2004-08-05 | Toyota Industries Corp | 半導体モジュールおよび半導体モジュール用リード |
JP2008171963A (ja) * | 2007-01-11 | 2008-07-24 | Hitachi Ltd | 半導体チップ冷却構造 |
JP2014222788A (ja) * | 2012-03-30 | 2014-11-27 | 三菱マテリアル株式会社 | パワーモジュール用基板の製造方法、ヒートシンク付パワーモジュール用基板の製造方法及びパワーモジュールの製造方法 |
JP2016146450A (ja) * | 2015-02-09 | 2016-08-12 | 株式会社デンソー | 電子装置 |
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CN117480602A (zh) | 2024-01-30 |
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