CN117480602A - 半导体模块 - Google Patents

半导体模块 Download PDF

Info

Publication number
CN117480602A
CN117480602A CN202280040728.XA CN202280040728A CN117480602A CN 117480602 A CN117480602 A CN 117480602A CN 202280040728 A CN202280040728 A CN 202280040728A CN 117480602 A CN117480602 A CN 117480602A
Authority
CN
China
Prior art keywords
insulating substrate
lead frame
wiring
semiconductor module
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202280040728.XA
Other languages
English (en)
Inventor
竹内悠次郎
熊谷幸博
大内贵之
串间宇幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Power Semiconductor Device Ltd
Original Assignee
Hitachi Power Semiconductor Device Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Power Semiconductor Device Ltd filed Critical Hitachi Power Semiconductor Device Ltd
Publication of CN117480602A publication Critical patent/CN117480602A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明提供在具有半导体芯片、在绝缘基板形成的配线以及引线框的半导体模块中具有比以往更高的散热效果的半导体模块。本发明的半导体模块(10)具备绝缘基板(1)、在绝缘基板(1)形成的配线(2)、半导体芯片(3)以及引线框(4)，半导体芯片(3)的一个面与配线(2)连接，另一个面与引线框(4)连接，配线(2)具有与引线框(4)连接的浮动配线，浮动配线与引线框(4)的连接点位于绝缘基板(1)的角部。

Description

半导体模块
技术领域
本发明涉及半导体模块。
背景技术
以往，已知具备用于将固定在绝缘基板的半导体芯片与外部配线连接的引线框的半导体模块。例如，在下述的专利文献1中公开了一种搭载配线基板10的半导体封装100，该配线基板10具备：绝缘基板11，其由陶瓷材料构成，在一个主面形成了安装部件的配线层；以及基板13，其配置在绝缘基板11的另一侧，具有相对于绝缘基板11的外周缘向外侧突出的突出部13c，且厚度比绝缘基板11大。半导体芯片20的发射极电极连接用的发射极配线图案12a与集电极电极连接用的集电极配线图案12b通过引线框(发射极端子18a以及集电极端子18b)与外部电极连接。
现有技术文献
专利文献
专利文献1：日本特开2017-054842号公报
发明内容
发明要解决的课题
在上述的专利文献1中，能够通过配置在配线基板10的下表面的基板13的突出部13c来固定冷却构造部40，因此无需为了固定冷却构造部40而使用硅脂等热阻大的粘接剂，能够得到高的冷却性能。
然而，为了应对与半导体模块的高性能化、小型化相伴的大电流化、高集成化，要求与以往相比进一步提高半导体芯片的散热效果。
本发明是鉴于上述情况而作出的，其目的在于提供一种在具有半导体芯片、在绝缘基板上形成的配线、以及引线框的半导体模块中具有比以往更高的散热效果的半导体模块。
用于解决课题的手段
用于实现上述目的的本发明的一个方式是一种半导体模块，其具备：绝缘基板、形成在绝缘基板的配线、半导体芯片和引线框，半导体芯片的一个面与配线连接，另一个面与引线框连接，上述配线具有与引线框连接的浮动配线，该浮动配线与引线框的连接点位于绝缘基板的角部。
本发明的更具体的结构记载在专利保护范围中。
发明效果
根据本发明，能够提供一种在具有半导体芯片、形成在绝缘基板的配线、以及引线框的半导体模块中具有比以往更高的散热效果的半导体模块。
通过以下的实施方式的说明，上述以外的课题、结构以及效果变得明确。
附图说明
图1是表示本发明的功率半导体模块的结构的一例的立体图。
图2是从图1的A方向观察时的功率半导体模块的俯视图。
图3是从图1的B方向观察时的功率半导体模块的仰视图。
图4是从图1的C方向观察时的功率半导体模块的侧视图。
图5是从图1的D方向观察时的功率半导体模块的侧视图。
图6是将图1的俯视图的一部分结构简化的图。
图7是在图6的E-E截面观察时的功率半导体模块的截面图。
具体实施方式
以下，参照附图对本发明的半导体模块进行详细说明。图1是表示本发明的功率半导体模块的结构的一例的立体图。图2是从图1的A方向观察时的功率半导体模块的俯视图，图3是从图1的B方向观察时的功率半导体模块的仰视图，图4是从图1的C方向观察时的功率半导体模块的侧视图，图5是从图1的D方向观察时的功率半导体模块的侧视图。如图1和图2所示，本发明的一个实施方式的半导体模块10在绝缘基板1的表面上依次层叠了配线2、半导体芯片3以及引线框4。半导体芯片3的一个面与形成在绝缘基板1的配线2连接，另一个面与引线框4连接。在此，作为半导体芯片3的一例，示出了使用二极管芯片和IGBT芯片的例子，但并不限于此。
多个绝缘基板1(图1及图2中为3个绝缘基板1)收容在树脂壳体7中。虽然未图示，但是绝缘基板1的表面与配线2、半导体芯片3以及引线框4一起被绝缘树脂密封。绝缘基板1和配线2的材料没有特别限定，若举一例，绝缘基板1可使用陶瓷，配线2可使用铜。
如图3～图5所示，在绝缘基板1的与设置有半导体芯片3的面相反侧的面上设置了至少具有基板的散热部件6。散热部件6可以构成为还具有散热片6a。散热片6a的结构可以是图示的圆筒形状，也可以是未图示的平板形状。散热部件6的冷却方法可以是空冷也可以是水冷。在空冷的情况下，例如能够设置风扇来对散热部件6、散热片6a进行冷却。另外，在水冷的情况下，例如能够构成为设置冷却通路而使水、冷却介质与散热部件、散热片6a接触。
图6是将图1的俯视图的一部分结构简化的图。图7是在图6的E-E截面观察时的功率半导体模块的截面图。在图6中，简化地表示了图2的引线框4的形状。如图6所示，引线框4经由第一连接点4a与配线2连接。端子5例如设置在绝缘基板1的两侧，来自一侧端子5的电流经过配线2，并经由半导体芯片3、引线框4被引导至另一侧的端子5。
在此，在本实施例中，构成为作为配线2，例如具有与两侧的端子5之间的电流的通道等作为电路使用的配线不同的不作为电路使用的浮动的配线即浮动配线2a。并且，在绝缘基板1的角部，将浮动配线2a与引线框4在第二连接点4b的位置连接。
如图7所示，从半导体芯片3产生的热在半导体芯片3的正下方经由配线2、绝缘基板1向散热部件6传导从而散热(散热路径11)。另外，从半导体芯片3产生的热经由引线框4向第一连接点4a传导，并经由配线2、绝缘基板1向散热部件6传导从而散热(散热路径12)。
至此为止是现有结构中也存在的散热路径，但在本发明中，从半导体芯片3产生的热还经由引线框4向第二连接点4b传导。传导至第二连接点4b的热经由浮动配线2a、绝缘基板1向散热构件6传导从而散热(散热路径13)。
这样，通过将配线2中的不作为配线发挥功能的浮动配线2a与引线框4连接，除了现有结构的散热路径11、12之外，还能够通过从引线框4向浮动配线2a、绝缘基板1以及散热部件6传递热的散热路径13来提高散热效果。
浮动配线2a设置在绝缘基板1的角部，由此能够不与现有的散热路径11、散热路径12干涉地追加散热路径13，因此能够提高散热效果。
基于相同的理由，在提高散热效果方面，优选浮动配线2a与引线框4的第二连接点4b相对于引线框4与配线2的另一连接点即第一连接点4a位于绝缘基板1的外周侧。
在绝缘基板1由陶瓷形成，配线2由铜形成的情况下，引线框4的厚度优选为1.0mm以上且1.2mm以下。从降低热阻的观点出发，优选引线框4的厚度厚(厚度厚容易传递热量)(经由散热路径12、13的散热效果变高)。另一方面，从提高抗热疲劳性的观点出发，优选引线框4的厚度薄(铜的引线框4的热膨胀率比陶瓷的绝缘基板1的热膨胀率大，因此薄时的热应力变小)。
作为本发明的发明人的研究结果，为了使热阻的降低与抗热疲劳性平衡，优选引线框4的厚度为1.0mm以上且1.2mm以下。越是设置有第二连接点4b的绝缘基板1的角部，由绝缘基板1与引线框4的热膨胀率之差引起的热疲劳越大，但通过将引线框4的厚度设为上述范围，能够兼顾热阻的降低和抗热疲劳性。
优先将散热部件6配置为经由绝缘基板1与浮动配线2a重叠。通过在释放来自半导体芯片3的热的浮动配线2a的正下方设置散热部件6，散热路径13的路径长度最短，能够提高散热效果。另外，在散热构件6具有散热片6a的情况下，优选将散热片6a配置为经由绝缘基板1与浮动配线2a重叠。
如以上说明的那样，表示了根据本发明，能够提供在具有半导体芯片、在绝缘基板形成的配线、以及引线框的半导体模块中，具有比以往更高的散热效果的半导体模块。
此外，本发明并不限于上述的实施例，包含各种变形例。
例如，上述实施例是为了容易理解地说明本发明而详细说明的实施例，并不一定限于具备所说明的全部结构。另外，能够将某实施例的一部分结构置换为其他实施例的结构，也能够对某实施例的结构追加其他实施例的结构。另外，关于各实施例的一部分结构，能够进行其他结构的追加、删除、置换。
附图标记的说明
1…绝缘基板、2…配线、2a…浮动配线、3…半导体芯片、4…引线框架、4a…第一连接点、4b…第二连接点、5…端子、6…散热部件、6a…散热片、7…树脂壳体、10…半导体模块、11、12、13…散热路径。

Claims (6)

1.一种半导体模块，其具备：绝缘基板、在所述绝缘基板形成的配线、半导体芯片、以及引线框，
其特征在于，
所述半导体芯片的一个面与所述配线连接，另一个面与所述引线框连接，
所述配线具有与所述引线框连接的浮动配线，
所述浮动配线与所述引线框的连接点位于所述绝缘基板的角部。
2.根据权利要求1所述的半导体模块，其特征在于，
所述浮动配线与所述引线框的连接点相对于所述引线框与所述配线的另一连接点位于所述绝缘基板的外周侧。
3.根据权利要求1或2所述的半导体模块，其特征在于，
所述绝缘基板由陶瓷形成，所述引线框由铜形成。
4.根据权利要求3所述的半导体模块，其特征在于，
所述引线框的厚度为1.0mm以上且1.2mm以下。
5.根据权利要求1或2所述的半导体模块，其特征在于，
在所述绝缘基板的与所述半导体芯片相反侧的面具有散热部件，将所述散热部件配置为经由所述绝缘基板与所述浮动配线重叠。
6.根据权利要求5所述的半导体模块，其特征在于，
所述散热部件具有散热片，将所述散热片配置为经由所述绝缘基板与所述浮动配线重叠。
CN202280040728.XA 2021-06-24 2022-05-09 半导体模块 Pending CN117480602A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021-104723 2021-06-24
JP2021104723A JP2023003573A (ja) 2021-06-24 2021-06-24 半導体モジュール
PCT/JP2022/019673 WO2022270161A1 (ja) 2021-06-24 2022-05-09 半導体モジュール

Publications (1)

Publication Number Publication Date
CN117480602A true CN117480602A (zh) 2024-01-30

Family

ID=84544466

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202280040728.XA Pending CN117480602A (zh) 2021-06-24 2022-05-09 半导体模块

Country Status (4)

Country Link
JP (1) JP2023003573A (zh)
CN (1) CN117480602A (zh)
DE (1) DE112022001960T5 (zh)
WO (1) WO2022270161A1 (zh)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63110693A (ja) * 1986-10-28 1988-05-16 株式会社東芝 半導体素子実装用基板
JP3956886B2 (ja) * 2002-11-22 2007-08-08 株式会社豊田自動織機 半導体モジュールおよび半導体モジュール用リード
JP2008171963A (ja) * 2007-01-11 2008-07-24 Hitachi Ltd 半導体チップ冷却構造
JP2014112732A (ja) * 2012-03-30 2014-06-19 Mitsubishi Materials Corp ヒートシンク付パワーモジュール用基板及びパワーモジュール
JP2016146450A (ja) * 2015-02-09 2016-08-12 株式会社デンソー 電子装置
JP2017054842A (ja) 2015-09-07 2017-03-16 株式会社東芝 配線基板、半導体装置、及び半導体パッケージ

Also Published As

Publication number Publication date
JP2023003573A (ja) 2023-01-17
DE112022001960T5 (de) 2024-01-11
WO2022270161A1 (ja) 2022-12-29

Similar Documents

Publication Publication Date Title
US7642640B2 (en) Semiconductor device and manufacturing process thereof
CN111261598B (zh) 封装结构及其适用的电源模块
KR102172689B1 (ko) 반도체 패키지 및 그 제조방법
JPH08139477A (ja) プリント配線板装置
KR20060121671A (ko) 전력 모듈 패키지 구조체
JP2001284524A (ja) 電力用半導体モジュール
US20060220188A1 (en) Package structure having mixed circuit and composite substrate
JP2007095860A (ja) 半導体装置
JP4046623B2 (ja) パワー半導体モジュールおよびその固定方法
US7310224B2 (en) Electronic apparatus with thermal module
EP0694968A2 (en) Multi-chip module semiconductor device
JP2017054855A (ja) 半導体装置、及び半導体パッケージ
JP2002050722A (ja) 半導体パッケージおよびその応用装置
JP2012074425A (ja) パワーモジュール
CN112687640B (zh) 散热板，其制造方法，以及包括其的半导体封装
CN117480602A (zh) 半导体模块
CN114709185A (zh) 功率模块及其内部电气连接方法
JPH05110277A (ja) 半導体装置
JPH08274228A (ja) 半導体搭載基板、電力用半導体装置及び電子回路装置
CN112397472A (zh) 半导体装置
JPH09213847A (ja) 半導体集積回路装置及びこの製造方法並びにそれを用いた電子装置
JP2006294729A (ja) 半導体装置
JP2003133514A (ja) パワーモジュール
JP3894749B2 (ja) 半導体装置
JPS6329413B2 (zh)

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination