WO2022269714A1 - 表示装置 - Google Patents
表示装置 Download PDFInfo
- Publication number
- WO2022269714A1 WO2022269714A1 PCT/JP2021/023465 JP2021023465W WO2022269714A1 WO 2022269714 A1 WO2022269714 A1 WO 2022269714A1 JP 2021023465 W JP2021023465 W JP 2021023465W WO 2022269714 A1 WO2022269714 A1 WO 2022269714A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chip
- display device
- layer
- organic
- output terminals
- Prior art date
Links
- 239000010410 layer Substances 0.000 claims description 306
- 239000010408 film Substances 0.000 claims description 223
- 239000011229 interlayer Substances 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 46
- 238000007789 sealing Methods 0.000 claims description 30
- 239000002245 particle Substances 0.000 claims description 26
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 9
- 238000005401 electroluminescence Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 24
- 239000004065 semiconductor Substances 0.000 description 24
- 239000011347 resin Substances 0.000 description 20
- 229920005989 resin Polymers 0.000 description 20
- 238000002347 injection Methods 0.000 description 14
- 239000007924 injection Substances 0.000 description 14
- 239000011777 magnesium Substances 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 239000011575 calcium Substances 0.000 description 10
- 239000002585 base Substances 0.000 description 9
- 238000005452 bending Methods 0.000 description 8
- 229920001721 polyimide Polymers 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 7
- 239000009719 polyimide resin Substances 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 6
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 6
- 229910052744 lithium Inorganic materials 0.000 description 6
- PQXKHYXIUOZZFA-UHFFFAOYSA-M lithium fluoride Chemical compound [Li+].[F-] PQXKHYXIUOZZFA-UHFFFAOYSA-M 0.000 description 6
- 229910052749 magnesium Inorganic materials 0.000 description 6
- -1 polysiloxane Polymers 0.000 description 6
- 239000011734 sodium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- 229910052791 calcium Inorganic materials 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 230000005525 hole transport Effects 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- 229920000178 Acrylic resin Polymers 0.000 description 4
- 239000004925 Acrylic resin Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052789 astatine Inorganic materials 0.000 description 4
- RYXHOMYVWAEKHL-UHFFFAOYSA-N astatine atom Chemical compound [At] RYXHOMYVWAEKHL-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005336 cracking Methods 0.000 description 4
- 239000011572 manganese Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000002788 crimping Methods 0.000 description 3
- 150000008376 fluorenones Chemical class 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 150000004866 oxadiazoles Chemical class 0.000 description 3
- 150000007978 oxazole derivatives Chemical class 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910052708 sodium Inorganic materials 0.000 description 3
- PJANXHGTPQOBST-UHFFFAOYSA-N stilbene Chemical class C=1C=CC=CC=1C=CC1=CC=CC=C1 PJANXHGTPQOBST-UHFFFAOYSA-N 0.000 description 3
- 229940042055 systemic antimycotics triazole derivative Drugs 0.000 description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- UWRZIZXBOLBCON-VOTSOKGWSA-N (e)-2-phenylethenamine Chemical class N\C=C\C1=CC=CC=C1 UWRZIZXBOLBCON-VOTSOKGWSA-N 0.000 description 2
- VERMWGQSKPXSPZ-BUHFOSPRSA-N 1-[(e)-2-phenylethenyl]anthracene Chemical class C=1C=CC2=CC3=CC=CC=C3C=C2C=1\C=C\C1=CC=CC=C1 VERMWGQSKPXSPZ-BUHFOSPRSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 2
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 2
- 229910052769 Ytterbium Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 150000007857 hydrazones Chemical class 0.000 description 2
- 150000002460 imidazoles Chemical class 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229940079865 intestinal antiinfectives imidazole derivative Drugs 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 150000004986 phenylenediamines Chemical class 0.000 description 2
- 229920000553 poly(phenylenevinylene) Polymers 0.000 description 2
- 229920000548 poly(silane) polymer Polymers 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229910052700 potassium Inorganic materials 0.000 description 2
- 239000011591 potassium Substances 0.000 description 2
- 150000003219 pyrazolines Chemical class 0.000 description 2
- 239000002096 quantum dot Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 2
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 2
- PFNQVRZLDWYSCW-UHFFFAOYSA-N (fluoren-9-ylideneamino) n-naphthalen-1-ylcarbamate Chemical compound C12=CC=CC=C2C2=CC=CC=C2C1=NOC(=O)NC1=CC=CC2=CC=CC=C12 PFNQVRZLDWYSCW-UHFFFAOYSA-N 0.000 description 1
- NVWCQPYOGQBFDC-UHFFFAOYSA-N 1,2,3-tris(2-phenylethenyl)benzene Chemical class C=1C=CC=CC=1C=CC(C=1C=CC=2C=CC=CC=2)=CC=CC=1C=CC1=CC=CC=C1 NVWCQPYOGQBFDC-UHFFFAOYSA-N 0.000 description 1
- BCMCBBGGLRIHSE-UHFFFAOYSA-N 1,3-benzoxazole Chemical class C1=CC=C2OC=NC2=C1 BCMCBBGGLRIHSE-UHFFFAOYSA-N 0.000 description 1
- 150000004057 1,4-benzoquinones Chemical class 0.000 description 1
- YZVWKHVRBDQPMQ-UHFFFAOYSA-N 1-aminopyrene Chemical class C1=C2C(N)=CC=C(C=C3)C2=C2C3=CC=CC2=C1 YZVWKHVRBDQPMQ-UHFFFAOYSA-N 0.000 description 1
- DDTHMESPCBONDT-UHFFFAOYSA-N 4-(4-oxocyclohexa-2,5-dien-1-ylidene)cyclohexa-2,5-dien-1-one Chemical class C1=CC(=O)C=CC1=C1C=CC(=O)C=C1 DDTHMESPCBONDT-UHFFFAOYSA-N 0.000 description 1
- PNJWIWWMYCMZRO-UHFFFAOYSA-N 4-penten-2-one Chemical class CC(=O)CC=C PNJWIWWMYCMZRO-UHFFFAOYSA-N 0.000 description 1
- 239000005725 8-Hydroxyquinoline Substances 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910016036 BaF 2 Inorganic materials 0.000 description 1
- KAKZBPTYRLMSJV-UHFFFAOYSA-N Butadiene Chemical class C=CC=C KAKZBPTYRLMSJV-UHFFFAOYSA-N 0.000 description 1
- 229930192627 Naphthoquinone Natural products 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229920002396 Polyurea Polymers 0.000 description 1
- NRCMAYZCPIVABH-UHFFFAOYSA-N Quinacridone Chemical class N1C2=CC=CC=C2C(=O)C2=C1C=C1C(=O)C3=CC=CC=C3NC1=C2 NRCMAYZCPIVABH-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000005083 Zinc sulfide Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000001454 anthracenes Chemical class 0.000 description 1
- PYKYMHQGRFAEBM-UHFFFAOYSA-N anthraquinone Natural products CCC(=O)c1c(O)c2C(=O)C3C(C=CC=C3O)C(=O)c2cc1CC(=O)OC PYKYMHQGRFAEBM-UHFFFAOYSA-N 0.000 description 1
- 150000004056 anthraquinones Chemical class 0.000 description 1
- 229940058303 antinematodal benzimidazole derivative Drugs 0.000 description 1
- 150000004982 aromatic amines Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- OYLGJCQECKOTOL-UHFFFAOYSA-L barium fluoride Chemical compound [F-].[F-].[Ba+2] OYLGJCQECKOTOL-UHFFFAOYSA-L 0.000 description 1
- 229910001632 barium fluoride Inorganic materials 0.000 description 1
- 125000003785 benzimidazolyl group Chemical class N1=C(NC2=C1C=CC=C2)* 0.000 description 1
- IOJUPLGTWVMSFF-UHFFFAOYSA-N benzothiazole Chemical class C1=CC=C2SC=NC2=C1 IOJUPLGTWVMSFF-UHFFFAOYSA-N 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 150000001788 chalcone derivatives Chemical class 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001893 coumarin derivatives Chemical class 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229940083761 high-ceiling diuretics pyrazolone derivative Drugs 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- ORUIBWPALBXDOA-UHFFFAOYSA-L magnesium fluoride Chemical compound [F-].[F-].[Mg+2] ORUIBWPALBXDOA-UHFFFAOYSA-L 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002790 naphthalenes Chemical class 0.000 description 1
- 150000002791 naphthoquinones Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- WCPAKWJPBJAGKN-UHFFFAOYSA-N oxadiazole Chemical compound C1=CON=N1 WCPAKWJPBJAGKN-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- UFQXGXDIJMBKTC-UHFFFAOYSA-N oxostrontium Chemical compound [Sr]=O UFQXGXDIJMBKTC-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229960003540 oxyquinoline Drugs 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- DGBWPZSGHAXYGK-UHFFFAOYSA-N perinone Chemical class C12=NC3=CC=CC=C3N2C(=O)C2=CC=C3C4=C2C1=CC=C4C(=O)N1C2=CC=CC=C2N=C13 DGBWPZSGHAXYGK-UHFFFAOYSA-N 0.000 description 1
- 125000002080 perylenyl group Chemical group C1(=CC=C2C=CC=C3C4=CC=CC5=CC=CC(C1=C23)=C45)* 0.000 description 1
- FIZIRKROSLGMPL-UHFFFAOYSA-N phenoxazin-1-one Chemical compound C1=CC=C2N=C3C(=O)C=CC=C3OC2=C1 FIZIRKROSLGMPL-UHFFFAOYSA-N 0.000 description 1
- UOMHBFAJZRZNQD-UHFFFAOYSA-N phenoxazone Natural products C1=CC=C2OC3=CC(=O)C=CC3=NC2=C1 UOMHBFAJZRZNQD-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920003227 poly(N-vinyl carbazole) Polymers 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000004033 porphyrin derivatives Chemical class 0.000 description 1
- JEXVQSWXXUJEMA-UHFFFAOYSA-N pyrazol-3-one Chemical class O=C1C=CN=N1 JEXVQSWXXUJEMA-UHFFFAOYSA-N 0.000 description 1
- 150000003222 pyridines Chemical class 0.000 description 1
- PYWVYCXTNDRMGF-UHFFFAOYSA-N rhodamine B Chemical class [Cl-].C=12C=CC(=[N+](CC)CC)C=C2OC2=CC(N(CC)CC)=CC=C2C=1C1=CC=CC=C1C(O)=O PYWVYCXTNDRMGF-UHFFFAOYSA-N 0.000 description 1
- YYMBJDOZVAITBP-UHFFFAOYSA-N rubrene Chemical compound C1=CC=CC=C1C(C1=C(C=2C=CC=CC=2)C2=CC=CC=C2C(C=2C=CC=CC=2)=C11)=C(C=CC=C2)C2=C1C1=CC=CC=C1 YYMBJDOZVAITBP-UHFFFAOYSA-N 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 150000003967 siloles Chemical class 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- FVRNDBHWWSPNOM-UHFFFAOYSA-L strontium fluoride Chemical compound [F-].[F-].[Sr+2] FVRNDBHWWSPNOM-UHFFFAOYSA-L 0.000 description 1
- 229910001637 strontium fluoride Inorganic materials 0.000 description 1
- 125000005504 styryl group Chemical group 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 150000004867 thiadiazoles Chemical class 0.000 description 1
- 150000001651 triphenylamine derivatives Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052984 zinc sulfide Inorganic materials 0.000 description 1
- DRDVZXDWVBGGMH-UHFFFAOYSA-N zinc;sulfide Chemical compound [S-2].[Zn+2] DRDVZXDWVBGGMH-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
Definitions
- the present invention relates to display devices.
- organic EL display devices using organic electroluminescence (hereinafter also referred to as "EL") elements have attracted attention as display devices that can replace liquid crystal display devices.
- EL organic electroluminescence
- a flexible organic EL display device has been proposed in which an organic EL element or the like is formed on a flexible resin substrate layer.
- Patent Literature 1 describes a gap for maintaining a minimum gap between an LSI terminal and an LSI chip when the LSI chip is mounted in an opening of an insulating film formed as a region for mounting the LSI (large scale integration) chip.
- An LSI chip mounting flexible wiring board provided with holding means is disclosed.
- the flexible wiring board can be restrained from being bent by the spacing of the spacing means, it is possible to prevent the flexible wiring board from straddling a plurality of terminals arranged side by side. Since the spacing means are arranged in the gap holding means, the conductive particles forming the anisotropic conductive film may aggregate between the spacing holding means and the bumps of the LSI chip, and the aggregated conductive particles may be linked. . In that case, there is a risk of short-circuiting between adjacent terminals due to the conductive particles that are connected, so there is room for improvement.
- the present invention has been made in view of this point, and its object is to suppress short-circuiting between terminals in the chip mounting portion.
- a display device comprises a flexible substrate layer, a thin film transistor layer provided on the flexible substrate layer, and a display region provided on the thin film transistor layer.
- a light-emitting element layer in which a plurality of light-emitting elements are arranged corresponding to the plurality of sub-pixels;
- a frame region is provided around the display region; and
- a terminal portion extends in one direction at an end of the frame region.
- a chip mounting portion having a rectangular shape in a plan view and having long sides extending along the direction in which the terminal portion extends is provided, and a plurality of chip mounting portions are arranged in a row in the chip mounting portion.
- the display device comprising:
- the chip mounting portion is characterized in that a chip support is provided between the plurality of chip terminals.
- FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the invention.
- FIG. 2 is a plan view of the display area of the organic EL display panel that constitutes the organic EL display device according to the first embodiment of the present invention.
- FIG. 3 is a cross-sectional view of the display area of the organic EL display panel that constitutes the organic EL display device according to the first embodiment of the invention.
- FIG. 4 is an equivalent circuit diagram of a thin film transistor layer forming an organic EL display panel of the organic EL display device according to the first embodiment of the present invention.
- FIG. 5 is a cross-sectional view showing an organic EL layer forming an organic EL display panel of the organic EL display device according to the first embodiment of the present invention.
- FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the invention.
- FIG. 2 is a plan view of the display area of the organic EL display panel that constitutes
- FIG. 6 is a plan view of a chip mounting portion and its surroundings in the frame region of the organic EL display panel of the organic EL display device according to the first embodiment of the present invention.
- FIG. 7 is a plan view showing output terminals and a chip support in a chip mounting portion in the frame area of the organic EL display panel of the organic EL display device according to the first embodiment of the present invention.
- FIG. 8 is a plan view showing input terminals and a chip support in a chip mounting portion in the frame area of the organic EL display panel of the organic EL display device according to the first embodiment of the present invention.
- 9 is a plan view showing the edge of the integrated circuit chip to be mounted and the conductive particles in FIG. 7.
- FIG. 10 is a cross-sectional view of the organic EL display device taken along line XX in FIG.
- FIG. 11 is a cross-sectional view of the organic EL display device taken along line XI-XI in FIG.
- FIG. 12 is a cross-sectional view of the organic EL display along line XII-XII in FIG.
- FIG. 13 is a cross-sectional view of a modification of the organic EL display device according to the first embodiment of the invention, and corresponds to FIG. 14 is a plan view showing output terminals and a chip support in a chip mounting portion in a frame region of an organic EL display panel constituting an organic EL display device according to the second embodiment of the present invention, which corresponds to FIG. It is a figure to do.
- FIG. 14 is a plan view showing output terminals and a chip support in a chip mounting portion in a frame region of an organic EL display panel constituting an organic EL display device according to the second embodiment of the present invention, which corresponds to
- FIG. 15 is a plan view of a modification of the organic EL display panel that constitutes the organic EL display device according to the second embodiment of the invention, and corresponds to FIG. 16 is a plan view showing output terminals and a chip support in a chip mounting portion in a frame region of an organic EL display panel of an organic EL display device according to a third embodiment of the present invention, which corresponds to FIG. is.
- FIG. 17 is a plan view of a first modified example of the organic EL display panel of the organic EL display device according to the third embodiment of the invention, which corresponds to FIG.
- FIG. 18 is a plan view of a second modified example of the organic EL display panel of the organic EL display device according to the third embodiment of the invention, which corresponds to FIG. FIG.
- FIG. 19 is a plan view of a third modified example of the organic EL display panel of the organic EL display device according to the third embodiment of the invention, which corresponds to FIG.
- FIG. 20 is an enlarged plan view of a chip mounting portion in the frame area of the organic EL display panel of the organic EL display device according to the fourth embodiment of the invention, and corresponds to FIG.
- FIG. 1 is a plan view showing a schematic configuration of the organic EL display device 70a of this embodiment.
- FIG. 2 is a plan view of the display area D of the organic EL display panel 50a that constitutes the organic EL display device 70a.
- 3 is a cross-sectional view of the display area D of the organic EL display panel 50a.
- FIG. 4 is an equivalent circuit diagram of the thin film transistor layer 30 forming the organic EL display panel 50a.
- FIG. 5 is a cross-sectional view showing the organic EL layer 33 forming the organic EL display panel 50a.
- FIG. 6 is a plan view of the chip mounting portion M and its surroundings in the frame area F of the organic EL display panel 50a.
- 7 is a plan view showing the first output terminal 18g, the second output terminal 18h, and the chip support Sa in the chip mounting portion M of the frame area F of the organic EL display panel 50a.
- FIG. 8 is a plan view showing the input terminal 18j and the chip support Sb in the chip mounting portion M of the frame area F of the organic EL display panel 50a.
- 9 is a plan view showing the end E of the integrated circuit chip 60 to be mounted and the conductive particles 64 in FIG.
- FIG. 10 is a cross-sectional view of an organic EL display device 70aa that is a modification of the organic EL display device 70a, and corresponds to FIG.
- the organic EL display device 70a includes, as shown in FIG. 1, an organic EL display panel 50a, an integrated circuit chip 60 mounted on a chip mounting portion M of the organic EL display panel 50a, which will be described later, and the organic EL display panel 50a. and a flexible printed wiring board 55 mounted on the terminal portion T.
- the organic EL display panel 50a includes, for example, a rectangular display area D for displaying an image, and a frame area F provided around the display area D in a frame shape.
- the rectangular display area D is exemplified, but the rectangular shape includes, for example, a shape with arc-shaped sides, a shape with arc-shaped corners, and a shape with arc-shaped corners.
- a substantially rectangular shape such as a shape with a notch is also included.
- a plurality of sub-pixels P are arranged in a matrix. Further, in the display region D, as shown in FIG. 2, for example, sub-pixels P having a red light-emitting region Lr for displaying red, sub-pixels P having a green light-emitting region Lg for displaying green, and a sub-pixel P having a blue light-emitting region Lb for displaying blue is provided so as to be adjacent to each other. In addition, in the display area D, for example, one pixel is configured by three adjacent sub-pixels P each having a red light emitting area Lr, a green light emitting area Lg, and a blue light emitting area Lb.
- a terminal portion T is provided so as to extend in one direction (horizontal direction in the drawing) at the lower end of the frame region F in FIG. Further, in the frame region F, as shown in FIG. 1, a chip mounting portion M is provided between the display region D and the terminal portion T so as to extend in one direction (horizontal direction in the figure). As shown in FIG. 1, the chip mounting portion M is provided in a rectangular shape in plan view so that the long side extends along the direction in which the terminal portion T extends.
- the organic EL display panel 50a includes a flexible substrate layer 10, a thin film transistor (hereinafter also referred to as "TFT") layer 30 provided on the flexible substrate layer 10, An organic EL element layer 40 provided as a light emitting element layer on the TFT layer 30 and a sealing film 45 provided to cover the organic EL element layer 40 are provided.
- TFT thin film transistor
- the flexible substrate layer 10 is made of, for example, polyimide resin and has flexibility. Although the flexible substrate layer 10 made of resin such as polyimide resin is exemplified in this embodiment, the flexible substrate layer 10 may be made of metal such as a metal film or a thin metal plate.
- the TFT layer 30 includes a base coat film 11 provided on the flexible substrate layer 10, and a plurality of first TFTs 9a and a plurality of second TFTs 9b provided on the base coat film 11 (see FIG. 4). , a plurality of third TFTs 9c and a plurality of capacitors 9d; there is
- a base coat film 11 a semiconductor pattern layer such as a semiconductor layer 12a to be described later, a gate insulating film 13, and first layers such as a gate line 14g to be described later are formed.
- a fourth wiring layer such as lines 20a and a second planarization film 21a are laminated in this order.
- the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are, for example, single-layer films or laminated films of inorganic insulating films such as silicon nitride, silicon oxide, and silicon oxynitride. It is composed of
- a plurality of gate lines 14g are provided as a first wiring layer so as to extend parallel to each other in the horizontal direction in the drawings.
- a plurality of light emission control lines 14e are provided as a first wiring layer so as to extend parallel to each other in the horizontal direction in the drawings.
- each light emission control line 14e is provided so as to be adjacent to each gate line 14g, as shown in FIG.
- a plurality of source lines 18f are provided as a second wiring layer so as to extend parallel to each other in the longitudinal direction of the drawings.
- the TFT layer 30 as shown in FIG.
- each sub-pixel P is provided with a first TFT 9a, a second TFT 9b, a third TFT 9c and a capacitor 9d.
- the first TFT 9a is electrically connected to the corresponding gate line 14g, source line 18f and second TFT 9b in each sub-pixel P, as shown in FIG.
- the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, and a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, which are provided on the base coat film 11 in this order. It has a source electrode 18a and a drain electrode 18b.
- FIG. 3 the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, and a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, which are provided on the base coat film 11 in this order. It has a source electrode 18a and a drain electrode 18b.
- the semiconductor layer 12a is provided in an island shape on the base coat film 11, and has a channel region, a source region and a drain region as will be described later.
- the gate insulating film 13 is provided so as to cover the semiconductor layer 12a.
- the gate electrode 14a is provided on the gate insulating film 13 so as to overlap with the channel region of the semiconductor layer 12a.
- the first interlayer insulating film 15 and the second interlayer insulating film 17 are provided in order so as to cover the gate electrode 14a.
- the source electrode 18a and the drain electrode 18b are provided on the second interlayer insulating film 17 so as to be separated from each other, as shown in FIG.
- the source electrode 18a and the drain electrode 18b are connected through respective contact holes formed in the laminated film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17. It is electrically connected to the source region and the drain region of the semiconductor layer 12a.
- the second TFT 9b is electrically connected to the corresponding first TFT 9a, power supply line 20a and third TFT 9c in each sub-pixel P, as shown in FIG.
- the second TFT 9b has substantially the same structure as the first TFT 9a and the third TFT 9c described later.
- the third TFT 9c is electrically connected to the corresponding second TFT 9b, the first electrode 31a of the organic EL element 35 described later, and the light emission control line 14e.
- the third TFT 9c includes a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, and a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, and a semiconductor layer 12b. It has a source electrode 18c and a drain electrode 18d.
- FIG. 1 As shown in FIG. 4, in each sub-pixel P, the third TFT 9c is electrically connected to the corresponding second TFT 9b, the first electrode 31a of the organic EL element 35 described later, and the light emission control line 14e.
- the third TFT 9c includes a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, a first interlayer insulating film 15, a second interlayer insulating film
- the semiconductor layer 12b is provided in an island shape on the base coat film 11 and has a channel region, a source region and a drain region like the semiconductor layer 12a.
- the gate insulating film 13 is provided so as to cover the semiconductor layer 12b, as shown in FIG.
- the gate electrode 14b is provided on the gate insulating film 13 so as to overlap with the channel region of the semiconductor layer 12b.
- the first interlayer insulating film 15 and the second interlayer insulating film 17 are provided in order so as to cover the gate electrode 14b.
- the source electrode 18c and the drain electrode 18d are provided on the second interlayer insulating film 17 so as to be separated from each other, as shown in FIG.
- the source electrode 18c and the drain electrode 18d are connected through respective contact holes formed in the laminated film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17. It is electrically connected to the source region and the drain region of the semiconductor layer 12b.
- first TFT 9a, the second TFT 9b and the third TFT 9c of the top gate type are illustrated in this embodiment, the first TFT 9a, the second TFT 9b and the third TFT 9c may be of the bottom gate type.
- the capacitor 9d is electrically connected to the corresponding first TFT 9a and power supply line 20a in each sub-pixel P, as shown in FIG.
- the capacitor 9d includes a lower conductive layer 14c provided as a first wiring layer, a first interlayer insulating film 15 provided to cover the lower conductive layer 14c, and a first interlayer insulating film 15 provided to cover the lower conductive layer 14c.
- An upper conductive layer 16c is provided as a third wiring layer on the insulating film 15 so as to overlap with the lower conductive layer 14c.
- the upper conductive layer 16c is electrically connected to the power line 20a through a contact hole (not shown) formed in the second interlayer insulating film 17 and the first planarizing film 19a.
- the first planarizing film 19a and the second planarizing film 21a have flat surfaces in the display area D, and are made of organic resin materials such as polyimide resin and acrylic resin, or polysiloxane-based SOG (spin on glass). ) is composed of materials, etc.
- a relay electrode 20b is provided as a fourth wiring layer. .
- the organic EL element layer 40 includes a plurality of first electrodes 31a provided in order corresponding to a plurality of sub-pixels P, a common edge cover 32a, a plurality of organic EL layers 33, and a common second electrode 34.
- the first electrode 31a, the organic EL layer 33, and the second electrode 34 constitute an organic EL element 35 (see FIG. 4). 35 are arranged in a matrix.
- the plurality of first electrodes 31a are provided in a matrix on the second planarization film 21a so as to correspond to the plurality of sub-pixels P, as shown in FIG.
- the first electrode 31a is formed through a contact hole formed in the first planarizing film 19a, the relay electrode 20b, and a contact hole formed in the second planarizing film 21a. It is electrically connected to the drain electrode 18d of each third TFT 9c.
- the first electrode 31 a also has a function of injecting holes into the organic EL layer 33 .
- the first electrode 31a is more preferably made of a material having a large work function in order to improve the efficiency of hole injection into the organic EL layer 33 .
- examples of materials constituting the first electrode 31a include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), and gold (Au). , titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium ( metal materials such as Ir) and tin (Sn).
- the material forming the first electrode 31a may be an alloy such as astatine (At)/astatine oxide (AtO 2 ).
- the material forming the first electrode 31a is, for example, conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). There may be. Also, the first electrode 31a may be formed by laminating a plurality of layers made of the above materials. Compound materials having a large work function include, for example, indium tin oxide (ITO) and indium zinc oxide (IZO).
- the edge cover 32a is provided in a lattice shape so as to cover the peripheral edge of each first electrode 31a.
- the edge cover 32a is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.
- each organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light emitting layer 3, an electron transport layer 4 and an electron injection layer provided in order on the first electrode 31a.
- Layer 5 is provided.
- the hole injection layer 1 is also called an anode buffer layer, and has the function of bringing the energy levels of the first electrode 31 a and the organic EL layer 33 close to each other and improving the efficiency of hole injection from the first electrode 31 a to the organic EL layer 33 .
- Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives and the like.
- the hole transport layer 2 has a function of improving the transport efficiency of holes from the first electrode 31 a to the organic EL layer 33 .
- Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylene vinylene, polysilane, triazole derivatives, and oxadiazole.
- the light-emitting layer 3 In the light-emitting layer 3, holes and electrons are injected from the first electrode 31a and the second electrode 34 when a voltage is applied by the first electrode 31a and the second electrode 34, and the holes and electrons are recombined. area.
- the light-emitting layer 3 is made of a material with high light-emitting efficiency. Examples of materials constituting the light-emitting layer 3 include metal oxinoid compounds [8-hydroxyquinoline metal complex], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, and coumarin derivatives.
- the electron transport layer 4 has a function of efficiently transferring electrons to the light emitting layer 3 .
- the materials constituting the electron transport layer 4 include, for example, organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, and fluorenone derivatives. , silole derivatives, and metal oxinoid compounds.
- the electron injection layer 5 has the function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 close to each other and improving the efficiency with which electrons are injected from the second electrode 34 into the organic EL layer 33. With this function, The driving voltage of the organic EL element can be lowered.
- the electron injection layer 5 is also called a cathode buffer layer.
- examples of materials constituting the electron injection layer 5 include lithium fluoride (LiF), magnesium fluoride (MgF 2 ), calcium fluoride (CaF 2 ), strontium fluoride (SrF 2 ), and barium fluoride.
- inorganic alkali compounds such as (BaF 2 ), aluminum oxide (Al 2 O 3 ), strontium oxide (SrO), and the like.
- the second electrode 34 is provided on the plurality of organic EL layers 33 so as to be common to the plurality of sub-pixels P, that is, to cover each organic EL layer 33 and the edge cover 32a as shown in FIG. there is
- the second electrode 34 also has a function of injecting electrons into the organic EL layer 33 .
- the second electrode 34 is more preferably made of a material with a small work function in order to improve the efficiency of injecting electrons into the organic EL layer 33 .
- examples of materials constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), and sodium (Na).
- the second electrode 34 is composed of, for example, magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), astatine (At)/astatine oxide (AtO 2 ), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), lithium fluoride (LiF)/calcium (Ca)/aluminum (Al), etc.
- the second electrode 34 may be formed of conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). . Also, the second electrode 34 may be formed by laminating a plurality of layers made of the above materials.
- Examples of materials with a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg)/copper (Cu), magnesium (Mg)/silver (Ag), sodium (Na)/potassium (K), lithium (Li)/aluminum (Al), lithium (Li)/calcium (Ca)/aluminum (Al), lithium fluoride (LiF)/calcium (Ca)/aluminum (Al) etc.
- the sealing film 40 is provided so as to cover the second electrode 34, and the first inorganic sealing film 41, the organic sealing film 42 and the second sealing film 42 are laminated on the second electrode 34 in this order. It has an inorganic sealing film 43 and has a function of protecting the organic EL layer 33 of the organic EL element 35 from moisture and oxygen.
- the first inorganic sealing film 41 and the second inorganic sealing film 43 are composed of an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.
- the organic sealing film 42 is made of an organic resin material such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.
- a first damming wall for suppressing the spreading of the ink forming the organic sealing film 42 is provided in a frame shape so as to surround the display region D.
- a second damming wall is provided in a frame shape so as to surround the first damming wall.
- the organic EL display panel 50a includes, in the chip mounting portion M of the frame area F, a chip under-chip circuit portion C provided in a rectangular shape extending in the lateral direction in the drawing, and a chip under-chip A plurality of first output-side terminal wirings 14tc and a plurality of second output-side terminal wirings 14td provided to extend parallel to each other on the display area D side (upper side in the figure) of the circuit section C, and under the chip.
- a plurality of input side terminal wirings 14tf are provided so as to extend parallel to each other on the terminal portion T side (lower side in the drawing) of the circuit portion C. As shown in FIG. Here, as shown in FIGS.
- the plurality of first output terminal wirings 14tc and the plurality of second output terminal wirings 14td are arranged along the extending direction of the chip mounting portion M (horizontal direction in the drawings). are provided alternately.
- the first output-side terminal wiring 14tc, the second output-side terminal wiring 14td, and the input-side terminal wiring 14tf are provided as a first wiring layer.
- the organic EL display panel 50a has the display area D of the under-chip circuit section C as a chip terminal on the side of the display area D of the under-chip circuit section C in the chip mounting area M of the frame area F.
- the plurality of first output terminals 18g and the plurality of second output terminals 18h are staggered along the extending direction of the chip mounting portion M (horizontal direction in the drawings). are provided alternately.
- the first output terminal 18g, the second output terminal 18h and the input terminal 18j are provided as a second wiring layer. Further, the plurality of first output terminals 18g are laminated on the plurality of first output terminal wirings 14tc, respectively, and are electrically connected to the plurality of first output terminal wirings 14tc, respectively. Further, as shown in FIG. 10, the plurality of second output terminals 18h are laminated on the plurality of second output terminal wirings 14td, respectively, and are electrically connected to the plurality of second output terminal wirings 14td. It is connected. Further, the plurality of input terminals 18j are stacked on the plurality of input terminal wirings 14tf and electrically connected to the plurality of input terminal wirings 14tf.
- the organic EL display panel 50a has a plurality of output terminals 18g between the plurality of first output terminals 18g and a plurality of second output terminals 18h in the chip mounting portion M of the frame region F.
- a chip support body Sa integrally provided between both of the input terminals 18j in a comb shape, and a chip support body Sb provided in an island shape one by one between a plurality of input terminals 18j.
- the chip support Sa is provided on the first inorganic insulating layer 15a formed on the same layer as the first interlayer insulating film 15 and made of the same material, and on the first inorganic insulating layer 15a.
- the organic insulating layer 19b is formed to be thicker at the central portion in the width direction than at both end portions in the width direction.
- the second output terminal wiring 14td and the second output terminal 18h are arranged at both ends of the chip support Sa in the width direction. Since the gap between the integrated circuit chip 60 and the chip support Sa is narrowed, the panel is prevented from flexing at the first output terminal 18g and the second output terminal 18h when the chip is crimped. Disconnection of the output terminal 18g, the second output terminal 18h, the first output terminal wiring 14tc, and the second output terminal wiring 14td can be suppressed (see FIG. 11). In addition, as shown in FIG. 6, the display area D side of the chip support Sa is arranged outside the chip mounting portion M (peripheral edge E of the integrated circuit chip 60). Also, since the gap between the integrated circuit chip 60 and the chip support Sa is narrowed, it is possible to suppress the bending of the panel when the chip is crimped (see FIG. 12).
- the chip support Sb is provided on the first inorganic insulating layer 15a formed of the same material as the first interlayer insulating film 15 in the same layer, and on the first inorganic insulating layer 15a.
- the input-side terminal wiring 14tf and the input terminals 18j are extended to both ends in the width direction of the chip support Sb, the gap between the integrated circuit chip 60 and the chip support Sb is narrowed. Therefore, the input terminal 18j and the input-side terminal wiring 14tf can be prevented from breaking. Further, since the terminal portion T side of the chip support Sb is arranged outside the chip mounting portion M as shown in FIG. Since the gap between is narrowed, it is possible to suppress the bending of the panel when the chip is crimped.
- the organic EL display device 70a including the chip supports Sa and Sb each having a single-layer structure of the organic insulating layer is exemplified.
- the organic EL display device 70aa may be provided with a chip support Saa having a two-layer structure.
- the chip support Saa includes, as shown in FIG. a second inorganic insulating layer 17a provided on the insulating layer 15a and made of the same material as the second interlayer insulating film 17 in the same layer; and a first planarizing film 19a provided on the second inorganic insulating layer 17a.
- the first organic insulating layer 19b is formed to be thicker at the central portion in the width direction than at both end portions in the width direction.
- the second organic insulating layer 21b is provided narrower than the first organic insulating layer 19b.
- a plurality of bumps 61 are provided on the back surface of the integrated circuit chip 60, as shown in FIG.
- the plurality of chip terminals of the plurality of first output terminals 18g, the plurality of second output terminals 18h, and the plurality of input terminals 18j provided in the chip mounting portion M of the frame area F of the organic EL display panel 50a are As shown in FIGS. 7 and 8, they are provided so as to correspond to the plurality of bumps 61 .
- the plurality of chip terminals (first output terminal 18g, second output terminal 18h, input terminal 18j) and the plurality of bumps 61 are connected via an anisotropic conductive film 65 as shown in FIGS.
- the anisotropic conductive film 65 includes a resin material 63 made of, for example, thermosetting resin, and conductive particles 64 dispersed in the resin material 63 .
- a flexible printed circuit board (FPC: flexible printed circuits) 55 is mounted on the terminal portion T via an anisotropic conductive film 65 .
- a gate signal is input to the first TFT 9a through the gate line 14g to turn on the first TFT 9a, and the gate of the second TFT 9b is turned on through the source line 18f.
- a predetermined voltage corresponding to the source signal is written to the electrode and the capacitor 9d, and when the light emission control signal is input to the third TFT 9c through the light emission control line 14e, the third TFT 9c is turned on, and the gate voltage of the second TFT 9b is increased.
- the corresponding current is supplied from the power supply line 20a to the organic EL layer 33, the light-emitting layer 3 of the organic EL layer 33 emits light to display an image.
- the gate voltage of the second TFT 9b is held by the capacitor 9d. maintained in each sub-pixel P.
- the manufacturing method of the organic EL display device of the present embodiment includes an organic EL display panel manufacturing process including a TFT layer forming process, an organic EL element layer forming process and a sealing film forming process, and a mounting process.
- ⁇ Organic EL display panel manufacturing process ⁇ ⁇ TFT layer forming process> First, for example, after coating a non-photosensitive polyimide resin (thickness of about 10 ⁇ m) on a glass substrate, the flexible substrate layer 10 is formed by pre-baking and post-baking the coating film. .
- a silicon oxide film (thickness of about 500 nm) and a silicon nitride film (thickness of about 100 nm) are sequentially formed on the substrate surface on which the flexible substrate layer 10 is formed by, for example, a plasma CVD method.
- a base coat film 11 is formed.
- an amorphous silicon film (about 50 nm thick) is formed by plasma CVD on the surface of the substrate on which the base coat film 11 is formed, and the amorphous silicon film is crystallized by laser annealing or the like to form a polysilicon film.
- the semiconductor film is patterned to form a semiconductor pattern layer such as the semiconductor layer 12a.
- an inorganic insulating film (approximately 100 nm) such as a silicon oxide film is formed on the substrate surface on which the semiconductor pattern layer is formed, for example, by plasma CVD, and a gate insulating film is formed so as to cover the semiconductor layer 12a and the like. form 13.
- the molybdenum film is patterned to form the gate line 14g and the first output side.
- a first wiring layer including the terminal wiring 14tc, the second output side terminal wiring 14td, the input side terminal wiring 14tf, and the like is formed.
- a silicon nitride film (thickness of about 100 nm) is formed by plasma CVD, for example, on the surface of the substrate on which the semiconductor layer 12a having the intrinsic region and the conductor region is formed, thereby forming the first interlayer insulating film 15. to form
- the molybdenum film is patterned to form the upper conductive layer 16c and the like. to form a third wiring layer.
- a silicon oxide film (thickness of about 300 nm) and a silicon nitride film (thickness of about 200 nm) are sequentially formed on the substrate surface on which the third wiring layer is formed by, for example, a plasma CVD method.
- a two-layer insulating film 17 is formed.
- a titanium film (about 50 nm thick), an aluminum film (about 600 nm thick), and a titanium film (about 50 nm thick) were formed in this order on the surface of the substrate where the contact hole was formed, by, for example, a sputtering method. Afterwards, these metal laminated films are patterned to form a second wiring layer including the source line 18f, the first output terminal 18g, the second output terminal 18h, the input terminal 18j, and the like.
- the coating film is , pre-bake, exposure, development and post-bake are performed to form the first planarizing film 19a, the organic insulating layer 19b, and the like.
- the organic insulating layer 19b is half-exposed using, for example, a gray-tone mask or the like, so that the center portion in the width direction is formed thicker than the both end portions in the width direction.
- a titanium film (about 50 nm thick), an aluminum film (about 600 nm thick), and a titanium film (about 50 nm thick) are formed on the substrate surface on which the first planarizing film 19a and the like are formed by, for example, a sputtering method. After forming films in order, these metal laminated films are patterned to form a fourth wiring layer such as the power supply line 20a.
- the surface of the substrate on which the fourth wiring layer is formed is coated with a polyimide-based photosensitive resin film (thickness of about 2.5 ⁇ m) by, for example, a spin coating method or a slit coating method.
- a polyimide-based photosensitive resin film thickness of about 2.5 ⁇ m
- the TFT layer 30 can be formed as described above.
- a first electrode 31a, an edge cover 32a, an organic EL layer 33 (hole injection layer 1, positive A hole-transporting layer 2, a light-emitting layer 3, an electron-transporting layer 4, an electron-injecting layer 5) and a second electrode 34 are formed to form an organic EL element layer 40.
- FIG. 1 An electrode 31a, an edge cover 32a, an organic EL layer 33 (hole injection layer 1, positive A hole-transporting layer 2, a light-emitting layer 3, an electron-transporting layer 4, an electron-injecting layer 5) and a second electrode 34 are formed to form an organic EL element layer 40.
- ⁇ Sealing film forming process> First, using a mask, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is applied to the surface of the substrate on which the organic EL element layer 40 formed in the organic EL element layer forming step is formed. is deposited by the plasma CVD method to form the first inorganic sealing film 41 .
- an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is applied to the surface of the substrate on which the organic EL element layer 40 formed in the organic EL element layer forming step is formed. is deposited by the plasma CVD method to form the first inorganic sealing film 41 .
- an organic resin material such as an acrylic resin is deposited on the surface of the substrate on which the first inorganic sealing film 41 is formed by, for example, an inkjet method to form an organic sealing film 42 .
- an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD on the surface of the substrate on which the organic sealing film 42 is formed. 2.
- a sealing film 45 is formed by forming an inorganic sealing film 43 .
- a laser beam is irradiated from the glass substrate side of the flexible substrate layer 10 to achieve flexibility.
- the glass substrate is peeled off from the bottom surface of the substrate layer 10, and then a protective sheet (not shown) on the back side is attached to the bottom surface of the flexible substrate layer 10 from which the glass substrate has been peeled off.
- the organic EL display panel 50a can be manufactured as described above.
- the protective sheet on the surface side of the organic EL display panel 50a manufactured in the organic EL display panel manufacturing process is irradiated with, for example, a laser beam, thereby partially removing the protective sheet and forming the chip mounting portion M. and the terminal portion T is exposed.
- the anisotropic conductive film 65 is temporarily fixed to the chip mounting portion M and the terminal portion T.
- the integrated circuit chip 60 and the flexible printed wiring board 55 are pressed with a crimping tool, thereby compressing the chip.
- An integrated circuit chip 60 and a flexible printed wiring board 55 are mounted on the mounting portion M and the terminal portion T, respectively.
- the organic EL display device 70a of the present embodiment can be manufactured.
- the chip in the chip mounting portion M of the frame area F, the chip is mounted between the plurality of first output terminals 18g and between the plurality of second output terminals 18h.
- Supports Sa are provided in the shape of both comb teeth, and chip supports Sb are provided like islands one by one between a plurality of input terminals 18j. Therefore, in the mounting process, the conductive particles 64 in the anisotropic conductive film 65 are pushed out by the chip support member Sa and the chip support member Sb to move, thereby forming the first output terminal 18g, the second output terminal 18h, and the second output terminal 18h.
- the organic EL display device 70a of the present embodiment in the chip mounting portion M of the frame area F, the plurality of first output terminals 18g, the plurality of second output terminals 18h, and the plurality of input terminals 18j for each chip. Since the chip supports Sa and Sb are provided near the terminals, it is possible to suppress bending of the organic EL display panel 50a near the bumps 61 of the integrated circuit chip 60 during the mounting process.
- the generation of cracks in the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 of the organic EL display panel 50a can be suppressed, and the gate insulating film 13 and the first interlayer insulating film 17 can be prevented from cracking. Breakage of the first output-side terminal wiring 14tc, the second output-side terminal wiring 14td, and the input-side terminal wiring 14tf provided between the interlayer insulating films 15 can be suppressed.
- FIG. 14 shows the first output terminal 18g, the second output terminal 18h, and the third output terminal 18i in the chip mounting portion M in the frame area F of the organic EL display panel 50b constituting the organic EL display device of this embodiment. and a chip support Sc, and is a view corresponding to FIG. 7 .
- 15 is a plan view of an organic EL display panel 50ba, which is a modification of the organic EL display panel 50b, and corresponds to FIG.
- the same parts as those in FIGS. 1 to 13 are denoted by the same reference numerals, and detailed description thereof will be omitted.
- the organic EL display device 70a including the organic EL display panel 50a provided with the output terminals 18g and 18h having a two-stage structure in plan view is exemplified in the present embodiment.
- An organic EL display device including an organic EL display panel 50b provided with three-tiered output terminals 18g, 18h and 18i is illustrated.
- the organic EL display device of this embodiment includes an organic EL display panel 50b and an integrated circuit chip mounted on a chip mounting portion M of the organic EL display panel 50b. 60, and a flexible printed wiring board 55 mounted on the terminal portion T of the organic EL display panel 50b.
- the organic EL display panel 50b includes, for example, a rectangular display area D for image display and a frame-like display area around the display area D. and a frame area F which is set.
- the organic EL display panel 50b includes a flexible substrate layer 10, a TFT layer 30 provided on the flexible substrate layer 10, and a TFT It has an organic EL element layer 40 provided on the layer 30 and a sealing film 45 provided to cover the organic EL element layer 40 .
- the organic EL display panel 50b includes, in the chip mounting portion M of the frame region F, a chip lower circuit portion C, and a plurality of second electrodes provided so as to extend parallel to each other on the display region D side of the chip lower circuit portion C.
- 1 output side terminal wiring 14tc, a plurality of second output side terminal wirings 14td, and a plurality of third output side terminal wirings 14te are arranged in parallel with each other on the side of the terminal portion T of the circuit portion C below the chip. and a plurality of input-side terminal wirings 14tf (see FIG. 6) provided so as to extend.
- FIG. 6 input-side terminal wirings
- each third output terminal wiring 14te is provided so as to be adjacent to each first output terminal wiring 14tc and each second output terminal wiring 14td.
- the third output-side terminal wiring 14te is provided as a first wiring layer like the first output-side terminal wiring 14tc, the second output-side terminal wiring 14td, and the like.
- the organic EL display panel 50b is provided as a chip terminal on the display area D side of the chip lower circuit portion C along the long side of the chip lower circuit portion C on the display area D side.
- a plurality of first output terminals 18g provided in a line on the display area D side, and a long side of the display area D side of the chip lower circuit section C serving as chip terminals on the display area D side of the chip lower circuit section C.
- a plurality of second output terminals 18h provided on the terminal portion T side so as to be arranged in a line along the .
- a plurality of third output terminals 18i see FIG.
- a plurality of input terminals 18j are arranged in a row along the long side of the terminal portion T side of the circuit portion C below the chip as chip terminals on the terminal portion T side of C.
- the plurality of first output terminals 18g, the plurality of third output terminals 18i and the plurality of second output terminals 18h are, as shown in FIG. They are arranged repeatedly in the order of the terminals 18h.
- the third output terminal 18i is provided as a second wiring layer like the first output terminal 18g and the second output terminal 18h.
- the plurality of third output terminals 18i are laminated on the plurality of third output-side terminal wirings 14te, respectively, and are electrically connected to the plurality of third output-side terminal wirings 14te, respectively. Further, the plurality of third output terminals 18i are provided to correspond to the plurality of bumps 61 on the back surface of the integrated circuit chip 60, similar to the plurality of first output terminals 18j and the plurality of second output terminals 18h. It is electrically connected to the plurality of bumps 61 through the anisotropic conductive film 65 .
- the organic EL display panel 50b is arranged between the plurality of first output terminals 18g and between the plurality of second output terminals 18h in the chip mounting portion M of the frame area F. It is provided with island-like chip supports Sc and island-like chip supports Sb (see FIGS. 6 and 8) each provided between a plurality of input terminals 18j. Note that, as shown in FIG. 14, the chip support Sc is not provided between the plurality of third output terminals 18i.
- the chip support Sc includes a first inorganic insulating layer 15a made of the same material as the first interlayer insulating film 15 and formed in the same layer. a second inorganic insulating layer 17a provided on the second interlayer insulating film 17a and formed in the same layer with the same material as the second interlayer insulating film 17; and an organic insulating layer 19b formed on the same layer by The first output-side terminal wiring 14tc and the first output terminal 18g, and the second output-side terminal wiring 14td and the second output terminal 18h are extended to both ends in the width direction of the chip support Sc.
- the gap between the circuit chip 60 and the chip support Sc is narrowed, the bending of the panel at the first output terminal 18g and the second output terminal 18h during chip crimping is suppressed, and the first output terminal 18g and the second output terminal are suppressed. 18h, disconnection of the first output-side terminal wiring 14tc and the second output-side terminal wiring 14td can be suppressed.
- the display area D side (upper side in the figure) of the chip support Sc provided on the display area D side is, as shown in FIG. Since the bumps 61 are arranged on the outer side, the gap between the integrated circuit chip 60 and the chip support Sc is narrowed even in a place where there is no bump 61, so that the panel can be restrained from bending when the chip is crimped.
- the organic EL display panel 50b is illustrated, an organic EL display panel 50ba as shown in FIG. 15 may be used. Specifically, in the organic EL display panel 50ba, the distance between the third output terminal 18i and the first output terminal 18g and the second output terminal 18h is designed to be relatively wide, and between the plurality of third output terminals 18i A chip carrier Sd is provided.
- FIG. 15 the distance between the third output terminal 18i and the first output terminal 18g and the second output terminal 18h is designed to be relatively wide, and between the plurality of third output terminals 18i A chip carrier Sd is provided.
- the chip support Sd is provided between the plurality of first output terminals 18g and the chip support (Sd) provided between the plurality of second output terminals 18h. connected to the chip support (Sd).
- the portion between the plurality of third output terminals 18i may be separated from the portion between the plurality of first output terminals 18g and the portion between the plurality of second output terminals 18h. may be connected to the portion between the first output terminals 18g or the portion between the plurality of second output terminals 18h.
- the organic EL display device of the present embodiment including the organic EL display panel 50b described above has flexibility, and each sub-pixel P has a An image is displayed by causing the light emitting layer 3 of the organic EL layer 33 to emit light through the 1TFT 9a, the second TFT 9b, and the third TFT 9c.
- the organic EL display device including the organic EL display panel 50b provided with the output terminals 18g, 18h, and 18i having a three-stage structure in plan view is exemplified, but the structure has four or more stages in plan view.
- the organic EL display device may include an organic EL display panel provided with an output terminal of .
- the organic EL display device including the organic EL display panel 50b of the present embodiment has the first wiring layer, the second wiring layer, and the first inorganic insulating layer in the manufacturing method of the organic EL display device 70a of the first embodiment. 15a, the second inorganic insulating layer 17a, and the organic insulating layer 19b.
- the organic EL display device including the organic EL display panel 50b of the present embodiment, in the chip mounting portion M of the frame area F, between the plurality of first output terminals 18g and between the plurality of second output terminals 18g.
- An island-like chip support Sc is provided between the output terminals 18h
- an island-like chip support Sb is provided between the input terminals 18j. Therefore, in the mounting process, the conductive particles 64 in the anisotropic conductive film 65 are pushed out by the chip supporter Sc and the chip supporter Sb and moved to the first output terminal 18g, the second output terminal 18h, and the second output terminal 18h. It becomes relatively dense on the chip terminals of the input terminal 18j, and becomes relatively sparse between the chip terminals. This makes it difficult for the conductive particles 64 to connect between the adjacent chip terminals, so that a short circuit between the adjacent chip terminals due to the connection of the conductive particles 64 can be suppressed. short circuit can be suppressed.
- the organic EL display device including the organic EL display panel 50b of the present embodiment, in the chip mounting portion M of the frame area F, the plurality of first output terminals 18g, the plurality of second output terminals 18h and the plurality of Since the chip supports Sc and Sb are provided near the chip terminals of the input terminal 18j, it is possible to suppress the deflection of the organic EL display panel 50b near the bumps 61 of the integrated circuit chip 60 during the mounting process. .
- the generation of cracks in the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 of the organic EL display panel 50b can be suppressed, and the gate insulating film 13 and the first interlayer insulating film 17 can be prevented from cracking. Breakage of the first output-side terminal wiring 14tc, the second output-side terminal wiring 14td, the third output-side terminal wiring 14te, and the input-side terminal wiring 14tf provided between the interlayer insulating films 15 can be suppressed.
- FIG. 16 shows the first output terminal 18g, the second output terminal 18h, and the chip support Se in the chip mounting portion M in the frame area F of the organic EL display panel 50c constituting the organic EL display device of this embodiment.
- 8 is a plan view corresponding to FIG. 7.
- FIG. 17, 18 and 19 show the organic EL display panel 50ca of the first modified example, the organic EL display panel 50cb of the second modified example, and the organic EL display panel 50cc of the second modified example of the organic EL display panel 50c.
- 17 is a plan view corresponding to FIG. 16.
- the organic EL display device 70a including the organic EL display panel 50a provided with the chip support formed to have a constant width was exemplified, but in the present embodiment, the width is partially widened or An organic EL display device including an organic EL display panel 50c provided with a narrow chip support is exemplified.
- the organic EL display device of the present embodiment includes an organic EL display panel 50c and an integrated circuit chip mounted on a chip mounting portion M of the organic EL display panel 50c. 60, and a flexible printed wiring board 55 mounted on the terminal portion T of the organic EL display panel 50c.
- the organic EL display panel 50c includes, for example, a rectangular display area D for image display and a frame-like display area around the display area D. and a frame area F which is set.
- the organic EL display panel 50c includes the flexible substrate layer 10, the TFT layer 30 provided on the flexible substrate layer 10, and the TFTs, as in the organic EL display panel 50a of the first embodiment. It has an organic EL element layer 40 provided on the layer 30 and a sealing film 45 provided to cover the organic EL element layer 40 .
- the organic EL display panel 50c includes a chip lower circuit section C and a chip mounting section M in the frame area F, as shown in FIG.
- a plurality of first output-side terminal wirings 14tc and a plurality of second output-side terminal wirings 14td provided to extend in parallel to each other on the display area D side of the lower circuit section C, and a terminal section T of the chip lower circuit section C.
- a plurality of input-side terminal wirings 14tf are provided so as to extend parallel (parallel) to each other.
- the organic EL display panel 50c similarly to the organic EL display panel 50a of the first embodiment, in the chip mounting portion M of the frame area F, the display area of the circuit portion C below the chip is displayed.
- a plurality of first output terminals 18g provided on the display area D side so as to be arranged in a row along the long side of the display area D side of the chip lower circuit section C as chip terminals on the D side, and the chip lower circuit section C a plurality of second output terminals 18h provided on the terminal portion T side so as to be aligned in a row along the long side of the display region D side of the chip lower circuit portion C as chip terminals on the display region D side of the chip;
- a plurality of input terminals 18j (see FIGS. 6 and 8) provided in a row along the long side of the terminal portion T side of the circuit portion C below the chip as chip terminals on the terminal portion T side of the circuit portion C.
- the organic EL display panel 50c has both comb teeth between the plurality of first output terminals 18g and between the plurality of second output terminals 18h in the chip mounting portion M of the frame region F. and a chip support Sb (see FIGS. 6 and 8) provided like islands one by one between a plurality of input terminals 18j.
- the chip support Se like the chip support Sa of the first embodiment, includes a first inorganic insulating layer 15a formed in the same layer as the first interlayer insulating film 15 and the first inorganic insulating layer 15a. a second inorganic insulating layer 17a provided on the second interlayer insulating film 17a and formed in the same layer with the same material as the second interlayer insulating film 17; and an organic insulating layer 19b formed on the same layer by The first output-side terminal wiring 14tc and the first output terminal 18g, and the second output-side terminal wiring 14td and the second output terminal 18h are extended to both ends of the chip support Se in the width direction.
- the gap between the circuit chip 60 and the chip support body Se is narrowed, the bending of the panel at the first output terminal 18g and the second output terminal 18h during chip crimping is suppressed, and the first output terminal 18g and the second output terminal are suppressed. 18h, disconnection of the first output-side terminal wiring 14tc and the second output-side terminal wiring 14td can be suppressed.
- the display area D side (the upper side in the figure) of the chip support Se is arranged outside the chip mounting portion M (peripheral edge E of the integrated circuit chip 60).
- the peripheral edge E of the integrated circuit chip 60 is provided with a wide width, the gap between the integrated circuit chip 60 and the chip support body Se is narrowed even at a location where there is no bump 61, so that the panel does not flex when the chip is crimped. can be further suppressed.
- the display area D side (upper side in the drawing) and the terminal portion T side (lower side in the drawing) of the chip support Se are triangular pyramidal so as to taper toward the tip. , the outlet of the resin material 63 of the anisotropic conductive film 65 used in the mounting process is widened, and the resin material 63 flows easily. are dispersed, and short-circuiting between adjacent chip terminals due to connection of the conductive particles 64 can be further suppressed.
- the organic EL display panel 50c provided with the chip support body Se that once widens and tapers at the peripheral edge E of the integrated circuit chip 60 is illustrated.
- the organic EL display panel 50ca provided with the body Sea
- the organic EL display panel 50cb provided with the chip support Seb as shown in FIG. 18, and the organic EL display provided with the chip support Sec as shown in FIG. It may be a panel 50cc.
- the display area D side (the upper side in the figure) of the chip support Sea is arranged outside the chip mounting portion M (peripheral edge E of the integrated circuit chip 60), as shown in FIG. Since the outer portion is widened at the peripheral edge E of the integrated circuit chip 60, the gap between the integrated circuit chip 60 and the chip support Seaa is narrowed even at a location where there is no bump 61, so that the chip is crimped. It is possible to further suppress the bending of the panel at time.
- the display area D side (upper side in the drawing) and the terminal portion T side (lower side in the drawing) of the chip support Sea are substantially half-width tapered toward the tip. It is provided in a spherical shape.
- the display area D side (the upper side in the drawing) of the chip support Seb is arranged outside the chip mounting portion M (peripheral edge E of the integrated circuit chip 60), as shown in FIG. and is provided in the shape of a triangular pyramid so that the outer portion tapers toward the tip.
- the display area D side (upper side in the drawing) and the terminal portion T side (lower side in the drawing) of the chip support Seb are formed into triangular pyramids so as to taper toward the tip. Since the resin material 63 of the anisotropic conductive film 65 used in the mounting process is easily discharged, the resin material 63 flows easily. 64 are dispersed, it is possible to further suppress short circuits between adjacent chip terminals due to connection of the conductive particles 64 .
- the display area D side (the upper side in the figure) of the chip support Sec is arranged outside the chip mounting portion M (peripheral edge E of the integrated circuit chip 60), as shown in FIG. and is provided in the shape of a triangular pyramid so that the outer portion tapers toward the tip.
- the display area D side (upper side in the drawing) and the terminal section T side (lower side in the drawing) of the chip support Sec are at the long side of the chip mounting section M, as shown in FIG.
- the discharge port of the resin material 63 of the anisotropic conductive film 65 used in the mounting process is obliquely widened with respect to the long side of the chip mounting portion M, Since the resin material 63 becomes easier to flow, the conductive particles 64 of the anisotropic conductive film 65 are dispersed, and short circuits between adjacent chip terminals due to the connection of the conductive particles 64 can be further suppressed.
- the organic EL display device of this embodiment which includes the organic EL display panel 50c described above, has flexibility, and each sub-pixel P has a An image is displayed by causing the light emitting layer 3 of the organic EL layer 33 to emit light through the 1TFT 9a, the second TFT 9b, and the third TFT 9c.
- the organic EL display device including the organic EL display panel 50c of the present embodiment has the first inorganic insulating layer 15a, the second inorganic insulating layer 17a and the organic It can be manufactured by changing the pattern shape of the insulating layer 19b.
- the organic EL display device including the organic EL display panel 50c of the present embodiment, in the chip mounting portion M of the frame area F, between the plurality of first output terminals 18g and between the plurality of second output terminals 18g.
- a chip support Se is provided like a comb between the output terminals 18h, and a chip support Sb like an island is provided between the input terminals 18j. Therefore, in the mounting process, the conductive particles 64 in the anisotropic conductive film 65 are pushed out by the chip supporter Se and the chip supporter Sb to move, thereby forming the first output terminal 18g, the second output terminal 18h, and the second output terminal 18h.
- the organic EL display device including the organic EL display panel 50c of the present embodiment, in the chip mounting portion M of the frame area F, the plurality of first output terminals 18g, the plurality of second output terminals 18h and the plurality of Since the chip supports Se and Sb are provided near the chip terminals of the input terminal 18j, it is possible to suppress the deflection of the organic EL display panel 50c near the bumps 61 of the integrated circuit chip 60 during the mounting process. .
- the generation of cracks in the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 of the organic EL display panel 50c can be suppressed, and the gate insulating film 13 and the first interlayer insulating film 17 can be prevented from cracking. Breakage of the first output-side terminal wiring 14tc, the second output-side terminal wiring 14td, and the input-side terminal wiring 14tf provided between the interlayer insulating films 15 can be suppressed.
- FIG. 20 shows a fourth embodiment of the display device according to the invention.
- FIG. 20 is an enlarged plan view of the chip mounting portion M in the frame region F of the organic EL display panel 50d constituting the organic EL display device of the present embodiment, and corresponds to FIG.
- the organic EL display device 70a including the organic EL display panel 50a in which the chip terminals are provided along the long side of the chip mounting portion M is exemplified.
- An organic EL display device including an organic EL display panel 50d in which chip terminals are also provided along the short sides of the portion M will be exemplified.
- the organic EL display device of the present embodiment includes an organic EL display panel 50d and an integrated circuit chip mounted on a chip mounting portion M of the organic EL display panel 50d. 60, and a flexible printed wiring board 55 mounted on the terminal portion T of the organic EL display panel 50d.
- the organic EL display panel 50d includes, for example, a rectangular display area D for image display and a frame-like display area around the display area D. and a frame area F which is set.
- the organic EL display panel 50d includes a flexible substrate layer 10, a TFT layer 30 provided on the flexible substrate layer 10, and a TFT It has an organic EL element layer 40 provided on the layer 30 and a sealing film 45 provided to cover the organic EL element layer 40 .
- the organic EL display panel 50d extends parallel to the chip mounting portion M in the frame area F toward the display area D side of the chip under circuit portion C and the chip under circuit portion C.
- the organic EL display panel 50d has the display area D of the under-chip circuit section C as a chip terminal on the side of the display area D of the under-chip circuit section C in the chip mounting area M of the frame area F.
- a plurality of second output terminals 18h provided on the terminal portion T side so as to be aligned along the long side of the display area D side, and a chip lower circuit portion C as a chip terminal on the terminal portion T side of the chip lower circuit portion C.
- a plurality of input terminals 18j are arranged in a row along the long side of the terminal portion T side of the portion C, and a plurality of input terminals 18j are arranged on the short side of the chip mounting portion M as chip terminals on the left side of the circuit portion C below the chip in the drawing.
- a plurality of short-side terminals 18k are provided so as to line up in a line along the edge.
- the organic EL display panel 50d has both comb teeth between the plurality of first output terminals 18g and between the plurality of second output terminals 18h in the chip mounting portion M of the frame region F.
- chip supports Sa provided integrally in a shape
- chip supports Sb provided like islands between a plurality of input terminals 18j, and islands each provided between a plurality of short-side terminals 18k.
- a chip support Sg provided in the .
- the chip support Sg like the chip support Sa of the first embodiment, includes a first inorganic insulating layer 15a made of the same material as the first interlayer insulating film 15 and formed in the same layer. a second inorganic insulating layer 17a provided on the second interlayer insulating film 17a and formed in the same layer with the same material as the second interlayer insulating film 17; and an organic insulating layer 19b formed on the same layer by Since the short-side terminal wiring 14tg and the short-side terminals 18k are extended to both ends in the width direction of the chip support Sg, the gap between the integrated circuit chip 60 and the chip support Sg is narrowed.
- the chip support Sg on the display area D side (upper side in the drawing) and the chip support Sg on the terminal portion T side (lower side in the drawing) are as shown in FIG. , are provided integrally with the chip support Sa and the chip support Sb, respectively. Even if the adjacent chip supports are integrally provided, the resin material 63 may be removed if at least one portion of the anisotropic conductive film 65 used in the mounting process serves as an outlet for the resin material 63 . liquidity can be secured.
- the organic EL display device of the present embodiment including the organic EL display panel 50d described above has flexibility, and each sub-pixel P has a An image is displayed by causing the light emitting layer 3 of the organic EL layer 33 to emit light through the 1TFT 9a, the second TFT 9b, and the third TFT 9c.
- the organic EL display device including the organic EL display panel 50d of the present embodiment has a first wiring layer, a second wiring layer, and a first inorganic insulating layer in the manufacturing method of the organic EL display device 70a of the first embodiment. 15a, the second inorganic insulating layer 17a, and the organic insulating layer 19b.
- a chip support Sa is provided like a comb between the output terminals 18h
- a chip support Sb is provided like an island between the plurality of input terminals 18j
- a chip support Sb is provided between the plurality of short-side terminals 18k.
- Chip supports Sg are provided one by one in the form of islands.
- the conductive particles 64 in the anisotropic conductive film 65 are pushed out by the chip supports Sa, Sb, and Sg to move the first output terminal 18g, the second output terminal 18h, and the input terminal 18h.
- the terminals 18j and 18k are relatively dense on the chip terminals, and relatively sparse between the chip terminals. This makes it difficult for the conductive particles 64 to connect between the adjacent chip terminals, so that a short circuit between the adjacent chip terminals due to the connection of the conductive particles 64 can be suppressed. short circuit can be suppressed.
- the organic EL display device including the organic EL display panel 50d of the present embodiment, in the chip mounting portion M of the frame area F, the plurality of first output terminals 18g, the plurality of second output terminals 18h, the plurality of Since the chip supports Sa, Sb, and Sg are provided in the vicinity of each chip terminal of the input terminal 18j and the plurality of short-side terminals 18k, the organic EL display panel in the vicinity of each bump 61 of the integrated circuit chip 60 in the mounting process. A deflection of 50d can be suppressed.
- the generation of cracks in the base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 of the organic EL display panel 50d can be suppressed, and the gate insulating film 13 and the first interlayer insulating film 17 can be prevented from cracking. Breakage of the first output-side terminal wiring 14tc, the second output-side terminal wiring 14td, the input-side terminal wiring 14tf, and the short-side terminal wiring 14tg provided between the interlayer insulating films 15 can be suppressed.
- the organic EL display device including the organic EL display panels 50a, 50b, 50c, and 50d was exemplified. can do.
- the organic EL display device in which the bumps are arranged in a regular array parallel or perpendicular to the long and short sides of the integrated circuit chip was exemplified, but the present invention is limited to this.
- the present invention can also be applied to an organic EL display device in which bumps are arranged in an oblique arrangement with respect to the long and short sides of an integrated circuit chip.
- the organic EL layer having a five-layer laminate structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer was exemplified.
- a three-layer structure of a hole injection layer/hole transport layer, a light emitting layer, and an electron transport layer/electron injection layer may be employed.
- the organic EL display device in which the first electrode is the anode and the second electrode is the cathode was exemplified. , and can also be applied to an organic EL display device in which the second electrode is an anode.
- the organic EL display device in which the electrode of the TFT connected to the first electrode is used as the drain electrode is exemplified. It can also be applied to a so-called organic EL display device.
- an organic EL display device was described as an example of a display device.
- QLED Quantum-dot light emitting diode
- the present invention is useful for flexible display devices.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
図1~図13は、本発明に係る表示装置の第1の実施形態を示している。なお、以下の各実施形態では、発光素子層を備えた表示装置として、有機EL素子層を備えた有機EL表示装置を例示する。ここで、図1は、本実施形態の有機EL表示装置70aの概略構成を示す平面図である。また、図2は、有機EL表示装置70aを構成する有機EL表示パネル50aの表示領域Dの平面図である。また、図3は、有機EL表示パネル50aの表示領域Dの断面図である。また、図4は、有機EL表示パネル50aを構成する薄膜トランジスタ層30の等価回路図である。また、図5は、有機EL表示パネル50aを構成する有機EL層33を示す断面図である。また、図6は、有機EL表示パネル50aの額縁領域Fにおけるチップ実装部M及びその周囲の平面図である。また、図7は、有機EL表示パネル50aの額縁領域Fのチップ実装部Mにおける第1出力端子18g、第2出力端子18h及びチップ支持体Saを示す平面図である。また、図8は、有機EL表示パネル50aの額縁領域Fのチップ実装部Mにおける入力端子18j及びチップ支持体Sbを示す平面図である。また、図9は、図7において、実装される集積回路チップ60の端部E及び導電性粒子64を示す平面図である。また、図10、図11及び図12は、図9中のX-X線、XI-XI線及びXII-XII線に沿った有機EL表示装置70aの断面図である。また、図13は、有機EL表示装置70aの変形例の有機EL表示装置70aaの断面図であり、図10に相当する図である。
<TFT層形成工程>
まず、例えば、ガラス基板上に非感光性のポリイミド樹脂(厚さ10μm程度)を塗布した後、その塗布膜に対して、プリベーク及びポストベークを行うことにより、可撓性基板層10を形成する。
上記TFT層形成工程で形成されたTFT層30の第2平坦化膜21a上に、周知の方法を用いて、第1電極31a、エッジカバー32a、有機EL層33(正孔注入層1、正孔輸送層2、発光層3、電子輸送層4、電子注入層5)及び第2電極34を形成して、有機EL素子層40を形成する。
まず、上記有機EL素子層形成工程で形成された有機EL素子層40が形成された基板表面に、マスクを用いて、例えば、窒化シリコン膜、酸化シリコン膜、酸窒化シリコン膜等の無機絶縁膜をプラズマCVD法により成膜して、第1無機封止膜41を形成する。
まず、上記有機EL表示パネル作製工程で作製された有機EL表示パネル50aの表面側の保護シートに、例えば、レーザー光を照射することにより、保護シートを部分的に除去して、チップ実装部M及び端子部Tを露出させる。
図14及び図15は、本発明に係る表示装置の第2の実施形態を示している。ここで、図14は、本実施形態の有機EL表示装置を構成する有機EL表示パネル50bの額縁領域Fのチップ実装部Mにおける第1出力端子18g、第2出力端子18h、第3出力端子18i及びチップ支持体Scを示す平面図であり、図7に相当する図である。また、図15は、有機EL表示パネル50bの変形例の有機EL表示パネル50baの平面図であり、図14に相当する図である。なお、以下の実施形態において、図1~図13と同じ部分については同じ符号を付して、その詳細な説明を省略する。
図16~図19は、本発明に係る表示装置の第3の実施形態を示している。ここで、図16は、本実施形態の有機EL表示装置を構成する有機EL表示パネル50cの額縁領域Fのチップ実装部Mにおける第1出力端子18g、第2出力端子18h及びチップ支持体Seを示す平面図であり、図7に相当する図である。また、図17、図18及び図19は、有機EL表示パネル50cにおける第1変形例の有機EL表示パネル50ca、第2変形例の有機EL表示パネル50cb及び第2変形例の有機EL表示パネル50ccの平面図であり、図16に相当する図である。
図20は、本発明に係る表示装置の第4の実施形態を示している。ここで、図20は、本実施形態の有機EL表示装置を構成する有機EL表示パネル50dの額縁領域Fのチップ実装部Mを拡大した平面図であり、図6に相当する図である。
上記各実施形態では、有機EL表示パネル50a、50b、50c及び50dを備えた有機EL表示装置を例示したが、本発明は、各実施形態の特徴部分を適宜組み合わせ有機EL表示装置等にも適用することができる。
E 延長線
F 額縁領域
M チップ実装部
P サブ画素
Sa,Sb,Sc,Sd,Sg,Saa,Se,Sea,Seb,Sec チップ支持体
T 端子部
10 可撓性基板層
13 ゲート絶縁膜
14a,14b ゲート電極(第1配線層)
14c 下層導電層(第1配線層)
14g ゲート線(第1配線層)
14e 発光制御線(第1配線層)
14tc,14td,14te 出力側端子配線
14tf 入力側端子配線
15 第1層間絶縁膜
15a 第1無機絶縁層
17 第2層間絶縁膜
17a 第2無機絶縁層
18a,18c ソース電極(第2配線層)
18b,18d ドレイン電極(第2配線層)
18f ソース線(第2配線層)
18g 第1出力端子(チップ用端子)
18h 第2出力端子(チップ用端子)
18i 第3出力端子(チップ用端子)
18j 入力端子(チップ用端子)
18k 短辺端子
19a 第1平坦化膜
19b 有機絶縁層,第1有機絶縁層
21a 第2平坦化膜
21b 第2有機絶縁層
30 TFT層(薄膜トランジスタ層)
35 有機EL素子(有機エレクトロルミネッセンス素子、発光素子)
40 有機EL素子層(発光素子層)
41 第1無機封止膜
42 有機封止膜
43 第2無機封止膜
45 封止膜
50a,50aa,50b,50ba,50c,50ca,50cb,50cc,50d 有機EL表示パネル
60 集積回路チップ
61 バンプ
64 導電性粒子
65 異方性導電膜
70a,70aa 有機EL表示装置
Claims (20)
- 可撓性基板層と、
上記可撓性基板層上に設けられた薄膜トランジスタ層と、
上記薄膜トランジスタ層上に設けられ、表示領域を構成する複数のサブ画素に対応して複数の発光素子が配列された発光素子層とを備え、
上記表示領域の周囲に額縁領域が設けられ、
上記額縁領域の端部に端子部が一方向に延びるように設けられ、
上記表示領域及び上記端子部の間に上記端子部の延びる方向に沿って長辺が延びる平面視で長方形状のチップ実装部が設けられ、
上記チップ実装部に一列に並ぶ複数のチップ用端子、及び該複数のチップ用端子に対応して互いに並行に延びて該複数のチップ用端子に電気的にそれぞれ接続された複数の端子配線が設けられた表示装置であって、
上記チップ実装部には、上記複数のチップ用端子の間にチップ支持体が設けられていることを特徴とする表示装置。 - 請求項1に記載された表示装置において、
上記チップ実装部には、上記複数のチップ用端子として、上記端子部側の長辺に沿って複数の入力端子が一列に並ぶように設けられ、
上記チップ支持体は、上記複数の入力端子の間に1つずつ島状に設けられていることを特徴とする表示装置。 - 請求項2に記載された表示装置において、
上記複数の入力端子に対して設けられた上記各チップ支持体の上記端子部側は、上記チップ実装部よりも外側に配置されていることを特徴とする表示装置。 - 請求項1に記載された表示装置において、
上記チップ実装部には、上記複数のチップ用端子として、上記表示領域側の長辺に沿って複数の出力端子が一列に並ぶように設けられ、
上記複数の出力端子は、上記表示領域側に一列に並ぶように設けられた複数の第1出力端子と、上記端子部側に一列に並ぶように設けられた複数の第2出力端子とを備え、
上記複数の第1出力端子及び上記複数の第2出力端子は、上記チップ実装部の長辺に沿って千鳥状に交互に配置され、
上記チップ支持体は、上記複数の第1出力端子の間、及び上記複数の第2出力端子の間に両櫛歯状に一体に設けられていることを特徴とする表示装置。 - 請求項4に記載された表示装置において、
上記複数の第1出力端子及び上記複数の第2出力端子に対して設けられた上記チップ支持体の上記表示領域側は、上記チップ実装部よりも外側に配置されていることを特徴とする表示装置。 - 請求項3又は5に記載された表示装置において、
上記チップ支持体の上記チップ実装部よりも外側の部分は、上記チップ実装部の周端で幅広に設けられていることを特徴とする表示装置。 - 請求項3、5又は6に記載された表示装置において、
上記チップ支持体の上記チップ実装部よりも外側の部分は、先端に向かって先細りに設けられていることを特徴とする表示装置。 - 請求項3、5、6又は7に記載された表示装置において、
上記チップ支持体の上記チップ実装部よりも外側の部分の先端は、上記チップ実装部の長辺に沿って千鳥状に交互に配置されていることを特徴とする表示装置。 - 請求項1~8の何れか1つに記載された表示装置において、
上記薄膜トランジスタ層は、上記可撓性基板層上に順に積層されたゲート絶縁膜、第1配線層、層間絶縁膜、第2配線層及び平坦化膜を備え、
上記チップ用端子は、上記第1配線層と同一材料により同一層に形成された上記端子配線上に設けられ、上記第2配線層と同一材料により同一層に形成され、
上記チップ支持体は、上記層間絶縁膜と同一材料により同一層に形成された無機絶縁層と、上記無機絶縁層上に設けられ、上記平坦化膜と同一材料により同一層に形成された有機絶縁層とを備え、
上記有機絶縁層は、幅方向の中央部が幅方向の両端部よりも厚く形成されていることを特徴とする表示装置。 - 請求項9に記載された表示装置において、
上記平坦化膜は、上記可撓性基板層側に設けられた第1平坦化膜と、上記可撓性基板層と反対側に設けられた第2平坦化膜と備え、
上記有機絶縁層は、上記第1平坦化膜と同一材料により同一層に形成された第1有機絶縁層と、該第1有機絶縁層上に設けられ、上記第2平坦化膜と同一材料により同一層に形成された第2有機絶縁層とを備え、
上記第2有機絶縁層は、上記第1有機絶縁層よりも幅狭に設けられていることを特徴とする表示装置。 - 請求項9又は10に記載された表示装置において、
上記端子配線及び上記チップ用端子は、上記チップ支持体の幅方向の両端部まで延長されていることを特徴とする表示装置。 - 請求項1に記載された表示装置において、
上記チップ実装部には、上記複数のチップ用端子として、上記表示領域側の長辺に沿って複数の出力端子が一列に並ぶように設けられ、
上記複数の出力端子は、上記表示領域側に一列に並ぶように設けられた複数の第1出力端子と、上記端子部側に一列に並ぶように設けられた複数の第2出力端子と、該複数の第1出力端子及び複数の第2出力端子の間に一列に並ぶように設けられた複数の第3出力端子とを備え、
上記複数の第1出力端子、上記複数の第3出力端子及び上記複数の第2出力端子は、上記チップ実装部の長辺に沿って該第1出力端子、該第3出力端子及び該第2出力端子の順に繰り返して配置されていることを特徴とする表示装置。 - 請求項12に記載された表示装置において、
上記チップ支持体は、上記複数の第1出力端子の間、及び上記複数の第2出力端子の間にそれぞれ設けられていることを特徴とする表示装置。
ことを特徴とする表示装置。 - 請求項13に記載された表示装置において、
上記チップ支持体は、上記複数の第3出力端子の間に設けられていないことを特徴とする表示装置。 - 請求項12に記載された表示装置において、
上記チップ支持体は、上記複数の第1出力端子の間、上記複数の第2出力端子の間、及び上記複数の第3出力端子の間にそれぞれ設けられ、
上記複数の第3出力端子の間に設けられた上記チップ支持体は、上記複数の第1出力端子の間に設けられた対応する上記チップ支持体、及び上記複数の第2出力端子の間に設けられた対応する上記チップ支持体にそれぞれ連結されていることを特徴とする表示装置。 - 請求項1~15の何れか1つに記載された表示装置において、
上記チップ実装部には、上記複数のチップ用端子として、該チップ実装部の短辺に沿って複数の短辺端子が一列に並ぶように設けられ、
上記チップ支持体は、上記複数の短辺端子の間に1つずつ島状に設けられていることを特徴とする表示装置。 - 請求項1~16の何れか1つに記載された表示装置において、
上記チップ実装部には、集積回路チップが異方性導電膜を介して実装されていることを特徴とする表示装置。 - 請求項17に記載された表示装置において、
上記集積回路チップの裏面には、上記複数のチップ用端子に対応するように複数のバンプが設けられ、
上記異方性導電膜には、導電性粒子が含有され、
上記複数のバンプと上記複数のチップ用端子とは、上記導電性粒子を介して電気的にそれぞれ接続されていることを特徴とする表示装置。 - 請求項1~18の何れか1つに記載された表示装置において、
上記発光素子層を覆うように設けられ、第1無機封止膜、有機封止膜及び第2無機封止膜が順に積層された封止膜を備えていることを特徴とする表示装置。 - 請求項1~19の何れか1つに記載された表示装置において、
上記各発光素子は、有機エレクトロルミネッセンス素子であることを特徴とする表示装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202180098301.0A CN117355884A (zh) | 2021-06-21 | 2021-06-21 | 显示装置 |
PCT/JP2021/023465 WO2022269714A1 (ja) | 2021-06-21 | 2021-06-21 | 表示装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2021/023465 WO2022269714A1 (ja) | 2021-06-21 | 2021-06-21 | 表示装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022269714A1 true WO2022269714A1 (ja) | 2022-12-29 |
Family
ID=84545298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2021/023465 WO2022269714A1 (ja) | 2021-06-21 | 2021-06-21 | 表示装置 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN117355884A (ja) |
WO (1) | WO2022269714A1 (ja) |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0990397A (ja) * | 1995-09-28 | 1997-04-04 | Sharp Corp | アクティブマトリクス基板およびそれを用いた表示装置 |
JP2002169172A (ja) * | 2000-11-17 | 2002-06-14 | Internatl Business Mach Corp <Ibm> | 液晶表示パネル、液晶表示パネルの製造方法、液晶表示装置、液晶表示装置の製造方法および基板の接合体 |
JP2002329747A (ja) * | 2001-02-06 | 2002-11-15 | Au Optronics Corp | 半導体装置の実装構造、その実装方法および液晶表示パネル |
JP2004252466A (ja) * | 2003-02-20 | 2004-09-09 | Samsung Electronics Co Ltd | 駆動ic及びこれを具備したディスプレイ装置 |
WO2007039959A1 (ja) * | 2005-10-05 | 2007-04-12 | Sharp Kabushiki Kaisha | 配線基板及びそれを備えた表示装置 |
CN101587874A (zh) * | 2008-05-22 | 2009-11-25 | 瀚宇彩晶股份有限公司 | 具有驱动集成电路的芯片及其对应的液晶显示器 |
US20140117320A1 (en) * | 2012-10-26 | 2014-05-01 | Samsung Display Co., Ltd. | Display apparatus and organic light-emitting display apparatus |
US20140140029A1 (en) * | 2012-11-19 | 2014-05-22 | Samsung Display Co., Ltd. | Display panel and bonding apparatus for manufacturing the same |
JP2015201256A (ja) * | 2014-04-04 | 2015-11-12 | セイコーエプソン株式会社 | 有機エレクトロルミネッセンス装置の製造方法および電子機器 |
CN105263253A (zh) * | 2014-07-16 | 2016-01-20 | 上海和辉光电有限公司 | 夹层面板及其制作方法 |
JP2016039078A (ja) * | 2014-08-08 | 2016-03-22 | 株式会社ジャパンディスプレイ | 表示装置、及びその製造方法 |
CN109524444A (zh) * | 2018-12-18 | 2019-03-26 | 武汉华星光电半导体显示技术有限公司 | 显示面板 |
US20200303468A1 (en) * | 2019-03-19 | 2020-09-24 | Samsung Display Co., Ltd. | Display device including input sensing unit and driving method thereof |
-
2021
- 2021-06-21 WO PCT/JP2021/023465 patent/WO2022269714A1/ja active Application Filing
- 2021-06-21 CN CN202180098301.0A patent/CN117355884A/zh active Pending
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0990397A (ja) * | 1995-09-28 | 1997-04-04 | Sharp Corp | アクティブマトリクス基板およびそれを用いた表示装置 |
JP2002169172A (ja) * | 2000-11-17 | 2002-06-14 | Internatl Business Mach Corp <Ibm> | 液晶表示パネル、液晶表示パネルの製造方法、液晶表示装置、液晶表示装置の製造方法および基板の接合体 |
JP2002329747A (ja) * | 2001-02-06 | 2002-11-15 | Au Optronics Corp | 半導体装置の実装構造、その実装方法および液晶表示パネル |
JP2004252466A (ja) * | 2003-02-20 | 2004-09-09 | Samsung Electronics Co Ltd | 駆動ic及びこれを具備したディスプレイ装置 |
WO2007039959A1 (ja) * | 2005-10-05 | 2007-04-12 | Sharp Kabushiki Kaisha | 配線基板及びそれを備えた表示装置 |
CN101587874A (zh) * | 2008-05-22 | 2009-11-25 | 瀚宇彩晶股份有限公司 | 具有驱动集成电路的芯片及其对应的液晶显示器 |
US20140117320A1 (en) * | 2012-10-26 | 2014-05-01 | Samsung Display Co., Ltd. | Display apparatus and organic light-emitting display apparatus |
US20140140029A1 (en) * | 2012-11-19 | 2014-05-22 | Samsung Display Co., Ltd. | Display panel and bonding apparatus for manufacturing the same |
JP2015201256A (ja) * | 2014-04-04 | 2015-11-12 | セイコーエプソン株式会社 | 有機エレクトロルミネッセンス装置の製造方法および電子機器 |
CN105263253A (zh) * | 2014-07-16 | 2016-01-20 | 上海和辉光电有限公司 | 夹层面板及其制作方法 |
JP2016039078A (ja) * | 2014-08-08 | 2016-03-22 | 株式会社ジャパンディスプレイ | 表示装置、及びその製造方法 |
CN109524444A (zh) * | 2018-12-18 | 2019-03-26 | 武汉华星光电半导体显示技术有限公司 | 显示面板 |
US20200303468A1 (en) * | 2019-03-19 | 2020-09-24 | Samsung Display Co., Ltd. | Display device including input sensing unit and driving method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN117355884A (zh) | 2024-01-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2020065710A1 (ja) | 表示装置 | |
WO2020044439A1 (ja) | 表示装置 | |
CN111819614B (zh) | 显示装置 | |
WO2021079412A1 (ja) | 表示装置 | |
CN112449711B (zh) | 显示装置 | |
WO2020039555A1 (ja) | 表示装置 | |
WO2019186702A1 (ja) | 表示装置 | |
US11417862B2 (en) | Display device including lead wiring lines covered by first and second organic films, and production method therefor | |
WO2022269714A1 (ja) | 表示装置 | |
CN113474830B (zh) | 显示装置及其制造方法 | |
WO2022269863A1 (ja) | 表示装置 | |
WO2020008588A1 (ja) | 表示装置及びその製造方法 | |
WO2023079595A1 (ja) | 表示装置 | |
WO2020115906A1 (ja) | 表示装置及びその製造方法 | |
WO2022269756A1 (ja) | 表示装置 | |
WO2022201487A1 (ja) | 表示装置 | |
WO2023007582A1 (ja) | 表示装置 | |
WO2022064562A1 (ja) | 表示装置 | |
US20230329038A1 (en) | Display device and method for manufacturing same | |
WO2023100365A1 (ja) | 表示装置 | |
WO2024013806A1 (ja) | 表示装置 | |
WO2023021623A1 (ja) | 表示装置及びその製造方法 | |
WO2023218637A1 (ja) | 表示装置 | |
WO2024105749A1 (ja) | 表示装置 | |
WO2023007549A1 (ja) | 表示装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21947003 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 202180098301.0 Country of ref document: CN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 18562021 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 21947003 Country of ref document: EP Kind code of ref document: A1 |