WO2022264212A1 - 炭化珪素半導体装置および炭化珪素半導体装置を用いた電力変換装置 - Google Patents

炭化珪素半導体装置および炭化珪素半導体装置を用いた電力変換装置 Download PDF

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WO2022264212A1
WO2022264212A1 PCT/JP2021/022527 JP2021022527W WO2022264212A1 WO 2022264212 A1 WO2022264212 A1 WO 2022264212A1 JP 2021022527 W JP2021022527 W JP 2021022527W WO 2022264212 A1 WO2022264212 A1 WO 2022264212A1
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region
silicon carbide
semiconductor device
carbide semiconductor
conductivity type
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French (fr)
Japanese (ja)
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史郎 日野
洸太朗 川原
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to US18/567,023 priority Critical patent/US20240274709A1/en
Priority to PCT/JP2021/022527 priority patent/WO2022264212A1/ja
Priority to JP2023529170A priority patent/JP7573747B2/ja
Priority to CN202180099162.3A priority patent/CN117461143A/zh
Priority to DE112021007820.8T priority patent/DE112021007820B4/de
Publication of WO2022264212A1 publication Critical patent/WO2022264212A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/141—VDMOS having built-in components
    • H10D84/146—VDMOS having built-in components the built-in components being Schottky barrier diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Definitions

  • the present disclosure relates to a silicon carbide semiconductor device and a power converter using the silicon carbide semiconductor device.
  • a unipolar switching element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) and a unipolar freewheeling diode such as a Schottky Barrier Diode (SBD) are incorporated.
  • a power semiconductor device is known (for example, Patent Document 1). Such a semiconductor device can be realized by arranging a MOSFET cell and an SBD cell in parallel on the same chip. It can be realized by making
  • the cost can be reduced compared to attaching a freewheeling diode to the switching element externally.
  • SiC silicon carbide
  • Such an SBD-embedded MOSFET has a Schottky diode composed of a Schottky electrode and a certain conductivity type (for example, n-type) semiconductor layer.
  • the electric field applied to the Schottky interface which is formed between well regions of the opposite conductivity type (for example, p-type), increases as the distance from the opposite conductivity type (for example, p-type) well regions on both sides increases.
  • the current path of the current flowing through the Schottky diode is spatially limited by the well regions of the opposite conductivity type (for example, p-type) on both sides, and there are cases where the maximum value of the current flowing through the Schottky diode cannot be sufficiently increased. .
  • the present disclosure has been made to solve the above-described problems, and by increasing the current flowing through the Schottky diode without increasing the electric field applied to the Schottky interface, a highly reliable silicon carbide semiconductor
  • the purpose is to provide an apparatus.
  • a silicon carbide semiconductor device of the present disclosure includes a first conductivity type drift layer of a silicon carbide semiconductor formed on a first main surface of a first conductivity type semiconductor substrate, and a surface layer of the drift layer spaced apart in a cross-sectional lateral direction. and a well region of a second conductivity type having a first spacing region of the first conductivity type therebetween, and a region formed between the well regions in which the first spacing region is not formed.
  • a second spacing region of a first conductivity type formed in a cross section of a semiconductor surface layer in the well region;
  • a contact region of the second conductivity type formed closer to the first separation region than the source region in the lateral direction, and a first conductivity type formed in a surface layer portion of the well region between the contact region and the first separation region.
  • a gate insulating film formed on the second spacing region and a well region adjacent to the second spacing region; a gate electrode formed on the gate insulating film; and a contact region formed on the contact region.
  • an ohmic electrode a Schottky electrode formed on the first spacing region and Schottky-connected to the first spacing region; a source electrode formed on the ohmic electrode and the Schottky electrode; and a drain electrode formed on the second main surface opposite to the second main surface.
  • silicon carbide semiconductor device According to the silicon carbide semiconductor device according to the present disclosure, a highly reliable silicon carbide semiconductor device can be obtained.
  • FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to a first embodiment
  • FIG. 1 is a plan view of a silicon carbide semiconductor device according to a first embodiment
  • FIG. 1 is a plan view of a silicon carbide semiconductor device according to a first embodiment
  • FIG. 4 is a cross-sectional view of a modification of the silicon carbide semiconductor device according to Embodiment 1
  • FIG. 9 is a cross-sectional view of a silicon carbide semiconductor device according to a second embodiment
  • FIG. 11 is a schematic diagram showing the configuration of a power converter diagram according to Embodiment 3;
  • the first conductivity type is n-type and the second conductivity type is p-type, but the conductivity types may be reversed.
  • FIG. 1 is a cross-sectional view of a part of an active region of a silicon carbide MOSFET with built-in Schottky barrier diode (SiC-MOSFET with built-in SBD), which is a silicon carbide semiconductor device according to a first embodiment.
  • FIG. 2 is a plan view of a part of the active region of the SBD-embedded SiC trench MOSFET shown in FIG.
  • a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type low-resistance silicon carbide.
  • a pair of well regions 30 made of p-type silicon carbide are provided in an upper layer portion of the drift layer 20 and separated from each other in a cross-sectional view.
  • a first separation region 21 that is part of the drift layer 20 is provided between the pair of well regions 30 .
  • n-type silicon carbide is provided at a position inside the cross-sectional lateral direction from the second spacing region 22 side toward the first spacing region 21 by a predetermined distance from the end of the well region 30 on the second spacing region 22 side.
  • a source region 40 composed of is formed. Further inside the source region 40, that is, inside the surface layer portion of the well region 30 on the side of the first separation region 21 from the source region 40 in the cross-sectional lateral direction, a contact region made of low-resistance p-type silicon carbide is formed. 35 are formed.
  • a region made of silicon carbide that is, a region formed as drift layer 20 is called a silicon carbide layer.
  • the source region 40 and the contact region 35 are formed in contact with each other.
  • An n-type current diffusion region 41 having a higher n-type impurity concentration than the first separation region 21 is formed in the surface layer portion of the well region 30 between the first separation region 21 and the contact region 35 .
  • An ohmic electrode 70 is formed on the surfaces of source region 40 and contact region 35 .
  • a Schottky electrode 71 is formed on the first separation region 21 and the current diffusion region 41, and the Schottky electrode 71 and the first separation region 21 are Schottky-connected.
  • the first separation region 21 and the Schottky electrode 71 constitute an SBD, and the interface between the first separation region 21 and the Schottky electrode 71 is the Schottky interface.
  • a gate insulating film 50 made of silicon oxide is formed on the surface of the source region 40 in the well region 30, on the second separation region 22, and on the well region 30 between the source region 40 and the second separation region 22. is formed.
  • a gate electrode 60 made of low resistance polycrystalline silicon is formed on the gate insulating film 50 in the region from the source region 40 to the second separation region 22 .
  • a surface layer portion of the well region 30 facing the gate electrode 60 with the gate insulating film 50 therebetween becomes a channel region under the portion where the gate electrode 60 is formed.
  • An interlayer insulating film 55 made of silicon oxide is formed on the gate electrode 60 and the gate insulating film 50 .
  • a contact hole formed by removing the gate insulating film 50 and the interlayer insulating film 55 is formed on the Schottky electrode 71 and the ohmic electrode 70, and the contact hole and the interlayer insulating film on the Schottky electrode 71 and the ohmic electrode 70 are formed.
  • a source electrode 80 is formed on 55 . Further, a rear surface ohmic electrode 72 and a drain electrode 81 are formed on the surface of the semiconductor substrate 10 opposite to the drift layer 20 .
  • FIG. 2 is a plan view near the silicon carbide layer surface of the active region of the SBD-embedded SiC-MOSFET according to the first embodiment of the present disclosure.
  • a current diffusion region 41, a contact region 35, a source region 40, a well region 30, and a second separation region 22 are formed in order from the inside so as to surround the first separation region 21.
  • the Schottky electrode 71 is also formed on the region from above the first separation region 21 to above the current diffusion region 41 .
  • An ohmic electrode 70 is formed on the contact region 35 .
  • the gate electrode 60 is formed outside the ohmic electrode 70 .
  • a well region 30 is formed below the current diffusion region 41 in cross section.
  • the unit cell of the active region of the SBD-embedded SiC-MOSFET according to the first embodiment of the present disclosure may be striped, as shown in the plan view of FIG. Even in a striped unit cell, a current diffusion region 41, a contact region 35, a source region 40, a well region 30, and a second separation region 22 are formed in order from the inside centering on the first separation region 21. .
  • Drift layer 20 made of silicon carbide having an impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less, n-type, and a thickness of 5 ⁇ m or more and 80 ⁇ m or less by (Chemical Vapor Deposition: CVD method). is epitaxially grown. Drift layer 20 may have a thickness of 80 ⁇ m or more depending on the withstand voltage of the silicon carbide semiconductor device.
  • an implantation mask is formed of photoresist or the like on a predetermined region of the surface of the drift layer 20, and ions of Al (aluminum), which is a p-type impurity, are implanted.
  • the depth of the Al ion implantation is about 0.5 ⁇ m or more and 3 ⁇ m or less, which does not exceed the thickness of the drift layer 20 .
  • the impurity concentration of ion-implanted Al is in the range of 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less, which is higher than the impurity concentration of the drift layer 20 .
  • the implantation mask is removed. A region implanted with Al ions in this step becomes the well region 30 .
  • an implantation mask is formed with a photoresist or the like so that a predetermined portion inside the well region 30 on the surface of the drift layer 20 is opened, and N (nitrogen), which is an n-type impurity, is ion-implanted.
  • the N ion implantation depth is assumed to be shallower than the thickness of the well region 30 .
  • the impurity concentration of ion-implanted N is in the range of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less, and exceeds the p-type impurity concentration of the well region 30 .
  • the region exhibiting the n-type becomes the source region 40 .
  • the implantation mask is removed.
  • contact regions 35 are formed by ion-implanting Al into a predetermined region inside the well region 30 with an impurity concentration higher than that of the well region 30 .
  • the impurity concentration of Al in the contact region 35 may be in the range of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • N is ion-implanted into the surface layer of the well region 30 between the contact region 35 and the first separation region 21 to form the current diffusion region 41 .
  • the N ion implantation depth is shallower than the thickness of the well region 30, for example, 10 nm or more and 200 nm or less.
  • the impurity concentration of N in the current diffusion region 41 may be in the range of 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less.
  • annealing is performed in an inert gas atmosphere such as argon (Ar) gas at a temperature of 1300 to 1900° C. for 30 seconds to 1 hour using a heat treatment apparatus.
  • This annealing electrically activates the implanted N and Al ions.
  • gate insulating film 50 having a thickness of 10 nm or more and 300 nm or less.
  • a silicon oxide film is formed.
  • a conductive polycrystalline silicon film is formed on the gate insulating film 50 by low pressure CVD, and patterned to form the gate electrode 60 .
  • an interlayer insulating film 55 made of silicon oxide is formed by low pressure CVD.
  • a rear surface ohmic electrode 72 is formed on the surface of the semiconductor substrate 10 on which the drift layer 20 is not formed.
  • a contact hole (first portion of the contact hole) penetrating through the interlayer insulating film 55 and the gate insulating film 50 to reach the contact region 35 and the source region 40 in the active region is formed by dry etching.
  • dry etching it is possible to form the contact holes perpendicular to the surface of the silicon carbide layer, to reduce the repetition cycle (cell pitch) of the unit cells, and to increase the on-current density per unit area. be able to.
  • a metal film containing nickel (Ni) as a main component by sputtering or the like heat treatment is performed at a temperature of 600 to 1100° C. to form a metal film containing Ni as a main component and a contact hole (first portion). ) to form a silicide between the silicon carbide layer and the metal film.
  • the metal film is Ni
  • the silicide becomes nickel silicide.
  • the remaining metal film other than the silicide formed by the reaction is removed by wet etching.
  • the silicide formed here becomes the ohmic electrode 70 .
  • a resist mask is formed on the surfaces of the ohmic electrode 70 and the interlayer insulating film 55 by photolithography.
  • an etchant containing hydrofluoric acid is used to etch the gate insulating film 50 and the interlayer insulating film above the region including the surface of the first separation region 21 and the surface of the current diffusion region 41 . 55 are wet etched.
  • the region wet-etched here also becomes a part of the contact hole (second part of the contact hole). After that, the resist mask is removed.
  • a Schottky electrode 71 made of Ti, Mo, or the like, which is Schottky-connected to the first spacing region 21 is formed on the surface of the first spacing region 21 and the surface of the current diffusion region 41 .
  • a source electrode 80 containing Al as a main component is formed on the Schottky electrode 71 and the ohmic electrode 70 .
  • a back surface ohmic electrode 72 on the back surface side and a drain electrode 81 on the bottom side in contact with the back surface ohmic electrode 72 are formed to form the silicon carbide semiconductor device of the present embodiment, the cross-sectional view of which is shown in FIG.
  • An SBD-embedded SiC-MOSFET can be manufactured.
  • the n-type impurity concentration of the current diffusion region 41 is higher than the n-type impurity concentration of the drift layer 20 , especially the first separation region 21 . Also, the n-type impurity concentration of the current diffusion region 41 is assumed to be lower than the n-type impurity concentration of the source region 40 .
  • the n-type impurity concentration of the current diffusion region 41 is formed lower than the p-type impurity concentration of the well region 30 .
  • the depletion layer extending from the pn junction surface between the current diffusion region 41 and the well region 30 to the current diffusion region 41 side extends to the Schottky electrode 71 formed on the current diffusion region 41 in the off state. The electric field applied to the Schottky electrode 71 can be reduced.
  • the drift layer 20 of the SBD-embedded SiC-MOSFET of the present embodiment does not need to have the same impurity concentration throughout the entire area, and as shown in the cross-sectional view of FIG.
  • the n-type impurity concentration up to the vicinity of the bottom position may be higher than the drift layer 20 on the semiconductor substrate 10 side of the well region 30 .
  • the n-type impurity concentration of the first spacing region 21 and the second spacing region 22 can be made higher than that of the drift layer 20 below the well region 30, and the on-state resistance can be further reduced.
  • the source region 40 and the contact region 35 may be formed apart from each other. If the source region 40 and the contact region 35 are formed in contact with each other, the size of the unit cell can be reduced, the on-current flowing per unit area can be increased, and the resistance can be further reduced.
  • the Schottky electrode 71 and the source electrode 80 may be made of the same material, or the source electrode 80 may be made by laminating a plurality of materials.
  • the silicon carbide semiconductor device of the present embodiment adjacent to the SBD formed between first spacing region 21 and Schottky electrode 71, there is a region where n-type current diffusion region 41 and Schottky electrode 71 are adjacent to each other. Therefore, in the first separation region 21, which is the region through which the unipolar current flows through the Schottky interface during freewheeling operation, the region through which the unipolar current substantially flows can be expanded in the transverse direction of the cross section. The unipolar current density flowing in the freewheeling state can be increased without widening the width to increase the field strength applied to the Schottky interface when the MOSFET is in the off state. Therefore, the chip size required to suppress the operation of the body diode formed between well region 30 and drift layer 20 is reduced compared to a silicon carbide semiconductor device in which current diffusion region 41 is not formed. and costs can be reduced.
  • FIG. 5 is a cross-sectional view of part of the active region in the silicon carbide semiconductor device of the second embodiment.
  • the surface layer portion of well region 30 between second spacing region 22 and contact region 35 is similar to current diffusion region 41 .
  • an n-type channel current diffusion region 42 is formed. Since other points are the same as those of the first embodiment, detailed description thereof will be omitted.
  • FIG. 5 is a cross-sectional view of part of an active region of an SBD-embedded SiC-MOSFET, which is the silicon carbide semiconductor device of the present embodiment.
  • SBD-embedded SiC-MOSFET which is the silicon carbide semiconductor device of the present embodiment.
  • n An n-type channel current diffusion region 42 having a high impurity concentration is formed.
  • the current diffusion region 41 and the channel current diffusion region 42 are formed with the same thickness and the same impurity concentration.
  • the SBD-embedded SiC-MOSFET of this embodiment can be manufactured by the same manufacturing method as the SBD-embedded SiC-MOSFET of the embodiment, but the current diffusion region 41 and the channel current diffusion region 42 are formed in the p-type well region 30.
  • N may be ion-implanted using the resist mask used at the time of formation. At this time, N ions are also implanted into the surface portions of the source region 40 and the contact region 35. However, since the density of the implanted ions is lower than the impurity concentration of the source region 40 and the contact region 35 by one order of magnitude or more, the source region 40 and the contact region 35 are hardly affected.
  • the silicon carbide semiconductor device of the present disclosure can be manufactured while suppressing an increase in manufacturing cost.
  • the channel resistance can be further reduced.
  • the p-type impurity may be boron (B) or gallium (Ga).
  • the n-type impurity may be phosphorus (P) instead of nitrogen (N).
  • the gate insulating film does not necessarily have to be an oxide film such as SiO 2 . may be a combination of Further, in the above-described embodiments, the crystal structure, the plane orientation of the main surface, the off-angle, the implantation conditions, and the like have been described using specific examples, but the scope of application is not limited to these numerical ranges.
  • the silicon carbide semiconductor device of a so-called vertical MOSFET with an SBD embedded therein has been described, but the present invention can also be applied to a MOSFET having a superjunction structure with an SBD embedded therein.
  • Embodiment 3 applies the silicon carbide semiconductor devices according to the first and second embodiments described above to a power converter. Although the present disclosure is not limited to a specific power converter, a case where the present disclosure is applied to a three-phase inverter will be described below as a third embodiment.
  • FIG. 6 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.
  • the power supply 100 is a DC power supply and supplies DC power to the power converter 200 .
  • the power supply 100 can be composed of various things, for example, it can be composed of a DC system, a solar battery, a storage battery, or it can be composed of a rectifier circuit or an AC/DC converter connected to an AC system. good too. Also, the power supply 100 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.
  • Power converter 200 is a three-phase inverter connected between power supply 100 and load 300 , converts DC power supplied from power supply 100 into AC power, and supplies AC power to load 300 .
  • the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a drive circuit 202 that outputs a drive signal for driving each switching element of the main conversion circuit 201. , and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202 .
  • the drive circuit 202 turns off each normally-off switching element by setting the voltage of the gate electrode and the voltage of the source electrode to the same potential.
  • the load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200 .
  • the load 300 is not limited to a specific application, but is an electric motor mounted on various electrical equipment, such as a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an electric motor for air conditioning equipment.
  • the main conversion circuit 201 includes a switching element and a freewheeling diode (not shown). By switching the switching element, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300 .
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and has six switching elements and It can consist of six freewheeling diodes in anti-parallel.
  • a silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device according to any one of the first to third embodiments described above is applied to each switching element of main conversion circuit 201 .
  • each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit.
  • Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 201 are connected to the load 300 .
  • the drive circuit 202 generates a drive signal for driving the switching element of the main converter circuit 201 and supplies it to the control electrode of the switching element of the main converter circuit 201 .
  • a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element.
  • the driving signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the driving signal is a voltage equal to or less than the threshold voltage of the switching element. signal (off signal).
  • the control circuit 203 controls the switching elements of the main converter circuit 201 so that desired power is supplied to the load 300 . Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the ON state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an ON signal is output to the switching element that should be in the ON state at each time point, and an OFF signal is output to the switching element that should be in the OFF state.
  • a control command control signal
  • the drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the silicon carbide semiconductor device according to the first and second embodiments is applied as the switching element of the main conversion circuit 201, the power with improved reliability of low loss and high-speed switching A conversion device can be implemented.
  • the present disclosure is not limited to this, and can be applied to various power converters.
  • a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used. You can apply it.
  • the present disclosure can be applied to a DC/DC converter or an AC/DC converter when power is supplied to a DC load or the like.
  • the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, an electric storage system, or the like.

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PCT/JP2021/022527 2021-06-14 2021-06-14 炭化珪素半導体装置および炭化珪素半導体装置を用いた電力変換装置 Ceased WO2022264212A1 (ja)

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US18/567,023 US20240274709A1 (en) 2021-06-14 2021-06-14 Silicon carbide semiconductor device and power conversion device using silicon carbide semiconductor device
PCT/JP2021/022527 WO2022264212A1 (ja) 2021-06-14 2021-06-14 炭化珪素半導体装置および炭化珪素半導体装置を用いた電力変換装置
JP2023529170A JP7573747B2 (ja) 2021-06-14 2021-06-14 炭化珪素半導体装置および炭化珪素半導体装置を用いた電力変換装置
CN202180099162.3A CN117461143A (zh) 2021-06-14 2021-06-14 碳化硅半导体装置以及使用碳化硅半导体装置的电力变换装置
DE112021007820.8T DE112021007820B4 (de) 2021-06-14 2021-06-14 Siliciumcarbid-halbleitereinrichtung und stromrichtereinrichtung, die die siliciumcarbid-halbleitereinrichtung verwendet

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JP2012099630A (ja) * 2010-11-02 2012-05-24 Panasonic Corp 半導体装置および電力変換器
WO2019124384A1 (ja) * 2017-12-19 2019-06-27 三菱電機株式会社 炭化珪素半導体装置および電力変換装置
WO2020110285A1 (ja) * 2018-11-30 2020-06-04 三菱電機株式会社 半導体装置
WO2021044624A1 (ja) * 2019-09-06 2021-03-11 三菱電機株式会社 炭化珪素半導体装置および電力変換装置
JP2021077774A (ja) * 2019-11-11 2021-05-20 株式会社日立製作所 半導体装置

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JP6923457B2 (ja) 2018-01-19 2021-08-18 株式会社日立製作所 炭化ケイ素半導体装置およびその製造方法、電力変換装置、自動車並びに鉄道車両
JP7002998B2 (ja) 2018-05-28 2022-01-20 株式会社日立製作所 半導体装置及びその製造方法、電力変換装置、３相モータシステム、自動車、並びに鉄道車両

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JP2012099630A (ja) * 2010-11-02 2012-05-24 Panasonic Corp 半導体装置および電力変換器
WO2019124384A1 (ja) * 2017-12-19 2019-06-27 三菱電機株式会社 炭化珪素半導体装置および電力変換装置
WO2020110285A1 (ja) * 2018-11-30 2020-06-04 三菱電機株式会社 半導体装置
WO2021044624A1 (ja) * 2019-09-06 2021-03-11 三菱電機株式会社 炭化珪素半導体装置および電力変換装置
JP2021077774A (ja) * 2019-11-11 2021-05-20 株式会社日立製作所 半導体装置

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