WO2022259676A1 - 半導体装置用基板 - Google Patents

半導体装置用基板 Download PDF

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Publication number
WO2022259676A1
WO2022259676A1 PCT/JP2022/011601 JP2022011601W WO2022259676A1 WO 2022259676 A1 WO2022259676 A1 WO 2022259676A1 JP 2022011601 W JP2022011601 W JP 2022011601W WO 2022259676 A1 WO2022259676 A1 WO 2022259676A1
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WO
WIPO (PCT)
Prior art keywords
copper plate
semiconductor device
recess
plate
recesses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/011601
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English (en)
French (fr)
Japanese (ja)
Inventor
智生 高井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Insulators Ltd
NGK Electronics Devices Inc
Original Assignee
NGK Insulators Ltd
NGK Electronics Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Insulators Ltd, NGK Electronics Devices Inc filed Critical NGK Insulators Ltd
Priority to DE112022002069.5T priority Critical patent/DE112022002069T5/de
Priority to CN202280040561.7A priority patent/CN117480599A/zh
Publication of WO2022259676A1 publication Critical patent/WO2022259676A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H10W70/6525—Cross-sectional shapes for securing the interconnections to the substrate, e.g. to prevent peeling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/80—Arrangements for protection of devices protecting against overcurrent or overload, e.g. fuses or shunts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/658—Shapes or dispositions of interconnections for devices provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires

Definitions

  • the present invention relates to substrates for semiconductor devices.
  • DBOC substrates Direct Bonding of Copper Substrates
  • a copper plate is provided on the surface of an insulating plate such as a ceramic sintered body
  • an insulating plate such as a ceramic sintered body
  • a concave portion as shown in Patent Document 1 can be formed on the peripheral edge of the copper plate.
  • the present invention has been made to solve the above problems, and provides a substrate for a semiconductor device capable of suppressing inhibition of wetting and spreading of a bonding material such as solder even if a concave portion is formed in a copper plate. for the purpose.
  • a substrate for a semiconductor device comprises: an insulating plate having a first surface and a second surface; a first copper plate bonded to the first surface of the insulating plate to form a conductive pattern; and a second copper plate bonded to the second surface, wherein a plurality of recesses are formed in at least one of the first copper plate and the second copper plate, and the diameter D1 of the opening of each recess is larger than the opening of the recess. It is smaller than the internal maximum diameter D2.
  • the edge of the first copper plate or the second copper plate which corresponds to the edge of the recess, protrudes radially inward of the opening and has an arc-shaped cross section. can be done.
  • the radius of curvature of the edge portion may be 2.0 ⁇ m or more.
  • the maximum diameter D2 with respect to the diameter D1 may be 1.08 or more.
  • the recess may be formed so as not to reach the insulating plate.
  • a plurality of recesses may be formed along the peripheral edge of at least one of the first copper plate and the second copper plate.
  • a plurality of recesses may be formed near the center of the first copper plate.
  • both the first copper plate and the second copper plate may be formed with a plurality of recesses.
  • the present invention even if recesses are formed in the copper plate, it is possible to suppress inhibition of wetting and spreading of the bonding material such as solder.
  • FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device having a semiconductor device substrate according to the present invention
  • FIG. 1 is a plan view of a substrate for a semiconductor device
  • FIG. 1 is an enlarged cross-sectional view of a substrate for a semiconductor device
  • FIG. 5 is a cross-sectional view showing another example of a recess
  • 4 is a cross-sectional view of a recess in Example 1.
  • FIG. 4 is an enlarged cross-sectional view of the edge of the recess in Example 1.
  • FIG. 11 is a cross-sectional view of a recess in Example 3
  • FIG. 11 is an enlarged cross-sectional view of the edge of the recess in Example 3;
  • FIG. 11 is a cross-sectional view of a recess in Example 4;
  • FIG. 12 is an enlarged cross-sectional view of the edge of the recess in Example 4;
  • FIG. 11 is a cross-sectional view of a recess in Example 6;
  • FIG. 12 is an enlarged cross-sectional view of the edge of the recess in Example 6;
  • FIG. 1 is a cross-sectional view of a semiconductor device having a semiconductor device substrate according to this embodiment.
  • the semiconductor device includes, for example, automobiles, air conditioners, industrial robots, commercial elevators, household microwave ovens, IH electric rice cookers, power generation (wind power generation, solar power generation, fuel cells, etc.), electric railways, It is used as a power module in various electronic devices such as UPS (uninterruptible power supply).
  • UPS uninterruptible power supply
  • a semiconductor device 1 As shown in FIG. 1, a semiconductor device 1 according to this embodiment includes a semiconductor device substrate 2, a first bonding material 5, a second bonding material 5', a semiconductor chip 6, bonding wires 7, and a heat sink 8. there is
  • the semiconductor device substrate 2 is a so-called DBOC substrate (Direct Bonding of Copper Substrate), and includes a plate-shaped insulating plate 3 which is an insulator, a first copper plate 4 bonded to its first surface (upper surface), and a second copper substrate. and a second copper plate 4' joined to two surfaces (lower surfaces).
  • DBOC substrate Direct Bonding of Copper Substrate
  • the insulating plate 3 is made of ceramics with high thermal conductivity, such as aluminum oxide, aluminum nitride, and silicon nitride.
  • the thickness of the insulating plate 3 is, for example, preferably 0.25 to 0.635 mm, more preferably 0.25 to 0.38 mm.
  • a transmission circuit such as a conductive pattern is formed on the first copper plate 4 .
  • the second copper plate 4' is formed in a flat plate shape.
  • the thickness of these copper plates 4, 4' is, for example, preferably 0.1 to 2.0 mm, more preferably 0.2 to 0.4 mm. If the copper plates 4, 4' are thick, the heat dissipation of the semiconductor device substrate 2 is enhanced, but on the other hand, the thermal stress may be increased and the reliability may be lowered. Therefore, the thickness of the copper plates 4 and 4' is set according to the use of the semiconductor device 1, the mechanical strength of the insulating plate 3, and the like. Further, recesses are formed in the second copper plate 4' as will be described later.
  • a semiconductor chip 6 is bonded to the upper surface of the semiconductor device substrate 2 , that is, to a portion of the upper surface of the first copper plate 4 with a first bonding material 5 interposed therebetween. Also, the semiconductor chip 6 and the first copper plate 4 are connected by bonding wires 7 .
  • a heat sink 8 is joined to the lower surface of the semiconductor device substrate 2, that is, the lower surface of the second copper plate 4' via the second joint material 5'.
  • the heat sink 8 is known and can be made of metal such as copper.
  • the joining materials 5, 5' can be formed with solder, silver solder, or the like.
  • solder for example, tin-silver-copper alloy, tin-zinc-bismuth alloy, tin-copper alloy, tin-silver-indium-bismuth.
  • a lead-free solder containing at least one alloy as a main component can be used.
  • FIG. 2 is a plan view of the semiconductor device substrate viewed from the second copper plate
  • FIG. 3 is an enlarged sectional view of FIG.
  • a plurality of recesses 9 are formed along the periphery of the second copper plate 4' at predetermined intervals in the second copper plate 4'.
  • Each recess 9 is formed in a hemispherical shape, and the planar shape of the opening is formed in a circular shape. Then, the above-described second bonding material 5 ′ flows into each recess 9 .
  • Each recess 9 is circular in plan view, and FIG. 3 is a cross-sectional view in the thickness direction of the second copper plate 4' passing through the center of the circle.
  • the diameter of the opening of each concave portion 9, which is circular in plan view, is represented by D1.
  • Each concave portion 9 is a cavity that is close to a sphere inside the second copper plate 4'. Therefore, the cross-sectional shape of each concave portion 9 is a shape obtained by cutting a part of a circle as shown in FIG.
  • D2 be the maximum dimension of the dimensions of the recesses 9 in the direction perpendicular to the thickness direction of the second copper plate 4'.
  • D3 be the maximum dimension among the dimensions of the recesses 9 in the thickness direction of the second copper plate 4'.
  • D3 is the depth dimension of each recess 9 .
  • the diameter D1 of the opening of each recess 9 is smaller than the maximum diameter D2 inside the opening. Therefore, the edge 91 of the second copper plate 4' corresponding to the opening edge of each recess 9 protrudes radially inward of the opening. Further, in this embodiment, the tip of the edge portion 91 is formed to have an arcuate cross-section.
  • the diameter D1 of each recess 9 is preferably 300-700 ⁇ m, more preferably 400-600 ⁇ m.
  • the maximum diameter D2 is preferably 320 to 700 ⁇ m, more preferably 450 to 700 ⁇ m.
  • the ratio of the maximum diameter D2 to the diameter D1 is preferably 1.05 to 1.20, more preferably 1.08 to 1.15.
  • the depth D3 of the recess 9 is smaller than the thickness of the second copper plate 4', preferably 100-400 ⁇ m, more preferably 250-390 ⁇ m.
  • the ratio of the depth D3 of the recess 9 to the diameter D1 of the recess 9 is preferably 0.5 to 0.8, more preferably 0.6 to 0.8.
  • the radius of curvature of the cross section of the edge 91 of the second copper plate 4' is preferably 1.5 to 10.0 ⁇ m, more preferably 2.0 to 8.0 ⁇ m.
  • the cross-sectional shape of the edge portion 91 does not necessarily have to be arcuate, and may be formed to have an acute angle.
  • the interval W between the concave portions 9 is preferably 0.1 to 0.5 mm, more preferably 0.15 to 0.3 mm.
  • a laminate is formed by arranging the first and second copper plates 4, 4' on the upper and lower surfaces of the insulating plate 3. As shown in FIG. Here, the surface of each copper plate used is oxidized. Next, this laminate is heated at 1065° C. to 1083° C. under a nitrogen atmosphere for about 10 minutes. As a result, a Cu--O eutectic liquid phase is generated at the interfaces where the insulating plate 3 and the first and second copper plates 4, 4' are joined, and each surface of the insulating plate 3 is wetted.
  • the laminate is cooled to solidify the Cu—O eutectic liquid phase, and the first and second copper plates 4 and 4 ′ are bonded to the insulating plate 3 .
  • the first and second copper plates 4, 4' may be joined to the insulating plate 3 in a vacuum with a brazing material containing an active metal such as titanium.
  • recesses 9 are formed in the second copper plate 4'.
  • a mask layer having circular through holes corresponding to the concave portions 9 of the second copper plate 4' is laminated on the second copper plate 4'.
  • the inner diameter of these through-holes is smaller than the diameter D1 of the opening of the recess 9, and can be, for example, 35 to 55% of the diameter D1.
  • etching is performed at an etching speed of 0.5 to 5 m/min to form recesses 9 .
  • the transmission circuit formed on the first copper plate 4 can be formed by, for example, a subtractive method or an additive method.
  • the following effects can be obtained. (1) Even if thermal stress due to temperature change of the semiconductor device 1 acts on the semiconductor device substrate 2, the plurality of recesses 9 can alleviate the thermal stress generated in the peripheral edge of the second copper plate 4'. As a result, cracking of the semiconductor device substrate 2 and peeling of the second copper plate 4' can be prevented.
  • the diameter D1 of the opening of the recess 9 is smaller than the maximum diameter D2 inside the recess 9, the area of the main surface of the second copper plate 4' can be increased while forming the recess 9. As a result, it is possible to reduce the obstruction of the wetting and spreading of the bonding material 5' such as solder flowing over the main surface of the flat second copper plate 4' by the recesses 9. As shown in FIG. As a result, the formation of cavities in the bonding material 5' between the second copper plate 4' and the heat sink 8 is suppressed, and the heat generated in the semiconductor chip 6 can be transferred to the heat sink 8 satisfactorily.
  • the second bonding material 5' is smoothly guided into the recess 9 from the main surface of the second copper plate 4'. , making it easier to flow into the recess 9 .
  • the larger the radius of curvature of the edge portion 91 the easier it is for the second bonding material 5' to flow. Therefore, formation of voids in the recess 9 can be suppressed. Therefore, partial discharge inside the voids can be suppressed, and deterioration of heat dissipation due to the voids can be suppressed.
  • one row of recesses 9 is formed along the periphery of the second copper plate 4', but two or more rows may be formed.
  • the recesses 9 are formed only in the second copper plate 4 ′, but the recesses 9 can also be formed in the first copper plate 4 .
  • one or more rows of recesses 9 can be formed along the peripheral edge of the first copper plate 4 as in the case of the second copper plate 4'.
  • the concave portion 9 can be formed in the vicinity of the center of the first copper plate 4 . This concave portion 9 can be used, for example, for positioning the semiconductor chip 6 .
  • the shape of the opening of the concave portion 9 is not particularly limited, and in addition to the circular shape described above, it may be an elliptical shape, or a rectangular shape with rounded corners.
  • the diameter D1 of the opening can be the maximum diameter.
  • a circumscribed circle equivalent diameter for the shape of the opening can be set.
  • the cross-sectional shape of the recess 9 may be a part of a substantially circular shape, or a part of an ellipse.
  • the recess 9 is formed in the second copper plate 4' and does not reach the insulating plate 3, but as shown in FIG. It may reach up to 3. In this case, the thermal stress relieving effect of the concave portion 9 is enhanced.
  • the volume of the second copper plate 4 ′ relatively increases when the recessed portion 9 does not reach the insulating plate 3 as compared with the case where the recessed portion 9 reaches the insulating plate 3 . Therefore, heat dissipation is enhanced. Furthermore, since the volume of the recess 9 is reduced, the formation of voids due to insufficient flow of the second bonding material 5' can be suppressed.
  • Alumina with a thickness of 0.32 mm was prepared as an insulating plate.
  • a copper plate having a thickness of 0.4 mm and having an oxidized surface was placed on both sides of the insulating plate, and heated at 1070° C. for about 10 minutes in a nitrogen atmosphere to bond the copper plate to the insulating plate.
  • a concave portion as described below was formed along the peripheral edge of one of the copper plates of the semiconductor device substrate thus obtained, and semiconductor device substrates according to Examples 1 to 6 were obtained.
  • the recess was formed by etching.
  • Table 1 shows the diameter of the through-holes formed in the recess mask and the etching speed.
  • a circuit pattern with a desired shape is formed by masking the surface of the copper plate of the bonded body in which an insulating plate and a copper plate are bonded with an etching resist or dry film, and chemically etching the unmasked copper plate portion. .
  • Etching speed indicates the speed at which the bonded material is passed through an etching area having a length of about 5 m. In the etching area, an etchant is sprayed toward the bonded body to etch the copper plate. By such etching, recesses as shown in Table 2 below were formed in Examples 1 to 6.
  • Example 6 penetrates the copper plate and reaches the insulating plate.
  • semiconductor device substrates according to Examples 1 to 6 were obtained.
  • the length of the edge portion in Table 2 below is the length of the portion that protrudes from the maximum diameter D2 of the recess, and is calculated by (D2-D1)/2.
  • 5 to 8 show the cross-sectional shapes of the recesses formed in Examples 1, 3, 4, and 6, and enlarged views of the edge portions, respectively.
  • each concave portion has an arcuate cross-section of the edge portion. Therefore, it is possible to make it easier for the bonding material to flow from the main surface of the copper plate toward the inside of the recess.

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/JP2022/011601 2021-06-09 2022-03-15 半導体装置用基板 Ceased WO2022259676A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112022002069.5T DE112022002069T5 (de) 2021-06-09 2022-03-15 Substrat für Halbleitervorrichtung
CN202280040561.7A CN117480599A (zh) 2021-06-09 2022-03-15 半导体装置用基板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021096735A JP7652631B2 (ja) 2021-06-09 2021-06-09 半導体装置用基板
JP2021-096735 2021-06-09

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WO2022259676A1 true WO2022259676A1 (ja) 2022-12-15

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CN (1) CN117480599A (https=)
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10332695A1 (de) * 2003-07-18 2005-02-03 Robert Bosch Gmbh Anordnung zur Befestigung eines Bauelements
JP2009094135A (ja) * 2007-10-04 2009-04-30 Fuji Electric Device Technology Co Ltd 半導体装置、半導体装置の製造方法、および半田ペースト塗布用のメタルマスク
WO2019167509A1 (ja) * 2018-03-01 2019-09-06 富士電機株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10332695A1 (de) * 2003-07-18 2005-02-03 Robert Bosch Gmbh Anordnung zur Befestigung eines Bauelements
JP2009094135A (ja) * 2007-10-04 2009-04-30 Fuji Electric Device Technology Co Ltd 半導体装置、半導体装置の製造方法、および半田ペースト塗布用のメタルマスク
WO2019167509A1 (ja) * 2018-03-01 2019-09-06 富士電機株式会社 半導体装置

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JP7652631B2 (ja) 2025-03-27
DE112022002069T5 (de) 2024-01-25
CN117480599A (zh) 2024-01-30
JP2022188583A (ja) 2022-12-21

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