WO2022252323A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2022252323A1
WO2022252323A1 PCT/CN2021/103171 CN2021103171W WO2022252323A1 WO 2022252323 A1 WO2022252323 A1 WO 2022252323A1 CN 2021103171 W CN2021103171 W CN 2021103171W WO 2022252323 A1 WO2022252323 A1 WO 2022252323A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
clock signal
area
display panel
common electrode
Prior art date
Application number
PCT/CN2021/103171
Other languages
English (en)
French (fr)
Inventor
肖邦清
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/431,155 priority Critical patent/US12032251B2/en
Publication of WO2022252323A1 publication Critical patent/WO2022252323A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present application relates to the technical field of display panels, in particular to a display panel.
  • An embodiment of the present application provides a display panel, which can reduce the frame width of the display panel while reducing the resistance difference between the clock signal lines.
  • An embodiment of the present application provides a display panel, including a non-display area, and the non-display area includes a GOA unit area, a wiring area, and a first wiring area arranged along a first direction;
  • the display panel includes:
  • DBS common electrode wiring located in the wiring area, and extending along the second direction;
  • each of the clock signal traces extends along the second direction;
  • a plurality of clock signal transfer lines are connected to the plurality of clock signal routing lines in one-to-one correspondence, each of the clock signal transfer lines passes through the winding area and extends to the GOA unit area along the first direction , at least one of the clock signal transfer lines is bent and arranged in the winding area;
  • the multiple clock signal transfer wires are located on different layers from the DBS common electrode wires and the multiple clock signal wires.
  • the overlapping area of each of the clock signal transition lines and the DBS common electrode wiring in the wiring area is the same.
  • the orthographic projection of the DBS common electrode wiring on the wiring area completely covers the wiring area, and a hollow area is set in the DBS common electrode wiring;
  • the hollowed out area includes a plurality of hollowed out structures arranged along the second direction, and each of the clock signal transition lines corresponds to at least one hollowed out structure;
  • the hollowed out area includes a plurality of hollowed out structures arranged along the second direction, and each of the clock signal transfer lines corresponds to one hollowed out structure;
  • the display panel further includes CF common electrode wiring and CF common electrode feedback wiring;
  • Both the CF common electrode wiring and the CF common electrode feedback wiring are located in the first wiring area and extend along the second direction.
  • the non-display area further includes a second routing area located between the GOA unit area and the routing area;
  • the display panel also includes voltage wiring and voltage transfer wires
  • the voltage wiring is located in the second wiring area and extends along the second direction; the voltage transfer line is connected to the voltage wiring and extends to the GOA unit area along the first direction , the voltage wiring and the voltage transfer wiring are located on different layers.
  • the display panel further includes a normal-phase signal wiring, a normal-phase signal transfer line, a reverse-phase signal trace, and a reverse-phase signal transfer wire;
  • Both the normal-phase signal trace and the reverse-phase signal trace are located in the second trace region and extend along the second direction;
  • the normal-phase signal transition line is connected to the normal-phase signal wiring and extends to the GOA unit area along the first direction, and the normal-phase signal transition line and the normal-phase signal wiring are located on different layers ;
  • the reverse signal transfer line is connected to the reverse signal routing line, and extends to the GOA unit area along the first direction, and the reverse phase signal routing line is located at a different location than the reverse phase signal transfer line Floor.
  • each clock signal routing includes a plurality of sub-wires cross-connected, and the plurality of sub-wires form a mesh structure.
  • both the CF common electrode wiring and the CF common electrode feedback wiring include a plurality of cross-connected sub-wires, and the plurality of sub-wires form a mesh structure.
  • the voltage routing includes multiple sub-wires cross-connected, and the multiple sub-wires form a mesh structure.
  • both the normal-phase signal wiring and the anti-phase signal wiring include a plurality of cross-connected sub-wires, and the plurality of sub-wires form a mesh structure.
  • the DBS common electrode wiring is located on the same layer as the plurality of clock signal wirings.
  • the CF common electrode wiring, the CF common electrode feedback wiring and the clock signal wiring are arranged on the same layer.
  • the voltage wiring is located on the same layer as the clock signal wiring, and the voltage transition line is located on the same layer as the clock signal transition line.
  • the normal-phase signal wiring, the reverse-phase signal wiring and the clock signal wiring are located on the same layer, and the normal-phase signal transition line, the reverse-phase signal transition line and the clock signal
  • the patch cords are on the same level.
  • the DBS common electrode wiring is located in the winding area and extends along the second direction, a plurality of clock signal wirings are arranged in the first wiring area along the first direction, and each clock signal wiring is along the Extending in the second direction, multiple clock signal transfer lines are connected to multiple clock signal routing lines in one-to-one correspondence, each clock signal transfer line passes through the winding area and extends to the GOA unit area along the first direction, at least one clock signal transfer line
  • the wiring is bent and set in the winding area to reduce the resistance difference between the clock signal lines through the bending setting of the clock signal transfer line.
  • the DBS common electrode wiring is located in the winding area to avoid setting the DBS common electrode wiring separately.
  • the wire increases the wiring space, thereby reducing the bezel width of the display panel.
  • FIG. 1 is a schematic structural diagram of a first metal layer of a display panel in the prior art.
  • FIG. 2 is a schematic diagram of the first structure of the first metal layer of the display panel provided by the embodiment of the present application.
  • FIG. 3 is a first structural schematic diagram of a non-display area of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a second structural schematic diagram of the first metal layer of the display panel provided by the embodiment of the present application.
  • FIG. 5 is a second structural schematic diagram of the non-display area of the display panel provided by the embodiment of the present application.
  • FIG. 6 is a third schematic structural diagram of the first metal layer of the display panel provided by the embodiment of the present application.
  • FIG. 7 is a third structural schematic diagram of the non-display area of the display panel provided by the embodiment of the present application.
  • FIG. 8 is a fourth structural schematic diagram of the first metal layer of the display panel provided by the embodiment of the present application.
  • a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more.
  • the term “comprise” and any variations thereof, are intended to cover a non-exclusive inclusion.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application in specific situations.
  • FIG. 2 it is a schematic structural diagram of a display panel provided by an embodiment of the present invention.
  • the display panel provided by the embodiment of the present invention includes a display area (not shown in the figure) and at least one non-display area 10 . If the display panel adopts a single driving mode, the display panel includes a non-display area 10, and the non-display area 10 is located on one side of the display area; if the display panel adopts a dual-drive mode, the display panel includes two non-display areas 10, And the two non-display areas 10 are located on opposite sides of the display area.
  • the non-display area 10 includes the GOA unit area 11, the wiring area 12 and the first wiring area 13, and the GOA unit area 11, the wiring area 12 and the first wiring area 13 are along the first direction A Arranged in order.
  • the GOA unit area 11 is arranged close to the display area, that is, the GOA unit area 11 is located between the display area and the winding area 12 .
  • the display panel includes GOA units (not shown in the figure), and the GOA units are located in the GOA unit area 11 .
  • the display panel further includes DBS (Data BM Less) common electrode wiring 1 , and the DBS common electrode wiring 1 is located in the wiring area 12 and extends along the second direction B.
  • the display panel further includes a plurality of clock signal traces 2 arranged sequentially along the first direction A in the first trace area 13 , and each clock signal trace 2 extends along the second direction B.
  • the DBS common electrode wiring 1 and the multiple clock signal wirings 2 can be located on the same layer, that is, the DBS common electrode wiring 1 and the multiple clock signal wirings 2 can be located in the first metal layer of the display panel.
  • the display panel also includes a plurality of clock signal transfer wires 3, the number of the plurality of clock signal transfer wires 3 is the same as that of the plurality of clock signal traces 2, and there is a one-to-one correspondence, and each clock signal transfer wire 3 corresponds to its corresponding clock signal trace 2 electrical connection.
  • the multiple clock signal transfer lines 3 and the multiple clock signal traces 2 are located on different layers, and the multiple clock signal transfer lines 3 may be located in the second metal layer of the display panel.
  • An insulating layer can be arranged between the first metal layer and the second metal layer, and a via hole is provided in the insulating layer, and a conductive material is filled in the via hole, and each clock signal transfer line 3 corresponds to the conductive material in the via hole.
  • the clock signal trace 2 is electrically connected.
  • each clock signal transition line 3 After each clock signal transition line 3 is electrically connected to its corresponding clock signal routing line 2, it extends along the first direction A through the winding area 12, and continues to extend along the first direction A to the GOA unit area 11, so as to be compatible with the GOA
  • the GOA units in the unit area 11 are electrically connected, so that each clock signal line 2 is electrically connected to the GOA unit through its corresponding clock signal transition line 3 .
  • the multiple clock signal routing lines 2 are arranged along the first direction A, the distances between the multiple clock signal routing lines 2 and the GOA unit area 11 are different. If the multiple clock signal transfer lines 3 are arranged in a straight line, multiple The length of the clock signal transfer line 3 is different (the clock signal transfer line 3 connected to the clock signal line 2 close to the GOA unit area 11 is shorter, and the clock signal line 3 connected to the clock signal line 2 far from the GOA unit area 11 The transfer line 3 is longer), that is, the length of the clock signal line (including the clock signal line 2 and the clock signal transfer line 3 connected to it) that transmits the clock signal is quite different, which leads to the difference in the resistance between the clock signal lines. Poor horizontal lines are prone to occur.
  • the present application sets up a winding area 12, and at least one clock signal transfer line 3 is bent and arranged in the winding area 12 to adjust the length of each clock signal transfer line 3 and reduce the gap between the clock signal lines for transmitting clock signals.
  • the difference in resistance reduces the generation of bad horizontal lines.
  • the clock signal transfer line 3 connected to the clock signal trace 2 farthest from the GOA unit area 11 may not be bent in the winding area 12, that is, the clock signal transfer line 3 may be straight, as shown in Figure 2 shown.
  • the remaining clock signal transfer wires 3 can be bent and set in the winding area 12, and the closer the clock signal routing 2 is to the GOA unit area 11, the bending length of the connected clock signal transfer wire 3 in the winding area 12 bigger.
  • the bending setting means that the clock signal transfer wires 3 are bent back and forth along the second direction B in the winding area 12 , as long as the clock signal transfer wires 3 do not intersect each other.
  • an additional winding area 12 is added in the non-display area 10, while the design of other wiring remains unchanged, such as DBS common electrode wiring 1, a plurality of clock signal wiring 2 and the winding area are arranged side by side in the non-display area 10 In this case, the width of the non-display area 10 becomes larger, as shown in FIG. 1 , which in turn causes the width of the frame area of the display panel to become larger.
  • the DBS common electrode wiring 1 is arranged in the winding area 12, and the clock signal transfer wiring 3 and the DBS common electrode wiring 1 are located on different layers (the clock signal transfer wiring 3 and the DBS common electrode wiring 1 will not be affected. signal transmission), thereby reducing the width of the first routing area 13, further reducing the width of the non-display area 10, and reducing the frame width of the display panel.
  • each clock signal transition line 3 extends through the winding area 12 along the first direction A, and the DBS common electrode wiring 1 is located in the winding area 12 and extends along the second direction B, so that each clock signal transition line 3 and The DBS common electrode wiring 1 overlaps in the winding area 12, and the overlap refers to the orthographic projection of each clock signal transfer line 3 on the winding area 12 and the DBS common electrode wiring 1 on the winding area 12.
  • the overlapping of the orthographic projection does not mean that the clock signal transfer line 3 covers the DBS common electrode line 1 .
  • each clock signal transfer line 3 and the DBS common electrode wiring 1 in the winding area 12 is the same, that is, the orthographic projection of each clock signal transfer line 3 on the winding area 12 is in the same area as the DBS common electrode wiring 1.
  • the overlapping areas of the orthographic projections on the winding area 12 are the same.
  • the overlapping part of the clock signal transfer line 3 and the DBS common electrode line 1 can form a capacitor, and by adjusting the overlapping area of the clock signal transfer line 3 and the DBS common electrode line 1, the capacitance can be adjusted to improve the connection between the clock signal lines. Capacitance differences further reduce the occurrence of poor horizontal lines.
  • the orthographic projection of the DBS common electrode wiring 1 on the winding area 12 can partially cover the winding area 12, and the bending lengths of different clock signal transfer lines 3 in the winding area 12 can be different, but each clock signal transfer line 3 and The overlapping area of the DBS common electrode wiring 1 in the wiring area 12 may be the same, as shown in FIG. 3 .
  • the orthographic projection of the DBS common electrode wiring 1 on the winding area 12 can completely cover the winding area 12 , and the DBS common electrode wiring 1 is provided with a hollow area.
  • the clock signal transfer line 3 connected to the clock signal trace 2 farthest from the GOA unit area 11 may not overlap with the hollowed out area, and the rest of the clock signal transfer lines 3 are bent and set in the winding area 12, all of which can be connected with the hollowed out area. area overlap.
  • the clock signal transition line 3 with a larger bending length has a larger overlapping area with the hollow area, so as to adjust the connection between each clock signal transition line 3 and the DBS common electrode wiring 1.
  • Overlap area to reduce capacitance difference between clock signal lines.
  • the hollowed out area includes a plurality of hollowed out structures 41 arranged along the second direction B.
  • the clock signal transfer line 3 connected to the clock signal trace 2 farthest from the GOA unit area 11 may not correspond to the hollow structure 41, while the rest of the clock signal transfer lines 3 are bent and arranged in the winding area 12
  • Each clock signal transfer wire 3 can correspond to at least one hollow structure 41 .
  • the clock signal transfer line 3 with a larger bending length has more corresponding hollow structures 41, that is, the clock signal transfer line 3 with a larger bending length in the winding area 12
  • the bending length of the clock signal transfer line 3 in the winding area 12 is getting larger and larger, so from top to bottom, the distribution density of the hollow structure 41 is getting larger and larger, so that in In the winding area 12 , the clock signal transfer wire 3 with a larger bending length has a larger overlapping area with the hollow structure 41 , so as to reduce the capacitance difference between the clock signal wires.
  • the hollowed out region includes a plurality of hollowed out structures 42 arranged along the second direction B.
  • the clock signal transfer line 3 connected to the clock signal trace 2 farthest from the GOA unit area 11 may not correspond to the hollow structure 41, while the rest of the clock signal transfer lines 3 are bent and arranged in the winding area 12
  • Each clock signal transfer wire 3 can correspond to a hollow structure 42 .
  • the clock signal transition wire 3 with a larger bending length in the winding area 12 has a larger area of the corresponding hollow structure 42 .
  • the bending length of the clock signal transfer line 3 in the winding area 12 is getting larger and larger, so from top to bottom, the area of the hollow structure 42 is getting larger and larger, so that in all In the winding area 12 , the clock signal transfer wire 3 with a larger bending length has a larger overlapping area with the hollow structure 42 , so as to reduce the capacitance difference between the clock signal wires.
  • the display panel further includes a CF common electrode wiring 5 and a CF common electrode feedback wiring 6 .
  • the CF common electrode wiring 5 is located in the first wiring area 13, and the CF common electrode wiring 5 is located on the side of the multiple clock signal wiring 2 away from the DBS common electrode wiring 1, and the CF common electrode wiring 5 is along the second direction B extension.
  • the CF common electrode feedback wiring 6 is located in the first wiring area 13, and the CF common electrode feedback wiring 6 is located on the side of the DBS common electrode wiring 1 away from the clock signal wiring 2, and the CF common electrode feedback wiring 6 is along the second Direction B extends.
  • the CF common electrode trace 5 and the CF common electrode feedback trace 6 can be arranged on the same layer as the multiple clock signal traces 2 , that is, the CF common electrode trace 5 and the CF common electrode feedback trace 6 can be located on the first metal layer.
  • the non-display area 10 further includes a second wiring area 14 located between the GOA unit area 11 and the wiring area 12 .
  • the display panel also includes a voltage wiring 71 and at least one voltage transfer line 72 .
  • the voltage wiring 71 is located in the second wiring area 14 , that is, the voltage wiring 71 is located between the GOA unit and the DBS common electrode wiring 1 , and the voltage wiring 71 extends along the second direction B.
  • the at least one voltage transfer line 72 is respectively connected to the voltage routing 71, and each voltage transfer line 72 extends along the first direction A to the GOA unit area 11 to be electrically connected to the GOA unit, so that The voltage wiring 71 is electrically connected to the GOA unit through at least one voltage transfer wire 72 .
  • the voltage trace 71 and the voltage transfer wire 72 are located on different layers, the voltage trace 71 can be located on the same layer as the multiple clock signal traces 2, that is, the voltage trace 71 can be located on the first metal layer, and the voltage transfer wire 72 It can be located on the same layer as the multiple clock signal transfer lines 3 , that is, the voltage transfer line 72 can be located on the second metal layer.
  • the insulating layer between the first metal layer and the second metal layer can be provided with a plurality of via holes, and the via holes are filled with conductive materials, and at least one voltage transfer line 72 can pass through the conductive materials in the via holes and the voltage wiring. 71 is electrically connected. The voltage wiring 71 and the voltage transfer wire 72 are used to transmit low voltage signals to the GOA unit.
  • the display panel further includes a normal-phase signal wiring 81 , at least one normal-phase signal transition line 82 , a reverse-phase signal wiring 91 and at least one reverse-phase signal transition line 92 .
  • Both the normal-phase signal wiring 81 and the negative-phase signal wiring 91 are located in the second wiring area 14 and extend along the second direction B. Referring to FIG.
  • the normal-phase signal wiring 81 is connected to the at least one normal-phase signal transition line 82, and each normal-phase signal transition line 82 extends along the first direction A to the GOA unit area 11 to communicate with the GOA unit Electrically connected so that the normal phase signal wiring 81 is electrically connected to the GOA unit through at least one normal phase signal transfer line 82 .
  • the normal-phase signal transfer line 82 and the normal-phase signal wiring 81 are located on different layers, and the normal-phase signal wiring 81 can be located on the same layer as the multiple clock signal wiring 2, that is, the normal-phase signal wiring 81 can be located on the first One metal layer, the normal-phase signal transition line 82 can be located on the same layer as the multiple clock signal transition lines 3 , that is, the normal-phase signal transition line 82 can be located on the second metal layer.
  • the insulating layer between the first metal layer and the second metal layer can be provided with a plurality of via holes, and the conductive material is filled in the via holes, and the positive phase signal transfer line 82 can pass through the conductive material in the via holes and the normal phase signal.
  • the wire 81 is electrically connected.
  • the normal phase signal wiring 81 and the normal phase signal transfer line 82 are used to transmit the normal phase signal to the GOA unit.
  • the inversion signal wiring 91 is connected to the at least one inversion signal transition line 92, and each inversion signal transition line 92 extends to the GOA unit area 11 along the first direction A to communicate with the GOA unit Electrical connection, so that the anti-phase signal wiring 91 is electrically connected to the GOA unit through at least one anti-phase signal transfer line 92 .
  • the anti-phase signal transfer line 92 is located on a different layer from the anti-phase signal line 91, and the anti-phase signal line 91 can be located on the same layer as a plurality of clock signal lines 2, that is, the anti-phase signal line 91 can be located on the first One metal layer, the reverse phase signal transition line 92 can be located on the same layer as the multiple clock signal transition lines 3 , that is, the reverse phase signal transition line 92 can be located on the second metal layer.
  • the insulating layer between the first metal layer and the second metal layer can be provided with a plurality of via holes, and the conductive material is filled in the via holes.
  • the wire 91 is electrically connected.
  • the anti-phase signal wiring 91 and the anti-phase signal transition line 92 are used to transmit the anti-phase signal to the GOA unit.
  • the display panel When the display panel is an 8K display panel, the display panel includes twelve clock signal routing lines 2, twelve clock signal transfer lines 3, twelve voltage transfer lines 72, six normal phase signal transfer lines 82 and six inverting signal lines Adapter line 92.
  • the twelve clock signal routing lines 2 are electrically connected to the twelve clock signal transfer lines 3 one by one, and the twelve clock signal transfer lines 3 are respectively electrically connected to the GOA unit; the twelve voltage transfer lines 72 are respectively connected to the The voltage traces 71 are electrically connected, and the twelve voltage transfer wires 72 are also electrically connected to the GOA unit; the six normal-phase signal transfer wires 82 are electrically connected to the normal-phase signal traces 81, and the six normal-phase signal transfer wires are electrically connected to the normal-phase signal transfer wires 81.
  • the wires 82 are also respectively electrically connected to the GOA units; the six reverse signal transfer wires 92 are respectively electrically connected to the reverse signal traces 91 , and the six reverse signal transfer wires 92 are also respectively connected to the
  • each of the clock signal traces 2, the CF common electrode traces 5, the CF common electrode feedback traces 6, the voltage traces 71, the normal-phase signal traces 81 and the reverse-phase signal traces 91 can be solid wires, such as Figure 2 to Figure 7.
  • Each of the clock signal traces 2, the CF common electrode traces 5, the CF common electrode feedback traces 6, the voltage traces 71, the positive-phase signal traces 81 and the reverse-phase signal traces 91 may include Multiple sub-lines are cross-connected, and the multiple sub-lines form a network structure, as shown in FIG. 8 .
  • the display panel also includes an array substrate (not shown in the figure), a color filter substrate (not shown in the figure) and a liquid crystal layer (not shown in the figure).
  • the clock signal trace 2 the CF common electrode trace 5, the CF common electrode feedback trace 6, the voltage trace 71, the normal-phase signal trace 81 and the reverse-phase signal trace 91 are arranged on the array substrate, and these traces are It is set as a mesh structure, which is helpful for ultraviolet light to pass through these traces to irradiate the frame glue, so as to realize the fixation of the frame glue.
  • the DBS common electrode traces are located in the winding area and extend along the second direction.
  • Multiple clock signal traces are arranged in the first trace area along the first direction, and each clock signal trace Extending along the second direction, multiple clock signal transfer lines are connected to multiple clock signal routing lines in one-to-one correspondence, each clock signal transfer line passes through the winding area and extends to the GOA unit area along the first direction, at least one clock signal The transfer line is bent and set in the winding area to reduce the resistance difference between the clock signal lines through the bending setting of the clock signal transfer line.
  • the DBS common electrode wiring is located in the winding area, avoiding the separate setting of the DBS common electrode The routing increases the routing space, thereby reducing the bezel width of the display panel.

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Abstract

一种显示面板，显示面板包括：DBS公共电极走线(1)，位于绕线区(12)；多条时钟信号走线(2)，沿第一方向(A)排列在第一走线区(13)；以及，多条时钟信号转接线(3)，与多条时钟信号走线(2)一一对应连接，每条时钟信号转接线(3)穿过绕线区(12)并沿第一方向(A)延伸至GOA单元区(11)，至少一条时钟信号转接线(3)在绕线区(12)中弯折设置。

Description

显示面板 技术领域
本申请涉及显示面板技术领域，尤其涉及一种显示面板。
 背景技术
液晶显示器的分辨率越高，所需  GOA（Gate Driver on Array）电路的时钟信号（CK）数量越多。同时8K产品的不同CK线间存在电容电阻差异，容易产生水平线不良。现有技术通过CK线绕线设计，减小电阻差异。但是CK线绕线会增加边框宽度，不利于液晶显示器窄边框的发展。
 技术问题
本申请实施例提供一种显示面板，能够在减小时钟信号线之间的电阻差异的同时，减小显示面板的边框宽度。
 技术解决方案
本申请实施例提供了一种显示面板，包括非显示区，所述非显示区包括沿第一方向排列的GOA单元区、绕线区和第一走线区；
所述显示面板包括：
DBS公共电极走线，位于所述绕线区，且沿第二方向延伸；
多条时钟信号走线，沿所述第一方向排列在所述第一走线区，且每条所述时钟信号走线沿所述第二方向延伸；以及，
多条时钟信号转接线，与所述多条时钟信号走线一一对应连接，每条所述时钟信号转接线穿过所述绕线区并沿所述第一方向延伸至所述GOA单元区，至少一条所述时钟信号转接线在所述绕线区中弯折设置；
其中，所述多条时钟信号转接线与所述DBS公共电极走线、所述多条时钟信号走线位于不同层。
可选地，每条所述时钟信号转接线与所述DBS公共电极走线在所述绕线区中的重叠面积相同。
可选地，距离所述GOA单元区越近的时钟信号走线，其连接的时钟信号转接线在所述绕线区的弯折长度越大。
可选地，所述DBS公共电极走线在所述绕线区上的正投影完全覆盖所述绕线区，所述DBS公共电极走线中设有镂空区；
距离所述GOA单元区越近的时钟信号走线，其连接的时钟信号转接线与所述镂空区的重叠面积越大。
可选地，所述镂空区包括沿所述第二方向排列的多个镂空结构，每条所述时钟信号转接线对应至少一个镂空结构；
距离所述GOA单元区越近的时钟信号走线，其连接的时钟信号转接线对应的镂空结构的个数越多。
可选地，所述镂空区包括沿所述第二方向排列的多个镂空结构，每条所述时钟信号转接线对应一个镂空结构；
距离所述GOA单元区越近的时钟信号走线，其连接的时钟信号转接线对应的镂空结构的面积越大。
可选地，所述显示面板还包括CF公共电极走线和CF公共电极反馈走线；
所述CF公共电极走线和所述CF公共电极反馈走线均位于所述第一走线区，且沿所述第二方向延伸。
可选地，所述非显示区还包括位于所述GOA单元区与所述绕线区之间的第二走线区；
所述显示面板还包括电压走线和电压转接线；
所述电压走线位于所述第二走线区，且沿所述第二方向延伸；所述电压转接线与所述电压走线连接，且沿所述第一方向延伸至所述GOA单元区，所述电压走线与所述电压转接线位于不同层。
可选地，所述显示面板还包括正相信号走线、正相信号转接线、反相信号走线和反相信号转接线；
所述正相信号走线和所述反相信号走线均位于所述第二走线区，且沿所述第二方向延伸；
所述正相信号转接线与所述正相信号走线连接，且沿所述第一方向延伸至所述GOA单元区，所述正相信号转接线与所述正相信号走线位于不同层；所述反相信号转接线与所述反相信号走线连接，且沿所述第一方向延伸至所述GOA单元区，所述反相信号走线与所述反相信号转接线位于不同层。
可选地，每条所述时钟信号走线包括交叉连接的多条子线，所述多条子线构成网状结构。
可选地，所述CF公共电极走线和所述CF公共电极反馈走线均包括交叉连接的多条子线，所述多条子线构成网状结构。
可选地，所述电压走线包括交叉连接的多条子线，所述多条子线构成网状结构。
可选地，所述正相信号走线和所述反相信号走线均包括交叉连接的多条子线，所述多条子线构成网状结构。
可选地，所述DBS公共电极走线与所述多条时钟信号走线位于同一层。
可选地，所述CF公共电极走线、所述CF公共电极反馈走线与所述时钟信号走线同层设置。
可选地，所述电压走线与所述时钟信号走线位于同一层，所述电压转接线与所述时钟信号转接线位于同一层。
可选地，所述正相信号走线、所述反相信号走线与所述时钟信号走线位于同一层，所述正相信号转接线、所述反相信号转接线与所述时钟信号转接线位于同一层。
 有益效果
本申请的有益效果为：DBS公共电极走线位于绕线区，且沿第二方向延伸，多条时钟信号走线沿第一方向排列在第一走线区，且每条时钟信号走线沿第二方向延伸，多条时钟信号转接线与多条时钟信号走线一一对应连接，每条时钟信号转接线穿过绕线区并沿第一方向延伸至GOA单元区，至少一条时钟信号转接线在绕线区中弯折设置，以通过时钟信号转接线的弯折设置，减小时钟信号线之间的电阻差异，同时DBS公共电极走线位于绕线区，避免单独设置DBS公共电极走线增加走线空间，从而减小显示面板的边框宽度。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有技术中的显示面板的第一金属层的结构示意图。
图2为本申请实施例提供的显示面板的第一金属层的第一个结构示意图。
图3为本申请实施例提供的显示面板的非显示区的第一个结构示意图。
图4为本申请实施例提供的显示面板的第一金属层的第二个结构示意图。
图5为本申请实施例提供的显示面板的非显示区的第二个结构示意图。
图6为本申请实施例提供的显示面板的第一金属层的第三个结构示意图。
图7为本申请实施例提供的显示面板的非显示区的第三个结构示意图。
图8为本申请实施例提供的显示面板的第一金属层的第四个结构示意图。
 本发明的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和实施例对本申请作进一步说明。
参见图2，是本发明实施例提供的显示面板的结构示意图。
本发明实施例提供的显示面板包括显示区（图中未示出）和至少一个非显示区10。若显示面板采用单驱动模式，则显示面板包括一个非显示区10，且该非显示区10位于显示区的一侧；若显示面板采用双驱动模式，则显示面板包括两个非显示区10，且两个非显示区10位于显示区的相对两侧。
如图2所示，非显示区10包括GOA单元区11、绕线区12和第一走线区13，且GOA单元区11、绕线区12和第一走线区13沿第一方向A依次排列。其中，GOA单元区11靠近显示区设置，即GOA单元区11位于显示区与绕线区12之间。
显示面板包括GOA单元（图中未示出），GOA单元位于GOA单元区11。显示面板还包括DBS（Data BM Less）公共电极走线1， DBS公共电极走线1位于绕线区12中，且沿第二方向B延伸。显示面板还包括多条时钟信号走线2，多条时钟信号走线2沿第一方向A依次排列在第一走线区13中，且每条时钟信号走线2沿第二方向B延伸。DBS公共电极走线1和多条时钟信号走线2可以位于同一层，即DBS公共电极走线1和多条时钟信号走线2可以位于显示面板的第一金属层中。
显示面板还包括多条时钟信号转接线3，多条时钟信号转接线3与多条时钟信号走线2的数量相同，且一一对应，每条时钟信号转接线3与其对应的时钟信号走线2电性连接。多条时钟信号转接线3与多条时钟信号走线2位于不同层，多条时钟信号转接线3可以位于显示面板的第二金属层中。第一金属层和第二金属层之间可以设置绝缘层，绝缘层中设有导通孔，导通孔中填充导电材料，每条时钟信号转接线3通过导通孔中的导电材料与其对应的时钟信号走线2电性连接。
每条时钟信号转接线3与其对应的时钟信号走线2电性连接后，沿第一方向A延伸穿过绕线区12，并继续沿第一方向A延伸至GOA单元区11，以与GOA单元区11中的GOA单元电性连接，使得每条时钟信号走线2通过其对应的时钟信号转接线3与GOA单元电性连接。
由于多条时钟信号走线2沿第一方向A排列，导致多条时钟信号走线2与GOA单元区11的距离不同，若多条时钟信号转接线3均呈直线型设置，会导致多条时钟信号转接线3的长度不同（距离GOA单元区11近的时钟信号走线2所连接的时钟信号转接线3较短，而距离GOA单元区11远的时钟信号走线2所连接的时钟信号转接线3较长），即传输时钟信号的时钟信号线（包括时钟信号走线2及其连接的时钟信号转接线3）的长度差别较大，进而导致时钟信号线之间的电阻具有差异，容易产生水平线不良。
因此，本申请设置绕线区12，至少一条时钟信号转接线3在绕线区12中弯折设置，以调整每条时钟信号转接线3的长度，减小传输时钟信号的时钟信号线之间的电阻差异，减小水平线不良的产生。
具体地，距离GOA单元区11最远的时钟信号走线2所连接的时钟信号转接线3可以在绕线区12中不弯折，即该时钟信号转接线3可以呈直线型，如图2所示。其余时钟信号转接线3都可以在绕线区12中弯折设置，且距离GOA单元区11越近的时钟信号走线2，其连接的时钟信号转接线3在绕线区12的弯折长度越大。其中，弯折设置是指时钟信号转接线3在绕线区12中沿第二方向B来回弯折，只要保证时钟信号转接线3之间不相交即可。
若在非显示区10中额外增加绕线区12，而其他走线的设计方式不变，如DBS公共电极走线1、多条时钟信号走线2和绕线区并排设置在非显示区10中，会导致非显示区10的宽度变大，如图1所示，进而导致显示面板的边框区的宽度变大。本申请将DBS公共电极走线1设置在绕线区12，且时钟信号转接线3与DBS公共电极走线1位于不同层（不会对时钟信号转接线3和DBS公共电极走线1中的信号传输产生影响），从而减小第一走线区13的宽度，进而减小非显示区10的宽度，减小显示面板的边框宽度。
由于每条时钟信号转接线3沿第一方向A延伸穿过绕线区12，而DBS公共电极走线1位于绕线区12且沿第二方向B延伸，使得每条时钟信号转接线3与DBS公共电极走线1在绕线区12中重叠，该重叠是指每条时钟信号转接线3在绕线区12上的正投影与所述DBS公共电极走线1在绕线区12上的正投影重叠，并非是指时钟信号转接线3覆盖在DBS公共电极走线1上。每条时钟信号转接线3与DBS公共电极走线1在绕线区12中的重叠面积相同，即每条时钟信号转接线3在绕线区12上的正投影与DBS公共电极走线1在绕线区12上的正投影的重叠面积相同。时钟信号转接线3与DBS公共电极走线1的重叠部分可以形成电容，通过调整时钟信号转接线3与DBS公共电极走线1的重叠面积，可以调整电容大小，以改善时钟信号线之间的电容差异，进一步减小水平线不良的产生。
DBS公共电极走线1在绕线区12上的正投影可以部分覆盖绕线区12，不同时钟信号转接线3在绕线区12的弯折长度可以不同，但每条时钟信号转接线3与DBS公共电极走线1在绕线区12中的重叠面积可以相同，如图3所示。
DBS公共电极走线1在绕线区12上的正投影可以完全覆盖绕线区12，DBS公共电极走线1中设有镂空区。距离所述GOA单元区11越近的时钟信号走线2，其连接的时钟信号转接线3与所述镂空区的重叠面积越大。或者，距离GOA单元区11最远的时钟信号走线2所连接的时钟信号转接线3可以与镂空区不重叠，其余时钟信号转接线3在绕线区12中弯折设置，都可以与镂空区重叠。而且，在所述绕线区12中弯折长度越大的时钟信号转接线3，与所述镂空区的重叠面积越大，以调整每条时钟信号转接线3与DBS公共电极走线1的重叠面积，减小时钟信号线之间的电容差异。
在一个实施方式中，如图4所示，所述镂空区包括沿所述第二方向B排列的多个镂空结构41。距离所述GOA单元区11越近的时钟信号走线2，其连接的时钟信号转接线3对应的镂空结构41的个数越多，每个镂空结构41的形状和大小可以相同。或者，距离GOA单元区11最远的时钟信号走线2所连接的时钟信号转接线3可以不对应镂空结构41，而其余时钟信号转接线3，即在所述绕线区12中弯折设置的每条时钟信号转接线3都可以对应至少一个镂空结构41。在所述绕线区12中弯折长度越大的时钟信号转接线3，其对应的镂空结构41的个数越多，即在所述绕线区12中弯折长度越大的时钟信号转接线3，与其重叠的镂空结构41的个数越多。如图5所示，从上到下，时钟信号转接线3在绕线区12中的弯折长度越来越大，因此从上到下，镂空结构41的分布密度越来越大，使得在所述绕线区12中弯折长度越大的时钟信号转接线3，与所述镂空结构41的重叠面积越大，以减小时钟信号线之间的电容差异。
在另一个实施方式中，如图6所示，所述镂空区包括沿所述第二方向B排列的多个镂空结构42。距离所述GOA单元区11越近的时钟信号走线2，其连接的时钟信号转接线3对应的镂空结构42的面积越大，每个镂空结构41的大小可以不同。或者，距离GOA单元区11最远的时钟信号走线2所连接的时钟信号转接线3可以不对应镂空结构41，而其余时钟信号转接线3，即在所述绕线区12中弯折设置的每条时钟信号转接线3都可以对应一个镂空结构42。在所述绕线区12中弯折长度越大的时钟信号转接线3，其对应的镂空结构42的面积越大。如图7所示，从上到下，时钟信号转接线3在绕线区12中的弯折长度越来越大，因此从上到下，镂空结构42的面积越来越大，使得在所述绕线区12中弯折长度越大的时钟信号转接线3，与所述镂空结构42的重叠面积越大，以减小时钟信号线之间的电容差异。
进一步地，如图2至7所示，所述显示面板还包括CF公共电极走线5和CF公共电极反馈走线6。CF公共电极走线5位于第一走线区13，且CF公共电极走线5位于多条时钟信号走线2远离DBS公共电极走线1的一侧，CF公共电极走线5沿第二方向B延伸。CF公共电极反馈走线6位于第一走线区13，且CF公共电极反馈走线6位于DBS公共电极走线1远离时钟信号走线2的一侧，CF公共电极反馈走线6沿第二方向B延伸。CF公共电极走线5和CF公共电极反馈走线6可以与多条时钟信号走线2同层设置，即CF公共电极走线5和CF公共电极反馈走线6可以位于第一金属层。
进一步地，如图2至7所示，所述非显示区10还包括位于所述GOA单元区11与所述绕线区12之间的第二走线区14。所述显示面板还包括电压走线71和至少一条电压转接线72。所述电压走线71位于所述第二走线区14，即电压走线71位于GOA单元与DBS公共电极走线1之间，且电压走线71沿所述第二方向B延伸。所述至少一条电压转接线72分别与所述电压走线71连接，且每条电压转接线72沿所述第一方向A延伸至所述GOA单元区11，以与GOA单元电性连接，使得电压走线71通过至少一条电压转接线72与GOA单元电性连接。所述电压走线71与所述电压转接线72位于不同层，电压走线71可以与多条时钟信号走线2位于同一层，即电压走线71可以位于第一金属层，电压转接线72可以与多条时钟信号转接线3位于同一层，即电压转接线72可以位于第二金属层。第一金属层和第二金属层之间的绝缘层可以设有多个导通孔，导通孔中填充导电材料，至少一条电压转接线72可以通过导通孔中的导电材料与电压走线71电性连接。电压走线71和电压转接线72用于向GOA单元传输低电压信号。
进一步地，如图2至7所示，所述显示面板还包括正相信号走线81、至少一条正相信号转接线82、反相信号走线91和至少一条反相信号转接线92。所述正相信号走线81和所述反相信号走线91均位于所述第二走线区14，且沿第二方向B延伸。所述正相信号走线81与所述至少一条正相信号转接线82连接，且每条正相信号转接线82沿所述第一方向A延伸至所述GOA单元区11，以与GOA单元电性连接，使得正相信号走线81通过至少一条正相信号转接线82与GOA单元电性连接。所述正相信号转接线82与所述正相信号走线81位于不同层，正相信号走线81可以与多条时钟信号走线2位于同一层，即正相信号走线81可以位于第一金属层，正相信号转接线82可以与多条时钟信号转接线3位于同一层，即正相信号转接线82可以位于第二金属层。第一金属层和第二金属层之间的绝缘层可以设有多个导通孔，导通孔中填充导电材料，正相信号转接线82可以通过导通孔中的导电材料与正相信号走线81电性连接。正相信号走线81和正相信号转接线82用于向GOA单元传输正相信号。
所述反相信号走线91与所述至少一条反相信号转接线92连接，且每条反相信号转接线92沿所述第一方向A延伸至所述GOA单元区11，以与GOA单元电性连接，使得反相信号走线91通过至少一条反相信号转接线92与GOA单元电性连接。所述反相信号转接线92与所述反相信号走线91位于不同层，反相信号走线91可以与多条时钟信号走线2位于同一层，即反相信号走线91可以位于第一金属层，反相信号转接线92可以与多条时钟信号转接线3位于同一层，即反相信号转接线92可以位于第二金属层。第一金属层和第二金属层之间的绝缘层可以设有多个导通孔，导通孔中填充导电材料，反相信号转接线92可以通过导通孔中的导电材料与反相信号走线91电性连接。反相信号走线91和反相信号转接线92用于向GOA单元传输反相信号。
在显示面板为8K显示面板时，显示面板包括十二条时钟信号走线2、十二条时钟信号转接线3、十二条电压转接线72、六条正相信号转接线82和六条反相信号转接线92。十二条时钟信号走线2与十二条时钟信号转接线3一一对应电性连接，且十二条时钟信号转接线3分别与GOA单元电性连接；十二条电压转接线72分别与电压走线71电性连接，且十二条电压转接线72还分别与GOA单元电性连接；六条正相信号转接线82分别与正相信号走线81电性连接，且六条正相信号转接线82还分别与GOA单元电性连接；六条反相信号转接线92分别与反相信号走线91电性连接，且六条反相信号转接线92还分别与GOA单元连接。
进一步地，每条时钟信号走线2、CF公共电极走线5、CF公共电极反馈走线6、电压走线71、正相信号走线81和反相信号走线91可以为实心线，如图2至图7所示。每条时钟信号走线2、CF公共电极走线5、CF公共电极反馈走线6、电压走线71、正相信号走线81和反相信号走线91中的每条走线均可以包括交叉连接的多条子线，且多条子线构成网状结构，如图8所示。显示面板还包括阵列基板（图中未示出）、彩膜基板（图中未示出）和液晶层（图中未示出）。在封装液晶层时，需要在液晶层周侧设置框胶，通过框胶固定阵列基板和彩膜基板，以将液晶层封装在阵列基板和彩膜基板之间。而时钟信号走线2、CF公共电极走线5、CF公共电极反馈走线6、电压走线71、正相信号走线81和反相信号走线91设于阵列基板上，将这些走线设置为网状结构，有助于紫外光穿过这些走线照射框胶，实现框胶的固定。
综上，本申请实施例中DBS公共电极走线位于绕线区，且沿第二方向延伸，多条时钟信号走线沿第一方向排列在第一走线区，且每条时钟信号走线沿第二方向延伸，多条时钟信号转接线与多条时钟信号走线一一对应连接，每条时钟信号转接线穿过绕线区并沿第一方向延伸至GOA单元区，至少一条时钟信号转接线在绕线区中弯折设置，以通过时钟信号转接线的弯折设置，减小时钟信号线之间的电阻差异，同时DBS公共电极走线位于绕线区，避免单独设置DBS公共电极走线增加走线空间，从而减小显示面板的边框宽度。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种显示面板，其中，包括非显示区，所述非显示区包括沿第一方向排列的GOA单元区、绕线区和第一走线区；
    所述显示面板包括：
    DBS公共电极走线，位于所述绕线区，且沿第二方向延伸；
    多条时钟信号走线，沿所述第一方向排列在所述第一走线区，且每条所述时钟信号走线沿所述第二方向延伸；以及，
    多条时钟信号转接线，与所述多条时钟信号走线一一对应连接，每条所述时钟信号转接线穿过所述绕线区并沿所述第一方向延伸至所述GOA单元区，至少一条所述时钟信号转接线在所述绕线区中弯折设置；
    其中，所述多条时钟信号转接线与所述DBS公共电极走线、所述多条时钟信号走线位于不同层。
  2. 如权利要求1所述的显示面板，其中，每条所述时钟信号转接线与所述DBS公共电极走线在所述绕线区中的重叠面积相同。
  3. 如权利要求1所述的显示面板，其中，距离所述GOA单元区越近的时钟信号走线，其连接的时钟信号转接线在所述绕线区的弯折长度越大。
  4. 如权利要求1所述的显示面板，其中，所述DBS公共电极走线在所述绕线区上的正投影完全覆盖所述绕线区，所述DBS公共电极走线中设有镂空区；
    距离所述GOA单元区越近的时钟信号走线，其连接的时钟信号转接线与所述镂空区的重叠面积越大。
  5. 如权利要求4所述的显示面板，其中，所述镂空区包括沿所述第二方向排列的多个镂空结构，每条所述时钟信号转接线对应至少一个镂空结构；
    距离所述GOA单元区越近的时钟信号走线，其连接的时钟信号转接线对应的镂空结构的个数越多。
  6. 如权利要求4所述的显示面板，其中，所述镂空区包括沿所述第二方向排列的多个镂空结构，每条所述时钟信号转接线对应一个镂空结构；
    距离所述GOA单元区越近的时钟信号走线，其连接的时钟信号转接线对应的镂空结构的面积越大。
  7. 如权利要求1所述的显示面板，其中，所述显示面板还包括CF公共电极走线和CF公共电极反馈走线；
    所述CF公共电极走线和所述CF公共电极反馈走线均位于所述第一走线区，且沿所述第二方向延伸。
  8. 如权利要求1所述的显示面板，其中，所述非显示区还包括位于所述GOA单元区与所述绕线区之间的第二走线区；
    所述显示面板还包括电压走线和电压转接线；
    所述电压走线位于所述第二走线区，且沿所述第二方向延伸；所述电压转接线与所述电压走线连接，且沿所述第一方向延伸至所述GOA单元区，所述电压走线与所述电压转接线位于不同层。
  9. 如权利要求8所述的显示面板，其中，所述显示面板还包括正相信号走线、正相信号转接线、反相信号走线和反相信号转接线；
    所述正相信号走线和所述反相信号走线均位于所述第二走线区，且沿所述第二方向延伸；
    所述正相信号转接线与所述正相信号走线连接，且沿所述第一方向延伸至所述GOA单元区，所述正相信号转接线与所述正相信号走线位于不同层；所述反相信号转接线与所述反相信号走线连接，且沿所述第一方向延伸至所述GOA单元区，所述反相信号走线与所述反相信号转接线位于不同层。
  10. 如权利要求1所述的显示面板，其中，所述时钟信号走线包括交叉连接的多条子线，所述多条子线构成网状结构。
  11. 如权利要求7所述的显示面板，其中，所述CF公共电极走线和所述CF公共电极反馈走线均包括交叉连接的多条子线，所述多条子线构成网状结构。
  12. 如权利要求8所述的显示面板，其中，所述电压走线包括交叉连接的多条子线，所述多条子线构成网状结构。
  13. 如权利要求9所述的显示面板，其中，所述正相信号走线和所述反相信号走线均包括交叉连接的多条子线，所述多条子线构成网状结构。
  14. 如权利要求1所述的显示面板，其中，所述DBS公共电极走线与所述多条时钟信号走线位于同一层。
  15. 如权利要求7所述的显示面板，其中，所述CF公共电极走线、所述CF公共电极反馈走线与所述时钟信号走线同层设置。
  16. 如权利要求8所述的显示面板，其中，所述电压走线与所述时钟信号走线位于同一层，所述电压转接线与所述时钟信号转接线位于同一层。
  17. 如权利要求9所述的显示面板，其中，所述正相信号走线、所述反相信号走线与所述时钟信号走线位于同一层，所述正相信号转接线、所述反相信号转接线与所述时钟信号转接线位于同一层。
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