WO2022252263A1 - 像素结构及其设计方法、显示面板 - Google Patents

像素结构及其设计方法、显示面板 Download PDF

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Publication number
WO2022252263A1
WO2022252263A1 PCT/CN2021/099045 CN2021099045W WO2022252263A1 WO 2022252263 A1 WO2022252263 A1 WO 2022252263A1 CN 2021099045 W CN2021099045 W CN 2021099045W WO 2022252263 A1 WO2022252263 A1 WO 2022252263A1
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Prior art keywords
thin film
film transistor
channel
voltage dividing
sub
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PCT/CN2021/099045
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English (en)
French (fr)
Inventor
吴伟
郑泽科
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Tcl华星光电技术有限公司
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Publication of WO2022252263A1 publication Critical patent/WO2022252263A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present application relates to the field of display technology, in particular to a pixel structure, a design method thereof, and a display panel.
  • the pixel structure of Multi-domain Vertical Alignment (MVA) products is usually divided into two pixel areas, namely the main pixel (Main pixel) area and the sub-pixel area. (Sub pixel) area.
  • the two pixel areas are driven by three thin film transistors (Thin Film Transistor, TFT), namely Main TFT, Sub TFT and Share TFT.
  • TFT Thin Film Transistor
  • Main TFT Main TFT
  • Sub TFT and Share TFT are connected in series to divide the voltage, so that when the input voltage of the data line is the same, the driving voltage of the sub pixel area is different from that of the main pixel area, so as to achieve the effect of increasing the viewing angle.
  • the channel width-to-length ratios of the Share TFT and Sub TFT in the pixel structure will change. Then, the divided voltage of the Share TFT and Sub TFT changes, which will cause the driving voltage of the sub-pixel area to change, thereby changing the brightness of the sub-pixel area, and causing uneven brightness of the entire display panel.
  • the present application provides a pixel structure, a design method, and a display panel, so as to alleviate the technical problem of uneven brightness in the existing display panel.
  • An embodiment of the present application provides a pixel structure, which includes a plurality of sub-pixel units, each of which includes a first pixel electrode and a second pixel electrode and a plurality of thin film transistors, and the plurality of thin film transistors include:
  • a first driving thin film transistor connected to the first pixel electrode
  • the channel width a and channel length b of the second driving thin film transistor and the channel width c and channel length d of the voltage dividing thin film transistor satisfy the relational expression:
  • n represents the number of channels of the voltage-dividing thin film transistor
  • e and f respectively represent the variation parameters of the channel widths of the second driving thin film transistor and the voltage-dividing thin film transistor, when the channel width changes
  • the value of the variation parameter is 1, and when the channel width does not change, the value of the variation parameter is 0.
  • each of the thin film transistors includes a source, a drain, and a semiconductor layer, the source and the drain are arranged on the semiconductor layer at intervals, and the source The region between the drain and the drain forms the channel of the thin film transistor, wherein the source and the drain are formed under the same photomask as the semiconductor layer, and the channel width of the thin film transistor is change.
  • the channel of the second driving thin film transistor and the channel of the voltage dividing thin film transistor are both U-shaped or I-shaped, and the channel of the voltage dividing thin film transistor The quantity is 1.
  • the channel of the second driving thin film transistor is U-shaped or I-shaped
  • the channel of the voltage dividing thin film transistor includes a first sub-channel and a second sub-channel
  • the first sub-channel is arranged in an I-type
  • the second sub-channel is arranged in an I-type
  • the second sub-channel is arranged in parallel with the first sub-channel at intervals, and the sub-channels
  • the number of channels of the piezoelectric thin film transistor is two.
  • each of the thin film transistors includes a source, a drain, and a semiconductor layer, the source and the drain are arranged on the semiconductor layer at intervals, and the source A region between the drain and the drain forms a channel of the thin film transistor, wherein the source and the drain are formed under different photomasks from the semiconductor layer.
  • the channel of the second driving thin film transistor is arranged in a U shape, and the channel of the voltage dividing thin film transistor is arranged in an I shape, then the channel of the second driving thin film transistor When the channel width changes, the channel width of the voltage-dividing thin film transistor does not change, and the number of channels of the voltage-dividing thin film transistor is one.
  • the channel of the second driving thin film transistor is arranged in a U shape, and the channel of the voltage dividing thin film transistor includes first sub-channels and second sub-channels arranged in parallel and spaced apart.
  • the first sub-channel and the second sub-channel are set in I-type, then the channel width of the second driving thin film transistor changes, and the channel width of the voltage dividing thin film transistor has no change, and the number of channels of the voltage dividing thin film transistor is 2.
  • the channel of the second driving thin film transistor is arranged in an I-type
  • the channel of the voltage dividing thin film transistor includes a first sub-channel and a second sub-channel arranged in parallel and spaced apart.
  • Channel, the first sub-channel and the second sub-channel are both set in I-type, then the channel widths of the second driving thin film transistor and the voltage dividing thin film transistor have no change, and the The number of channels of the voltage dividing thin film transistor is two.
  • the channel width a and channel length b of the second driving thin film transistor and the channel width c and channel length d of the voltage dividing thin film transistor also satisfy the relationship Mode:
  • An embodiment of the present application also provides a display panel, which includes a first substrate and a second substrate oppositely arranged, and a plurality of liquid crystal molecules arranged between the first substrate and the second substrate, wherein the first The substrate includes the pixel structure of one of the aforementioned embodiments.
  • the embodiment of the present application also provides a pixel structure design method, the pixel structure includes a plurality of sub-pixel units, each of the sub-pixel units includes a first pixel electrode and a second pixel electrode, the first pixel electrode and the A plurality of thin film transistors are arranged between the second pixel electrodes, and the plurality of thin film transistors include:
  • a first driving thin film transistor connected to the first pixel electrode
  • the pixel structure design method includes:
  • a and b represent the channel width and channel length of the second driving thin film transistor respectively
  • c and d represent the channel width and channel length of the voltage dividing thin film transistor respectively
  • n represents the channel width and channel length of the voltage dividing thin film transistor.
  • the number of channels of the transistor, e and f respectively represent the variation parameters of the channel width of the second driving thin film transistor and the voltage dividing thin film transistor, when the channel width changes, the variation parameter The value is 1, and when the channel width does not change, the value of the variation parameter is 0.
  • the preset channel width and preset channel length based on the second driving thin film transistor and the voltage dividing thin film transistor and the source of the thin film transistor , the amount of variation of the drain, and the step of determining the channel length and channel width of the second driving thin film transistor and the voltage dividing thin film transistor further includes:
  • the channel width a and channel length b of the second driving thin film transistor in the display panel and the channel width c and channel length d of the voltage dividing thin film transistor satisfy the relation:
  • the voltage division ratio of the second driving thin film transistor and the voltage division thin film transistor satisfying this relationship is basically the same as the preset voltage division ratio when designing the pixel structure, so that it will not be affected by the ultraviolet exposure, development, wet etching and other processes or processes in the array process.
  • FIG. 1 is a schematic top view of a pixel structure provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the detailed structure of the thin film transistor in FIG. 1 .
  • FIG. 3 is a schematic diagram of the film layer structure of the driving transistor provided by the embodiment of the present application.
  • FIG. 4 is a trend diagram of the variation of the voltage division ratio with the variation of the source and the drain provided by the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another top view of the pixel structure provided by the embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a pixel structure design method provided by an embodiment of the present application.
  • FIG. 1 is a schematic top view of the pixel structure provided by the embodiment of the present application.
  • FIG. 2 is a schematic diagram of the detailed structure of the thin-film transistor in FIG. 1 .
  • the pixel structure 100 includes a plurality of sub-pixel units 1 , and FIG. 1 schematically shows one sub-pixel unit 1 .
  • Each sub-pixel unit 1 includes a first pixel electrode 11 and a second pixel electrode 12 and a plurality of thin film transistors 20 .
  • the multiple thin film transistors 20 include a first driving thin film transistor 21 connected to the first pixel electrode 11; a second driving thin film transistor 22 connected to the second pixel electrode 12; 22 connected to the voltage dividing thin film transistor 23 .
  • the first pixel electrode 11 and the second pixel electrode 12 are arranged oppositely, and a plurality of thin film transistors 20 are arranged between the first pixel electrode 11 and the second pixel electrode 12.
  • Both the first pixel electrode 11 and the second pixel electrode 12 include a plurality of domains, such as two domains, four domains, etc., as shown in FIG. 1 , each pixel electrode is divided into four domains, Of course, the present application is not limited thereto.
  • the multiple thin film transistors 20 include a first driving thin film transistor 21 , a second driving thin film transistor 22 and a voltage dividing thin film transistor 23 .
  • the first driving thin film transistor 21 is electrically connected to the first pixel electrode 11 for providing a driving voltage to the first pixel electrode 11 .
  • the second driving thin film transistor 22 is connected to the second pixel electrode 12, and the second driving thin film transistor 22 is also connected in series with the voltage dividing thin film transistor 23, and the second driving thin film transistor 22 is used to give
  • the second pixel electrode 12 provides a driving voltage
  • the voltage dividing thin film transistor 23 is used to share the voltage of the second driving thin film transistor 22 so that the second driving thin film transistor 22 provides the voltage to the second pixel electrode 12.
  • the driving voltage is different from the driving voltage provided by the first driving thin film transistor 21 to the first pixel electrode 11, so as to achieve the effect of increasing the viewing angle.
  • the voltage dividing ratio of the voltage dividing thin film transistor 23 and the second driving thin film transistor 22 is related to the channel length and channel width of the voltage dividing thin film transistor 23 and the second driving thin film transistor 22 .
  • the ratio of the channel width-length ratio of the voltage dividing thin film transistor 23 to the channel width-length ratio of the second driving thin film transistor 22 is the ratio of the voltage dividing thin film transistor 23 and the second driving thin film transistor.
  • a voltage division ratio of 22, wherein the width-to-length ratio of the channel refers to the ratio of the channel width to the channel length.
  • the driving voltage for driving the second pixel electrode 12 will change, thereby changing the brightness. Therefore, when different areas of the display substrate are affected by processes or equipment such as ultraviolet exposure, development, and wet etching, the channel width-to-length ratios of the voltage-dividing thin film transistor 23 and the second driving thin-film transistor 22 are different, which will cause the voltage division to change, thereby Affects the display brightness, thereby causing uneven brightness of the entire display panel.
  • the present application defines the channel width of the second driving thin film transistor 22 as a and the channel length as b, and the channel width of the voltage dividing thin film transistor 23 as c and the channel length as d.
  • a distance between the channel width a and channel length b of the second driving thin film transistor 22 and the channel width c and channel length d of the voltage dividing thin film transistor 23 can be set.
  • n represents the number of channels of the voltage dividing thin film transistor 23, e and f respectively represent the variation parameters of the channel widths of the second driving thin film transistor 22 and the voltage dividing thin film transistor 23, when the channel When the width changes, the value of the variation parameter is 1, and when the channel width does not change, the value of the variation parameter is 0.
  • the second driving thin film The voltage division ratio of the transistor 22 and the voltage dividing thin film transistor 23 is basically the same as the preset voltage division ratio when designing the pixel structure 100, so as to alleviate the problem of uneven brightness in the existing display panel.
  • the channel width of the second driving thin film transistor 22 and the voltage dividing thin film transistor 23 changes refers to the channel width of the second driving thin film transistor 22 and the voltage dividing thin film transistor 23 actually prepared.
  • the preset channel width refers to the channel width that can be realized under the ideal process state, that is, when the pixel structure 100 is designed, the design-defined channel width.
  • the channel width of the thin film transistor changes depends on the preparation process of the thin film transistor and the channel type of the thin film transistor. For thin film transistors manufactured by non-4mask process, whether the channel width of the thin film transistor changes also depends on the channel type of the thin film transistor.
  • the thin film transistors 20 are prepared on the base substrate by adopting the 4mask process, which can save photomasks, simplify the process flow, and save costs.
  • the preparation process of the thin film transistor 20 includes sequentially preparing the gate, the semiconductor layer, the source and the drain on the base substrate, of course, an insulating layer is also provided between the gate and the semiconductor layer, such as gate insulating layer.
  • the second driving thin film transistor 22 includes a gate 41, a gate An insulating layer 411, a semiconductor layer 224, and a source 222 and a drain 223 disposed on the semiconductor layer 224 at intervals, and the region between the source 222 and the drain 223 forms the channel of the second thin film transistor 22
  • the channel 221, and the portion where the source electrode 222 and the drain electrode 223 are in contact with the semiconductor layer 224 is also provided with an ohmic contact layer 225 to ensure good electrical conductivity.
  • the semiconductor layer 224 is located below the source electrode 222 and the drain electrode 223, there is a space between the source electrode 222 and the drain electrode 223, and the part of the semiconductor layer 224 corresponding to the space is is the channel 221 of the second driving thin film transistor 22 .
  • the source electrode and the drain electrode of the thin film transistor 20 are patterned and formed under the same photomask as the semiconductor layer, and the photomask includes a half-tone mask (Half-Tone Mask, HTM) or Gray tone mask (Gray Tone Mask, GTM), etc.
  • HTM half-tone mask
  • GTM Gray tone mask
  • the source electrode and the drain electrode When using the same photomask to prepare the semiconductor layer, the source electrode and the drain electrode, different regions on the base substrate are affected by processes or equipment such as ultraviolet exposure, development, and wet etching, so that the prepared There is a difference between the line width of the source and the drain and the preset line width, for example, the actual line width of the source and the drain is larger than the preset line width, wherein the preset line width refers to The line width that can be realized in an ideal process state, that is, the line width that is defined when designing the pixel structure 100 .
  • the semiconductor layer, the source and the drain are formed under the same photomask, when the line width of the source and the drain increases, correspondingly, the source and the drain The distance between the drains will be reduced, which will cause the channel length and channel width of the thin film transistor 20 to change.
  • the channel width of the thin film transistor 20 is also Increase x, at this time the variation parameter value of the channel width of the thin film transistor 20 is 1;
  • the channel length of the thin film transistor 20 is reduced by x; when the number of channels of the thin film transistor 20 is two, the thin film transistor 20 The channel length of transistor 20 is reduced by 2x.
  • the channel length of the thin film transistor 20 is equal to the distance between the source and the drain, and the channel width of the thin film transistor 20 is actually filled between the source and the drain. The width of the semiconductor layer between them shall prevail.
  • the pixel structure 100 also includes a data line 30, a shared discharge bar 50 (Share bar) arranged parallel to the data line 30, and a gate line 40 vertically insulated and intersected with the data line 30, wherein the data
  • the line 30 and the shared discharge rod 50 are all set on the same layer as the source or the drain
  • the gate line 40 is set on the same layer as the gate of the thin film transistor 20, and the gate line 40 It is electrically connected to the gate of each thin film transistor 20 .
  • the "same layer setting" in this application means that in the preparation process, the film layer formed by the same material is patterned to obtain at least two different features, and the at least two different features are the same layer settings.
  • the data line 30 and the source electrode of the thin film transistor 20 in this embodiment are obtained by patterning the same conductive film layer, then the data line 30 and the source electrode of the thin film transistor 20 are arranged on the same layer .
  • the source 212 of the first driving thin film transistor 21 and the source 222 of the second driving thin film transistor 22 are integrally designed and electrically connected to the data line 30 , the first driving thin film transistor 21
  • the drain 213 is electrically connected to the first pixel electrode 11 through the first via hole 111
  • the drain 223 of the second driving thin film transistor 22 is electrically connected to the second pixel electrode 12 through the second via hole 121
  • the drain 223 of the second driving thin film transistor 22 is also electrically connected to the source 233 of the voltage dividing thin film transistor 23
  • the drain 234 of the voltage dividing thin film transistor 23 is electrically connected to the shared voltage dividing bar 50 .
  • Both the source and the drain of the TFT 20 are set in an I-type configuration, and correspondingly, the channels of the TFT 20 are also set in an I-type configuration.
  • the channel 211 of the first driving thin film transistor 21 and the channel 221 of the second driving thin film transistor 22 are both I-shaped and arranged in parallel.
  • the channel includes a first sub-channel 231 and a second sub-channel 232, the first sub-channel 231 and the second sub-channel 232 are both in an I-type configuration, the first sub-channel 231 and the second sub-channel 232
  • the second sub-channels 232 are arranged in parallel and at intervals.
  • the width of the first sub-channel 231 is equal to the width of the second sub-channel 232 , that is, the channel width c of the voltage dividing thin film transistor 23 .
  • the channel of the thin film transistor 20 is set in I-type, which means that the number of channels of the thin film transistor 20 is one, so the channel of the voltage-dividing thin film transistor 23 includes two I-type sub-channels, which means that the channel number of the thin film transistor 20 is one.
  • the number of channels of the voltage-dividing thin film transistor 23 is two, and the channel length d of the voltage-dividing thin film transistor 23 is equal to the channel length d1 of the first sub-channel 231 and the channel length d1 of the second sub-channel 232. sum of channel lengths d2.
  • the channel width a and channel length b of the second driving thin film transistor 22 and the channel width c and channel length d of the voltage dividing thin film transistor 23 satisfy the relational expression:
  • the voltage dividing ratio of the voltage dividing thin film transistor 23 and the second driving thin film transistor 22 satisfying the relational expression is basically unchanged compared with the preset voltage dividing ratio, and will not affect the brightness of the pixel area, and thus will not produce The phenomenon of uneven brightness.
  • the voltage dividing thin film transistor 23 and the second driving thin film transistor 22 are shown in Table 1, wherein the preset parameters include the preset channel width and the preset channel length of the voltage dividing thin film transistor 23, and the second The preset channel width and the preset channel length of the driving thin film transistor 22, the preset parameters in this application refer to the channel width c and the channel length d of the voltage dividing thin film transistor 23 actually obtained by the manufacturing process and The channel width a and channel length b of the second driving thin film transistor 22 satisfy the relational expression: When the preset parameter is used, the conventional preset parameter is the preset parameter when the channel width and length of the manufactured thin film transistor do not satisfy the relational expression.
  • the numerical unit of each preset parameter in Table 1 is micron.
  • the actual voltage division ratio refers to the voltage division ratio of the voltage division thin film transistor 23 and the second driving thin film transistor 22 actually manufactured based on preset parameters, and the actual voltage division ratio is equal to the voltage division thin film transistor The ratio of the aspect ratio of 23 to the aspect ratio of the second driving thin film transistor 22 .
  • the abscissa X represents the variation of the source and the drain x
  • the ordinate Y represents the value of the actual voltage division ratio
  • curve A represents the change trend of the actual voltage division ratio corresponding to the conventional preset parameters with the variation of the source and drain
  • curve B represents the corresponding value of the preset parameters of the present application
  • the variation trend of the actual voltage division ratio with the variation of source and drain Comparing curve A and curve B, it can be seen clearly and intuitively that the actual pressure division ratio corresponding to the preset parameters of the present application has little change compared with the set preset pressure division ratio, while the actual pressure division ratio corresponding to the conventional preset parameters The pressure ratio has a larger variation trend than the set preset pressure division ratio.
  • the channel width and channel length of the voltage-dividing thin film transistor 23 and the second driving thin-film transistor 22 prepared based on the preset parameters of the present application only need to satisfy the relational expression of this embodiment, and the obtained actual voltage division Compared with the preset voltage division ratio, the ratio basically remains unchanged, so that uneven brightness will not occur.
  • this embodiment is only an example for the preset parameters of the present application, and the preset parameters of the present application also satisfy the relational expression:
  • M represents the preset channel width of the voltage dividing thin film transistor 23
  • N represents the preset channel length of the voltage dividing thin film transistor 23
  • O represents the preset channel width of the second driving thin film transistor 22
  • P represents the second driving thin film transistor.
  • the preset channel length of the transistor 22 , n represents the channel number of the voltage dividing thin film transistor 23 .
  • FIG. 5 is another schematic top view of the pixel structure provided by the embodiment of the present application.
  • the first pixel electrode 11 in the pixel structure 101 is located in the area surrounded by the second pixel electrode 12, and a plurality of thin film transistors 20 are located between the first pixel electrode 11 and the the same side of the second pixel electrode 12 .
  • the source of the first driving thin film transistor 21 and the source of the second driving thin film transistor 22 are arranged in a U shape, and the drain of the first driving thin film transistor 21 is connected to the second driving thin film transistor.
  • the drains of the transistors 22 are respectively located in the corresponding U-shaped source openings, and the channels of the first driving thin film transistor 21 and the second driving thin film transistor 22 are also arranged in a U shape.
  • the source of the voltage-dividing thin film transistor 23 and the drain of the voltage-dividing thin film transistor 23 are both set in I-type, then the channel of the voltage-dividing thin film transistor 23 is also set in I-type, and the thin film
  • the channel of the transistor is set in I-shape or U-shape, it means that the number of channels of the thin film transistor is one, so optionally, in this embodiment, the channel of the voltage-dividing thin film transistor 23 can also be set in U-shape .
  • the channel width a and channel length b of the second driving thin film transistor 22 and the channel width c and channel length d of the voltage dividing thin film transistor 23 satisfy the relational expression:
  • the voltage dividing ratio of the voltage dividing thin film transistor 23 and the second driving thin film transistor 22 satisfying the relational expression is basically unchanged compared with the preset voltage dividing ratio, and will not affect the brightness of the pixel area, and thus will not produce The phenomenon of uneven brightness.
  • the channel width a and channel length b of the second driving thin film transistor 22 are different from the channel width c and channel length of the voltage dividing thin film transistor 23
  • the relationship between d satisfies: Where n represents the number of channels of the voltage dividing thin film transistor 23, e and f represent the variation parameters of the channel widths of the second driving thin film transistor 22 and the voltage dividing thin film transistor 23 respectively, and for the 4mask process prepared
  • the variation parameter of the channel width of the thin film transistor is 1, and the voltage dividing ratio of the voltage dividing thin film transistor 23 and the second driving thin film transistor 22 satisfying the relational expression is compared with the preset voltage dividing ratio It is closer, and will not affect the brightness of the pixel area, and thus will not produce uneven brightness.
  • the thin film transistor When using a non-4mask process to prepare the thin film transistor, the thin film transistor still includes a source, a drain, and a semiconductor layer, the source and the drain are spaced on the semiconductor layer, the source and The region between the drains forms the channel of the thin film transistor, but unlike the thin film transistor produced by the 4mask process, the source and the drain are formed in different photomasks from the semiconductor layer. Under the formation, that is, the source and the drain are formed under one photomask, and the semiconductor layer is formed under another photomask, so that the variation of the channel width of the thin film transistor is the same as that of the channel width during the 4mask process.
  • the variation of the channel width is different, but the variation of the channel length of the thin film transistor is the same as the variation of the channel length in the 4mask process. At this time, the variation of the channel width of the thin film transistor is related to the channel type of the thin film transistor.
  • the channel of the second driving thin film transistor is arranged in a U shape, and the channel of the voltage dividing thin film transistor is arranged in an I shape, then the channel width of the second driving thin film transistor change, the channel width of the voltage-dividing thin film transistor does not change, and the number of channels of the voltage-dividing thin film transistor is 1, at this time, the channel width a and channel length b of the second driving thin film transistor are related to the The relationship between the channel width c and the channel length d of the voltage dividing thin film transistor satisfies:
  • the voltage dividing ratio of the voltage dividing thin film transistor and the second driving thin film transistor satisfying the relational expression is basically unchanged compared with the preset voltage dividing ratio, and will not affect the brightness of the pixel area, and thus will not cause brightness fluctuations. average phenomenon.
  • the channel of the second driving thin film transistor is arranged in a U shape, and the channel of the voltage dividing thin film transistor includes a first sub-channel and a second sub-channel arranged in parallel and spaced apart, so If both the first sub-channel and the second sub-channel are set in I type, the channel width of the second driving thin film transistor changes, but the channel width of the voltage dividing thin film transistor does not change, and the The number of channels of the voltage dividing thin film transistor is 2, at this time, the distance between the channel width a and channel length b of the second driving thin film transistor and the channel width c and channel length d of the voltage dividing thin film transistor satisfy the relation:
  • the voltage dividing ratio of the voltage dividing thin film transistor and the second driving thin film transistor satisfying the relational expression is basically unchanged compared with the preset voltage dividing ratio, and will not affect the brightness of the pixel area, and thus will not cause brightness fluctuations. average phenomenon.
  • the channel of the second driving thin film transistor is set in I-type
  • the channel of the voltage dividing thin film transistor includes a first sub-channel and a second sub-channel arranged in parallel and spaced apart, so If both the first sub-channel and the second sub-channel are set in I type, the channel widths of the second driving thin film transistor and the voltage dividing thin film transistor do not change, and the voltage dividing thin film transistor
  • the number of channels is 2.
  • the channel width a and channel length b of the second driving thin film transistor and the channel width c and channel length d of the voltage dividing thin film transistor satisfy the relational expression:
  • the voltage dividing ratio of the voltage dividing thin film transistor and the second driving thin film transistor satisfying the relational expression is basically unchanged compared with the preset voltage dividing ratio, and will not affect the brightness of the pixel area, and thus will not cause brightness fluctuations. average phenomenon.
  • FIG. 6 is a schematic flowchart of a method for designing a pixel structure provided in an embodiment of the present application.
  • the pixel structure 100 includes a plurality of sub-pixel units 1, each of which includes a first pixel electrode 11 and a second pixel electrode 12, and between the first pixel electrode 11 and the second pixel electrode 12 A plurality of thin film transistors 20 are provided, and the plurality of thin film transistors 20 include a first driving thin film transistor 21 connected to the first pixel electrode 11; a second driving thin film transistor 22 connected to the second pixel electrode 12; A voltage dividing thin film transistor 23 connected to the second driving thin film transistor 22 .
  • the pixel structure design method is used to design the pixel structure of one of the above embodiments, the method includes:
  • S201 Obtain a preset channel width and a preset channel length of the second driving thin film transistor 22 and the voltage dividing thin film transistor 23;
  • S203 Based on the preset channel width and preset channel length of the second driving thin film transistor 22 and the voltage dividing thin film transistor 23 and the variation of the source and drain of the thin film transistor, determine the first The channel length and channel width of the second driving thin film transistor 22 and the voltage dividing thin film transistor 23, the channel length and channel width of the second driving thin film transistor 22 and the voltage dividing thin film transistor 23 satisfy the relational expression : Wherein, a and b represent the channel width and channel length of the second driving thin film transistor 22 respectively, c and d represent the channel width and channel length of the voltage dividing thin film transistor 23 respectively, and n represents the divided The number of channels of the pressure thin film transistor 23, e and f respectively represent the variation parameters of the channel widths of the second driving thin film transistor and the voltage dividing thin film transistor, when the channel width changes, the change The value of the amount parameter is 1, and when the channel width does not change, the value of the change amount parameter is 0.
  • the voltage dividing ratio of the voltage dividing thin film transistor and the second driving thin film transistor is basically unchanged compared with the preset voltage dividing ratio, which will not affect the brightness of the pixel area, and thus will not cause uneven brightness.
  • the voltage dividing ratio of the voltage dividing thin film transistor and the second driving thin film transistor is closer than the preset voltage dividing ratio.
  • An embodiment of the present application also provides a display panel, which includes a first substrate and a second substrate oppositely arranged, and a plurality of liquid crystal molecules arranged between the first substrate and the second substrate, wherein the first The substrate includes the pixel structure of one of the aforementioned embodiments.
  • the first substrate is an array substrate
  • the second substrate is a color filter substrate.
  • the present application provides a pixel structure and its design method, and a display panel.
  • the pixel structure includes a plurality of sub-pixel units, and each sub-pixel unit includes a first pixel electrode and a second pixel electrode.
  • a plurality of thin film transistors are provided, and the plurality of thin film transistors include a first driving thin film transistor connected to the first pixel electrode; a second driving thin film transistor connected to the second pixel electrode; a voltage dividing thin film transistor connected to the second driving thin film transistor ;
  • the channel width and channel length of the second driving thin film transistor and the channel width and channel length of the voltage dividing thin film transistor meet the preset relational expression, so that the voltage dividing of the second driving thin film transistor and the voltage dividing thin film transistor
  • the ratio is basically the same as the preset voltage division ratio when designing the pixel structure, so it will not be affected by factors such as ultraviolet exposure, development, wet etching and other processes or equipment in the array process, which solves the problem of Share TFT and Sub in the existing

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Abstract

一种像素结构（100）及其设计方法、显示面板；像素结构（100）包括多个薄膜晶体管（20），其中，第二驱动薄膜晶体管（22）的沟道宽度（a）、沟道长度（b）与分压薄膜晶体管（23）的沟道宽度（c）、沟道长度之间满足预设的关系式，使第二驱动薄膜晶体管（22）和分压薄膜晶体管（23）的分压比与设计像素结构（100）时的预设分压比基本相同，以缓解现有显示面板存在亮度不均的问题。

Description

像素结构及其设计方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素结构及其设计方法、显示面板。
背景技术
在液晶显示(Liquid Crystal Display，LCD)行业，多畴垂直配向型(Multi-domain Vertical Alignment，MVA)产品的像素结构通常分为两个像素区，分别为主像素(Main pixel)区和副像素(Sub pixel)区。两个像素区由3个薄膜晶体管(Thin Film Transistor，TFT)驱动，分别为Main TFT、Sub TFT和Share TFT。其中Sub TFT和Share TFT串联分压，使得在相同数据线(data line)输入电压时，副像素区的驱动电压与主像素区不同，从而达到增大视角的效果。
然而在阵列(array)工艺中，显示基板的不同区域由于受紫外曝光、显影、湿蚀刻等制程或设备的影响时，会导致像素结构中Share TFT和Sub TFT的沟道宽长比发生变化，进而使Share TFT和Sub TFT的分压发生变化，如此会导致副像素区的驱动电压发生变化，从而改变副像素区亮度，进而引起整个显示面板的亮度不均。
因此，现有显示面板存在亮度不均的技术问题需要解决。
技术问题
本申请提供一种像素结构以及设计方法、显示面板，以缓解现有显示面板存在亮度不均的技术问题。
技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种像素结构，其包括多个子像素单元，每一所述子像素单元包括第一像素电极和第二像素电极以及多个薄膜晶体管，多个所述薄膜晶体管包括：
与所述第一像素电极连接的第一驱动薄膜晶体管；
与所述第二像素电极连接的第二驱动薄膜晶体管；以及
与所述第二驱动薄膜晶体管连接的分压薄膜晶体管；
其中，所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000001
其中n表示所述分压薄膜晶体管的沟道数量，e、f分别表示所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道宽度的变化量参数，当所述沟道宽度发生变化时，所述变化量参数的值为1，当所述沟道宽度无变化时，所述变化量参数的值为0。
在本申请实施例提供的像素结构中，每一所述薄膜晶体管均包括源极、漏极以及半导体层，所述源极和所述漏极间隔设置于所述半导体层上，所述源极和所述漏极之间的区域形成所述薄膜晶体管的沟道，其中，所述源极和所述漏极与所述半导体层在同一光罩下形成，则所述薄膜晶体管的沟道宽度发生变化。
在本申请实施例提供的像素结构中，所述第二驱动薄膜晶体管的沟道和所述分压薄膜晶体管的沟道均呈U型设置或I型设置，所述分压薄膜晶体管的沟道数量为1。
在本申请实施例提供的像素结构中，所述第二驱动薄膜晶体管的沟道呈U型设置或I型设置，所述分压薄膜晶体管的沟道包括第一子沟道和第二子沟道，所述第一子沟道呈I型设置，所述第二子沟道呈I型设置，且所述第二子沟道与所述第一子沟道平行间隔设置，且所述分压薄膜晶体管的沟道数量为2。
在本申请实施例提供的像素结构中，每一所述薄膜晶体管均包括源极、漏极以及半导体层，所述源极和所述漏极间隔设置于所述半导体层上，所述源极和所述漏极之间的区域形成所述薄膜晶体管的沟道，其中，所述源极和所述漏 极与所述半导体层在不同的光罩下形成。
在本申请实施例提供的像素结构中，所述第二驱动薄膜晶体管的沟道呈U型设置，且所述分压薄膜晶体管的沟道呈I型设置，则所述第二驱动薄膜晶体管的沟道宽度发生变化，所述分压薄膜晶体管的沟道宽度无变化，且所述分压薄膜晶体管的沟道数量为1。
在本申请实施例提供的像素结构中，所述第二驱动薄膜晶体管的沟道呈U型设置，且所述分压薄膜晶体管的沟道包括平行间隔设置的第一子沟道和第二子沟道，所述第一子沟道和所述第二子沟道均呈I型设置，则所述第二驱动薄膜晶体管的沟道宽度发生变化，所述分压薄膜晶体管的沟道宽度无变化，且所述分压薄膜晶体管的沟道数量为2。
在本申请实施例提供的像素结构中，所述第二驱动薄膜晶体管的沟道呈I型设置，且所述分压薄膜晶体管的沟道包括平行间隔设置的第一子沟道和第二子沟道，所述第一子沟道和所述第二子沟道均呈I型设置，则所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道宽度均无变化，且所述分压薄膜晶体管的沟道数量为2。
在本申请实施例提供的像素结构中，所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间还满足关系式：
Figure PCTCN2021099045-appb-000002
本申请实施例还提供一种显示面板，其包括相对设置的第一基板和第二基板、设置于所述第一基板和所述第二基板之间的多个液晶分子，其中所述第一基板包括前述实施例其中之一的像素结构。
本申请实施例还提供一种像素结构设计方法，所述像素结构包括多个子像素单元，每一所述子像素单元包括第一像素电极和第二像素电极，所述第一像素电极和所述第二像素电极之间设置有多个薄膜晶体管，多个所述薄膜晶体管包括：
与所述第一像素电极连接的第一驱动薄膜晶体管；
与所述第二像素电极连接的第二驱动薄膜晶体管；以及
与所述第二驱动薄膜晶体管连接的分压薄膜晶体管；
所述像素结构设计方法包括：
基于所述第二驱动薄膜晶体管和所述分压薄膜晶体管的预设沟道宽度和预设沟道长度以及所述薄膜晶体管的源极、漏极的变异量，确定所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道长度和沟道宽度，所述第二驱动薄膜晶体管和所述分压薄膜晶体管沟道长度和沟道宽度之间满足关系式：
Figure PCTCN2021099045-appb-000003
其中，a和b分别表示所述第二驱动薄膜晶体管的沟道宽度和沟道长度，c和d分别表示所述分压薄膜晶体管的沟道宽度和沟道长度，n表示所述分压薄膜晶体管的沟道数量，e、f分别表示所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道宽度的变化量参数，当所述沟道宽度发生变化时，所述变化量参数的值为1，当所述沟道宽度无变化时，所述变化量参数的值为0。
在本申请实施例提供的像素结构设计方法中，所述基于所述第二驱动薄膜晶体管和所述分压薄膜晶体管的预设沟道宽度和预设沟道长度以及所述薄膜晶体管的源极、漏极的变异量，确定所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道长度和沟道宽度的步骤还包括：
获取所述第二驱动薄膜晶体管和所述分压薄膜晶体管的预设沟道宽度和预设沟道长度；
确定所述薄膜晶体管的源极、漏极的变异量。
在本申请实施例提供的像素结构设计方法中，所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间还满足关系式：
Figure PCTCN2021099045-appb-000004
有益效果
本申请提供的像素结构及其制备方法、显示面板中所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000005
满足该关系式的第二驱动薄膜晶体管和分压薄膜晶体管的分压比与设计像素结构时的预设分压比基本相同，如此不会受到阵列工艺中紫外曝光、显影、湿蚀刻等制程或设备等因素的影响，解决了现有像素结构中因Share TFT和Sub TFT的沟道宽长比发生变化，导致Share TFT和Sub TFT的分压发生变化，引起的整个显示面板的亮度不均的问题。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的像素结构的一种俯视结构示意图。
图2为图1中薄膜晶体管的细节结构示意图。
图3为本申请实施例提供的驱动晶体管的膜层结构示意图。
图4为本申请实施例提供的分压比随源极和漏极的变异量的变化趋势图。
图5为本申请实施例提供的像素结构的又一种俯视结构示意图。
图6为本申请实施例提供的像素结构设计方法的流程示意图。
本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用 以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
请结合参照图1至图3，图1为本申请实施例提供的像素结构的一种俯视结构示意图，图2为图1中薄膜晶体管的细节结构示意图，图3为本申请实施例提供的驱动晶体管的膜层结构示意图。所述像素结构100包括多个子像素单元1，图1示意性示出了一个所述子像素单元1。每一所述子像素单元1包括第一像素电极11和第二像素电极12以及多个薄膜晶体管20。多个所述薄膜晶体管20包括与所述第一像素电极11连接的第一驱动薄膜晶体管21；与所述第二像素电极12连接的第二驱动薄膜晶体管22；与所述第二驱动薄膜晶体管22连接的分压薄膜晶体管23。
具体地，继续参照图1，所述第一像素电极11和所述第二像素电极12相对设置，所述第一像素电极11和所述第二像素电极12之间设置有多个薄膜晶体管20。所述第一像素电极11和所述第二像素电极12均包括多个畴区，比如可以为二畴、四畴等，如图1示出的即为每个像素电极分成四个畴区，当然地，本申请不限于此。
多个所述薄膜晶体管20包括第一驱动薄膜晶体管21、第二驱动薄膜晶体管22以及分压薄膜晶体管23。所述第一驱动薄膜晶体管21与所述第一像素电极11电连接，用于给所述第一像素电极11提供驱动电压。所述第二驱动薄膜晶体管22与所述第二像素电极12连接，且所述第二驱动薄膜晶体管22还与所述分压薄膜晶体管23串联连接，所述第二驱动薄膜晶体管22用于给所述第二像素电极12提供驱动电压，所述分压薄膜晶体管23用于分担所述第二驱动薄膜晶体管22的电压，使所述第二驱动薄膜晶体管22提供给所述第二像素电极12的驱动电压与所述第一驱动薄膜晶体管21提供给所述第一像素电极11的驱动电压不同，从而达到增大视角的效果。
所述分压薄膜晶体管23和所述第二驱动薄膜晶体管22的分压比与所述分压薄膜晶体管23和所述第二驱动薄膜晶体管22的沟道长度和沟道宽度的大小有关。具体地，所述分压薄膜晶体管23的沟道宽长比与所述第二驱动薄膜晶体 管22的沟道宽长比的比值即为所述分压薄膜晶体管23和所述第二驱动薄膜晶体管22的分压比，其中所述沟道的宽长比是指沟道宽度与沟道长度的比值。
当分压薄膜晶体管23和第二驱动薄膜晶体管22的分压比变化时，会导致驱动所述第二像素电极12的驱动电压发生变化，从而改变亮度。因此当显示基板不同区域由于紫外曝光、显影和湿蚀刻等制程或设备的影响，导致分压薄膜晶体管23和第二驱动薄膜晶体管22的沟道宽长比不同，则会导致分压变化，从而影响显示亮度，而从引起整个显示面板的亮度不均。
本申请定义所述第二驱动薄膜晶体管22的沟道宽度为a，沟道长度为b，所述分压薄膜晶体管23的沟道宽度为c，沟道长度为d。为了改善显示面板亮度不均的问题，可以设置所述第二驱动薄膜晶体管22的沟道宽度a、沟道长度b与所述分压薄膜晶体管23的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000006
其中n表示所述分压薄膜晶体管23的沟道数量，e、f分别表示所述第二驱动薄膜晶体管22和所述分压薄膜晶体管23的沟道宽度的变化量参数，当所述沟道宽度发生变化时，所述变化量参数的值为1，当所述沟道宽度无变化时，所述变化量参数的值为0。如此，通过使第二驱动薄膜晶体管22的沟道宽度a、沟道长度b与分压薄膜晶体管23的沟道宽度c、沟道长度d之间满足预设的关系式，使第二驱动薄膜晶体管22和分压薄膜晶体管23的分压比与设计像素结构100时的预设分压比基本相同，以缓解现有显示面板存在亮度不均的问题。
需要说明的是，所述第二驱动薄膜晶体管22和所述分压薄膜晶体管23的沟道宽度是否发生变化是指实际制备得到的所述第二驱动薄膜晶体管22和所述分压薄膜晶体管23的沟道宽度相较于预设沟道宽度的变化，其中预设沟道宽度是指在理想工艺状态下能够实现的沟道宽度，也即在设计像素结构100时，设 计定义出来的沟道宽度。而薄膜晶体管的沟道宽度是否发生变化取决于薄膜晶体管的制备工艺以及薄膜晶体管的沟道类型，比如对于采用4mask工艺(即采用四道光罩)制备的薄膜晶体管，薄膜晶体管的沟道宽度将会发生变化；对于采用非4mask工艺制备的薄膜晶体管，薄膜晶体管的沟道宽度是否发生变化还取决于薄膜晶体管的沟道类型。
下面先以采用4mask工艺制备的薄膜晶体管为例具体阐述本申请的像素结构：
在薄膜晶体管的制备工艺中，采用4mask工艺在衬底基板上制备各所述薄膜晶体管20，能够节省光罩，简化工艺流程，节约成本。所述薄膜晶体管20的制备工艺包括依次制备在衬底基板上的栅极、半导体层以及源极和漏极，当然地，所述栅极与所述半导体层之间还设置有绝缘层，如栅极绝缘层。
具体地，参照图3，以所述第二驱动薄膜晶体管22为例说明薄膜晶体管的具体膜层结构，所述第二驱动薄膜晶体管22包括依次制备在衬底基板60上的栅极41、栅极绝缘层411、半导体层224以及间隔设置在半导体层224上的源极222和漏极223，所述源极222和所述漏极223之间的区域形成所述第二薄膜晶体管22的沟道221，且所述源极222和所述漏极223与所述半导体层224接触的部分还设置有欧姆接触层225，以保证良好的导电性能。具体地，所述半导体层224位于所述源极222和所述漏极223下方，所述源极222和所述漏极223之间具有间隔，所述半导体层224对应所述间隔的部分即为所述第二驱动薄膜晶体管22的沟道221。
另外，所述薄膜晶体管20的所述源极和所述漏极与所述半导体层在同一光罩下图案化形成，所述光罩包括半色调掩膜板(Half-Tone Mask，HTM)或灰阶色调掩膜板(Gray Tone Mask，GTM)等。
在使用同一光罩制备所述半导体层、所述源极和所述漏极时，衬底基板上不同区域由于受紫外曝光、显影、湿蚀刻等制程或设备的影响，使制得的所述源极和所述漏极的线宽与预设的线宽存在差异，比如实际制得所述源极和所述漏极的线宽比预设的线宽大，其中预设的线宽是指在理想工艺状态下能够实现的线宽，也即在设计像素结构100时，设计定义出来的线宽。
进一步地，因所述半导体层、所述源极和所述漏极在同一光罩下形成，当 所述源极和所述漏极的线宽增大，相应地，所述源极和所述漏极之间的间隔就会减小，如此则会导致所述薄膜晶体管20的沟道长度和沟道宽度发生变化。具体地，当所述源极和所述漏极的线宽变异量为x时，比如所述源极和所述漏极的线宽增大x，则所述薄膜晶体管20的沟道宽度也增大x，此时所述薄膜晶体管20的沟道宽度的变化量参数值为1；所述薄膜晶体管20的沟道长度则减小，具体减小量需根据所述薄膜晶体管20的沟道数量来确定，比如所述薄膜晶体管20的沟道数量为一个时，则所述薄膜晶体管20的沟道长度减小x，所述薄膜晶体管20的沟道数量为二个时，则所述薄膜晶体管20的沟道长度减小2x。其中，所述薄膜晶体管20的沟道长度等于所述源极和所述漏极之间的间隔距离，所述薄膜晶体管20的沟道宽度以实际填充在所述源极和所述漏极之间的所述半导体层的宽度为准。
同时，所述像素结构100还包括数据线30、与所述数据线30平行设置的共享放电棒50(Share bar)以及与所述数据线30垂直绝缘相交的栅极线40，其中所述数据线30、所述共享放电棒50均与所述源极或所述漏极同层设置，所述栅极线40与所述薄膜晶体管20的栅极同层设置，且所述栅极线40与各所述薄膜晶体管20的栅极电连接。
需要说明的是，本申请中的“同层设置”是指在制备工艺中，将相同材料形成的膜层进行图案化处理得到至少两个不同的特征，则所述至少两个不同的特征同层设置。比如，本实施例的所述数据线30与所述薄膜晶体管20的源极由同一导电膜层进行图案化处理后得到，则所述数据线30与所述薄膜晶体管20的源极同层设置。
进一步地，所述第一驱动薄膜晶体管21的源极212和所述第二驱动薄膜晶体管22的源极222一体式设计且与所述数据线30电连接，所述第一驱动薄膜晶体管21的漏极213通过第一过孔111与所述第一像素电极11电连接，所述第二驱动薄膜晶体管22的漏极223通过第二过孔121与所述第二像素电极12电连接，且所述第二驱动薄膜晶体管22的漏极223还同时与所述分压薄膜晶体管23的源极233电连接，所述分压薄膜晶体管23的漏极234与所述共享分压棒50电连接。
所述薄膜晶体管20的源极和漏极均呈I型设置，则对应地，所述薄膜晶体管20的沟道也均呈I设置。具体地，如图2所示，所述第一驱动薄膜晶体管21的 沟道211和所述第二驱动薄膜晶体管22的沟道221均呈I型且平行设置，所述分压薄膜晶体管23的沟道包括第一子沟道231和第二子沟道232，所述第一子沟道231和所述第二子沟道232均呈I型设置，所述第一子沟道231和所述第二子沟道232平行间隔设置。且所述第一子沟道231的宽度等于所述第二子沟道232的宽度，也即为所述分压薄膜晶体管23的沟道宽度c。其中所述薄膜晶体管20的沟道呈I型设置，表示所述薄膜晶体管20的沟道数量为一个，故所述分压薄膜晶体管23的沟道包括两个I型子沟道，表示所述分压薄膜晶体管23的沟道数量为2个，则所述分压薄膜晶体管23的沟道长度d等于所述第一子沟道231的沟道长度d1与所述第二子沟道232的沟道长度d2之和。
此时，所述第二驱动薄膜晶体管22的沟道宽度a、沟道长度b与所述分压薄膜晶体管23的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000007
满足该关系式的所述分压薄膜晶体管23和所述第二驱动薄膜晶体管22的分压比相较于预设的分压比基本不变，不会影响像素区的亮度，进而不会产生亮度不均的现象。
具体地，以所述分压薄膜晶体管23与所述第二驱动薄膜晶体管22的预设分压比为44％为例，可选地，所述分压薄膜晶体管23和所述第二驱动薄膜晶体管22的常规预设参数和本申请的预设参数如表1所示，其中预设参数包括所述分压薄膜晶体管23的预设沟道宽度和预设沟道长度，以及所述第二驱动薄膜晶体管22的预设沟道宽度和预设沟道长度，本申请的预设参数是指通过工艺制备后实际得到的所述分压薄膜晶体管23的沟道宽度c和沟道长度d与所述第二驱动薄膜晶体管22的沟道宽度a和沟道长度b之间满足关系式：
Figure PCTCN2021099045-appb-000008
时的预设参数，而常规预设参数即制得的薄膜晶体管的沟道宽长不满足该关系式时的预设参数。表1中各预设参数的数值单位为微米。
Figure PCTCN2021099045-appb-000009
表1
基于表1示出的预设参数，能够计算出源极和漏极的变异量x在-1至1的范围内所述分压薄膜晶体管23与所述第二驱动薄膜晶体管22的实际分压比，如表2所示：
Figure PCTCN2021099045-appb-000010
Figure PCTCN2021099045-appb-000011
表2
其中所述实际分压比是指基于预设参数实际制得的所述分压薄膜晶体管23与所述第二驱动薄膜晶体管22的分压比，该实际分压比等于所述分压薄膜晶体管23的宽长比与所述第二驱动薄膜晶体管22的宽长比的比值。比如，以源极和漏极变异量x＝0.1微米为例，基于常规预设参数制得的所述分压薄膜晶体管23的沟道宽度为4.4+0.1＝4.5，所述分压薄膜晶体管23的沟道长度为10-2*0.1＝9.8，所述第二驱动薄膜晶体管22的沟道宽度为5+0.1＝5.1，所述第二驱动薄膜晶体管22的沟道长度为5-0.1＝4.9，则常规预设参数对应的实际分压比 为(4.5/9.8)/(5.1/4.9)＝0.4412；基于本申请预设参数制得的所述分压薄膜晶体管23的沟道宽度为4.7+0.1＝4.8，所述分压薄膜晶体管23的沟道长度为10.68-2*0.1＝10.48，所述第二驱动薄膜晶体管22的沟道宽度为5+0.1＝5.1，所述第二驱动薄膜晶体管22的沟道长度为5-0.1＝4.9，则常规预设参数对应的实际分压比为(4.8/10.48)/(5.1/4.9)＝0.4401。
从表2中可以看出，在随着源极和漏极的变异量逐渐变化时，常规预设参数对应的实际分压比相较于预设分压比变化趋势较大，而本申请的预设参数对应的实际分压比相较于预设分压比变化较小。具体地，请参照图4，图4为本申请实施例提供的分压比随源极和漏极的变异量的变化趋势图，在图4中横坐标X表示源极和漏极的变异量x，纵坐标Y表示实际分压比的值，曲线A表示常规预设参数对应的实际分压比随源极和漏极的变异量的变化趋势，曲线B表示本申请的预设参数对应的实际分压比随源极和漏极的变异量的变化趋势。比较曲线A和曲线B，可以清楚直观的看出，本申请的预设参数对应的实际分压比相较于设定的预设分压比变化较小，而常规预设参数对应的实际分压比相较于设定的预设分压比变化趋势较大。
因此，基于本申请的预设参数制得的分压薄膜晶体管23和第二驱动薄膜晶体管22的沟道宽度以及沟道长度只需满足本实施例的关系式，即可使得到的实际分压比相较于预设分压比基本保持不变，从而不会产生亮度不均的现象。当然地，对于本申请的预设参数本实施例仅是示例，本申请的预设参数也满足关系式：
Figure PCTCN2021099045-appb-000012
其中M表示分压薄膜晶体管23的预设沟道宽度，N表示分压薄膜晶体管23的预设沟道长度，O表示第二驱动薄膜晶体管22的预设沟道宽度，P表示第二驱动薄膜晶体管22的预设沟道长度，n表示分压薄膜晶体管23的沟道数量。
在一种实施例中，请参照图5，图5为本申请实施例提供的像素结构的又一种俯视结构示意图。与上述实施例不同的是，所述像素结构101中的第一像素电极11位于所述第二像素电极12围成的区域内，多个薄膜晶体管20位于所述第一像素电极11和所述第二像素电极12的同一侧。
具体地，所述第一驱动薄膜晶体管21的源极和所述第二驱动薄膜晶体管22的源极均呈U型设置，所述第一驱动薄膜晶体管21的漏极和所述第二驱动薄膜晶体管22的漏极分别位于对应的U型源极开口内，则所述第一驱动薄膜晶体管21的沟道和所述第二驱动薄膜晶体管22的沟道也均呈U型设置。
可选地，所述分压薄膜晶体管23的源极和所述分压薄膜晶体管23的漏极均呈I型设置，则所述分压薄膜晶体管23的沟道也呈I型设置，而薄膜晶体管的沟道呈I型或U型设置时，表示薄膜晶体管的沟道数量为一个，故可选地，在本实施例中，所述分压薄膜晶体管23的沟道也可呈U型设置。
此时，所述第二驱动薄膜晶体管22的沟道宽度a、沟道长度b与所述分压薄膜晶体管23的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000013
满足该关系式的所述分压薄膜晶体管23和所述第二驱动薄膜晶体管22的分压比相较于预设的分压比基本不变，不会影响像素区的亮度，进而不会产生亮度不均的现象。其他说明请参照上述实施例，在此不再赘述。
在一种实施例中，与上述实施例不同的是，所述第二驱动薄膜晶体管22的沟道宽度a、沟道长度b与所述分压薄膜晶体管23的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000014
其中n表示分压薄膜晶体管23的沟道数量，e、f分别表示所述第二驱动薄膜晶体管22和所述分压薄膜晶体管23的沟道宽度的变化量参数，而对于采用4mask工艺制备的薄膜晶体管，薄膜晶体管的沟道宽 度的变化量参数为1，满足该关系式的所述分压薄膜晶体管23和所述第二驱动薄膜晶体管22的分压比相较于预设的分压比更为接近，不会影响像素区的亮度，进而不会产生亮度不均的现象。其他说明请参照上述实施例，在此不再赘述。
然后接着以采用非4mask工艺制备的薄膜晶体管为例具体阐述本申请的像素结构：
在采用非4mask工艺制备所述薄膜晶体管时，所述薄膜晶体管仍包括源极、漏极以及半导体层，所述源极和所述漏极间隔设置于所述半导体层上，所述源极和所述漏极之间的区域形成所述薄膜晶体管的沟道，但是与采用4mask工艺制备所述薄膜晶体管不同的是，所述源极和所述漏极与所述半导体层在不同的光罩下形成，也即所述源极和所述漏极在一道光罩下形成，所述半导体层在另一道光罩下形成，如此所述薄膜晶体管的沟道宽度的变化情况与4mask工艺时沟道宽度的变化情况不同，但所述薄膜晶体管的沟道长度的变化情况与4mask工艺时沟道长度的变化情况相同。此时所述薄膜晶体管的沟道宽度的变化情况与所述薄膜晶体管的沟道类型相关。
下面将列举不同的薄膜晶体管沟道类型来简述在非4mask工艺下薄膜晶体管的沟道长度和沟道宽度满足的关系式：
在一种实施例中，所述第二驱动薄膜晶体管的沟道呈U型设置，且所述分压薄膜晶体管的沟道呈I型设置，则所述第二驱动薄膜晶体管的沟道宽度发生变化，所述分压薄膜晶体管的沟道宽度无变化，且所述分压薄膜晶体管的沟道数量为1，此时所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000015
满足该关系式的所述分压薄膜晶体管和所述第二驱动薄膜晶体管的分压比相 较于预设的分压比基本不变，不会影响像素区的亮度，进而不会产生亮度不均的现象。
在一种实施例中，所述第二驱动薄膜晶体管的沟道呈U型设置，且所述分压薄膜晶体管的沟道包括平行间隔设置的第一子沟道和第二子沟道，所述第一子沟道和所述第二子沟道均呈I型设置，则所述第二驱动薄膜晶体管的沟道宽度发生变化，所述分压薄膜晶体管的沟道宽度无变化，且所述分压薄膜晶体管的沟道数量为2，此时所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000016
满足该关系式的所述分压薄膜晶体管和所述第二驱动薄膜晶体管的分压比相较于预设的分压比基本不变，不会影响像素区的亮度，进而不会产生亮度不均的现象。
在一种实施例中，所述第二驱动薄膜晶体管的沟道呈I型设置，且所述分压薄膜晶体管的沟道包括平行间隔设置的第一子沟道和第二子沟道，所述第一子沟道和所述第二子沟道均呈I型设置，则所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道宽度均无变化，且所述分压薄膜晶体管的沟道数量为2，此时所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000017
满足该关系式的所述分压薄膜晶体管和所述第二驱动薄膜晶体管的分压比相较于预设的分压比基本不变，不会影响像素区的亮度，进而不会产生亮度不均的现象。
在一种实施例中，提供一种像素结构设计方法，请参照图1至6，图6为本申请实施例提供的像素结构设计方法的流程示意图。所述像素结构100包括多个子像素单元1，每一所述子像素单元1包括第一像素电极11和第二像素电极12，所述第一像素电极11和所述第二像素电极12之间设置有多个薄膜晶体管20，多个所述薄膜晶体管20包括与所述第一像素电极11连接的第一驱动薄膜晶体管21；与所述第二像素电极12连接的第二驱动薄膜晶体管22；与所述第二驱动薄膜晶体管22连接的分压薄膜晶体管23。
所述像素结构设计方法用于设计上述实施例其中之一的像素结构，该方法包括：
S201:获取所述第二驱动薄膜晶体管22和所述分压薄膜晶体管23的预设沟道宽度和预设沟道长度；
S202:确定所述薄膜晶体管的源极、漏极的变异量；
S203:基于所述第二驱动薄膜晶体管22和所述分压薄膜晶体管23的预设沟道宽度和预设沟道长度以及所述薄膜晶体管的源极、漏极的变异量，确定所述第二驱动薄膜晶体管22和所述分压薄膜晶体管23的沟道长度和沟道宽度，所述第二驱动薄膜晶体管22和所述分压薄膜晶体管23沟道长度和沟道宽度之间满足关系式：
Figure PCTCN2021099045-appb-000018
其中，a和b分别表示所述第二驱动薄膜晶体管22的沟道宽度和沟道长度，c和d分别表示所述分压薄膜晶体管23的沟道宽度和沟道长度，n表示所述分压薄膜晶体管23的沟道数量，e、f分别表示所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道宽度的变化量参数，当所述沟道宽度发生变化时，所述变化量参数的值为1，当所述沟道宽度无变化时，所述变化量参数的值为0。
具体地，当所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压 薄膜晶体管的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000019
时，所述分压薄膜晶体管和所述第二驱动薄膜晶体管的分压比相较于预设的分压比基本不变，不会影响像素区的亮度，进而不会产生亮度不均的现象。
而当所述第二驱动薄膜晶体管22的沟道宽度a、沟道长度b与所述分压薄膜晶体管23的沟道宽度c、沟道长度d之间满足关系式：
Figure PCTCN2021099045-appb-000020
时，所述分压薄膜晶体管和所述第二驱动薄膜晶体管的分压比相较于预设的分压比更为接近。
本申请实施例还提供一种显示面板，其包括相对设置的第一基板和第二基板、设置于所述第一基板和所述第二基板之间的多个液晶分子，其中所述第一基板包括前述实施例其中之一的像素结构。可选地，所述第一基板为阵列基板，所述第二基板为彩膜基板。
根据上述实施例可知：
本申请提供一种像素结构及其设计方法、显示面板，像素结构包括多个子像素单元，每一子像素单元包括第一像素电极和第二像素电极，第一像素电极和第二像素电极之间设置有多个薄膜晶体管，多个薄膜晶体管包括与第一像素电极连接的第一驱动薄膜晶体管；与第二像素电极连接的第二驱动薄膜晶体管；与第二驱动薄膜晶体管连接的分压薄膜晶体管；第二驱动薄膜晶体管的沟道宽度、沟道长度与分压薄膜晶体管的沟道宽度、沟道长度之间满足预设的关系式，使第二驱动薄膜晶体管和分压薄膜晶体管的分压比与设计像素结构时的预设分压比基本相同，如此不会受到阵列工艺中紫外曝光、显影、湿蚀刻等制程或设备等因素的影响，解决了现有像素结构中因Share TFT和Sub TFT的沟道宽长比发生变化，导致Share TFT和Sub TFT的分压发生变化，引起的整个显示面板的亮度不均的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种像素结构，其包括多个子像素单元，每一所述子像素单元包括第一像素电极和第二像素电极以及多个薄膜晶体管，多个所述薄膜晶体管包括：
    与所述第一像素电极连接的第一驱动薄膜晶体管；
    与所述第二像素电极连接的第二驱动薄膜晶体管；以及
    与所述第二驱动薄膜晶体管连接的分压薄膜晶体管；
    其中，所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间满足关系式：
    Figure PCTCN2021099045-appb-100001
    其中n表示所述分压薄膜晶体管的沟道数量，e、f分别表示所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道宽度的变化量参数，当所述沟道宽度发生变化时，所述变化量参数的值为1，当所述沟道宽度无变化时，所述变化量参数的值为0。
  2. 根据权利要求1所述的像素结构，其中，每一所述薄膜晶体管均包括源极、漏极以及半导体层，所述源极和所述漏极间隔设置于所述半导体层上，所述源极和所述漏极之间的区域形成所述薄膜晶体管的沟道，其中，所述源极和所述漏极与所述半导体层在同一光罩下形成，则所述薄膜晶体管的沟道宽度发生变化。
  3. 根据权利要求2所述的像素结构，其中，所述第二驱动薄膜晶体管的沟道和所述分压薄膜晶体管的沟道均呈U型设置或I型设置，所述分压薄膜晶体管的沟道数量为1。
  4. 根据权利要求2所述的像素结构，其中，所述第二驱动薄膜晶体管的沟道呈U型设置或I型设置，所述分压薄膜晶体管的沟道包括第一子沟道和第二子沟道，所述第一子沟道呈I型设置，所述第二子沟道呈I型设置，且所述第二子 沟道与所述第一子沟道平行间隔设置，且所述分压薄膜晶体管的沟道数量为2。
  5. 根据权利要求1所述的像素结构，其中，每一所述薄膜晶体管均包括源极、漏极以及半导体层，所述源极和所述漏极间隔设置于所述半导体层上，所述源极和所述漏极之间的区域形成所述薄膜晶体管的沟道，其中，所述源极和所述漏极与所述半导体层在不同的光罩下形成。
  6. 根据权利要求5所述的像素结构，其中，所述第二驱动薄膜晶体管的沟道呈U型设置，且所述分压薄膜晶体管的沟道呈I型设置，则所述第二驱动薄膜晶体管的沟道宽度发生变化，所述分压薄膜晶体管的沟道宽度无变化，且所述分压薄膜晶体管的沟道数量为1。
  7. 根据权利要求5所述的像素结构，其中，所述第二驱动薄膜晶体管的沟道呈U型设置，且所述分压薄膜晶体管的沟道包括平行间隔设置的第一子沟道和第二子沟道，所述第一子沟道和所述第二子沟道均呈I型设置，则所述第二驱动薄膜晶体管的沟道宽度发生变化，所述分压薄膜晶体管的沟道宽度无变化，且所述分压薄膜晶体管的沟道数量为2。
  8. 根据权利要求5所述的像素结构，其中，所述第二驱动薄膜晶体管的沟道呈I型设置，且所述分压薄膜晶体管的沟道包括平行间隔设置的第一子沟道和第二子沟道，所述第一子沟道和所述第二子沟道均呈I型设置，则所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道宽度均无变化，且所述分压薄膜晶体管的沟道数量为2。
  9. 根据权利要求1所述的像素结构，其中，所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间还满足关系式：
    Figure PCTCN2021099045-appb-100002
  10. 一种显示面板，其中，包括相对设置的第一基板和第二基板、设置于所述第一基板和所述第二基板之间的多个液晶分子，其中所述第一基板包括像素结构，所述像素结构包括多个子像素单元，每一所述子像素单元包括第一像素电极和第二像素电极以及多个薄膜晶体管，多个所述薄膜晶体管包括：
    与所述第一像素电极连接的第一驱动薄膜晶体管；
    与所述第二像素电极连接的第二驱动薄膜晶体管；以及
    与所述第二驱动薄膜晶体管连接的分压薄膜晶体管；
    其中，所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间满足关系式：
    Figure PCTCN2021099045-appb-100003
    其中n表示所述分压薄膜晶体管的沟道数量，e、f分别表示所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道宽度的变化量参数，当所述沟道宽度发生变化时，所述变化量参数的值为1，当所述沟道宽度无变化时，所述变化量参数的值为0。
  11. 根据权利要求10所述的显示面板，其中，每一所述薄膜晶体管均包括源极、漏极以及半导体层，所述源极和所述漏极间隔设置于所述半导体层上，所述源极和所述漏极之间的区域形成所述薄膜晶体管的沟道，其中，所述源极和所述漏极与所述半导体层在同一光罩下形成，则所述薄膜晶体管的沟道宽度发生变化。
  12. 根据权利要求11所述的显示面板，其中，所述第二驱动薄膜晶体管的沟道和所述分压薄膜晶体管的沟道均呈U型设置或I型设置，所述分压薄膜晶体管的沟道数量为1。
  13. 根据权利要求11所述的显示面板，其中，所述第二驱动薄膜晶体管的沟道呈U型设置或I型设置，所述分压薄膜晶体管的沟道包括第一子沟道和第二子沟道，所述第一子沟道呈I型设置，所述第二子沟道呈I型设置，且所述第二子沟道与所述第一子沟道平行间隔设置，且所述分压薄膜晶体管的沟道数量为2。
  14. 根据权利要求10所述的显示面板，其中，每一所述薄膜晶体管均包括源极、漏极以及半导体层，所述源极和所述漏极间隔设置于所述半导体层上，所述源极和所述漏极之间的区域形成所述薄膜晶体管的沟道，其中，所述源极 和所述漏极与所述半导体层在不同的光罩下形成。
  15. 根据权利要求14所述的显示面板，其中，所述第二驱动薄膜晶体管的沟道呈U型设置，且所述分压薄膜晶体管的沟道呈I型设置，则所述第二驱动薄膜晶体管的沟道宽度发生变化，所述分压薄膜晶体管的沟道宽度无变化，且所述分压薄膜晶体管的沟道数量为1。
  16. 根据权利要求14所述的显示面板，其中，所述第二驱动薄膜晶体管的沟道呈U型设置，且所述分压薄膜晶体管的沟道包括平行间隔设置的第一子沟道和第二子沟道，所述第一子沟道和所述第二子沟道均呈I型设置，则所述第二驱动薄膜晶体管的沟道宽度发生变化，所述分压薄膜晶体管的沟道宽度无变化，且所述分压薄膜晶体管的沟道数量为2。
  17. 根据权利要求10所述的像素结构，其中，所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间还满足关系式：
    Figure PCTCN2021099045-appb-100004
  18. 一种像素结构设计方法，其中，所述像素结构包括多个子像素单元，每一所述子像素单元包括第一像素电极和第二像素电极，所述第一像素电极和所述第二像素电极之间设置有多个薄膜晶体管，多个所述薄膜晶体管包括：
    与所述第一像素电极连接的第一驱动薄膜晶体管；
    与所述第二像素电极连接的第二驱动薄膜晶体管；以及
    与所述第二驱动薄膜晶体管连接的分压薄膜晶体管；
    所述像素结构设计方法包括：
    基于所述第二驱动薄膜晶体管和所述分压薄膜晶体管的预设沟道宽度和预设沟道长度以及所述薄膜晶体管的源极、漏极的变异量，确定所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道长度和沟道宽度，所述第二驱动薄膜晶体管和所述分压薄膜晶体管沟道长度和沟道宽度之间满足关系式：
    Figure PCTCN2021099045-appb-100005
    其中，a和b分别表示所述第二驱动薄膜晶体管的沟道宽度和沟道长度，c和d分别表示所述分压薄膜晶体管的沟道宽度和沟道长度，n表示所述分压薄膜晶体管的沟道数量，e、f分别表示所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道宽度的变化量参数，当所述沟道宽度发生变化时，所述变化量参数的值为1，当所述沟道宽度无变化时，所述变化量参数的值为0。
  19. 根据权利要求18所述的像素结构设计方法，其中，所述基于所述第二驱动薄膜晶体管和所述分压薄膜晶体管的预设沟道宽度和预设沟道长度以及所述薄膜晶体管的源极、漏极的变异量，确定所述第二驱动薄膜晶体管和所述分压薄膜晶体管的沟道长度和沟道宽度的步骤还包括：
    获取所述第二驱动薄膜晶体管和所述分压薄膜晶体管的预设沟道宽度和预设沟道长度；
    确定所述薄膜晶体管的源极、漏极的变异量。
  20. 根据权利要求18所述的像素结构设计方法，其中，所述第二驱动薄膜晶体管的沟道宽度a、沟道长度b与所述分压薄膜晶体管的沟道宽度c、沟道长度d之间还满足关系式：
    Figure PCTCN2021099045-appb-100006
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