WO2022247017A1 - 显示面板及其制作方法 - Google Patents

显示面板及其制作方法 Download PDF

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Publication number
WO2022247017A1
WO2022247017A1 PCT/CN2021/111704 CN2021111704W WO2022247017A1 WO 2022247017 A1 WO2022247017 A1 WO 2022247017A1 CN 2021111704 W CN2021111704 W CN 2021111704W WO 2022247017 A1 WO2022247017 A1 WO 2022247017A1
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WIPO (PCT)
Prior art keywords
layer
electrode
display panel
channel region
metal layer
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PCT/CN2021/111704
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English (en)
French (fr)
Inventor
罗传宝
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/436,142 priority Critical patent/US20220384767A1/en
Publication of WO2022247017A1 publication Critical patent/WO2022247017A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a manufacturing method thereof.
  • Mini-Light Emitting Diode (Mini-LED) display panels and Micro-Light Emitting Diode (Micro-LED) display panels have high contrast and high color rendering performance, which can be compared with Organic Light Emitting Diodes (Organic Light -Emitting Diode (OLED) display panels are comparable in characteristics, becoming a hotspot for the layout of major panel manufacturers.
  • Organic Light Emitting Diodes Organic Light -Emitting Diode (OLED) display panels are comparable in characteristics, becoming a hotspot for the layout of major panel manufacturers.
  • Thin Film Transistor is currently the main driving element in Mini-LED displays, Micro-LED displays, LCD displays and OLED displays, and is directly related to the development direction of high-performance flat panel display devices.
  • Thin-film transistors have various structures, and there are also various materials for preparing the active layer of thin-film transistors with corresponding structures.
  • metal oxide thin-film transistors Metal Oxide TFT
  • have high field-effect mobility ⁇ 10cm2/V s)
  • the characteristics of simple preparation process, good uniformity of large-area deposition, fast response speed and high transmittance in the visible light range are considered to be the most potential backplane technology for the development of displays in the direction of large size and flexibility.
  • Embodiments of the present application provide a display panel and a manufacturing method thereof, which can solve the problem of performance degradation of the channel region in the current display panel due to the influence of external ambient light.
  • an embodiment of the present application provides a display panel, including: a base substrate, a light absorbing layer, and a driving circuit layer that are sequentially stacked, the driving circuit layer includes a first metal layer and an active layer, and the first metal The layer includes a first electrode and a second electrode arranged at intervals in the same layer, and the active layer is arranged on the first metal layer and includes a channel region;
  • the vertical projection of the light absorbing layer on the base substrate covers the vertical projection of the gap region between the first electrode and the second electrode on the base substrate.
  • the active layer includes the channel region formed of a semiconductor metal oxide material, the first electrode is a source, the second electrode is a drain, and the drain is on the substrate
  • the vertical projection on the substrate overlays the vertical projection of the channel region on the base substrate.
  • the light absorbing layer includes a thiophene-based organic semiconductor material.
  • the entire surface of the light absorbing layer is disposed on the base substrate.
  • the driving circuit layer further includes a gate insulating layer and a second metal layer stacked on the active layer, the second metal layer includes a gate, and the gate is connected to the channel Area corresponding settings;
  • the second metal layer is composed of an anti-reflection layer and a stacked metal layer, and the anti-reflection layer is located between the stacked metal layer and the gate insulating layer.
  • the anti-reflection layer is an indium zinc oxide film
  • the stacked metal layer is a composite metal layer formed of copper and molybdenum.
  • the active layer further includes a non-channel region, the non-channel region is formed by conducting the semiconductor metal oxide material, and the first electrode and the second electrode pass through the non-channel region It is electrically connected with the channel region, and the thickness of the active layer is 300 angstroms to 500 angstroms.
  • a first buffer layer is further provided between the light absorbing layer and the first metal layer, and the first buffer layer is a silicon oxide film layer.
  • the embodiment of the present application also discloses a method for manufacturing a display panel, including:
  • a driving circuit layer is formed on the light absorbing layer, the driving circuit layer includes a first metal layer and an active layer, the first metal layer includes a first electrode and a second electrode arranged at intervals in the same layer, the active layer a layer is disposed on the first metal layer and includes a channel region;
  • the vertical projection of the light absorbing layer on the base substrate covers the vertical projection of the gap region between the first electrode and the second electrode on the base substrate.
  • the display panel and its manufacturing method disclosed in the present application can absorb the ambient light directly or indirectly irradiated on the channel region through the gap between the first electrode and the second electrode by setting the light absorbing layer, so that the light placed on the first The channel region on the metal layer is well protected, greatly reducing the problem of performance degradation of the channel region of the active layer caused by external ambient light.
  • FIG. 1 is a schematic structural diagram of a display panel disclosed in Embodiment 1 of the present application.
  • Fig. 2a is one of the schematic diagrams of the manufacturing process of a display panel disclosed in Embodiment 2 of the present application.
  • Fig. 2b is one of the schematic diagrams of the manufacturing process of a display panel disclosed in Embodiment 2 of the present application.
  • FIG. 2c is one of the schematic diagrams of the manufacturing process of a display panel disclosed in Embodiment 2 of the present application.
  • FIG. 2d is one of the schematic diagrams of the manufacturing process of a display panel disclosed in Embodiment 2 of the present application.
  • FIG. 2e is one of the schematic diagrams of the manufacturing process of a display panel disclosed in Embodiment 2 of the present application.
  • FIG. 2f is one of the schematic diagrams of the manufacturing process of a display panel disclosed in Embodiment 2 of the present application.
  • FIG. 2g is one of the schematic diagrams of the manufacturing process of a display panel disclosed in Embodiment 2 of the present application.
  • FIG. 2h is one of the schematic diagrams of the manufacturing process of a display panel disclosed in Embodiment 2 of the present application.
  • FIG. 3 is a schematic structural diagram of another display panel disclosed in Embodiment 3 of the present application.
  • the present application provides a display panel and a manufacturing method thereof.
  • the display panel includes: a base substrate, a light absorbing layer, and a driving circuit layer that are sequentially stacked.
  • the driving circuit layer includes a first metal layer and an active layer.
  • the first The metal layer includes a first electrode and a second electrode arranged at intervals in the same layer, and the active layer is arranged on the first metal layer and includes a channel region; wherein, the projection of the light-absorbing layer on the base substrate covers the first electrode A projection of a gap region between an electrode and the second electrode on the substrate substrate.
  • the display panel and its manufacturing method disclosed in the present application can absorb the ambient light directly or indirectly irradiated on the channel region through the gap between the first electrode and the second electrode by setting the light absorbing layer, so that the light placed on the first The channel region on the metal layer is well protected, greatly reducing the problem of performance degradation of the channel region of the active layer caused by external ambient light.
  • Fig. 1 is a schematic structural view of a display panel disclosed in an embodiment of the present application.
  • the display panel includes: a base substrate 10, a light absorbing layer 20, a first buffer layer 30 and a driving circuit layer stacked in sequence
  • the driving circuit layer includes a first metal layer 40, a second buffer layer 50, an active layer 60, a gate insulating layer 70, a second metal layer 80, a first passivation layer 90, an indium tin oxide layer 100, a third metal layer 110, a second passivation protection layer 120 and an LED light-shielding layer 130
  • a light emitting unit 140 is disposed on the driving circuit layer.
  • the base substrate 10 is made of, for example, glass, plastic, polyimide or other inorganic or organic materials, which may be a flat or curved rigid substrate, or a bendable flexible substrate.
  • the base substrate 10 is provided with a light absorbing layer 20 and a driving circuit layer.
  • the light absorbing layer 20 is, for example, disposed on the entire surface of the base substrate 10, and the driving circuit layer is formed with a thin film transistor structure, and the thin film transistor structure includes a source and a drain arranged at intervals and a channel above the source and the drain. Area.
  • the vertical projection of the light-absorbing layer 20 on the base substrate 10 covers the vertical projection of the gap region between the source and the drain on the substrate 10, thereby preventing ambient light from irradiating the channel through the gap region The problem of performance degradation of the thin film transistor caused by the region.
  • the light absorbing layer 20 is specifically a P-type organic semiconductor layer, which is made of, for example, a thiophene-based organic semiconductor material with strong light response characteristics, so as to reduce the influence of external ambient light on the channel region.
  • the light-absorbing layer may be a thiophene-based organic semiconductor with strong light-response characteristics such as 5,11-bis(triethylsilylethynyl)-dithiophene (DiF-TESADT).
  • DiF-TESADT 5,11-bis(triethylsilylethynyl)-dithiophene
  • a-Si amorphous silicon
  • the material composition of the light absorbing layer 20 in this embodiment may only contain the thiophene-based organic semiconductor material, or may contain or be doped with other components other than the thiophene-based organic semiconductor material.
  • the driving circuit layer includes a first metal layer 40 and an active layer 60
  • the first metal layer 40 includes a first electrode 41 and a second electrode 42 arranged at intervals in the same layer
  • the first electrode 41 and the second electrode A gap region is formed between the two electrodes 42
  • the active layer 60 is disposed on the first metal layer 40 and includes the channel region.
  • the vertical projection of the light-absorbing layer 20 on the base substrate 10 covers the vertical projection of the gap region between the first electrode 41 and the second electrode 42 on the substrate 10, thereby preventing external ambient light from passing through the gap region directly. Or the problem of performance degradation of the thin film transistor caused by indirect irradiation to the channel region.
  • the first metal layer 40 is, for example, made of an opaque metal material
  • the vertical projection of the second electrode 42 in the first metal layer 40 on the base substrate 10 at least covers the thin film transistor
  • the ambient light on one side of the base substrate 10 avoids the problem of increasing the manufacturing process caused by additionally setting a light-shielding layer under the channel region.
  • the first electrode 41 is, for example, the source electrode in the thin film transistor structure
  • the second electrode 42 is, for example, the drain electrode in the thin film transistor structure.
  • the electrode type of the second electrode 42 is limited.
  • the first electrode 41 can also be a drain in a thin film transistor structure
  • the second electrode 42 can also be a source in a thin film transistor structure. .
  • the type of the thin film transistor structure is, for example, a metal oxide thin film transistor
  • the active layer 60 includes, for example, the channel region formed of a semiconducting metal oxide material, and the planarized area under the metal oxide thin film transistor
  • the light-absorbing layer 20 can absorb ambient light well, and prevent ambient light from directly or indirectly irradiating the channel region of the first active layer 60 through the gap region.
  • the active layer 60 also includes, for example, a non-channel region, which is formed by conducting a semiconductor metal oxide material, and the first electrode 41 and the second electrode 42 are connected to the channel through the non-channel region.
  • the channel region is electrically connected
  • the thickness of the active layer is, for example, 300 angstroms to 500 angstroms.
  • the type of the thin film transistor structure in the driving circuit layer may also be an amorphous silicon thin film transistor or a low temperature polysilicon thin film transistor.
  • the driving circuit layer may include both low temperature polysilicon thin film transistors and metal oxide thin film transistors.
  • the driving circuit layer further includes a gate insulating layer 70 and a second metal layer 80 stacked on the active layer 60, and the second metal layer 80 includes a gate 81 in a thin film transistor structure and a A binding portion 82 for connecting external electrical signals.
  • the thin film transistor structure is a top gate (TOP Gate) structure in which the gate 81 is located above the active layer 60 , and the gate 81 is arranged corresponding to the channel region of the thin film transistor.
  • TOP Gate top gate
  • the gate 81 and the second electrode 42 are respectively arranged above and below the channel region, when the light absorbing layer 20 is not provided, the substrate 10 is away from the environment on the side of the channel region.
  • the second metal layer 80 includes an anti-reflection layer and an overlay metal layer, and the anti-reflection layer is located between the overlay metal layer and the gate insulating layer 70 .
  • the anti-reflection layer can reduce the light reflection of the ambient light incident on the driving circuit layer on the surface of the gate 81 close to the channel region, further reducing the performance degradation of the thin film transistor caused by ambient light irradiating the channel region, It should be noted that the ambient light incident into the driving circuit layer includes the ambient light incident from both sides of the display panel.
  • the anti-reflection layer is an indium zinc oxide film
  • the stacked metal layer is a composite metal layer formed of copper and molybdenum.
  • a first buffer layer 30 is provided between the light-absorbing layer 20 and the first metal layer 40, and its material is, for example, silicon oxide with stable performance. Since the light-absorbing layer 20 is an organic film layer, the first buffer layer 30 A buffer layer 30 can avoid peeling off of the film layer directly formed on the light absorbing layer 20 and the light absorbing layer 20 due to stress mismatch in the subsequent process.
  • a second buffer layer 50 is further disposed between the first metal layer 40 and the active layer 60, and the second buffer layer 50 may be a single-layer buffer layer formed of silicon oxide or silicon oxide and nitride A stacked buffer layer formed of silicon, the second buffer layer 50 is formed with a first type via hole 51 at the position corresponding to the first electrode 41 and the second electrode 42, and the active layer 60 fills the first type via hole 51 , and in contact with the first electrode 41 and the second electrode 42 to realize electrical connection.
  • a first passivation protection layer 90 and an indium tin oxide layer 100 are stacked on the second metal layer 80 , and the first passivation protection layer 90 is electrically connected to the second electrode 42
  • a second type of via hole 91 is formed on the non-channel area and the position corresponding to the bonding portion 82.
  • the indium tin oxide layer 100 includes a plurality of pixel electrodes located in the display area and thermal oxidation protection layer terminals located in the non-display area. , the plurality of pixel electrodes and thermal oxidation protective layer terminals are formed by patterning the indium tin oxide layer 100 .
  • the pixel electrode is electrically connected to the non-channel region of the active layer 60 through the second type via hole 91, and then electrically connected to the second electrode 42 of the first metal layer 40 through the conductive non-channel region,
  • the thermal oxidation protection layer terminal is electrically connected to the bonding portion of the second metal layer 80 through the second type via hole 91 .
  • the third metal layer 110, the second passivation protection layer 120 and the LED light-shielding layer 130 are sequentially stacked on the indium tin oxide layer 100, wherein the third metal layer 110 includes The electrodes correspond to a plurality of LED binding terminals provided, and the LED binding terminals are electrically connected to the light-emitting unit 140; the LED light-shielding layer 130 is disposed above the thin film transistor structure, and is used to shield the channel region from the base substrate Ambient light on 10 sides.
  • FIG. 2a is one of the schematic diagrams of the manufacturing process of a display panel disclosed in the embodiment of the present application, which specifically shows the film layers of the substrate, the light absorbing layer, the first buffer layer and the first metal layer of the display panel.
  • a base substrate 10 is provided.
  • the base substrate 10 is made of, for example, glass, plastic, polyimide or other inorganic or organic materials, which may be a flat or curved rigid substrate. , or a bendable flexible substrate.
  • the light-absorbing layer 20 is disposed on the base substrate 10 in an entire surface manner, thereby reducing or eliminating the ambient light from the base substrate 10 side directly irradiating the channel region of the active layer or passing through the gate and the first
  • the phenomenon of increased illumination in the channel region caused by the multiple reflections of the metal layer 40 prevents performance degradation of the metal oxide thin film transistor.
  • the light-absorbing layer 20 can be formed on the base substrate 10 by full-surface coating, and the light-absorbing layer 20 in a stable form can be formed after being cured by ultraviolet radiation and thermally baked at high temperature.
  • the light absorbing layer 20 may also be formed on the base substrate 10 by thin film deposition or other methods.
  • a full-surface light-absorbing layer 20 is provided, which can better absorb ambient light from both sides of the display panel, and reduce or eliminate the ambient light incident on the gate of the second metal layer 80 from the side of the base substrate 10.
  • the multiple reflections of light through the gate and the first metal layer 40 lead to increased illumination in the channel region.
  • the number of photomasks can be reduced and the process cost can be reduced.
  • the thickness of the light-absorbing layer 20 is, for example, 1-3 microns, the thermal baking temperature is 200-250° C., and the thermal-baking time is 1-2 hours. After this baking process, the light-absorbing layer 20 within the above thickness range has excellent properties. Film-forming properties and optical properties.
  • the display panel also includes, for example, a first buffer layer 30, which is disposed between the light-absorbing layer 20 and the driving circuit layer, and its material is, for example, silicon oxide with stable performance. Since the light-absorbing layer 20 is an organic film layer The first buffer layer 30 can avoid peeling off of the film layer directly formed on the light-absorbing layer 20 and the light-absorbing layer 20 due to stress mismatch in the subsequent process. Specifically, the first buffer layer 30 is, for example, a silicon oxide film layer formed on the light absorbing layer 20 by chemical vapor deposition (CVD) after the light absorbing layer 20 is cured at high temperature. Preferably, the entire surface of the first buffer layer 30 is disposed on the light absorbing layer 20 .
  • CVD chemical vapor deposition
  • the driving circuit layer of the display panel includes, for example, an opaque first metal layer 40
  • the first metal layer 40 includes a first electrode 41 and a second electrode 42 .
  • the vertical projection of the second electrode 42 in the first metal layer 40 on the base substrate 10 at least covers the vertical projection of the channel region in the thin film transistor structure on the base substrate 10, so that the second electrode 42 Multiplexed as a light-shielding layer, effectively blocking the ambient light directly incident on the side of the channel region close to the base substrate 10 from the side of the base substrate 10, avoiding the process technology caused by additionally setting a light-shielding layer under the channel region Added questions.
  • the first metal layer 40 is formed on the first buffer layer 30 by, for example, physical vapor sputtering deposition (PVD).
  • the first metal layer 40 may be a single-layer metal layer formed of molybdenum (Mo) or molybdenum (Mo )/copper (Cu), the first metal layer 40 is patterned through a wet etching process, and then the first electrode 41 and the second electrode 42 are formed.
  • the wet etching process for example, uses hydrogen peroxide (H2O2)
  • H2O2 hydrogen peroxide
  • a chemical solution is used as an etchant, and the thickness of the first metal layer 40 is, for example, 5000-8000 angstroms.
  • the first metal layer 40 further includes an anti-reflection layer formed of IZO, for example, the anti-reflection layer is stacked on the single-layer metal layer formed by molybdenum (Mo) or molybdenum (Mo)/copper (Cu ) to reduce the amount of ambient light that directly or indirectly irradiates the first metal layer and generates reflections.
  • an anti-reflection layer formed of IZO
  • the anti-reflection layer is stacked on the single-layer metal layer formed by molybdenum (Mo) or molybdenum (Mo)/copper (Cu ) to reduce the amount of ambient light that directly or indirectly irradiates the first metal layer and generates reflections.
  • the driving circuit layer of the display panel further includes, for example, a second buffer layer 50 formed on the first metal layer 40.
  • the second buffer layer 50 may be a single-layer buffer layer formed of silicon oxide or silicon oxide and silicon oxide.
  • a stacked buffer layer formed of silicon nitride, the second buffer layer 50 is formed by chemical vapor deposition, for example, after the entire second buffer layer 50 is formed on the first metal layer 40, the second buffer layer 50 is patterned, and etched to form a plurality of first-type via holes 51 , and the plurality of first-type via holes 51 are correspondingly disposed on the first electrode 41 and the second electrode 42 of the first metal layer 40 .
  • high-temperature annealing treatment is performed on the second buffer layer 50 .
  • the high-temperature annealing treatment takes 2-3 hours at a temperature of 300-400° C.
  • the driving circuit layer of the display panel further includes an active layer 60 formed on the second buffer layer 50.
  • the active layer 60 includes a channel region and a non-channel region, and the non-channel region passes through the second buffer layer 50.
  • Several first-type via holes 51 on the second buffer layer 50 overlap with the first electrode 41 and the second electrode 42 of the first metal layer 40 respectively.
  • the material of the active layer 60 is, for example, Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO) and Indium Gallium Tin Oxide (Indium Gallium Tin Oxide, Any one or more of semiconductor metal oxides such as IGTO).
  • Metal oxide thin film transistors formed using semiconductor metal oxide materials such as IGZO, IGZTO, and IGTO have the characteristics of high field-effect mobility, simple preparation process, good uniformity of large-area deposition, fast response speed, and high transmittance in the visible light range. Applying it to display panels and Mini LED/Micro LED display devices can effectively solve the problem of large metal wire voltage power consumption due to the high current required by LED chips and the relatively high voltage of metal wires.
  • the semiconductor metal oxide is more sensitive to hydrogen in the film, in this embodiment, the light-absorbing layer 20 made of a thiophene-based organic semiconductor material with lower hydrogen content and higher chemical stability can ensure a good light-absorbing effect. At the same time, the situation of deterioration of the transistor caused by the introduction of the hydrogen element is avoided.
  • the thickness of the active layer is, for example, 300-500 angstroms.
  • the driving circuit layer of the display panel further includes, for example, a gate insulating layer 70 and a second metal layer 80 formed on the active layer 60, and the second metal layer 80 includes a groove with the active layer 60.
  • the channel region corresponds to the gate and the binding part.
  • the gate insulating layer 70 and the second metal layer 80 are specifically formed by continuous deposition. After the stacked structure of the gate insulating layer 70 and the second metal layer 80 is formed, for example, the gate self-alignment process is used to complete the gate. After the patterning of the pole insulating layer 70, the active layer 60 is treated with plasma, so that the non-channel region of the active layer 60 is conductorized to have the characteristics of a conductor.
  • the second metal layer 80 adopts, for example, a three-layer stacked structure of IZO/Mo/Cu, and the second metal layer 80 can reduce the reflectance of light on the surface of the second metal layer 80 .
  • the Mo metal layer is arranged between the IZO and the Cu metal layer, the IZO is arranged on the side of the Mo metal layer close to the gate insulating layer 70, and the Cu metal layer is arranged on a side of the Mo metal layer away from the gate insulating layer 70.
  • IZO is used as a low-reflection functional layer, which can reduce the light reflectance of light on the side of the second metal layer 80 close to the gate insulating layer 70.
  • the thickness of the IZO layer is controlled within a relatively thin range, for example, from 150 angstroms to 300 Angstroms.
  • the material of the gate insulating layer 70 can be a single-layer thin film formed of silicon oxide or a stacked structure formed of at least two materials of silicon oxide, silicon nitride, and aluminum oxide, and its thickness is between 2000 angstroms and 5000 angstroms.
  • the driving circuit layer of the display panel further includes, for example, a first passivation protection layer 90 formed on the second metal layer 80 .
  • the first passivation protection layer 90 is formed by, for example, chemical vapor deposition. After forming the entire first passivation protection layer 90 on the second metal layer 80, the first passivation protection layer 90 is patterned. processing and etching to form a plurality of second-type via holes 91 , and the plurality of second-type via holes 91 are formed on the non-channel region corresponding to the active layer 60 and on the bonding portion.
  • the first passivation protection layer 90 can be a single-layer thin film formed of silicon oxide or a stacked structure formed of at least two materials selected from silicon oxide, silicon nitride and aluminum oxide, with a thickness of 2000-5000 angstroms.
  • the display panel further includes, for example, an indium tin oxide (Indium Tin Oxide, ITO) layer 100 formed on the first passivation protection layer 90 of the driving circuit layer, and the indium tin oxide layer 100 is formed by physical vapor deposition, for example. way to obtain.
  • the indium tin oxide layer 100 includes a plurality of pixel electrodes located in the display area and thermal oxidation protective layer terminals located in the non-display area, and the plurality of pixel electrodes and thermal oxidation protective layer terminals are formed by patterning the indium tin oxide layer 100 .
  • the pixel electrode is electrically connected to the non-channel region of the active layer 60 through the second type via hole 91, and then electrically connected to the drain of the first metal layer 40 through the conductive non-channel region.
  • the protection layer terminal is electrically connected to the binding portion of the second metal layer 80 through the second type via hole 91 .
  • the display panel further includes, for example, a third metal layer 110 formed on the indium tin oxide layer 100, and the third metal layer 110 includes a plurality of LED binding terminals corresponding to the plurality of pixel electrodes.
  • the third metal layer 110 is obtained by, for example, physical vapor deposition.
  • the third metal layer 110 can be a single-layer metal layer formed by Cu, or a stacked metal layer formed by Cu/Mo.
  • the plurality of LEDs bound The terminals are obtained, for example, by wet etching the third metal layer 110 .
  • the display panel further includes, for example, a second passivation protection layer 120 and an LED light-shielding layer 130 stacked on the third metal layer 110 in sequence.
  • a black matrix (BM) or other high light-shielding photoresist material is used to pattern the LED light-shielding layer 130, and the LED light-shielding layer 130
  • the layer 130 includes a plurality of light-shielding patterns corresponding to the thin film transistors of the driving circuit layer, and the patterning of the second passivation protection layer 120 is completed by using the plurality of light-shielding patterns as a photomask.
  • the second passivation protection layer 120 may be a single-layer thin film formed of silicon oxide or a stacked structure formed of at least two materials among silicon oxide, silicon nitride and aluminum oxide, and its thickness is 2000-5000 angstroms.
  • the display panel further includes a plurality of light emitting units 140, such as LED driving chips, and each LED driving chip is correspondingly arranged on the LED binding terminal.
  • the display panel is formed, for example, by performing solder paste printing, anisotropic conductive film attachment and LED chip mass transfer process on the display panel.
  • this embodiment does not limit the size of the LED driver chip, which may be, for example, a Micro-LED driver chip, a Mini-LED driver chip or an LED chip on a common packaging substrate.
  • the light emitting unit 140 may also be, for example, an OLED light emitting unit.
  • the present application discloses a display panel and its manufacturing method.
  • the display panel and its manufacturing method are similar to the structure of the display panel disclosed in Embodiment 1 of the present application and the manufacturing method of the display panel disclosed in Embodiment 2.
  • this embodiment will not repeat the same parts, the difference is that the light-absorbing layer 20 in this embodiment is arranged on the base substrate 10 in a patterned manner, and the patterned light-absorbing layer 20 is placed on the first
  • the vertical projection on the metal layer 40 can at least cover the gap area between the first electrode 41 and the second electrode 42, so as to effectively prevent the thin film transistor from being directly or indirectly irradiated by the external ambient light to the channel region through the gap area.
  • the material of the light-absorbing layer 20 is saved, and the manufacturing cost is reduced.
  • the present application does not specifically limit the patterning method of the light absorbing layer 20.
  • the light absorbing layer 20 may also cover the first electrode 41 and the second electrode 41 while covering the gap region. Two electrodes 42 .
  • the present application provides a display panel and a manufacturing method thereof.
  • the display panel includes: a base substrate, a light-absorbing layer, and a driving circuit layer that are sequentially stacked, and the driving circuit layer includes a first metal layer and an active layer.
  • the first metal layer includes a first electrode and a second electrode arranged at intervals in the same layer, the active layer is arranged on the first metal layer and includes a channel region; wherein, the light-absorbing layer is on the base substrate
  • the projection of covers the projection of the gap region between the first electrode and the second electrode on the base substrate.
  • the display panel and its manufacturing method disclosed in the present application can absorb the ambient light directly or indirectly irradiated on the channel region through the gap between the first electrode and the second electrode by setting the light absorbing layer, so that the light placed on the first The channel region on the metal layer is well protected, greatly reducing the problem of performance degradation of the channel region of the active layer caused by external ambient light.

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Abstract

本申请提供一种显示面板及其制作方法，显示面板中的吸光层在衬底基板上的投影覆盖第一电极和第二电极之间的间隙区域在衬底基板上的投影，以吸收通过第一电极和第二电极之间的间隙而直接或间接照射到沟道区上的环境光，使设置于第一金属层上的沟道区被很好的保护，减少因外界环境光射入导致的有源层沟道区性能劣化的问题。

Description

显示面板及其制作方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及其制作方法。
 背景技术
小型发光二极管（Mini-Light Emitting Diode，Mini-LED）显示面板和微型发光二极管（Micro-Light Emitting Diode，Micro-LED）显示面板具有高对比度、高显色性能等可与有机发光二极管（Organic Light-Emitting Diode，OLED）显示面板相媲美的特点，成为各大面板厂商布局热点。
薄膜晶体管（Thin Film Transistor，TFT）是目前Mini-LED显示器、Micro-LED显示器、LCD显示器和OLED显示器中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管有源层的材料也具有多种，其中，金属氧化物薄膜晶体管（Metal Oxide TFT）具有场效应迁移率高（≥10cm2/V·s）、制备工艺简单、大面积沉积均匀性好、响应速度快及可见光范围内透过率高等特点，被认为是显示器朝着大尺寸及柔性化方向发展的最有潜力的背板技术。
现有的金属氧化物薄膜晶体管显示面板结构中，外界环境光能够被金属遮光层及栅极的反射而射入到由金属氧化物半导体材料形成的沟道区域，造成沟道区性能的劣化，影响金属氧化物薄膜晶体管显示面板的稳定性。
 技术问题
本申请实施例提供一种显示面板及其制作方法，可以解决目前的显示面板中的沟道区因受到外界环境光照影响，导致的沟道区性能劣化的问题。
 技术解决方案
一方面，本申请实施例提供一种显示面板，包括：依次层叠设置的衬底基板、吸光层和驱动电路层，所述驱动电路层包括第一金属层和有源层，所述第一金属层包括同层间隔设置的第一电极和第二电极，所述有源层设置于所述第一金属层上并包括沟道区；
其中，所述吸光层在所述衬底基板上的垂直投影覆盖所述第一电极和所述第二电极之间的间隙区域在所述衬底基板上的垂直投影。
可选的，所述有源层包括半导体金属氧化物材料形成的所述沟道区，所述第一电极为源极，所述第二电极为漏极，所述漏极在所述衬底基板上的垂直投影覆盖所述沟道区在所述衬底基板上的垂直投影。
可选的，所述吸光层包括噻吩系有机半导体材料。
可选的，所述吸光层和所述间隙区域在所述衬底基板上的垂直投影重合。
可选的，所述吸光层整面设置于所述衬底基板上。
可选的，所述驱动电路层还包括层叠设置于所述有源层上的栅极绝缘层和第二金属层，所述第二金属层包括栅极，所述栅极与所述沟道区对应设置；
其中，所述第二金属层由减反射层和叠置金属层构成，且所述减反射层位于所述叠置金属层和所述栅极绝缘层之间。
可选的，所述减反射层为氧化铟锌薄膜；所述叠置金属层为铜和钼形成的复合金属层。
可选的，所述有源层还包括非沟道区，所述非沟道区由半导体金属氧化物材料导体化形成，所述第一电极和所述第二电极通过所述非沟道区与所述沟道区电性连接，所述有源层的厚度为300埃到500埃。
可选的，所述吸光层和所述第一金属层之间还设置有第一缓冲层，所述第一缓冲层为氧化硅膜层。
另一方面，本申请实施例还公开了一种显示面板的制作方法，包括：
提供一衬底基板；
在衬底基板上形成吸光层，所述吸光层经烘烤热固化处理；
在所述吸光层上形成驱动电路层，所述驱动电路层包括第一金属层和有源层，所述第一金属层包括同层间隔设置的第一电极和第二电极，所述有源层设置于所述第一金属层上并包括沟道区；
其中，所述吸光层在所述衬底基板上的垂直投影覆盖所述第一电极和所述第二电极之间的间隙区域在所述衬底基板上的垂直投影。
 有益效果
本申请公开的显示面板及其制作方法，通过设置吸光层，能够吸收通过第一电极和第二电极之间的间隙而直接或间接照射到沟道区上的环境光，从而使设置于第一金属层上的沟道区被很好的保护，大大减少因外界环境光射入导致的有源层沟道区性能劣化的问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例一公开的一种显示面板的结构示意图。
图2a是本申请实施例二公开的一种显示面板的制作过程示意图之一。
图2b是本申请实施例二公开的一种显示面板的制作过程示意图之一。
图2c是本申请实施例二公开的一种显示面板的制作过程示意图之一。
图2d是本申请实施例二公开的一种显示面板的制作过程示意图之一。
图2e是本申请实施例二公开的一种显示面板的制作过程示意图之一。
图2f是本申请实施例二公开的一种显示面板的制作过程示意图之一。
图2g是本申请实施例二公开的一种显示面板的制作过程示意图之一。
图2h是本申请实施例二公开的一种显示面板的制作过程示意图之一。
图3是本申请实施例三公开的另一显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。以下分别进行详细说明，需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
本申请提供一种显示面板及其制作方法，该显示面板，包括：依次层叠设置的衬底基板、吸光层和驱动电路层，该驱动电路层包括第一金属层和有源层，该第一金属层包括同层间隔设置的第一电极和第二电极，该有源层设置于该第一金属层上并包括沟道区；其中，该吸光层在该衬底基板上的投影覆盖该第一电极和该第二电极之间的间隙区域在该衬底基板上的投影。本申请公开的显示面板及其制作方法，通过设置吸光层，能够吸收通过第一电极和第二电极之间的间隙而直接或间接照射到沟道区上的环境光，从而使设置于第一金属层上的沟道区被很好的保护，大大减少因外界环境光射入导致的有源层沟道区性能劣化的问题。
实施例一
图1是本申请实施例公开的一种显示面板的结构示意图，如图1所示，该显示面板包括：依次层叠设置的衬底基板10、吸光层20、第一缓冲层30和驱动电路层，该驱动电路层包括依次层叠设置的第一金属层40、第二缓冲层50、有源层60、栅极绝缘层70、第二金属层80、第一钝化保护层90、氧化铟锡层100、第三金属层110、第二钝化保护层120和LED遮光层130，该驱动电路层上设置有发光单元140。
本实施例中，该衬底基板10例如由玻璃、塑料、聚酰亚胺或其他无机或有机材料制成，其具体可以是平面或曲面的刚性基板，或可弯折的柔性基板。
本实施例中，该衬底基板10上设置有吸光层20和驱动电路层。该吸光层20例如整面设置于该衬底基板10上，该驱动电路层形成有薄膜晶体管结构，该薄膜晶体管结构包括间隔设置的源极和漏极以及位于源极和漏极上方的沟道区。该吸光层20在衬底基板10上的垂直投影覆盖该源极和漏极之间的间隙区域在该衬底基板10上的垂直投影，进而避免外界环境光通过该间隙区域照射到该沟道区引起的薄膜晶体管性能劣化的问题。
本实施例中，该吸光层20具体为P型有机半导体层，其例如由具有较强光响应特征的噻吩系有机半导体材料制成，以减少外界环境光对沟道区的影响。具体的，该吸光层可以是如5，11-双（三乙基硅乙炔基）邻二噻吩（DiF-TESADT）等较强光响应特征的噻吩系有机半导体。相比于非晶硅（a-Si）材料，DiF-TESADT的C-H键能为414KJ/mol，Si-H键能为377KJ/mol，具备氢含量更低和化学稳定性更高等优点，从而能够在保证良好吸光效果的同时很好的避免因氢离子引入导致的有源层60沟道区被污染的问题。需要说明的是，本实施例中的吸光层20的材料成分可以仅包含噻吩系有机半导体材料，还可以包含或掺杂除噻吩系有机半导体材料以外的其他成分的。
本实施例中，该驱动电路层包括第一金属层40和有源层60，该第一金属层40包括同层间隔设置的第一电极41和第二电极42，该第一电极41和第二电极42之间形成有间隙区域，该有源层60设置于该第一金属层40上，并包括该沟道区。该吸光层20在衬底基板10上的垂直投影覆盖该第一电极41和第二电极42之间的间隙区域在该衬底基板10上的垂直投影，进而避免外界环境光通过该间隙区域直接或间接照射到该沟道区引起的薄膜晶体管性能劣化的问题。
本实施例中，该第一金属层40例如为不透光的金属材料制成，并且，该第一金属层40中的第二电极42在衬底基板10上的垂直投影至少覆盖该薄膜晶体管结构中的沟道区在该衬底基板10上的垂直投影，从而使该第二电极42复用为遮光层，有效阻挡从衬底基板10一侧直接射入到该沟道区靠近该衬底基板10一侧的环境光，避免了在沟道区下方额外设置遮光层导致的制程工艺增加的问题。
本实施例中，该第一电极41例如为该薄膜晶体管结构中的源极，该第二电极42例如为该薄膜晶体管结构中的漏极，当然，本实施例并不对该第一电极41和第二电极42的电极类型进行限制，在本申请的其他实施例中，该第一电极41还可以是薄膜晶体管结构中的漏极，该第二电极42还可以是薄膜晶体管结构中的源极。
本实施例中，该薄膜晶体管结构的类型例如为金属氧化物薄膜晶体管，该有源层60例如包括由半导体金属氧化物材料形成的该沟道区，位于金属氧化物薄膜晶体管下方的整面化的吸光层20能够很好的吸收环境光，避免外界环境光通过该间隙区域直接或间接照射到该第有源层60的沟道区域。进一步地，该有源层60例如还包括非沟道区，该非沟道区由半导体金属氧化物材料导体化形成，该第一电极41和第二电极42通过该非沟道区与该沟道区电性连接，该有源层的厚度例如为300埃到500埃。当然，本实施例并不对该薄膜晶体管结构的类型进行限制，在本申请的其他实施例中，该驱动电路层中的薄膜晶体管结构的类型还可以是非晶硅薄膜晶体管、低温多晶硅薄膜晶体管，该薄膜晶体管结构的类型可以是一种或多种，例如该驱动电路层可以同时包括低温多晶硅薄膜晶体管和金属氧化物薄膜晶体管。
本实施例中，该驱动电路层还包括层叠设置于有源层60上的栅极绝缘层70和第二金属层80，该第二金属层80包括薄膜晶体管结构中的栅极81和用于连接外部电信号的绑定部82。即该薄膜晶体管结构为栅极81位于有源层60上方的顶栅（TOP Gate）结构，该栅极81与该薄膜晶体管的沟道区对应设置。在该薄膜晶体管结构中，由于沟道区的上方和下方分别设置有栅极81和第二电极42，在未设置该吸光层20时，该衬底基板10远离该沟道区一侧的环境光能够通过第一电极41和第二电极42之间的间隙区域照射到该栅极81上，再经过栅极81对环境光的反射穿过该沟道区照射到该第二电极42上，由此，射入到栅极81和第二电极42之间的环境光会经过多次反射重复照射该沟道区，因此，通过设置吸光层20能够很好的避免该衬底基板10远离该沟道区一侧的环境光通过第一电极41和第二电极42之间的间隙区域直接或间接照射该沟道区。
本实施例中，该第二金属层80包括减反射层和叠置金属层，该减反射层位于叠置金属层和栅极绝缘层70之间。该减反射层能够减少射入到驱动电路层中的环境光在该栅极81靠近该沟道区的表面上的光反射，进一步减少环境光照射沟道区引起的薄膜晶体管性能劣化的问题，需要说明的是该射入到驱动电路层中的环境光包括从该显示面板两侧射入的环境光。
本实施例中，该减反射层为氧化铟锌薄膜；该叠置金属层为铜和钼形成的复合金属层。
本实施例中，该吸光层20和该第一金属层40之间例如还设置有第一缓冲层30，其材料例如为性能稳定的氧化硅，由于该吸光层20为有机膜层，该第一缓冲层30可以避免后续制程中直接形成在该吸光层20上的膜层与该吸光层20应力不匹配而产生剥离脱落的情形。
本实施例中，该第一金属层40和该有源层60之间还设置有第二缓冲层50，该第二缓冲层50可以是氧化硅形成的单层缓冲层或氧化硅与氮化硅形成的叠置缓冲层，该第二缓冲层50对应第一电极41和第二电极42的位置上形成有第一类过孔51，该有源层60填充于该第一类过孔51中，并与该第一电极41和第二电极42相接触，以实现电连接。
本实施例中，该第二金属层80上例如还层叠设置有第一钝化保护层90和氧化铟锡层100，该第一钝化保护层90在与该第二电极42电性连接的非沟道区上以及对应该绑定部82的位置上形成有第二类过孔91，该氧化铟锡层100包括位于显示区的多个像素电极和位于非显示区的热氧化保护层端子，该多个像素电极以及热氧化保护层端子通过对氧化铟锡层100的图案化所形成。该像素电极通过该第二类过孔91与该有源层60的非沟道区电连接，进而通过该导体化的非沟道区与该第一金属层40的第二电极42电连接，该热氧化保护层端子通过该第二类过孔91与该第二金属层80的绑定部电连接。
本实施例中，该氧化铟锡层100上还依次层叠设置有第三金属层110、第二钝化保护层120和LED遮光层130，其中，该第三金属层110包括与该多个像素电极对应设置的多个LED绑定端子，该LED绑定端子与发光单元140电性连接；该LED遮光层130设置于该薄膜晶体管结构的上方，用于遮挡该沟道区远离该衬底基板10一侧的环境光。
实施例二
本实施例公开了一种显示面板的制作方法，以制作形成实施例一中的显示面板。具体的，图2a是本申请实施例公开的一种显示面板的制作过程示意图之一，其具体示出了显示面板的衬底基板、吸光层、第一缓冲层以及第一金属层的膜层结构。结合图1和图2a所示，提供一衬底基板10，该衬底基板10例如由玻璃、塑料、聚酰亚胺或其他无机或有机材料制成，其具体可以是平面或曲面的刚性基板，或可弯折的柔性基板。
该吸光层20以整面设置的方式设置于该衬底基板10上，从而减少或消除自衬底基板10一侧的环境光直接照射到有源层的沟道区或经过栅极与第一金属层40的多次反射导致的沟道区光照增多的现象，防止金属氧化物薄膜晶体管性能劣化。优选的，该吸光层20具体可以通过整面涂布的方式形成于该衬底基板10上，并经过紫外照射固化和高温热烘烤处理后形成稳定形态的吸光层20。在本申请的其他实施例中，该吸光层20还可以采用薄膜沉积或其他方式形成于衬底基板10上。本实施例设置整面性的吸光层20，能够更好的吸收来自显示面板两侧的环境光，并减少或消除自衬底基板10一侧射入到第二金属层80的栅极的环境光经过栅极与第一金属层40的多次反射导致的沟道区光照增多的现象，同时，由于无需图案化制程，还能够减少光罩次数，降低工艺成本。该吸光层20的厚度例如为1~3微米，热烘烤温度为200~250℃，热烘烤时长1~2h，在经过此烘烤制程后的上述厚度范围内的吸光层20具备优良的成膜性能和光学性能。
该显示面板例如还包括第一缓冲层30，该第一缓冲层30设置在该吸光层20和驱动电路层之间，其材料例如为性能稳定的氧化硅，由于该吸光层20为有机膜层，该第一缓冲层30可以避免后续制程中直接形成在该吸光层20上的膜层与该吸光层20应力不匹配而产生剥离脱落的情形。具体的，该第一缓冲层30例如是在该吸光层20经过高温热固化处理后，在该吸光层20上采用化学气象沉积（CVD）的方式形成的氧化硅膜层。优选的，该第一缓冲层30整面设置在该吸光层20上。
该显示面板的驱动电路层例如包括不透光的第一金属层40，该第一金属层40包括第一电极41和第二电极42。该第一金属层40中的第二电极42在衬底基板10上的垂直投影至少覆盖该薄膜晶体管结构中的沟道区在该衬底基板10上的垂直投影，从而使该第二电极42复用为遮光层，有效阻挡从衬底基板10一侧直接射入到该沟道区靠近该衬底基板10一侧的环境光，避免了在沟道区下方额外设置遮光层导致的制程工艺增加的问题。该第一金属层40例如采用物理气相溅射沉积（PVD）的方式形成在该第一缓冲层30上，该第一金属层40可以是钼（Mo）形成的单层金属层或钼（Mo）/铜（Cu）形成的叠置金属层，该第一金属层40经过湿蚀刻制程进行图案化，进而形成该第一电极41和第二电极42，该湿蚀刻制程例如采用双氧水（H2O2）系药液作为蚀刻剂，该第一金属层40的厚度例如在5000埃-8000埃。在其他实施例中，该第一金属层40还包括由IZO形成的减反射层，该减反射层例如叠加设置在该钼（Mo）形成的单层金属层或钼（Mo）/铜（Cu）形成的叠置金属层之上，以减少直接或间接照射到该第一金属层上并产生反射的环境光的量。
参照图2b，该显示面板的驱动电路层例如还包括形成在该第一金属层40上的第二缓冲层50，该第二缓冲层50可以是氧化硅形成的单层缓冲层或氧化硅与氮化硅形成的叠置缓冲层，该第二缓冲层50例如采用化学气象沉积的方式形成，在该第一金属层40上形成整面的第二缓冲层50后，对该第二缓冲层50进行图案化处理，并蚀刻形成若干第一类过孔51，该若干第一类过孔51对应设置在该第一金属层40的第一电极41和第二电极42上。形成该若干第一类过孔51后对该第二缓冲层50进行高温退火处理，高温退火处理时长在2-3小时，温度为300-400℃。
参照图2c，该显示面板的驱动电路层例如还包括形成在该第二缓冲层50上的有源层60，该有源层60包括沟道区和非沟道区，非沟道区通过第二缓冲层50上的若干第一类过孔51分别与第一金属层40的第一电极41和第二电极42搭接。该有源层60的材料例如为铟镓锌氧化物（Indium Gallium Zinc Oxide，IGZO）、铟镓锌锡氧化物（Indium Gallium Zinc Tin Oxide，IGZTO）以及铟镓锡氧化物（Indium Gallium Tin Oxide，IGTO）等半导体金属氧化物中的任意一种或多种。使用IGZO、IGZTO、IGTO等半导体金属氧化物材料形成的金属氧化物薄膜晶体管具有场效应迁移率高、制备工艺简单、大面积沉积均匀性好、响应速度快及可见光范围内透过率高等特点，将其应用于显示面板及Mini LED/Micro LED显示装置中，能够有效解决因LED芯片所需电流较高，金属走线电压相对较高，导致的金属线电压功耗较大的问题。同时，由于半导体金属氧化物对薄膜中氢较为敏感，本实施例中通过采用氢含量更低和化学稳定性更高的噻吩系有机半导体材料制成的吸光层20，能够在保证良好吸光效果的同时，避免氢元素的引入导致的晶体管劣化的情形。该有源层的厚度例如在300埃-500埃。
参照图2d，该显示面板的驱动电路层例如还包括形成在该有源层60上的栅极绝缘层70和第二金属层80，该第二金属层80包括与该有源层60的沟道区对应设置的栅极以及绑定部。该栅极绝缘层70和该第二金属层80具体通过连续沉积形成，在形成该栅极绝缘层70和第二金属层80的叠置结构后，例如采用栅极自对准工艺完成该栅极绝缘层70的图形化，随后采用等离子体处理该有源层60，使该有源层60的非沟道区被导体化而具有导体的特性。该第二金属层80例如采用IZO/Mo/Cu的三层叠置结构，该第二金属层80能够降低光线在该第二金属层80表面的反射率。具体的，Mo金属层设置在IZO和Cu金属层之间，IZO设置在Mo金属层靠近该栅极绝缘层70的一侧，Cu金属层设置在Mo金属层远离该栅极绝缘层70的一侧，IZO作为低反射功能层，能够降低光线在该第二金属层80靠近栅极绝缘层70一侧的光反射率，IZO层的厚度控制在相对较薄的范围内，例如在150埃到300埃。该栅极绝缘层70材质可以是氧化硅形成的单层薄膜或氧化硅、氮化硅及三氧化二铝中的至少两种材质形成的叠置结构，其厚度在2000埃-5000埃。
参照图2e，该显示面板的驱动电路层例如还包括形成在该第二金属层80上的第一钝化保护层90。该第一钝化保护层90例如通过化学气象沉积的方式形成，在该第二金属层80上形成整面的第一钝化保护层90后，对该第一钝化保护层90进行图案化处理，蚀刻形成若干第二类过孔91，该若干第二类过孔91形成在对应该有源层60的非沟道区域上以及该绑定部上。该第一钝化保护层90可以是氧化硅形成的单层薄膜或氧化硅、氮化硅及三氧化二铝中的至少两种材质形成的叠置结构，其厚度在2000埃-5000埃。
参照图2f，该显示面板例如还包括形成在该驱动电路层的第一钝化保护层90上的氧化铟锡（Indium Tin Oxide，ITO）层100，该氧化铟锡层100例如通过物理气象沉积的方式获得。该氧化铟锡层100包括位于显示区的多个像素电极和位于非显示区的热氧化保护层端子，该多个像素电极以及热氧化保护层端子通过对氧化铟锡层100的图案化所形成。该像素电极通过第二类过孔91与该有源层60的非沟道区电连接，进而通过该导体化的非沟道区与该第一金属层40的漏极电连接，该热氧化保护层端子通过第二类过孔91与该第二金属层80的绑定部电连接。
参照图2g，该显示面板例如还包括形成在该氧化铟锡层100上的第三金属层110，该第三金属层110包括与该多个像素电极对应设置的多个LED绑定端子。该第三金属层110例如通过物理气象沉积的方式获得，该第三金属层110可以是Cu形成的单层金属层，也可以是Cu/Mo形成的叠置金属层，该多个LED绑定端子例如通过对该第三金属层110的湿蚀刻制程获得。
参照图2h，该显示面板例如还包括依次层叠设置在该第三金属层110上的第二钝化保护层120和LED遮光层130。具体的，在该第二钝化保护层120整面设置于该第三金属层110上后，利用黑色矩阵（BM）或其他高遮光的光阻材料图形化形成LED遮光层130，该LED遮光层130包括对应该驱动电路层的薄膜晶体管设置的多个遮光图案，并以该多个遮光图案作为光罩完成对该第二钝化保护层120的图形化。该第二钝化保护层120可以是氧化硅形成的单层薄膜或氧化硅、氮化硅及三氧化二铝中的至少两种材质形成的叠置结构，其厚度在2000埃-5000埃。
本实施例中，该显示面板还包括多个发光单元140，该发光单元140例如为LED驱动芯片，每个LED驱动芯片对应设置在该LED绑定端子上。该显示面板例如通过在该显示面板上进行锡膏印刷、异方性导电膜贴附及LED芯片巨量转移制程后所形成。当然，本实施例对该LED驱动芯片的尺寸不作限制，其例如可以是Micro-LED驱动芯片、Mini-LED驱动芯片或普通封装基板的LED芯片。在其他实施例中，该发光单元140例如还可以是OLED发光单元。
实施例3
参照图3，本申请公开了一种显示面板及该显示面板的制作方法，该显示面板及其制作犯法与本申请实施例一公开的显示面板的结构和实施例二公开的显示面板的制作方法相类似，本实施例对于相同的部分不再赘述，不同的是，本实施例中的吸光层20采用图案化的方式设置于衬底基板10上，图案化的该吸光层20在该第一金属层40上的垂直投影可以至少覆盖该第一电极41和该第二电极42之间的间隔区域，以在有效避免外界环境光通过该间隙区域直接或间接照射到沟道区引起的薄膜晶体管性能劣化的问题的同时，节省吸光层20的材料，降低生产制造成本。当然，本申请对该吸光层20的图案化方式并不作具体限定，在本申请的其他实施例中，该吸光层20例如还可以在覆盖该间隙区域的同时，覆盖该第一电极41和第二电极42。
综上所述，本申请提供一种显示面板及其制作方法，该显示面板，包括：依次层叠设置的衬底基板、吸光层和驱动电路层，该驱动电路层包括第一金属层和有源层，该第一金属层包括同层间隔设置的第一电极和第二电极，该有源层设置于该第一金属层上并包括沟道区；其中，该吸光层在该衬底基板上的投影覆盖该第一电极和该第二电极之间的间隙区域在该衬底基板上的投影。本申请公开的显示面板及其制作方法，通过设置吸光层，能够吸收通过第一电极和第二电极之间的间隙而直接或间接照射到沟道区上的环境光，从而使设置于第一金属层上的沟道区被很好的保护，大大减少因外界环境光射入导致的有源层沟道区性能劣化的问题。
以上对本申请实施例所提供的一种显示面板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，包括：依次层叠设置的衬底基板、吸光层和驱动电路层，所述驱动电路层包括第一金属层和有源层，所述第一金属层包括同层间隔设置的第一电极和第二电极，所述有源层设置于所述第一金属层上并包括沟道区；
    其中，所述吸光层在所述衬底基板上的垂直投影覆盖所述第一电极和所述第二电极之间的间隙区域在所述衬底基板上的垂直投影。
  2. 根据权利要求1所述的显示面板，其中，所述有源层包括半导体金属氧化物材料形成的所述沟道区，所述第一电极为源极，所述第二电极为漏极，所述漏极在所述衬底基板上的垂直投影覆盖所述沟道区在所述衬底基板上的垂直投影。
  3. 根据权利要求2所述的显示面板，其中，所述吸光层包括噻吩系有机半导体材料。
  4. 根据权利要求2所述的显示面板，其中，所述吸光层和所述间隙区域在所述衬底基板上的垂直投影重合。
  5. 根据权利要求2所述的显示面板，其中，所述吸光层整面设置于所述衬底基板上。
  6. 根据权利要求2所述的显示面板，其中，所述驱动电路层还包括层叠设置于所述有源层上的栅极绝缘层和第二金属层，所述第二金属层包括栅极，所述栅极与所述沟道区对应设置；
    其中，所述第二金属层由减反射层和叠置金属层构成，且所述减反射层位于所述叠置金属层和所述栅极绝缘层之间。
  7. 根据权利要求6所述的显示面板，其中，所述减反射层为氧化铟锌薄膜；所述叠置金属层为铜和钼形成的复合金属层。
  8. 根据权利要求2所述的显示面板，其中，所述有源层还包括非沟道区，所述非沟道区由半导体金属氧化物材料导体化形成，所述第一电极和所述第二电极通过所述非沟道区与所述沟道区电性连接，所述有源层的厚度为300埃到500埃。
  9. 根据权利要求1所述的显示面板，其中，所述吸光层和所述第一金属层之间还设置有第一缓冲层，所述第一缓冲层为氧化硅膜层。
  10. 根据权利要求1所述的显示面板，其中，所述吸光层的厚度为1至3微米。
  11. 根据权利要求10所述的显示面板，其中，所述有源层包括半导体金属氧化物材料形成的所述沟道区，所述第一电极为源极，所述第二电极为漏极，所述漏极在所述衬底基板上的垂直投影覆盖所述沟道区在所述衬底基板上的垂直投影。
  12. 根据权利要求11所述的显示面板，其中，所述吸光层包括噻吩系有机半导体材料。
  13. 根据权利要求11所述的显示面板，其中，所述吸光层和所述间隙区域在所述衬底基板上的垂直投影重合。
  14. 根据权利要求11所述的显示面板，其中，所述吸光层整面设置于所述衬底基板上。
  15. 根据权利要求11所述的显示面板，其中，所述驱动电路层还包括层叠设置于所述有源层上的栅极绝缘层和第二金属层，所述第二金属层包括栅极，所述栅极与所述沟道区对应设置；
    其中，所述第二金属层由减反射层和叠置金属层构成，且所述减反射层位于所述叠置金属层和所述栅极绝缘层之间。
  16. 根据权利要求15所述的显示面板，其中，所述减反射层为氧化铟锌薄膜；所述叠置金属层为铜和钼形成的复合金属层。
  17. 根据权利要求11所述的显示面板，其中，所述有源层还包括非沟道区，所述非沟道区由半导体金属氧化物材料导体化形成，所述第一电极和所述第二电极通过所述非沟道区与所述沟道区电性连接，所述有源层的厚度为300埃到500埃。
  18. 根据权利要求10所述的显示面板，其中，所述吸光层和所述第一金属层之间还设置有第一缓冲层，所述第一缓冲层为氧化硅膜层。
  19. 一种显示面板的制作方法，其中，包括：
    提供一衬底基板；
    在衬底基板上形成吸光层，所述吸光层经烘烤热固化处理；
    在所述吸光层上形成驱动电路层，所述驱动电路层包括第一金属层和有源层，所述第一金属层包括同层间隔设置的第一电极和第二电极，所述有源层设置于所述第一金属层上并包括沟道区；
    其中，所述吸光层在所述衬底基板上的垂直投影覆盖所述第一电极和所述第二电极之间的间隙区域在所述衬底基板上的垂直投影。
  20. 根据权利要求19所述的显示面板的制作方法，其中，所述烘烤热固化处理包括紫外照射固化处理和热烘烤处理，所述热烘烤处理的温度为200至250摄氏度，热烘烤时长为1至2小时。
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