WO2022246599A1 - 封装结构及其制造方法、电子设备 - Google Patents

封装结构及其制造方法、电子设备 Download PDF

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Publication number
WO2022246599A1
WO2022246599A1 PCT/CN2021/095508 CN2021095508W WO2022246599A1 WO 2022246599 A1 WO2022246599 A1 WO 2022246599A1 CN 2021095508 W CN2021095508 W CN 2021095508W WO 2022246599 A1 WO2022246599 A1 WO 2022246599A1
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WO
WIPO (PCT)
Prior art keywords
layer
connection
connection layer
substrate
plastic
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PCT/CN2021/095508
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English (en)
French (fr)
Inventor
胡骁
蒋尚轩
赵南
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华为技术有限公司
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Priority to PCT/CN2021/095508 priority Critical patent/WO2022246599A1/zh
Priority to CN202180088468.9A priority patent/CN116802794A/zh
Publication of WO2022246599A1 publication Critical patent/WO2022246599A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Definitions

  • the present application relates to the technical field of electronic packaging, in particular to a packaging structure, a manufacturing method thereof, and electronic equipment.
  • Chips and other packaging structures need to be heterogeneously integrated through high-density interconnect lines.
  • Electronic packaging technology has brought huge challenges, and packaging costs have risen rapidly.
  • the size of the packaging structure continues to rise while the process node (also called feature size) of the integrated circuit technique (integrated circuit technique) decreases.
  • the packaging structure 1 shown in FIG. 1 is manufactured using fan-out unit (Fan out unit) technology, and the number of redistribution layers (Redistribution Layer, RDL) is limited to 5 layers due to cost and yield constraints.
  • an embodiment of the present application provides a package structure, the package structure comprising: a first plastic encapsulation layer, at least two dies, a plurality of connection layers and a first filling layer, each of the connection layers includes A substrate with a plurality of via holes, and a redistribution layer covering the first surface of the substrate and electrically connected to the plurality of via holes, the substrate has the first surface and the second surface oppositely arranged , the substrate is a glass substrate, and the plurality of connection layers include a first connection layer and a second connection layer;
  • the first plastic encapsulation layer is used to at least partially wrap each of the dies, and a plurality of first bumps of each of the dies are exposed from the first plastic encapsulation layer;
  • the first connection layer is disposed on a side of the first plastic encapsulation layer that exposes a plurality of first bumps of each die, and the redistribution layer in the first connection layer is close to the first plastic encapsulation layer , and the multiple first bumps of each die are electrically connected to the wiring of the redistribution layer in the first connection layer, and the first filling layer is used to fill the first connection layer and each of the first connection layers the space between the dies;
  • the second connection layer is disposed on the second surface of the substrate in the first connection layer, the redistribution layer in the second connection layer is close to the first connection layer, and the substrate in the first connection layer is The plurality of via holes are electrically connected to the wiring in the redistribution layer in the second connection layer.
  • the number of layers of the redistribution layer is limited to less than 5 layers due to the limitation of cost and yield.
  • the redistribution layer and multiple connection layers of the glass substrate replace the redistribution layer in the related art, and the number of connection layers in the packaging structure can be set according to the redistribution requirements, and the cost and yield are no longer limited, that is, Under the action of the connection layer including the glass substrate, the number of rewiring layers in the packaging structure is no longer limited, and can meet the ever-increasing demand for high-density interconnection of multiple bare chips in the packaging structure.
  • the packaging structure uses a glass substrate instead of the high-cost packaging substrate in the related art, the cost of the packaging structure is significantly reduced.
  • including multiple glass substrates in the packaging structure can improve the reliability of the packaging structure, reduce the reliability risk of welding between the packaging structure and the PCB, and improve the adaptability between the packaging structure and the PCB.
  • the multiple connection layers further include: a third connection layer disposed on the second surface of the substrate in the second connection layer, and the redistribution layer in the third connection layer is close to The second connection layer, and the wiring of the redistribution layer in the third connection layer are electrically connected to a plurality of via holes on the substrate in the second connection layer.
  • the number of connection layers in the package structure can be set according to needs, so as to meet the wiring requirements of different package structures.
  • the encapsulation structure further includes a second filling layer and/or a third filling layer,
  • the second filling layer is used to fill the space between the first connection layer and the second connection layer;
  • the third filling layer is used to fill the space between the second connection layer and the third connection layer.
  • filling between the first connection layer and the second connection layer, and between the second connection layer and the third connection layer can improve the reliability and stability of the electrical connection between the connection layers, and enhance the drop resistance of the packaging structure. Performance, thereby improving the reliability and structural stability of the package structure.
  • the first plastic encapsulation layer is also used to wrap the first filling layer and the first connection layer, and the second surface of the substrate in the first connection layer is exposed. Describe the first plastic seal layer.
  • the die, the first filling layer, and the first connection layer can be plastic-sealed together, which can enhance the reliability and structural stability of the electrical connection between the die and the first connection layer, thereby improving the reliability and structural stability of the packaging structure. stability.
  • the packaging structure further includes: a second plastic encapsulation layer and/or a third plastic encapsulation layer;
  • the second plastic sealing layer is at least used to wrap the second connection layer and the first plastic sealing layer, and the second surface of the substrate in the second connection layer is exposed to the second plastic sealing layer;
  • the third plastic sealing layer is at least used to wrap the third connecting layer, the second connecting layer and the first plastic sealing layer, and the second surface of the substrate in the third connecting layer is exposed to the The third plastic sealing layer.
  • the reliability and structural stability of the packaging structure can be further enhanced by increasing the arrangement of the second molding layer and/or the third molding layer to mold different parts together.
  • the second surface of at least one die is exposed to the packaging structure, each of the die has a first surface and a second surface opposite to each other, and each of the The first surface of the die is provided with a plurality of first bumps.
  • the thickness of the packaging structure can be reduced, and the size of the packaging structure can be reduced, so that it can be installed in an electronic device with a smaller given space, and the application range of the packaging structure can be expanded.
  • the thermal expansion coefficients of the substrates in each of the connection layers are different, and the thermal expansion coefficients of the substrates in each of the connection layers range from close to The order of farthest increases in order.
  • the CTE of the substrate in the first connection layer close to the die can be set close to the CTE of the die, which solves the reliability stress problem of the packaging structure itself
  • the CTE of the substrate in the target connection layer close to the PCB can be set close to the CTE of the PCB , which solves the reliability risk of soldering between the package structure and the PCB, and improves the adaptability between the package structure and the PCB.
  • the CTE of the substrate in the connection layer is continuously increasing between the die and the PCB, which further improves the reliability of the package structure itself, reduces the reliability risk of welding between the package structure and the PCB, and improves the reliability of the package structure and the PCB. adaptability.
  • embodiments of the present application provide a method for manufacturing a packaging structure, including:
  • a plurality of via holes are respectively formed on the provided plurality of substrates, each of the substrates has a first surface and a second surface opposite to each other, and each of the substrates is a glass substrate;
  • a rewiring layer electrically connected to a plurality of via holes on the substrate is respectively formed on the first surface of each of the substrates to obtain a plurality of connection layers, and each of the connection layers includes a rewiring layer and the rewiring layer.
  • a substrate covered by layers, the plurality of connection layers comprising a first connection layer and a second connection layer;
  • the second connection layer is installed on the second surface of the substrate in the first connection layer, the redistribution layer in the second connection layer is close to the first connection layer, and the redistribution layer in the second connection layer is
  • the wiring in the wiring layer is electrically connected to a plurality of via holes on the substrate in the first connection layer.
  • the packaging structure can be manufactured using a simple and easy-to-implement processing technology, and compared with the rewiring layer of the packaging structure prepared on the packaging substrate in the technology, the number of layers of the rewiring layer is limited by cost and yield. Restricted within 5 layers, this application replaces the redistribution layers in the related art with multiple connection layers including redistribution layers and glass substrates in the package structure, so that the layers of the connection layers in the package structure can be adjusted according to the redistribution needs.
  • the cost and yield are no longer limited, that is, under the action of the connection layer including the glass substrate, the number of rewiring layers in the packaging structure is no longer limited, and it can meet the ever-increasing packaging structure.
  • the packaging structure uses a glass substrate instead of the high-cost packaging substrate in the related art, the cost of the packaging structure is significantly reduced.
  • including multiple glass substrates in the packaging structure can improve the reliability of the packaging structure, reduce the reliability risk of welding between the packaging structure and the PCB, and improve the adaptability between the packaging structure and the PCB.
  • the multiple connection layers further include a third connection layer
  • the method further includes:
  • the redistribution layer in the third connection layer is close to the second connection layer, and the redistribution layer in the third connection layer
  • the wiring of the wiring layer is electrically connected to a plurality of via holes on the substrate in the second connection layer. In this way, the number of connection layers in the package structure can be set according to needs, so as to meet the wiring requirements of different package structures.
  • the first plastic encapsulation layer is also used to wrap the first filling layer and the first connection layer, and the second surface of the substrate in the first connection layer is exposed out the first plastic layer.
  • the die, the first filling layer, and the first connection layer can be plastic-sealed together, which can enhance the reliability and stability of the electrical connection between the die and the first connection layer, thereby improving the reliability and structural stability of the packaging structure sex.
  • the method further includes at least one of the following operations:
  • Plastic sealing at least the second connection layer and the first plastic sealing layer to form a second plastic sealing layer for wrapping at least the second connection layer and the first plastic sealing layer, and in the second connection layer
  • the second surface of the substrate is exposed to the second plastic encapsulation layer
  • At least the third connection layer, the second connection layer and the first plastic sealing layer are plastic-sealed to form at least the third connection layer, the second connection layer and the first plastic sealing layer
  • the third plastic encapsulation layer, and the second surface of the substrate in the third connection layer is exposed to the third plastic encapsulation layer.
  • plastic encapsulation can be performed to form the second plastic encapsulation layer and/or the third plastic encapsulation layer, which can further enhance the reliability and structural stability of the packaging structure.
  • the method further includes at least one of the following operations:
  • the second plastic sealing layer is also used to wrap the second filling layer
  • the space between the second connection layer and the third connection layer is filled to form a third filling layer, and the third plastic sealing layer is also used to wrap the third filling layer.
  • filling between the first connection layer and the second connection layer, and between the second connection layer and the third connection layer can improve the reliability and stability of the electrical connection between the connection layers, and enhance the drop resistance of the packaging structure. performance, thereby improving the reliability and stability of the package structure.
  • the method further includes:
  • Thinning treatment is performed on at least one of the first plastic sealing layer, the second plastic sealing layer and the third plastic sealing layer.
  • the thermal expansion coefficients of the substrates in each of the connection layers are different, and the thermal expansion coefficients of the substrates in each of the connection layers range from close to The order of farthest increases in order.
  • the CTE of the substrate in the first connection layer close to the die can be set close to the CTE of the die, which solves the reliability stress problem of the packaging structure itself
  • the CTE of the substrate in the target connection layer close to the PCB can be set close to the CTE of the PCB , which solves the reliability risk of soldering between the package structure and the PCB, and improves the adaptability between the package structure and the PCB.
  • the CTE of the substrate in the connection layer is continuously increasing between the die and the PCB, which further improves the reliability of the package structure itself, reduces the reliability risk of welding between the package structure and the PCB, and improves the reliability of the package structure and the PCB. adaptability.
  • an embodiment of the present application provides a packaging structure
  • the packaging structure includes a fourth plastic packaging layer, at least two bare chips, a first rewiring layer, at least one connection layer and a fourth filling layer
  • each The connection layer includes a substrate with a plurality of via holes, and a redistribution layer covering the first surface of the substrate and electrically connected to the plurality of via holes, and the substrate has the first A surface and a second surface, each of the substrates is a glass substrate, and the at least one connection layer includes a fourth connection layer;
  • the fourth plastic encapsulation layer is used to at least partially wrap each of the dies, and the plurality of first bumps of each of the dies are exposed from the fourth plastic encapsulation layer;
  • the first redistribution layer covers a side of the fourth plastic encapsulation layer that exposes a plurality of first bumps of each die, and the wiring in the first redistribution layer is connected to each of the a plurality of first bumps of the die are electrically connected;
  • the fourth connection layer is disposed on the side of the first redistribution layer away from each of the dies, the redistribution layer in the fourth connection layer is close to the first redistribution layer, and the fourth The wiring of the redistribution layer in the connection layer is electrically connected to the wiring of the first redistribution layer;
  • the fourth filling layer is used to fill the space between the fourth connection layer and the first redistribution layer.
  • the number of layers of the redistribution layer is limited to less than 5 layers due to the limitation of cost and yield.
  • the redistribution layer and multiple connection layers of the glass substrate replace the redistribution layer in the related art, and the number of connection layers in the packaging structure can be set according to the redistribution requirements, and the cost and yield are no longer limited, that is, Under the action of the connecting layer including the glass substrate, the number of layers of the rewiring layer in the packaging structure is no longer limited, which can meet the ever-increasing demand for high-density interconnection of multiple bare chips in the packaging structure.
  • the packaging structure uses a glass substrate instead of the high-cost packaging substrate in the related art, the cost of the packaging structure is significantly reduced.
  • including multiple glass substrates in the packaging structure can improve the reliability of the packaging structure, and can also reduce the reliability risk of welding between the packaging structure and the PCB, and improve the adaptability between the packaging structure and the PCB.
  • the first redistribution layer is directly provided on the side of each die with multiple first bumps, since the first redistribution layer can be directly prepared on the side of each die with the first bumps, not only can further improve the performance of each die
  • the reliability of the connection between the chip and the first rewiring layer improves the overall reliability of the packaging structure, and can also reduce the thickness of the packaging structure.
  • the at least one connection layer further includes:
  • the fifth connection layer is arranged on the second surface of the substrate in the fourth connection layer, the redistribution layer in the fifth connection layer is close to the fourth connection layer, and the redistribution layer in the fifth connection layer
  • the wiring is electrically connected to a plurality of via holes on the substrate in the fourth connection layer. In this way, the number of connection layers in the package structure can be set according to needs, so as to meet the wiring requirements of different package structures.
  • the encapsulation structure further includes: a fifth filling layer, where the fifth filling layer is used to fill a space between the fourth connection layer and the fifth connection layer.
  • the fifth filling layer is used to fill a space between the fourth connection layer and the fifth connection layer.
  • the packaging structure further includes: a fifth plastic encapsulation layer and/or a sixth plastic encapsulation layer;
  • the fifth plastic encapsulation layer is at least used to wrap the fourth connection layer, the fourth filling layer, the first redistribution layer and the fourth plastic encapsulation layer, and the first part of the substrate in the fourth connection layer
  • the fifth plastic sealing layer is exposed on two sides;
  • the sixth plastic encapsulation layer is at least used to wrap the fifth connection layer, the fourth connection layer, the fourth filling layer, the first redistribution layer and the fourth plastic encapsulation layer, and the first The second surface of the substrate in the fifth connection layer is exposed to the sixth plastic encapsulation layer.
  • the reliability and structural stability of the packaging structure can be further enhanced by adding the arrangement of the fifth plastic sealing layer and/or the sixth plastic sealing layer to plastic seal different parts together.
  • the second surface of at least one die is exposed to the packaging structure, each of the die has a first surface and a second surface opposite to each other, and each of the The first surface of the die is provided with a plurality of first bumps.
  • the thickness of the packaging structure can be reduced, and the size of the packaging structure can be reduced, so that it can be installed in an electronic device with a smaller given space, and the application range of the packaging structure can be expanded.
  • the thermal expansion coefficients of the substrates in each of the connection layers are different, and the thermal expansion coefficients of the substrates in each of the connection layers range from close to The order of farthest increases in order.
  • the CTE of the substrate in the first connection layer close to the die can be set close to the CTE of the die, which solves the reliability stress problem of the packaging structure itself
  • the CTE of the substrate in the target connection layer close to the PCB can be set close to the CTE of the PCB , which solves the reliability risk of soldering between the package structure and the PCB, and improves the adaptability between the package structure and the PCB.
  • the CTE of the substrate in the connection layer is continuously increasing between the die and the PCB, which further improves the reliability of the package structure itself, reduces the reliability risk of welding between the package structure and the PCB, and improves the reliability of the package structure and the PCB. adaptability.
  • the embodiments of the present application provide a method for manufacturing a packaging structure, the method comprising:
  • a plurality of via holes are respectively formed on at least one provided substrate, each of the substrates has a first surface and a second surface opposite to each other, and each of the substrates is a glass substrate;
  • a rewiring layer electrically connected to a plurality of via holes on the substrate is respectively formed on the first surface of each of the substrates to obtain at least one connection layer, and each of the connection layers includes a rewiring layer and the rewiring layer.
  • the redistribution layer in the fourth connection layer is close to the fourth connection layer, and the fourth connection layer
  • the wiring of the redistribution layer in the layer is electrically connected to the wiring of the first redistribution layer
  • the packaging structure can be manufactured using a simple and easy-to-implement processing technology, and compared with the rewiring layer of the packaging structure prepared on the packaging substrate in the technology, the number of layers of the rewiring layer is limited by cost and yield Restricted within 5 layers, this application replaces the redistribution layers in the related art with multiple connection layers including redistribution layers and glass substrates in the package structure, so that the layers of the connection layers in the package structure can be adjusted according to the redistribution needs.
  • the cost and yield are no longer limited, that is, under the action of the connection layer including the glass substrate, the number of rewiring layers in the packaging structure is no longer limited, which can meet the requirements of the ever-improving packaging structure.
  • the packaging structure uses a glass substrate instead of the high-cost packaging substrate in the related art, the cost of the packaging structure is significantly reduced.
  • including multiple glass substrates in the packaging structure can improve the reliability of the packaging structure, reduce the reliability risk of welding between the packaging structure and the PCB, and improve the adaptability between the packaging structure and the PCB.
  • the first redistribution layer is directly arranged on the side of each die with multiple first bumps, since the first redistribution layer can be directly prepared on the side of each die with the first bumps, not only can further improve the performance of each die
  • the reliability of the connection between the chip and the first rewiring layer improves the overall reliability of the packaging structure, and can also reduce the thickness of the packaging structure.
  • the at least one connection layer further includes a fifth connection layer
  • the method further includes:
  • the redistribution layer in the fifth connection layer is close to the fourth connection layer, and the redistribution layer in the fifth connection layer
  • the wiring of the wiring layer is electrically connected to a plurality of via holes on the substrate in the fourth connection layer.
  • the method further includes: filling a space between the fourth connection layer and the fifth connection layer to form a fifth filling layer.
  • filling the space between the connection layers can improve the reliability and stability of the electrical connection between the connection layers, enhance the anti-drop performance of the package structure, and further improve the reliability and stability of the package structure.
  • the method further includes at least one of the following operations:
  • the fifth plastic sealing layer of the first redistribution layer and the fourth plastic sealing layer, and the second surface of the substrate in the fourth connection layer is exposed to the fifth plastic sealing layer;
  • At least the fifth connection layer, the fourth connection layer, the fourth filling layer, the first redistribution layer, and the fourth plastic encapsulation layer are plastic-encapsulated to form at least the fifth connection layer.
  • layer, the fourth connection layer, the fourth filling layer, the first redistribution layer and the sixth molding layer of the fourth molding layer, and the second surface of the substrate in the fifth connection layer is covered
  • the sixth plastic sealing layer is exposed.
  • the reliability and structural stability of the packaging structure can be further enhanced by adding the arrangement of the fifth plastic sealing layer and/or the sixth plastic sealing layer to plastic seal different parts together.
  • the method further includes: performing thinning treatment on at least one of the fourth plastic encapsulation layer, the fifth plastic encapsulation layer, and the sixth plastic encapsulation layer.
  • the thermal expansion coefficients of the substrates in each of the connection layers are different, and the thermal expansion coefficients of the substrates in each of the connection layers range from close to The order of farthest increases in order.
  • the CTE of the substrate in the first connection layer close to the die can be set close to the CTE of the die, which solves the reliability stress problem of the packaging structure itself
  • the CTE of the substrate in the target connection layer close to the PCB can be set close to the CTE of the PCB , which solves the reliability risk of soldering between the package structure and the PCB, and improves the adaptability between the package structure and the PCB.
  • the CTE of the substrate in the connection layer is continuously increasing between the die and the PCB, which further improves the reliability of the package structure itself, reduces the reliability risk of welding between the package structure and the PCB, and improves the reliability of the package structure and the PCB. adaptability.
  • an electronic device including:
  • a printed circuit board PCB the packaging structure is electrically connected to the PCB.
  • the packaging structure itself has low cost and good reliability, the cost of the electronic device can be reduced and the reliability of the electronic device can be improved. Moreover, since the number of redistribution layers in the packaging structure is no longer limited, it can meet the high-density interconnection requirements of multiple bare chips of electronic equipment.
  • FIG. 1 shows a schematic structural diagram of a packaging structure in the related art.
  • FIGS. 2A-2C show a schematic structural diagram of a packaging structure according to an embodiment of the present application.
  • 3A and 3B are schematic structural diagrams of another package structure according to an embodiment of the present application.
  • FIG. 4 shows a schematic diagram of a manufacturing process of a manufacturing method of a packaging structure according to an embodiment of the present application.
  • FIG. 5 shows a schematic diagram of a manufacturing process of another manufacturing method of a packaging structure according to an embodiment of the present application.
  • FIGS. 6A-6C show schematic structural diagrams of yet another package structure according to an embodiment of the present application.
  • FIG. 7A and 7B are schematic structural diagrams of yet another package structure according to an embodiment of the present application.
  • FIG. 8 shows a schematic diagram of a manufacturing process of another manufacturing method of a packaging structure according to an embodiment of the present application.
  • FIG. 9 shows a schematic diagram of a manufacturing process of another manufacturing method of a packaging structure according to an embodiment of the present application.
  • first plastic sealing layer 22 second plastic sealing layer; 23 third plastic sealing layer; 24 fourth plastic sealing layer; 25 fifth plastic sealing layer; 26 sixth plastic sealing layer; 2nth plastic sealing layer; 2m mth plastic sealing layer;
  • FIG. 1 shows a schematic structural diagram of a packaging structure in the related art.
  • the bare chip in the package structure 1 is interconnected with the redistribution layer RDL through the bump of the chip, and the RDL is connected to the solder ball (C4 bump for short) manufactured by the C4 method (Controlled Collapsed Chip Connection). ) is interconnected with the package substrate of the package structure 1 .
  • the package structure 1 is then interconnected with the PCB to be connected through solder balls on the package substrate.
  • FIG. 1 shows a schematic structural diagram of a packaging structure in the related art.
  • the yield rate of the package structure 1 decreases, which will cause a large loss of yield rate, resulting in a sharp increase in the cost of the package structure 1 .
  • the C4 bump under the RDL still needs to be connected to the packaging substrate, and due to the continuous increase in capacity and bandwidth requirements, the size of the RDL continues to increase, which leads to the continuous increase in the size of the packaging substrate, making the packaging substrate good.
  • the rate of decline continues, and the delivery time of the packaging substrate (the time from the entrusted production of the packaging substrate to the completion of production and delivery of the packaging substrate) is continuously lengthened, resulting in higher and higher prices of the packaging substrate.
  • the present application provides a packaging structure and a manufacturing method thereof.
  • 2A-2C show a schematic structural diagram of a packaging structure according to an embodiment of the present application.
  • the packaging structure 2 includes: a first plastic encapsulation layer 21 , at least two bare chips 10 , multiple connection layers and a first underfill layer (Underfill) 31 .
  • the encapsulation structure 2 may include multiple connection layers as shown in FIG. 2A , such as connection layers 41 , 42 . . . 4n, where n is equal to the number of connection layers in the encapsulation structure 2 .
  • the package structure 2 shown in FIG. 2B includes a first connection layer 41 and a second connection layer 42 .
  • the package structure 2 shown in FIG. 2C includes a first connection layer 41 , a second connection layer 42 and a third connection layer 43 .
  • each of the connecting layers includes a plurality of vias (here and hereinafter the vias can be vias manufactured by technologies such as through-silicon vias (Through Silicon Via, TSV). ) substrate, and a redistribution layer covering the first surface of the substrate and electrically connected to the plurality of via holes (for example, as shown in Figures 2A-2C, the first connection layer 41 includes a redistribution layer 411 and a substrate 412, the substrate 412 is provided with a plurality of via holes K), the substrate has the first surface (the surface covered with the redistribution layer) and the second surface oppositely arranged, and the substrate in each connection layer is Glass base board.
  • the vias can be vias manufactured by technologies such as through-silicon vias (Through Silicon Via, TSV).
  • TSV Through Silicon Via
  • the first plastic encapsulation layer 21 is used to at least partially wrap each of the die 10, and a plurality of first bumps 101 of each of the die 10 are exposed to the The first plastic sealing layer 21 .
  • the first connection layer 41 is disposed on the side of the first plastic encapsulation layer 21 exposing a plurality of first bumps 101 of each die 10 , and the first connection The redistribution layer 411 in the layer 41 is close to the first plastic encapsulation layer 21, and the multiple first bumps 101 of each die 10 are electrically connected to the wiring of the redistribution layer 411 in the first connection layer 41 , the first filling layer 31 is used to fill the space between the first connection layer 41 and each of the dies 10 . That is, the first filling layer 31 fills the space between the redistribution layer 411 and each die 10 .
  • the second connection layer 42 is disposed on the second surface of the substrate 412 in the first connection layer 41, and the redistribution layer 421 in the second connection layer 42 is close to the first connection layer 41.
  • a connection layer 41 , and the plurality of vias K on the substrate 412 in the first connection layer 41 are electrically connected to the wiring in the redistribution layer 421 in the second connection layer 42 .
  • the plurality of connection layers may further include: a third connection layer 43 .
  • the third connection layer 43 is disposed on the second surface of the substrate 422 in the second connection layer 42, the redistribution layer 431 in the third connection layer 43 is close to the second connection layer 42, and the third connection
  • the wiring of the redistribution layer 431 in the layer 43 is electrically connected to the plurality of via holes K on the substrate 422 in the second connection layer 42 .
  • the package structure 2 further includes a plurality of second bumps 50, and the plurality of second bumps 50 are arranged between the first plastic sealing layer 21 and the plurality of connecting layers.
  • the second surface of the substrate in the farthest connection layer that is, the outermost connection layer among the plurality of connection layers
  • each second bump 50 covers the corresponding via hole on the substrate, which is the same as the covered through-hole electrical connections.
  • the plurality of second bumps 50 in Figure 2A are arranged on the second surface of the substrate 4n2 of the connection layer 4n, and the plurality of second bumps 50 in Figure 2B
  • the bumps 50 are disposed on the second surface of the substrate 422 of the second connection layer 42
  • the plurality of second bumps 50 in FIG. 2C are disposed on the second surface of the substrate 432 of the third connection layer 43 .
  • connection layer 41, the second connection layer 42 in FIG. 2A also includes a plurality of third bumps, each third bump is arranged on the second surface of the substrate of the connection layer, and each third bump covers the The corresponding via holes on the substrate are electrically connected to the covered via holes.
  • a plurality of third bumps 413 on the second surface of the substrate 412 in the first connection layer 41 in FIG. 2A-FIG. A plurality of third protrusions 423 .
  • the third bump, the above-mentioned first bump, and the second bump can be solder bumps (Solder Bump), such as solder bumps made of tin-based alloys, copper pillar bumps (Copper Pillar bumps) whose raw materials include copper. Bump) etc., the present application is not limited to this.
  • each redistribution layer includes wiring and a dielectric layer for wrapping the wiring.
  • at least part of the wiring on the side of the rewiring layer in each connection layer away from the covered substrate is exposed to the dielectric layer, so that the exposed wiring can be electrically connected to the first bump or the third bump by welding or the like. connected together.
  • the material of the dielectric layer can be polyimide (Polyimide, PI), poly-p-phenylene benzobisoxazole fiber (Poly-p-phenylene benzobisoxazole, PBO), ABF (Ajinomoto Build-up Film) and other dielectric materials
  • the wiring may be made of metal materials such as copper, which is not limited in the present application.
  • the number of layers of the redistribution layer is limited to less than 5 layers due to the limitation of cost and yield.
  • the rewiring Layers and multiple connection layers of the glass substrate replace the redistribution layer in the related art, and the number of connection layers in the packaging structure can be set according to the redistribution requirements, and the cost and yield are no longer limited, that is, including Under the action of the connection layer of the glass substrate, the number of rewiring layers in the packaging structure can no longer be limited, which can meet the ever-increasing demand for high-density interconnection of multiple bare chips in the packaging structure.
  • the packaging structure uses a glass substrate instead of the high-cost packaging substrate in the related art, the cost of the packaging structure is significantly reduced.
  • including multiple glass substrates in the packaging structure can improve the reliability of the packaging structure, and can also reduce the reliability risk of welding between the packaging structure and the PCB, and improve the adaptability between the packaging structure and the PCB.
  • a filling layer can be added between the connection layers of the package structure 2 to improve the reliability and stability of the electrical connection between the connection layers, enhance the drop resistance of the package structure, and further improve the reliability and stability of the package structure. structural stability.
  • the package structure 2 may further include a second filling layer 32 .
  • the second filling layer 32 is used to fill the space between the first connection layer 41 and the second connection layer 42, that is, to fill the redistribution layer 421 of the second connection layer 42 with the The space between the substrates 412 of the first connection layer 41 is described above. In this way, the second filling layer is filled between the first connection layer and the second connection layer, as shown in FIG.
  • the package structure 2 may further include a third filling layer 33 .
  • the third filling layer 33 is used to fill the space between the second connection layer 42 and the third connection layer 43, that is, to fill the redistribution layer 431 of the third connection layer 43 with the The space between the substrates 422 of the second connection layer 42 is described above.
  • the first plastic sealing layer 21 is also used to wrap the first filling layer 31 and the first connection layer 41 , and the first The second surface of the substrate 412 in the connecting layer 41 is exposed to the first plastic encapsulation layer 21 .
  • the die, the first filling layer, and the first connection layer can be plastic-sealed together, which can enhance the reliability and structural stability of the electrical connection between the die and the first connection layer, thereby improving the reliability and structural stability of the packaging structure. stability.
  • FIG. 3A and 3B are schematic structural diagrams of another package structure according to an embodiment of the present application.
  • the difference between the encapsulation structure 3 shown in FIG. 3A and FIG. 3B and the encapsulation structure 2 is that the plastic encapsulation layer corresponding to each connection layer is used for wrapping The connection layer and other parts of the packaging structure located above the connection layer (the side of the connection layer where the die is disposed).
  • the encapsulation structure 3 may further include: a second plastic encapsulation layer 22 , a third plastic encapsulation layer 23 . . . an nth plastic encapsulation layer 2n.
  • n is the number of connecting layers in the packaging structure 3, and the number of plastic sealing layers can be n.
  • the second plastic sealing layer 22 is at least used to wrap the second connecting layer 42 and the first plastic sealing layer 21, and the second surface of the substrate 422 in the second connecting layer 42 is exposed to the second plastic sealing layer twenty two.
  • the second plastic sealing layer 22 can also wrap the second filling layer 32 .
  • the second plastic encapsulation layer 22 can "the second connection layer 42, the second filling layer 32, the first plastic encapsulation layer 21 and each die 10, the first filling layer 31 and the first connection layer wrapped by the first plastic encapsulation layer.”
  • the 41” plastic package is wrapped in a common space, which can enhance the reliability and structural stability of the package structure.
  • the third plastic sealing layer 23 is at least used to wrap the third connecting layer 43, the second connecting layer 42 and the first plastic sealing layer 21, and the second of the substrate 432 in the third connecting layer 43 The surface is exposed to the third plastic sealing layer 23 .
  • the third plastic sealing layer 23 can also wrap the third filling layer 33 .
  • the encapsulation structure 3 itself includes the second plastic encapsulation layer 22 , and the objects wrapped by the third plastic encapsulation layer 23 may be the third connection layer 43 , the third filling layer 33 and the second encapsulation layer.
  • the packaging structure 3 itself only includes the first plastic sealing layer 21, and the objects wrapped by the third plastic sealing layer 23 can be the third connecting layer 43, the third filling layer 33, the second connecting layer 42 and the first plastic sealing layer.
  • Layer 21 that is to say, the third plastic packaging layer 23 can package the "third connection layer 43 and other parts of the package structure 3 on the side of the redistribution layer 431 away from the substrate 432" in a common space, which can enhance the reliability of the package structure. and structural stability.
  • the molding method of the third plastic sealing layer 23 to set the plastic sealing layer to perform plastic sealing on "the connection layer and other parts of the package structure above the connection layer” until the nth plastic sealing layer 2n is set, which is used to wrap the entire package structure, and the second surface of the substrate 4n2 of the nth connection layer 4n is exposed to the nth plastic encapsulation layer 2n.
  • the encapsulation structure 3 is as shown in FIG. 3B , and the encapsulation structure 3 may further include a second plastic encapsulation layer 22 and a third encapsulation layer 23 .
  • the number of plastic sealing layers in the packaging structure is greater than 3
  • the number of plastic sealing layers can also be set based on the number of connection layers, so that when manufacturing the packaging structure During the process, the currently prepared unfinished packaging structure can be plastic-sealed every time the connection of a connection layer is completed, which can not only enhance the reliability and structural stability of the packaging structure, but also facilitate the first connection of the substrate in the connection layer.
  • a plurality of third bumps are manufactured on the two sides and the electrical connection between the new connection layer and the unfinished packaging structure is facilitated subsequently.
  • the thermal expansion coefficients of the substrates in each connection layer are not completely the same or different from each other. And the coefficient of thermal expansion of the substrate in each of the connection layers increases sequentially according to the order of the distance between the substrate and each of the dies from near to far.
  • the package structure 2 or 3 needs to be provided with 6 connection layers, the first Connection layer 41, second connection layer 42...sixth connection layer 46, the CTE of the substrate in 41-46 can be set to w1, w2, w3, w4, w5 and w6 in sequence and a ⁇ w1 ⁇ w2 ⁇ w3 ⁇ w4 ⁇ w5 ⁇ w6 ⁇ b.
  • the CTE of the substrate 412 in the first connecting layer 41 close to the bare chip can be set close to the CTE of the bare chip 10, which solves the reliability stress problem of the packaging structure itself, and can be set close to the connecting layer of the PCB (as shown in FIG. 2A,
  • the connection layer 4n in Fig. 3A, as the connection layer 42 in Fig. 2B, or the CTE of the substrate in Fig. 2C, the connection layer 43 in Fig. 3B) is close to the CTE of PCB, which solves the problem of reliable soldering between the packaging structure and the PCB. Sexual risk, improve the adaptability between package structure and PCB.
  • the CTE between the bare chip 10 and the PCB can be continuously increased, which further improves the reliability of the packaging structure itself, and reduces the packaging structure.
  • the reliability risk of soldering between PCBs improves the adaptability between the package structure and the PCB.
  • FIG. 4 shows a schematic diagram of a manufacturing process of a manufacturing method of a packaging structure according to an embodiment of the present application. As shown in FIG. 4, the method includes step S11 to step S18. Wherein, in order to clarify the manufacturing process of the package structure 2 in schematic diagrams 2A-2C, the process shown in FIG. 4 is illustrated by taking the example of manufacturing the package structure 2 shown in FIG. layer 41 , a second connection layer 42 and a third connection layer 43 .
  • the manufacturing process of package structure 2 is:
  • step S11 a plurality of via holes K are formed on the provided substrate 412 having a first surface M1 and a second surface M2 opposite to each other.
  • a redistribution layer 411 electrically connected to a plurality of via holes K on the substrate 412 is formed on the first surface M1 of the substrate 412 to obtain a first connection layer 41, which includes The redistribution layer 411 and the substrate 412 .
  • first connection layer 41 which includes The redistribution layer 411 and the substrate 412 .
  • exposed wiring 414 for electrically connecting with the plurality of first bumps 101 is manufactured.
  • pads and the like may also be formed on the exposed wiring 414 to facilitate electrical connection with the plurality of first bumps 101 .
  • step S11 and step S12 of manufacturing the first connection layer 41 continue to manufacture all remaining connection layers of the package structure 2 , such as the second connection layer 42 and the third connection layer 43 , and then perform step S13 . It is also possible to perform step S13 after the first connection layer 41 is manufactured, and then manufacture the corresponding connection layer referring to the manufacturing process of the first connection layer (step S11 and step S12 ) before using the corresponding connection layer subsequently. For example, the second connection layer 42 and the third connection layer 43 are manufactured respectively before step S17 and step S18.
  • step S13 a plurality of first bumps 101 of at least two bare chips 10 are respectively electrically connected to the redistribution layer 411 in the first connection layer 41 (only two bare chips 10 are schematically shown in FIG. 4 ), This enables the plurality of first bumps 101 of each die 10 to be respectively connected to the exposed wiring 414 on the redistribution layer 411 .
  • the bare chip 10 may be soldered to the corresponding position of the redistribution layer 411 in a flip-chip manner.
  • step S14 the space between each of the bare chips 10 and the redistribution layer 411 of the first connection layer 41 is filled to form a first filling layer 31.
  • the space between the bare chip 10 and the rewiring layer 411 can be filled with an underfill glue, and the first filling layer 31 is formed after heating and curing (for the manufacturing method of other filling layers in this application, please refer to the manufacture of the first filling layer 31 Way).
  • step S15 at least each of the die 10 is plastic-encapsulated to form a first plastic-encapsulation layer 21 that at least partially wraps each of the die 10 , and a plurality of first bumps on each of the die 10 101 is exposed from the first plastic encapsulation layer 21 .
  • the first connection layer 41, each of the die 10 and the first filling layer 31 can be directly plastic-encapsulated to form the first plastic-encapsulation layer 21, and the first plastic-encapsulation layer 21 is used to wrap the first connection layer 41 , each of the die 10 and the first filling layer 31 and expose the second surface of the substrate 412 in the first connection layer 41 .
  • the plastic sealing process in this application can be realized by using a plastic sealing process.
  • step S16 the third bumps 413 of the first connection layer are respectively manufactured at positions corresponding to each via hole K on the second surface M2 of the substrate 412 .
  • Each third bump 413 covers the corresponding via hole K on the substrate 412 and is electrically connected to the covered via hole K.
  • the second connection layer 42 is installed on the second surface M2 of the substrate 412 in the first connection 41, and the redistribution layer 421 in the second connection layer 42 is close to the first connection layer 41 , and electrically connect the exposed wiring 424 in the redistribution layer 421 in the second connection layer 42 to the plurality of via holes K on the substrate 412 in the first connection layer 41 .
  • the unfinished packaging structure manufactured in step S16 may also be fixedly installed on the surface of the redistribution layer 421 of the second connection layer 42, so that each of the third bumps 413 is electrically connected to the redistribution layer of the connection layer 42. Wiring 424 exposed on the surface of 421 .
  • the space between the second connection layer 42 and the first connection layer 41 (that is, the space between the substrate 412 and the redistribution layer 421 ) is filled to form the second filling layer 32 .
  • the third bumps 423 are manufactured on the second surface M2 of the substrate 422 at positions corresponding to each via hole K, respectively.
  • step S18 the third connection layer 43 is installed on the second surface M2 of the substrate 422 in the second connection layer 42, and the redistribution layer 431 in the third connection layer 43 is close to the second connection layer 42 , and electrically connect the wiring 434 of the redistribution layer 431 in the third connection layer 43 with the plurality of via holes K on the substrate 422 in the second connection layer 42 .
  • the unfinished packaging structure manufactured in step S17 can also be installed on the surface of the redistribution layer 431 of the third connection layer 43, so that each of the third bumps 423 is electrically connected to the redistribution layer of the connection layer 43 Wiring 434 exposed on the surface of 431 .
  • the space between the third connection layer 43 and the second connection layer 42 (that is, the space between the substrate 422 and the redistribution layer 431 ) is filled to form the third filling layer 33 .
  • the second bumps 50 are respectively manufactured at the positions corresponding to each via hole K on the second surface M2 of the substrate 432 to obtain the packaging structure 2 .
  • the manufacturing process of manufacturing the package structure 2 can refer to the above step S11-step S18. If the number of connection layers in the package structure 2 is two or more than three, the electrical connection of other connection layers can be continued by referring to the implementation process of the electrical connection of the second connection layer and the third connection layer.
  • FIG. 5 shows a schematic diagram of a manufacturing process of another manufacturing method of a packaging structure according to an embodiment of the present application.
  • the manufacturing method for manufacturing the package structure 3 in FIGS. 3A-3B may include steps S21 to S32 .
  • the manufacturing process of the packaging structure 3 shown in FIG. 3B is taken as an example to illustrate the process.
  • Step S21-Step S26 is similar to the implementation process of Step S11-Step S16 described above, and reference may be made to Step S11-Step S16, which will not be repeated here.
  • the second connection layer 42 is installed on the second surface M2 of the substrate 412 in the first connection 41, and the redistribution layer 421 in the second connection layer 42 is close to the first connection layer 41 , and electrically connect the exposed wiring 424 in the redistribution layer 421 in the second connection layer 42 to the plurality of via holes K on the substrate 412 in the first connection layer 41 .
  • the unfinished packaging structure manufactured in step S26 may also be fixedly installed on the surface of the redistribution layer 421 of the second connection layer 42, so that each of the third bumps 413 is electrically connected to the redistribution layer 421 of the second connection layer 42.
  • the wiring 424 is exposed on the surface of the wiring layer 421 . Then, the space between the second connection layer 42 and the first connection layer 41 (that is, the space between the substrate 412 and the redistribution layer 421 ) is filled to form the second filling layer 32 .
  • step S28 at least the second connection layer 42 and the first plastic sealing layer 21 are plastic-sealed to form a second plastic sealing layer for wrapping at least the second connection layer 42 and the first plastic sealing layer 21 22 , and the second surface M2 of the substrate 422 in the second connection layer 42 is exposed to the second plastic encapsulation layer 22 .
  • the second connection layer 42, the second filling layer 32 and the first plastic sealing layer 21 can be directly plastic-sealed to form the second Plastic sealing layer 22.
  • the second plastic encapsulation layer 22 can wrap the first plastic encapsulation layer 21 , the second filling layer 32 and the second connection layer 42 , and expose the second surface M2 of the substrate 422 of the second connection layer 42 . In this way, after the electrical connection of a connection layer is completed, plastic packaging can be performed, which can further enhance the reliability and structural stability of the packaging structure.
  • step S29 the third bumps 423 are manufactured on the second surface M2 of the substrate 422 at positions corresponding to each via hole K, respectively.
  • Each third bump 423 covers the corresponding via hole K on the substrate 422 and is electrically connected to the covered via hole K.
  • step S30 the third connection layer 43 is installed on the second surface M2 of the substrate 422 in the second connection layer 42, and the redistribution layer 431 in the third connection layer 43 is close to the second connection layer 42 , and electrically connect the wiring 434 of the redistribution layer 431 in the third connection layer 43 with the plurality of via holes K on the substrate 422 in the second connection layer 42 .
  • the unfinished packaging structure manufactured in step S29 can also be fixedly installed on the surface of the redistribution layer 431 of the third connection layer 43, so that each of the third bumps 423 is electrically connected to the surface of the third connection layer 43.
  • the wiring 434 is exposed on the surface of the redistribution layer 431 .
  • the space between the third connection layer 43 and the second connection layer 42 that is, the space between the substrate 422 and the redistribution layer 431 ) is filled to form the third filling layer 33 .
  • step S31 at least the third connection layer 43, the second connection layer 42 and the first plastic sealing layer 21 are plastic-sealed to form at least the third connection layer 43, the second The connecting layer 42 and the third molding layer 23 of the first molding layer 21 , and the second surface of the substrate 432 in the third connecting layer 43 is exposed to the third molding layer 23 .
  • the unfinished packaging structure that is, the second plastic sealing layer 22, the third connecting layer 43, the The third filling layer 33
  • the third plastic encapsulation layer 23 wraps the second plastic encapsulation layer 22 , the third filling layer 33 and the third connection layer 43 , and exposes the second surface of the substrate 432 of the third connection layer 43 .
  • step S32 the second bumps 50 are manufactured on the second surface M2 of the substrate 432 at positions corresponding to each via hole K to obtain the packaging structure 3 .
  • the manufacturing process of manufacturing the packaging structure 3 can refer to the above step S21-step S32. If the number of connection layers in the package structure 3 is two or more than three, the electrical connection of other connection layers can be continued by referring to the implementation process of the electrical connection of the second connection layer and the third connection layer. Wherein, for the packaging structure 3 shown in FIG. 3A and FIG. 3B , during the manufacturing process, plastic sealing is performed after each layer of connection layer is installed.
  • the method further includes: performing at least one of the first plastic sealing layer, the second plastic sealing layer and the third plastic sealing layer For the thinning treatment, the next step is performed after the plastic sealing layer is formed and the thinning treatment is performed, or the thinning treatment for the plastic sealing layer can be performed after the entire packaging structure is manufactured.
  • the thickness of the packaging structure reduce the size of the packaging structure, so that it can be installed in electronic equipment with a smaller given space, and expand the application range of the packaging structure.
  • Figures 2A-5 show the thickness of the thinned first plastic layer, second plastic layer, and third plastic layer, which can be thinned to expose the side of the die and the first bump. The opposite side.
  • the packaging structure 4 includes: a fourth plastic encapsulation layer 24 , at least two bare chips 10 , a first redistribution layer 70 , at least one connection layer, and a fourth filling layer 34 .
  • the package structure 4 may include a fourth connection layer 44 as shown in FIG. 6B .
  • the package structure 4 may also include two connection layers, such as a fourth connection layer 44 and a fifth connection layer 45 , as shown in FIG. 6C .
  • the package structure 4 may also include multiple connection layers as shown in FIG. 6A , such as the fourth connection layer 44 .
  • the difference between the package structure 4 and the package structure 2 is that a first redistribution layer is added between the die and the connection layer in the package structure 4 .
  • the packaging structure 4 can solve the above-mentioned technical problems, since the first redistribution layer can be directly prepared on the side with the first bump of each die, it can not only further improve the distance between each die and the first redistribution layer
  • the connection reliability is improved, the overall reliability of the packaging structure is improved, and the thickness of the packaging structure can also be reduced.
  • the fourth plastic encapsulation layer 24 is used to at least partially wrap each of the dies 10 , and a plurality of first bumps 101 of each die 10 are exposed. Describe the fourth plastic sealing layer 24.
  • the first redistribution layer 70 covers the first surface of the fourth plastic encapsulation layer 24 exposing the plurality of first bumps 101 of each die 10 , and The wiring in the first redistribution layer 70 is electrically connected to the plurality of first bumps 101 of each die 10 .
  • each of the connection layers includes a substrate with a plurality of via holes, and a redistribution layer covering the first surface of the substrate and electrically connected to the plurality of via holes (
  • the fourth connection layer 44 includes a redistribution layer 441 and a substrate 442, and the substrate 442 is provided with a via hole K)
  • the substrate has the first surface and (the side covered with the redistribution layer) the second surface, and each substrate is a glass substrate.
  • the fourth connection layer 44 covers the side of the first redistribution layer 70 away from each die 10 , and the redistribution layer 441 of the fourth connection layer 44 close to the first redistribution layer 70 .
  • the wires of the redistribution layer 441 in the fourth connection layer 44 are electrically connected to the wires of the first redistribution layer 70 .
  • the fourth filling layer 34 is used to fill the space between the fourth connection layer 44 and the first redistribution layer 70, that is, to fill the space between the first redistribution layer 70 and the first redistribution layer 70. Space between redistribution layers 441 .
  • the at least one connection layer further includes: a fifth connection layer 45 .
  • the fifth connection layer 45 is arranged on the second surface of the substrate 442 in the fourth connection layer 44, the redistribution layer 451 in the fifth connection layer 45 is close to the fourth connection layer 44, and the fifth The wiring of the redistribution layer 451 in the connection layer 45 is electrically connected to the plurality of vias K on the substrate 442 in the fourth connection layer 44 .
  • the package structure 4 also includes a plurality of second bumps 50 (the setting positions of which are similar to those of the second bumps in the package structures 2 and 3 above, and can be referred to above text, will not be repeated here).
  • other connection layers other than the connection layer provided with a plurality of second bumps 50 also include a plurality of third bumps (such as the fourth connection layer 44 in FIG. 6A and FIG. 6C ).
  • each third bump is disposed on the second surface of the substrate of the connection layer, and each third bump covers the corresponding via hole on the substrate and is in line with the covered via hole. hole electrical connection.
  • the encapsulation structure 4 further includes a fifth filling layer filling a space between two adjacent connection layers.
  • the encapsulation structure 4 further includes a fifth filling layer 35 .
  • the fifth filling layer 35 is used to fill the space between the fourth connection layer 44 and the fifth connection layer 45 . That is, the fifth filling layer 35 fills the space between the redistribution layer 451 and the substrate 442 .
  • FIG. 7A and 7B are schematic structural diagrams of yet another package structure according to an embodiment of the present application.
  • the package structure 5 may also include
  • the plastic sealing layer corresponding to the connecting layer is used to wrap the connecting layer and other parts of the package structure above the connecting layer (the side of the connecting layer where the die is disposed).
  • the encapsulation structure 5 may further include a fifth plastic encapsulation layer 25 . . . the mth plastic encapsulation layer 2m.
  • m-3 is the number of layers of the connecting layer in the package structure 5, and the number of layers of the plastic sealing layer can be m-2 (including the fourth plastic sealing layer and the plastic sealing layer corresponding to each connecting layer).
  • the fifth plastic encapsulation layer 25 is at least used to wrap the fourth connection layer 44, the fourth filling layer 34, the first redistribution layer 70 and the fourth plastic encapsulation layer 24, and the fourth connection layer
  • the second surface of the substrate 442 in 44 is exposed to the fifth plastic encapsulation layer 25 .
  • the fourth connection layer 44 , the fourth filling layer 34 , the first redistribution layer 70 and the fourth plastic encapsulation layer 24 are other parts of the packaging structure above the fourth connection layer 44 .
  • the plastic sealing method of the fifth plastic sealing layer 25 to set the plastic sealing layer to perform plastic sealing on "the connection layer and other parts of the packaging structure located above the connection layer”
  • the mth plastic sealing layer 2m is set, which is used to wrap the entire package structure, and the second surface of the substrate 4m2 of the mth connection layer 4m is exposed to the mth plastic encapsulation layer 2m.
  • the encapsulation structure 5 is as shown in FIG. 7B , and the encapsulation structure 5 may further include a fifth plastic encapsulation layer 25 and a sixth encapsulation layer 26 .
  • the fifth plastic encapsulation layer 25 is at least used to wrap the fourth connection layer 44 , the fourth filling layer 34 , the first redistribution layer 70 and the fourth plastic encapsulation layer 24 , and the fourth connection layer 44
  • the second surface of the middle substrate 442 is exposed to the fifth plastic encapsulation layer 25 .
  • the fourth connection layer 44 , the fourth filling layer 34 , the first redistribution layer 70 and the fourth plastic encapsulation layer 24 are other parts of the packaging structure above the fourth connection layer 44 .
  • the sixth plastic encapsulation layer 26 is at least used to wrap the fifth connection layer 45, the fourth connection layer 44, the fourth filling layer 34, the first redistribution layer 70 and the fourth plastic encapsulation layer 24, and the The second surface of the substrate 452 in the fifth connection layer 45 is exposed to the sixth plastic encapsulation layer 26 .
  • the sixth plastic sealing layer 26 can also wrap the fifth filling layer 35 . Then the fifth connection layer 45, the fifth filling layer 35, the fourth connection layer 44, the fourth filling layer 34, the first redistribution layer 70 and the fourth plastic encapsulation layer 24 are located in the fifth Other parts of the package structure above the connection layer 45 .
  • connection layer and other parts of the package structure located above the connection layer are packaged in a common space through the plastic package layer, which can enhance the reliability and structural stability of the package structure 5 .
  • the second surface of at least one die 10 is exposed to the packaging structure 4 or 5, and each die 10 has an opposite arrangement.
  • the first surface and the second surface of each die 10 are provided with a plurality of first bumps 101 on the first surface.
  • the thermal expansion coefficients of the substrates in each connection layer are not completely the same or different from each other. And the coefficient of thermal expansion of the substrate in each of the connection layers increases sequentially in the order of the distance between the substrate and the fourth plastic encapsulation layer 24 from short to long. For example, assuming the thermal expansion coefficient a of the bare chip 10 , the thermal expansion coefficient of the PCB to which the packaging structure 4 or 5 is subsequently connected is b (b>a).
  • the encapsulation structure 4 or 5 needs to set three connection layers, the fourth connection layer 44, the fifth connection layer 45 and the sixth connection layer 46, then the fourth connection layer 44, the fifth connection layer 45 and the sixth connection layer 46 can be provided
  • the CTEs of the middle substrate are w1, w2 and w3 in sequence, and a ⁇ w1 ⁇ w2 ⁇ w3 ⁇ b. In this way, the CTE of the substrate 442 in the fourth connecting layer 44 close to the bare chip 10 can be set close to the CTE of the bare chip 10, which solves the reliability stress problem of the packaging structure itself, and can be set close to the connecting layer of the PCB (that is, the first connecting layer).
  • the CTE of the substrate in the six connection layers is close to the CTE of the PCB, which solves the reliability risk of welding between the package structure and the PCB, and improves the adaptability between the package structure and the PCB.
  • the CTE between the bare chip 10 and the PCB can be continuously increased, which further improves the reliability of the packaging structure itself and reduces the relationship between the packaging structure and the PCB.
  • the reliability risk of soldering between them improves the adaptability between the package structure and the PCB.
  • FIG. 8 shows a schematic diagram of a manufacturing process of another manufacturing method of a packaging structure according to an embodiment of the present application. As shown in FIG. 8, the method includes step S41 to step S51. Among them, in order to clarify the manufacturing process of the packaging structure 4 of schematic diagrams 6A-6C, the manufacturing process of the packaging structure 4 shown in FIG. 6C is taken as an example in FIG. layer 44 and a fifth connection layer 45 .
  • the manufacturing process is:
  • step S41 at least two bare chips 10 are plastic-encapsulated to form a fourth plastic-encapsulation layer 24, and the fourth plastic-encapsulation layer 24 is at least used to wrap each of the bare chips 10 and multiple parts of each of the bare chips 10
  • the first bumps 101 are exposed to the fourth plastic encapsulation layer 24 .
  • step S42 on the fourth molding layer 24 exposing the plurality of first bumps 101 of each die 10, a first contact electrically connected to the plurality of first bumps 101 of each die is formed.
  • redistribution layer 70 wherein, exposed wiring (not marked in the figure) is also manufactured on the side of the first redistribution layer 70 away from the bare chip.
  • step S43 the fourth bumps 701 are respectively manufactured at the exposed wiring on the side of the first redistribution layer 70 away from the plurality of first bumps 101, so as to use the plurality of fourth bumps 701 to implement the subsequent Connect the electrical connection between the layers.
  • step S44 a plurality of via holes K are formed on the provided substrate 442 having a first surface M1 and a second surface M2 opposite to each other.
  • step S45 a redistribution layer 441 electrically connected to a plurality of via holes K on the substrate 442 is formed on the first surface M1 of the substrate 442 to obtain a fourth connection layer 44, which includes The redistribution layer 441 and the substrate 442 .
  • a fourth connection layer 44 which includes The redistribution layer 441 and the substrate 442 .
  • step S44 and step S45 of manufacturing the fourth connection layer 44 continue to manufacture the fifth connection layer of the package structure 4 , and then perform step S46 . It is also possible to execute step S46 after the fourth connection layer 44 is manufactured, and then manufacture the corresponding connection layer referring to the manufacturing process of the fourth connection layer (step S44 and step S45 ) before the corresponding connection layer needs to be used subsequently. For example, the fifth connection layer 45 is manufactured before step S49.
  • step S46 the unfinished packaging structure manufactured in step S43 is fixedly installed on the redistribution layer 441 of the fourth connection layer 44 (that is, installed on the side of the first redistribution layer 70 away from the fourth plastic packaging layer 24 The fourth connection layer 44 ), and electrically connect the first redistribution layer 70 to the redistribution layer 441 of the fourth connection layer 44 .
  • the exposed wires 444 on the redistribution layer 441 are electrically connected to the plurality of fourth bumps 701 of the first redistribution layer 70 .
  • step S47 the space between the fourth connection layer 44 and the first redistribution layer 70 (that is, the space between the first redistribution layer 70 and the redistribution layer 441) is filled to form a fourth filling Layer 34.
  • step S48 third bumps are respectively formed on the second surface M2 of the substrate 442 of the fourth connection layer 44 at positions corresponding to each of the via holes K in the substrate 442 of the fourth connection layer 44 443 , each third bump 443 covers the corresponding via hole K on the substrate 442 and is electrically connected to the covered via hole K.
  • step S49 installing the fifth connection layer 45 on the second surface of the substrate 442 in the fourth connection layer 44, the redistribution layer 451 in the fifth connection layer 45 is close to the fourth connection layer 44, and The wiring 454 of the redistribution layer 451 in the fifth connection layer 45 is electrically connected to the plurality of vias K on the substrate 442 in the fourth connection layer 44 .
  • step S50 the space between the fifth connection layer 45 and the fourth connection layer 44 (that is, the space between the substrate 442 and the redistribution layer 451 ) is filled to form the fifth filling layer 35 .
  • step S51 the second bumps 50 are respectively manufactured on the second surface M2 of the substrate 452 at positions corresponding to the via holes K to obtain the packaging structure 4 .
  • step S50 if the number of layers of the connection layer in the package structure 4 is greater than 2, after step S50 is completed, new third bumps are directly manufactured at the positions corresponding to the via holes K on the second surface M2 of the substrate 452, Then, referring to the realization process of the electrical connection of the fourth connection layer and the fifth connection layer, the electrical connection of other connection layers is continued.
  • FIG. 9 shows a schematic diagram of a manufacturing process of another manufacturing method of a packaging structure according to an embodiment of the present application.
  • the manufacturing method for manufacturing the package structure 5 in FIGS. 7A-7B may include steps S61 to S73 .
  • the manufacturing process of the packaging structure 5 shown in FIG. 7B is taken as an example to illustrate the process.
  • step S61-step S67 is similar to the above-mentioned step S41-step S47, and reference may be made to step S41-step S17, which will not be repeated here.
  • step S68 the fourth connection layer 44, the fourth filling layer 34, the first redistribution layer 70 and the fourth plastic packaging layer 24 are plastic-encapsulated to form the fifth plastic packaging layer 25, wherein the fifth plastic packaging layer 25 is used to wrap the fourth connection layer 44, the fourth filling layer 34, the first redistribution layer 70 and the fourth plastic encapsulation layer 24, and the second surface M2 of the substrate 442 in the fourth connection layer 44 is exposed.
  • Five plastic sealing layers 25 are used to wrap the fourth connection layer 44, the fourth filling layer 34, the first redistribution layer 70 and the fourth plastic encapsulation layer 24, and the second surface M2 of the substrate 442 in the fourth connection layer 44 is exposed.
  • step S69 third bumps 443 are respectively formed on the second surface M2 of the substrate 442 of the fourth connection layer 44 at positions corresponding to the via holes K in the substrate 442 of the fourth connection layer 44 .
  • Each third bump 443 covers the corresponding via hole K on the substrate 442 and is electrically connected to the covered via hole K.
  • step S70 installing the fifth connection layer 45 on the second surface of the substrate 442 in the fourth connection layer 44, the redistribution layer 451 in the fifth connection layer 45 is close to the fourth connection layer 44, and The exposed wiring 454 of the redistribution layer 451 in the fifth connection layer 45 is electrically connected to the plurality of via holes K on the substrate 442 in the fourth connection layer 44 .
  • step S71 the space between the fifth connection layer 45 and the fourth connection layer 44 (that is, the space between the substrate 442 and the redistribution layer 451 ) is filled to form the fifth filling layer 35 .
  • step S72 the fifth connection layer 45, the fifth filling layer 35, the fourth connection layer 44, the fourth filling layer 34, the first redistribution layer 70 and the first
  • the fourth plastic sealing layer 24 is plastic sealed to form the sixth plastic sealing layer 26 , and the second surface of the substrate 452 in the fifth connecting layer 45 is exposed to the sixth plastic sealing layer 26 . That is, the fifth connection layer 45 , the fifth filling layer 35 and the fifth plastic sealing layer 25 are plastic-sealed to form the sixth plastic sealing layer 26 .
  • step S73 the second bumps 50 are respectively manufactured on the second surface M2 of the substrate 452 at positions corresponding to the via holes K to obtain the packaging structure 5 .
  • the manufacturing process of manufacturing the packaging structure 5 can refer to the above step S61-step S73. If the number of connection layers in the package structure 5 is two or more than three, the electrical connection of other connection layers can be continued by referring to the implementation process of the electrical connection between the fourth connection layer and the fifth connection layer. That is to say, for the packaging structure 5 shown in FIG. 7A and FIG. 7B , during the manufacturing process, plastic sealing is performed after each layer of connection layer is installed.
  • the method may further include: performing thinning treatment on the fourth plastic sealing layer, the fifth plastic sealing layer and/or the sixth plastic sealing layer , the next step can be performed after the plastic sealing layer is formed and thinned, or the "fifth plastic sealing layer", "fifth plastic sealing layer and fourth plastic sealing layer", "fourth plastic sealing layer” can be completed after the entire packaging structure is manufactured. Thinning treatment of plastic sealing layer, fifth plastic sealing layer and sixth plastic sealing layer".
  • Figures 6A-9 show the thicknesses of the thinned fourth, fifth, and sixth plastic encapsulation layers, which can be thinned to expose the side of the die that is not provided with the first bump .
  • an electrical test can be performed on the currently manufactured unfinished packaging structure to ensure the yield of the final manufactured packaging structure .
  • an electrical test may be performed after at least one of the following steps: step S16 , step S17 , and step S18 .
  • an electrical test may be performed after at least one of the following steps: step S26 , step S29 , and step S32 .
  • an electrical test may be performed after at least one of the following steps: step S43 , step S48 , and step S51 .
  • an electrical test may be performed after at least one of the following steps: step S63 , step S69 , and step S73 .
  • each block in a flowchart or block diagram may represent a module, a portion of a program segment, or an instruction that includes one or more Executable instructions.
  • the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved.
  • each block in the block diagrams and/or flowcharts, and combinations of blocks in the block diagrams and/or flowcharts can be implemented with hardware (such as circuits or ASIC (Application Specific Integrated Circuit, application-specific integrated circuit)), or can be implemented with a combination of hardware and software, such as firmware.
  • hardware such as circuits or ASIC (Application Specific Integrated Circuit, application-specific integrated circuit)
  • firmware such as firmware

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Abstract

本申请涉及一种封装结构及其制造方法、电子设备。该封装结构包括：至少两个裸片；第一塑封层包裹每个裸片且暴露出每个裸片的多个第一凸块；第一连接层和第二连接层，每个连接层包括基板以及覆盖在基板的第一面且与基板的多个过孔电连接的重布线层，基板为玻璃基板，多个连接层包括；第一连接层在第一塑封层暴露出裸片的多个第一凸块的一面，且裸片的多个第一凸块电连接到第一连接层中重布线层，第一填充层填充第一连接层与每个裸片之间的空间；第二连接层设置在第一连接层中基板的第二面，且第一连接层中基板上的多个过孔与第二连接层中重布线层电连接。实现多裸片的高密度互连，重布线层层数不受限，成本低，自身以及与PCB之间互连的可靠性高。

Description

封装结构及其制造方法、电子设备 技术领域
本申请涉及电子封装技术领域，尤其涉及一种封装结构及其制造方法、电子设备。
背景技术
随着数据中心和AI计算对于数据传输带宽的需求越来越高，小芯片(chiplet)技术被广泛的采用。芯片等封装结构间需要通过高密度的互连线进行异质集成，电子封装技术带来了巨大的挑战，封装成本上涨飞速。并且，随着对封装结构的集成度和容量要求的不断提高，在集成电路工艺(integrated circuit technique)的工艺节点(也称特征尺寸)下降的同时，封装结构尺寸却不断地攀升。利用扇出型单元(Fan out unit)技术制造的如图1所示的封装结构1，受成本以及良率的限制重布线层(Redistribution Layer，RDL)的层数受限在5层以内。且由于封装结构1中裸片(die)的极低介电常数材料(Extreme low-k dielectric，ELK)的强度低，使得封装结构1的可靠性风险越来越高；同时由于封装结构1与印制电路板(Print Circuit Board，PCB)的热膨胀系数(coefficient of thermal expansion，CTE)之间的差异较大，使得焊接的可靠性风险也越来越高。如何降低封装结构成本的同时，实现多裸片之间的高密度互连，保证封装结构内部、以及封装结构的基板与PCB之间的可靠性是亟待解决的技术问题。
发明内容
有鉴于此，为解决上述技术问题，提出了一种封装结构及其制造方法、电子设备。
第一方面，本申请的实施例提供了一种封装结构，所述封装结构包括：第一塑封层、至少两个裸片、多个连接层和第一填充层，每个所述连接层包括带有多个过孔的基板、以及覆盖在所述基板的第一面且与所述多个过孔电连接的重布线层，所述基板具有相对设置的所述第一面和第二面，所述基板为玻璃基板，所述多个连接层包括第一连接层和第二连接层；
所述第一塑封层用于至少部分包裹每个所述裸片，且每个所述裸片的多个第一凸块被暴露出所述第一塑封层；
所述第一连接层设置在所述第一塑封层暴露出每个所述裸片的多个第一凸块的一面，所述第一连接层中的重布线层靠近所述第一塑封层，且每个所述裸片的多个第一凸块电连接到所述第一连接层中重布线层的布线，所述第一填充层用于填充所述第一连接层与每个所述裸片之间的空间；
所述第二连接层设置在所述第一连接层中基板的第二面，所述第二连接层中的重布线层靠近所述第一连接层，且所述第一连接层中基板上的多个过孔与所述第二连接层中重布线层中的布线电连接。
通过第一方面，相比于技术中在封装基板上制备封装结构的重布线层，受成本以及良率的限制重布线层的层数受限在5层以内，本申请将封装结构中用包括重布线层和玻璃基板的多个连接层代替了相关技术中的重布线层，就可以根据重布线需要对封装结构中连接层的层数进行设置，成本以及良率不再受限，也即在包括玻璃基板的连接层的作用下，可以使得封装结构中重布线层的层数不再受限，可以满足不断提高的封装结构中多裸片的高密度互连需 求。且由于封装结构中以玻璃基板代替相关技术中成本高的封装基板，显著降低了封装结构的成本。另一方面，封装结构中包括多个玻璃基板可以提高封装结构的可靠性，还可以降低封装结构与PCB之间焊接的可靠性风险，提高封装结构与PCB之间的适配性。
在一种可能的实现方式中，所述多个连接层还包括：第三连接层，设置在所述第二连接层中基板的第二面，所述第三连接层中的重布线层靠近所述第二连接层，且所述第三连接层中重布线层的布线与所述第二连接层中基板上的多个过孔电连接。这样，可以根据需要对封装结构中的连接层的个数进行设置，以满足不同封装结构的布线需求。
在一种可能的实现方式中，所述封装结构还包括第二填充层和/或第三填充层，
所述第二填充层用于填充所述第一连接层和所述第二连接层之间的空间；
所述第三填充层用于填充所述第二连接层和所述第三连接层之间的空间。
这样，在第一连接层和第二连接层之间、第二连接层和第三连接层之间分别进行填充可以提高连接层之间电连接的可靠性和稳定性，增强封装结构的抗跌落性能，进而提高封装结构的可靠性和结构稳定性。
在一种可能的实现方式中，所述第一塑封层还用于包裹所述第一填充层和所述第一连接层，且所述第一连接层中基板的第二面被裸露出所述第一塑封层。这样，可以将裸片、第一填充层、第一连接层塑封在一起，可以增强裸片与第一连接层之间电连接的可靠性和结构稳定性，进而提高封装结构的可靠性和结构稳定性。
在一种可能的实现方式中，所述封装结构还包括：第二塑封层和/或第三塑封层；
所述第二塑封层至少用于包裹所述第二连接层和所述第一塑封层，且所述第二连接层中基板的第二面被裸露出所述第二塑封层；
所述第三塑封层至少用于包裹所述第三连接层、所述第二连接层和所述第一塑封层，且所述第三连接层中的基板的第二面被裸露出所述第三塑封层。
这样，通过增加第二塑封层和/或第三塑封层的设置将不同的部分塑封在一起，可以进一步增强封装结构的可靠性和结构稳定性。
在一种可能的实现方式中，至少一个所述裸片的第二表面被暴露出所述封装结构，每个所述裸片具有相对设置的第一表面和第二表面，且每个所述裸片的所述第一表面设置有多个第一凸块。这样，可以减小封装结构的厚度，缩减封装结构的尺寸，使其可以安装的到给定空间更小的电子设备中，扩大封装结构的使用范围。
在一种可能的实现方式中，每个所述连接层中基板的热膨胀系数不同，且每个所述连接层中基板的热膨胀系数按照基板与所述第一塑封层之间的距离由近到远的顺序依次增大。这样，可以设置靠近裸片的第一连接层中的基板CTE接近裸片的CTE，解决了封装结构本身的可靠性应力问题，且可以设置靠近PCB的目标连接层中基板的CTE接近PCB的CTE，解决了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。并且，连接层中基板的CTE在裸片与PCB之间不断递增，进一步提高了封装结构本身的可靠性，降低了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。
第二方面，本申请的实施例提供了一种封装结构的制造方法，包括：
在提供的多个基板上分别形成多个过孔，每个所述基板具有相对设置的第一面和第二面，每个所述基板为玻璃基板；
在每个所述基板的第一面分别形成与所述基板上的多个过孔电连接的重布线层，得到多 个连接层，每个所述连接层包括重布线层以及所述重布线层所覆盖的基板，所述多个连接层包括第一连接层和第二连接层；
将至少两个裸片的多个第一凸块分别电连接到所述第一连接层中重布线层的布线；
对每个所述裸片和所述第一连接层之间的空间进行填充，形成第一填充层；
至少对每个所述裸片进行塑封，形成至少部分包裹每个所述裸片的第一塑封层，且每个所述裸片的多个第一凸块被暴露出所述第一塑封层；
在所述第一连接层中基板的第二面安装所述第二连接层，所述第二连接层中的重布线层靠近所述第一连接层，以及将所述第二连接层中重布线层中的布线与所述第一连接层中基板上的多个过孔电连接。
通过第二方面，可以利用简单、易于实现的加工工艺制造出封装结构，且相比于技术中在封装基板上制备封装结构的重布线层，受成本以及良率的限制重布线层的层数受限在5层以内，本申请将封装结构中用包括重布线层和玻璃基板的多个连接层代替了相关技术中的重布线层，就可以根据重布线需要对封装结构中连接层的层数进行设置，成本以及良率不再受限，也即在包括玻璃基板的连接层作用下，可以使得封装结构中重布线层的层数不再受限，可以满足不断提高的封装结构中多裸片的高密度互连需求。且由于封装结构中以玻璃基板代替相关技术中成本高的封装基板，显著降低了封装结构的成本。另一方面，封装结构中包括多个玻璃基板可以提高封装结构的可靠性，还可以降低封装结构与PCB之间焊接的可靠性风险，提高封装结构与PCB之间的适配性。
在一种可能的实现方式中，所述多个连接层还包括第三连接层，所述方法还包括：
在所述第二连接层中基板的第二面安装所述第三连接层，所述第三连接层中的重布线层靠近所述第二连接层，以及将所述第三连接层中重布线层的布线与所述第二连接层中基板上的多个过孔电连接。这样，可以根据需要对封装结构中的连接层的个数进行设置，以满足不同封装结构的布线需求。
在一种可能的实现方式中，所述所述第一塑封层还用于包裹所述第一填充层和所述第一连接层，且所述第一连接层中基板的第二面被裸露出所述第一塑封层。这样，可以将裸片、第一填充层、第一连接层塑封在一起，可以增强裸片与第一连接层之间电连接的可靠性和稳定性，进而提高封装结构的可靠性和结构稳定性。
在一种可能的实现方式中，所述方法还包括以下至少一项操作：
至少对所述第二连接层和所述第一塑封层进行塑封，形成至少用于包裹所述第二连接层和所述第一塑封层的第二塑封层，且所述第二连接层中基板的第二面被裸露出所述第二塑封层；
至少对所述第三连接层、所述第二连接层和所述第一塑封层进行塑封，形成至少用于包裹所述第三连接层、所述第二连接层和所述第一塑封层的第三塑封层，且所述第三连接层中基板的第二面被裸露出所述第三塑封层。
这样，在完成一个连接层的电连接后，就可以进行塑封形成第二塑封层和/或第三塑封层，可以进一步增强封装结构的可靠性和结构稳定性。
在一种可能的实现方式中，所述方法还包括以下至少一项操作：
对所述第一连接层和所述第二连接层之间的空间进行填充，形成第二填充层，所述第二塑封层还用于包裹所述第二填充层；
对所述第二连接层和所述第三连接层之间的空间进行填充，形成第三填充层，所述第三塑封层还用于包裹所述第三填充层。
这样，在第一连接层和第二连接层之间、第二连接层和第三连接层之间分别进行填充可以提高连接层之间电连接的可靠性和稳定性，增强封装结构的抗跌落性能，进而提高封装结构的可靠性和稳定性。
在一种可能的实现方式中，所述方法还包括：
对所述第一塑封层、所述第二塑封层和所述第三塑封层中的至少一个进行减薄处理。这样，可以减小封装结构的厚度，缩减封装结构的尺寸，使其可以安装的到给定空间更小的电子设备中，扩大封装结构的使用范围。
在一种可能的实现方式中，每个所述连接层中基板的热膨胀系数不同，且每个所述连接层中基板的热膨胀系数按照基板与每个所述裸片之间的距离由近到远的顺序依次增大。这样，可以设置靠近裸片的第一连接层中的基板CTE接近裸片的CTE，解决了封装结构本身的可靠性应力问题，且可以设置靠近PCB的目标连接层中基板的CTE接近PCB的CTE，解决了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。并且，连接层中基板的CTE在裸片与PCB之间不断递增，进一步提高了封装结构本身的可靠性，降低了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。
第三方面，本申请的实施例提供了一种封装结构，所述封装结构包括第四塑封层、至少两个裸片、第一重布线层、至少一个连接层和第四填充层，每个所述连接层包括带有多个过孔的基板、以及覆盖在所述基板的第一面且与所述多个过孔电连接的重布线层，所述基板具有相对设置的所述第一面和第二面，每个所述基板为玻璃基板，所述至少一个连接层包括第四连接层；
所述第四塑封层用于至少部分包裹每个所述裸片，且每个所述裸片的多个第一凸块被暴露出所述第四塑封层；
所述第一重布线层覆盖在所述第四塑封层的暴露出每个所述裸片的多个第一凸块的一面，且所述第一重布线层中的布线与每个所述裸片的多个第一凸块电连接；
所述第四连接层设置在所述第一重布线层远离每个所述裸片的一面，所述第四连接层中的重布线层靠近所述第一重布线层，且所述第四连接层中重布线层的布线与所述第一重布线层的布线电连接；
所述第四填充层用于填充所述第四连接层与所述第一重布线层之间的空间。
通过第三方面，相比于技术中在封装基板上制备封装结构的重布线层，受成本以及良率的限制重布线层的层数受限在5层以内，本申请将封装结构中用包括重布线层和玻璃基板的多个连接层代替了相关技术中的重布线层，就可以根据重布线需要对封装结构中连接层的层数进行设置，成本以及良率不再受限，也即在包括玻璃基板的连接层的作用下，可以使得封装结构中重布线层的层数不再受限，可以满足不断提高的封装结构中多裸片的高密度互连需求。且由于封装结构中以玻璃基板代替相关技术中成本高的封装基板，显著降低了封装结构的成本。另一方面，封装结构中包括多个玻璃基板可以提高封装结构的可靠性，还可以降低封装结构与PCB之间焊接的可靠性风险，提高封装结构与PCB之间的适配性。并且，直接在各裸片具有多个第一凸块的一面设置第一重布线层，由于第一重布线层可直接制备在各裸片具有第一凸块的一面，不仅能够进一步提高各裸片于第一重布线层之间的连接可靠性、提 高封装结构整体的可靠性，还能够缩减封装结构的厚度。
在一种可能的实现方式中，所述至少一个连接层还包括：
第五连接层，设置在所述第四连接层中基板的第二面，所述第五连接层中的重布线层靠近所述第四连接层，且所述第五连接层中重布线层的布线与所述第四连接层中基板上的多个过孔电连接。这样，可以根据需要对封装结构中的连接层的个数进行设置，以满足不同封装结构的布线需求。
在一种可能的实现方式中，所述封装结构还包括：第五填充层，所述第五填充层用于填充所述第四连接层和所述第五连接层之间的空间。这样，对连接层之间的空间进行填充可以提高连接层之间电连接的可靠性和稳定性，增强封装结构的抗跌落性能，进而提高封装结构的可靠性和稳定性。
在一种可能的实现方式中，所述封装结构还包括：第五塑封层和/或第六塑封层；
所述第五塑封层至少用于包裹所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层，且所述第四连接层中基板的第二面被暴露出所述第五塑封层；
所述第六塑封层至少用于包裹所述第五连接层、所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层，且所述第五连接层中基板的第二面被暴露出所述第六塑封层。
这样，通过增加第五塑封层和/或第六塑封层的设置将不同的部分塑封在一起，可以进一步增强封装结构的可靠性和结构稳定性。
在一种可能的实现方式中，至少一个所述裸片的第二表面被暴露出所述封装结构，每个所述裸片具有相对设置的第一表面和第二表面，且每个所述裸片的所述第一表面设置有多个第一凸块。这样，可以减小封装结构的厚度，缩减封装结构的尺寸，使其可以安装的到给定空间更小的电子设备中，扩大封装结构的使用范围。
在一种可能的实现方式中，每个所述连接层中基板的热膨胀系数不同，且每个所述连接层中基板的热膨胀系数按照基板与所述第四塑封层之间的距离由近到远的顺序依次增大。这样，可以设置靠近裸片的第一连接层中的基板CTE接近裸片的CTE，解决了封装结构本身的可靠性应力问题，且可以设置靠近PCB的目标连接层中基板的CTE接近PCB的CTE，解决了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。并且，连接层中基板的CTE在裸片与PCB之间不断递增，进一步提高了封装结构本身的可靠性，降低了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。
第四方面，本申请的实施例提供了一种封装结构的制造方法，所述方法包括：
对至少两个裸片进行塑封，形成用于至少部分包裹每个所述裸片的第四塑封层，且每个所述裸片的多个第一凸块被暴露出所述第四塑封层；
在所述第四塑封层暴露出每个所述裸片的多个第一凸块的一面形成与每个所述裸片的芯多个第一凸块电连接的第一重布线层；
在提供的至少一个基板上分别形成多个过孔，每个所述基板具有相对设置的第一面和第二面，每个所述基板为玻璃基板；
在每个所述基板的第一面分别形成与所述基板上的多个过孔电连接的重布线层，得到至少一个连接层，每个所述连接层包括重布线层以及所述重布线层所覆盖的基板，所述至少一个连接层包括第四连接层；
在所述第一重布线层远离所述第四塑封层的一面安装所述第四连接层，所述第四连接层中的重布线层靠近所述第四连接层，且所述第四连接层中重布线层的布线与所述第一重布线层的布线电连接；
对所述第四连接层与所述第一重布线层之间的空间进行填充，形成第四填充层。
通过第四方面，可以利用简单、易于实现的加工工艺制造出封装结构，且相比于技术中在封装基板上制备封装结构的重布线层，受成本以及良率的限制重布线层的层数受限在5层以内，本申请将封装结构中用包括重布线层和玻璃基板的多个连接层代替了相关技术中的重布线层，就可以根据重布线需要对封装结构中连接层的层数进行设置，成本以及良率不再受限，也即在包括玻璃基板的连接层的作用下，可以使得封装结构中重布线层的层数不再受限，可以满足不断提高的封装结构中多裸片的高密度互连需求。且由于封装结构中以玻璃基板代替相关技术中成本高的封装基板，显著降低了封装结构的成本。另一方面，封装结构中包括多个玻璃基板可以提高封装结构的可靠性，还可以降低封装结构与PCB之间焊接的可靠性风险，提高封装结构与PCB之间的适配性。并且，直接在各裸片具有多个第一凸块的一面设置第一重布线层，由于第一重布线层可直接制备在各裸片具有第一凸块的一面，不仅能够进一步提高各裸片于第一重布线层之间的连接可靠性、提高封装结构整体的可靠性，还能够缩减封装结构的厚度。
在一种可能的实现方式中，所述至少一个连接层还包括第五连接层，所述方法还包括：
在所述第四连接层中基板的第二面安装所述第五连接层，所述第五连接层中的重布线层靠近所述第四连接层，以及将所述第五连接层中重布线层的布线与所述第四连接层中基板上的多个过孔电连接。这样，可以根据需要对封装结构中的连接层的个数进行设置，依次完成每个连接层的装配，满足不同封装结构的布线需求。
在一种可能的实现方式中，所述方法还包括：对所述第四连接层和所述第五连接层之间的空间进行填充，形成第五填充层。这样，对连接层之间的空间进行填充可以提高连接层之间电连接的可靠性和稳定性，增强封装结构的抗跌落性能，进而提高封装结构的可靠性和稳定性。
在一种可能的实现方式中，所述方法还包括以下至少一项操作：
对所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层进行塑封，形成用于包裹所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层的第五塑封层，且所述第四连接层中基板的第二面被暴露出所述第五塑封层；
至少对所述第五连接层、所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层进行塑封，形成至少用于包裹所述第五连接层、所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层的第六塑封层，且所述第五连接层中基板的第二面被暴露出所述第六塑封层。
这样，通过增加第五塑封层和/或第六塑封层的设置将不同的部分塑封在一起，可以进一步增强封装结构的可靠性和结构稳定性。
在一种可能的实现方式中，所述方法还包括：对所述第四塑封层、第五塑封层和所述第六塑封层中的至少一个进行减薄处理。这样，可以减小封装结构的厚度，缩减封装结构的尺寸，使其可以安装的到给定空间更小的电子设备中，扩大封装结构的使用范围。
在一种可能的实现方式中，每个所述连接层中基板的热膨胀系数不同，且每个所述连接 层中基板的热膨胀系数按照基板与所述第四塑封层之间的距离由近到远的顺序依次增大。这样，可以设置靠近裸片的第一连接层中的基板CTE接近裸片的CTE，解决了封装结构本身的可靠性应力问题，且可以设置靠近PCB的目标连接层中基板的CTE接近PCB的CTE，解决了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。并且，连接层中基板的CTE在裸片与PCB之间不断递增，进一步提高了封装结构本身的可靠性，降低了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。
第五方面，本申请的实施例提供了一种电子设备，包括：
如第一方面所述的封装结构、或者如第三方面所述的封装结构；
印制电路板PCB，所述封装结构与所述PCB电连接。
通过第五方面所提供的电子设备，由于封装结构本身具有成本低，可靠性好，可以降低电子设备的成本，提高电子设备的可靠性。且由于封装结构中重布线层的层数不再受限，可以满足电子设备的多裸片高密度互连需求。
根据下面参考附图对示例性实施例的详细说明，本申请的其它特征及方面将变得清楚。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本申请的示例性实施例、特征和方面，并且用于解释本申请的原理。
图1示出相关技术中封装结构的结构示意图。
图2A-图2C示出根据本申请一实施例的一种封装结构的结构示意图。
图3A、图3B示出根据本申请一实施例的另一种封装结构的结构示意图。
图4示出根据本申请一实施例的一种封装结构的制造方法的制造过程示意图。
图5示出根据本申请一实施例的另一种封装结构的制造方法的制造过程示意图。
图6A-图6C示出根据本申请一实施例的又一种封装结构的结构示意图。
图7A、图7B示出根据本申请一实施例的再一种封装结构的结构示意图。
图8示出根据本申请一实施例的又一种封装结构的制造方法的制造过程示意图。
图9示出根据本申请一实施例的再一种封装结构的制造方法的制造过程示意图。
附图标记说明：
1相关技术中的封装结构；2、3、4、5本申请的封装结构；
10裸片；101第一凸块；
21第一塑封层；22第二塑封层；23第三塑封层；24第四塑封层；25第五塑封层；26第六塑封层；2n第n塑封层；2m第m塑封层；
31第一填充层；32第二填充层；33第三填充层；34第四填充层；35第五填充层；
41第一连接层；42第二连接层；43第三连接层；44第四连接层；45第五连接层；
411、421、431、441、451、4n1、4m1重布线层；414、424、434、444、454布线；
412、422、432、442、452、4n2、4m2基板；K过孔；413、423、443第三凸块；
50第二凸块；
70第一重布线层；701第四凸块。
具体实施方式
以下将参考附图详细说明本申请的各种示例性实施例、特征和方面。附图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本申请，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本申请同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本申请的主旨。
图1示出相关技术中封装结构的结构示意图。如图1所示，相关技术中，封装结构1中的裸片通过芯片的凸块与重布线层RDL互连，RDL通过利用C4法(Controlled Collapsed Chip Connection)制造的焊球(可简称C4 bump)与封装结构1的封装基板互连。封装结构1再通过封装基板上的锡球(solder ball)与所要连接的PCB互连。而如图1所示的方式在RDL的层数超过5层后封装结构1的良率降低，会造成很大的良率损失，导致封装结构1的成本急剧上升。并且，FO异质集成方案中RDL下方的C4 bump仍然需要和封装基板相连，而由于容量、带宽需求的不断提高，RDL的尺寸不断增大导致封装基板尺寸也需要不断增大，使得封装基板良率不断下降，封装基板的交期(封装基板从下订单委托生产到生产完成交付封装基板的时间)被不断拉长，导致封装基板价格越来越高。再有相关技术中因为先进工艺节点(特征尺寸小的工艺)的使用，裸片内ELK强度越来越低，封装结构1和裸片之间的可靠性应力问题(Chip Package Integration，CPI)越来越严重。而为了缓解这个问题，相关技术中通过使用低CTE的封装基板。但低CTE的封装基板会和PCB的CTE发生较大的失配，导致封装结构1安装到PCB上之后长时间锡球蠕变，引发锡球破裂等可靠性问题(Package Board interaction，PBI)，封装基板的选择很难兼顾裸片和PCB的不同CTE需求。
而为解决相关技术中所存在的问题，本申请提供了一种封装结构及其制造方法。图2A-图2C示出根据本申请一实施例的一种封装结构的结构示意图。如图2A-图2C所示，该封装结构2包括：第一塑封层21、至少两个裸片10、多个连接层和第一填充层(Underfill)31。其中，封装结构2中可以如图2A所示包括多个连接层，如连接层41、42…4n，其中，n等于封装结构2中连接层的层数。且图2B和图2C给出了封装结构2中包括两个连接层和三个连接层的结构示意图，如图2B所示的封装结构2包括第一连接层41、第二连接层42。如图2C所示的封装结构2包括第一连接层41、第二连接层42和第三连接层43。
如图2A-图2C所示，每个所述连接层包括带有多个过孔(此处以及下文中过孔可为利用硅通孔(Through Silicon Via，TSV)等技术所制造的过孔)的基板、以及覆盖在所述基板的第一面且与所述多个过孔电连接的重布线层(例如，如图2A-图2C中第一连接层41包括重布线层411和基板412，基板412上设置有多个过孔K)，所述基板具有相对设置的所述第一面(覆盖有重布线层的一面)和第二面，且每个连接层中的基板均为玻璃基板。
如图2A-图2C所示，所述第一塑封层21用于至少部分包裹每个所述裸片10，且每个所述裸片10的多个第一凸块101被暴露出所述第一塑封层21。
如图2A-图2C所示，所述第一连接层41设置在所述第一塑封层21暴露出每个所述裸片10的多个第一凸块101的一面，所述第一连接层41中的重布线层411靠近所述第一塑封层21，且每个所述裸片10的多个第一凸块101电连接到所述第一连接层41中重布线层411的 布线，所述第一填充层31用于填充所述第一连接层41与每个所述裸片10之间的空间。也即第一填充层31填充在重布线层411与每个裸片10之间的空间。
如图2A-图2C所示，所述第二连接层42设置在所述第一连接层41中基板412的第二面，所述第二连接层42中的重布线层421靠近所述第一连接层41，且所述第一连接层41中基板412上的多个过孔K与所述第二连接层42中重布线层421中的布线电连接。
在一种可能的实现方式中，如图2C所示，所述多个连接层还可以包括：第三连接层43。第三连接层43设置在所述第二连接层42中基板422的第二面，所述第三连接层43中的重布线层431靠近所述第二连接层42，且所述第三连接层43中重布线层431的布线与所述第二连接层42中基板422上的多个过孔K电连接。
其中，如图2A-图2C所示，所述封装结构2还包括多个第二凸块50，所述多个第二凸块50设置在多个连接层中与第一塑封层21之间的距离最远的连接层(也即多个连接层中最外层的连接层)中基板的第二面，且每个第二凸块50覆盖在基板上对应的过孔上，与所覆盖的过孔电连接。例如图2A、图2B、图2C所示3种封装结构2中，图2A中的多个第二凸块50设置于连接层4n的基板4n2的第二面，图2B中的多个第二凸块50设置于第二连接层42的基板422的第二面，图2C中的多个第二凸块50设置于第三连接层43的基板432的第二面。
其中，如图2A-图2C所示，封装结构2的多个连接层中除设置有多个第二凸块50的连接层之外的其他连接层(如图2A-图2C中的第一连接层41、图2A中的第二连接层42)还包括多个第三凸块，每个第三凸块设置于所在连接层的基板的第二面，且每个第三凸块覆盖在基板上对应的过孔上并与所覆盖的过孔电连接。例如，如图2A-图2C中的第一连接层41中基板412的第二面上的多个第三凸块413，图2A中的第二连接层42中基板422的第二面上的多个第三凸块423。这样，在进行第一连接层41与每个裸片10、连接层之间进行电连接时，可以直接利用第三凸块进行焊接，能提高第一连接层41与每个裸片10之间、连接层之间电连接的稳固性。
其中，第三凸块以及上述第一凸块、第二凸块可以是钎料凸块(Solder Bump)，如锡基合金为原料的焊锡凸块、原料包括铜的铜柱凸块(Copper Pillar Bump)等等，本申请对此不作限制。
其中，各重布线层中包括布线和用于包裹布线的介电层。并且，每个连接层中重布线层远离所覆盖的基板的一面上至少部分布线被裸露出介电层，以使得被裸露的布线可以与第一凸块或第三凸块通过焊接等方式电连接到一起。介电层的材料可以是聚酰亚胺(Polyimide，PI)、聚对苯撑苯并二噁唑纤维(Poly-p-phenylene benzobisoxazole，PBO)、ABF(Ajinomoto Build-up Film)等介电材料，布线可以是铜等金属材料，本申请对此不作限制。
相比于技术中在封装基板上制备封装结构的重布线层，受成本以及良率的限制重布线层的层数受限在5层以内，在本申请所提供的封装结构中用包括重布线层和玻璃基板的多个连接层代替了相关技术中的重布线层，就可以根据重布线需要对封装结构中连接层的层数进行设置，成本以及良率不再受限，也即在包括玻璃基板的连接层作用下，可以使得封装结构中重布线层的层数不再受限，可以满足不断提高的封装结构中多裸片的高密度互连需求。且由于封装结构中以玻璃基板代替相关技术中成本高的封装基板，显著降低了封装结构的成本。另一方面，封装结构中包括多个玻璃基板可以提高封装结构的可靠性，还可以降低封装结构 与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。
在本申请中，可以在封装结构2的连接层之间增设填充层，提高连接层之间电连接的可靠性和稳定性，增强封装结构的抗跌落性能，进而可以提高封装结构的可靠性和结构稳定性。例如，如图2B、图2C所示，所述封装结构2还可以包括第二填充层32。所述第二填充层32用于填充所述第一连接层41和所述第二连接层42之间的空间，也即用于填充所述第二个连接层42的重布线层421与所述第一个连接层41的基板412之间的空间。这样，在第一连接层和第二连接层之间填充第二填充层，如图2C所示，所述封装结构2还可以包括第三填充层33。所述第三填充层33用于填充所述第二连接层42和所述第三连接层43之间的空间，也即用于填充所述第三个连接层43的重布线层431与所述第二个连接层42的基板422之间的空间。
在一种可能的实现方式中，如图2A-图2C所示，所述第一塑封层21还用于包裹所述第一填充层31和所述第一连接层41，且所述第一连接层41中基板412的第二面被裸露出所述第一塑封层21。这样，可以将裸片、第一填充层、第一连接层塑封在一起，可以增强裸片与第一连接层之间电连接的可靠性和结构稳定性，进而提高封装结构的可靠性和结构稳定性。
图3A、图3B示出根据本申请一实施例的另一种封装结构的结构示意图。在一种可能的实现方式中，如图3A、图3B所示的封装结构3与封装结构2的区别在于，对应于每个连接层的塑封层，对应于该连接层的塑封层用于包裹该连接层以及位于该连接层上方(该连接层的设置有裸片一方)的封装结构的其他部分。
例如，如图3A所示，所述封装结构3还可以包括：第二塑封层22、第三塑封层23…第n塑封层2n。其中，n为封装结构3中连接层的层数，则塑封层的层数可以为n。则所述第二塑封层22至少用于包裹第二连接层42和所述第一塑封层21，且所述第二连接层42中基板422的第二面被裸露出所述第二塑封层22。其中，第二塑封层22还可以包裹第二填充层32。也即第二塑封层22可以将“第二连接层42、第二填充层32、第一塑封层21以及第一塑封层包裹的每个裸片10、第一填充层31和第一连接层41”塑封包裹在一个共同的空间内，可以增强封装结构的可靠性和结构稳定性。所述第三塑封层23至少用于包裹所述第三连接层43、所述第二连接层42和所述第一塑封层21，且所述第三连接层43中的基板432的第二面被裸露出所述第三塑封层23。其中，第三塑封层23还可以包裹第三填充层33。并且，封装结构3本身包括第二塑封层22，则第三塑封层23所包裹的对象则可以为第三连接层43、第三填充层33和第二塑封层。封装结构3本身仅包括第一塑封层21，则第三塑封层23所包裹的对象则可以为第三连接层43、第三填充层33、所述第二连接层42和所述第一塑封层21。也即第三塑封层23可以将“第三连接层43以及重布线层431的远离基板432的一面上的封装结构3的其他部分”塑封包裹在一个共同的空间内，可以增强封装结构的可靠性和结构稳定性。继续参照第三塑封层23的塑封方式设置塑封层对“该连接层以及位于该连接层上方的封装结构的其他部分”进行塑封，直至设置所述第n塑封层2n，其用于包裹整个封装结构，且第n连接层4n的基板4n2的第二面被裸露出第n塑封层2n。
假定n为3，则封装结构3即为如图3B所示，该封装结构3还可以包括第二塑封层22、第三塑封层23。
在本申请中，参照上述第二塑封层和第三塑封层的设置，若封装结构中连接层的数量大于3，也可以基于连接层的层数设置塑封层的个数，这样在制造封装结构的过程中，可以每 完成一个连接层的连接就对当前所制备出的未完成封装结构进行一次塑封，这样既能增强封装结构的可靠性和结构稳定性，还便于在连接层中基板的第二面制造多个第三凸块以及便于后续进行新一个连接层与未完成封装结构之间的电连接。
在一种可能的实现方式中，每个所述连接层中基板的热膨胀系数不完全相同或各不相同。且每个所述连接层中基板的热膨胀系数按照基板与各所述裸片之间的距离由近到远的顺序依次增大。举例来说，假定裸片10的热膨胀系数a，该封装结构2或3后续所要电连接的PCB的热膨胀系数为b(b＞a)，封装结构2或3需要设置6个连接层，第一连接层41、第二连接层42…第六连接层46，则可以设置41-46中基板的CTE依次为w1、w2、w3、w4、w5和w6且a≤w1＜w2＜w3＜w4＜w5＜w6≤b。这样，可以设置靠近裸片的第一连接层41中的基板412的CTE接近裸片10的CTE，解决了封装结构本身的可靠性应力问题，且可以设置靠近PCB的连接层(如图2A、图3A中的连接层4n，如图2B中的连接层42，或者如图2C、图3B中的连接层43)中基板的CTE接近PCB的CTE，解决了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。并且通过每个连接层具有不完全相同或完全不同的CTE的基板的设置，可以实现从裸片10到PCB之间的CTE不断递增，进一步提高了封装结构本身的可靠性，降低了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。
本申请还提供一种用于制造上述图2A-图2C的封装结构2的制造方法，该方法的加工工艺简单且易于实现，可以快速地制造出封装结构2。图4示出根据本申请一实施例的一种封装结构的制造方法的制造过程示意图。如图4所示，该方法包括步S11至步骤S18。其中，为清楚示意图2A-图2C的封装结构2的制造过程，图4中以制造图2C中所示出的为示例进行过程示意，则封装结构2包括三个连接层，分别为第一连接层41、第二连接层42和第三连接层43。封装结构2的制造过程为：
在步骤S11中，在提供的基板412上形成多个过孔K，所述基板412具有相对设置的第一面M1和第二面M2。
在步骤S12中，在所述基板412的第一面M1形成与所述基板412上的多个过孔K电连接的重布线层411，得到第一连接层41，该第一连接层41包括重布线层411以及基板412。其中，重布线层411远离基板412的一面还制造出裸露的、用于与多个第一凸块101电连接的布线414。并且，还可以在裸露的布线414上形成焊盘等，以便于与多个第一凸块101实现电连接。
其中，可以参照制造第一连接层41的步骤S11和步骤S12，再继续制造出封装结构2的剩余所有连接层，如第二连接层42和第三连接层43，然后再执行步骤S13。也可以制造出第一连接层41之后即执行步骤S13，而后在后续需要使用对应的连接层之前参照第一连接层的制造过程(步骤S11和步骤S12)制造出对应的连接层。如，在步骤S17、步骤S18之前分别制造出第二连接层42和第三连接层43。
在步骤S13中，将至少两个裸片10的多个第一凸块101分别电连接到第一连接层41中重布线层411(图4中仅示意性画出两个裸片10)，使得每个所述裸片10的多个第一凸块101可以分别连接到重布线层411上裸露的布线414。其中，可以采用倒装的方式将裸片10焊接到重布线层411的对应位置。
在步骤S14中，对每个所述裸片10和所述第一连接层41的重布线层411之间的空间进 行填充，形成第一填充层31。其中，可以利用底部填充胶对裸片10与重布线层411之间的空间进行填充，加热固化后形成第一填充层31(本申请其他填充层的制造方式可参考第一填充层31的制造方式)。
在步骤S15中，至少对每个所述裸片10进行塑封，形成至少部分包裹每个所述裸片10的第一塑封层21，且每个所述裸片10的多个第一凸块101被暴露出所述第一塑封层21。其中，可以如图4所示直接对所述第一连接层41、每个所述裸片10以及所述第一填充层31进行塑封，形成第一塑封层21，则所述第一塑封层21用于包裹所述第一连接层41、每个所述裸片10以及所述第一填充层31并暴露出所述第一连接层41中基板412的第二面。其中，可以利用塑封工艺实现本申请中的塑封过程。
在步骤S16中，在基板412的第二面M2上每个过孔K对应的位置分别制造出第一连接层的第三凸块413。每个第三凸块413覆盖在基板412上对应的过孔K上并与所覆盖的过孔K电连接。
在步骤S17中，在所述第一连接41中基板412的第二面M2安装所述第二连接层42，所述第二连接层42中的重布线层421靠近所述第一连接层41，以及将所述第二连接层42中重布线层421中裸露的布线424与所述第一连接层41中基板412上的多个过孔K电连接。或者也可以将步骤S16中制造出的未完成封装结构固定安装到第二连接层42的重布线层421的表面，使每个所述第三凸块413电连接到连接层42的重布线层421表面裸露的布线424。而后对第二连接层42与第一连接层41之间的空间(也即基板412与重布线层421之间的空间)填充，形成第二填充层32。再之后，在基板422的第二面M2上每个过孔K对应的位置分别制造出第三凸块423。
在步骤S18中，在所述第二连接层42中基板422的第二面M2安装所述第三连接层43，所述第三连接层43中的重布线层431靠近所述第二连接层42，以及将所述第三连接层43中重布线层431的布线434与所述第二连接层42中基板422上的多个过孔K电连接。同样，也可以将步骤S17中制造出的未完成封装结构安装到第三连接层43的重布线层431的表面，使每个所述第三凸块423电连接到连接层43的重布线层431表面裸露的布线434。而后对第三连接层43与第二连接层42之间的空间(也即基板422与重布线层431之间的空间)填充，形成第三填充层33。再之后，在基板432的第二面M2上每个过孔K对应的位置分别制造出第二凸块50，得到封装结构2。
其中，制造封装结构2的制造过程可以参见上述步骤S11-步骤S18。若封装结构2中连接层的层数为两个或大于3个，可以参照可以参照上述第二连接层、第三连接层的电连接的实现过程，继续进行其他连接层的电连接。
本申请还提供一种用于制造上述图3A-图3B的封装结构3的制造方法，其与上述制造图2A-图2C的封装结构3的制造过程相似。图5示出根据本申请一实施例的另一种封装结构的制造方法的制造过程示意图。如图5所示，制造上述图3A-图3B的封装结构3的制造方法可以包括步骤S21至步骤S32。其中，为清楚示意图3A-图3B的封装结构3的制造过程，图5中以制造图3B中所示出的封装结构3为示例进行过程示意。
步骤S21-步骤S26与上述步骤S11-步骤S16的实现过程相似，可以参照步骤S11-步骤S16，此处不予赘述。
在步骤S27中，在所述第一连接41中基板412的第二面M2安装所述第二连接层42， 所述第二连接层42中的重布线层421靠近所述第一连接层41，以及将所述第二连接层42中重布线层421中裸露的布线424与所述第一连接层41中基板412上的多个过孔K电连接。或者也可以将步骤S26中制造出的未完成封装结构固定安装到第二连接层42的重布线层421的表面，使每个所述第三凸块413电连接到第二连接层42的重布线层421表面裸露的布线424。而后对第二连接层42与第一连接层41之间的空间(也即基板412与重布线层421之间的空间)填充，形成第二填充层32。
在步骤S28中，至少对所述第二连接层42和所述第一塑封层21进行塑封，形成至少用于包裹所述第二连接层42和所述第一塑封层21的第二塑封层22，且所述第二连接层42中基板422的第二面M2被裸露出所述第二塑封层22。其中，可以如图5所示直接对第二连接层42、所述第二填充层32和第一塑封层21(也即步骤S27执行完所得到的未完成封装结构)进行塑封，形成第二塑封层22。第二塑封层22可以包裹第一塑封层21、第二填充层32和第二连接层42，并暴露出第二连接层42的基板422的第二面M2。这样，在完成一个连接层的电连接后，就可以进行塑封，可以进一步增强封装结构的可靠性和结构稳定性。
在步骤S29中，在基板422的第二面M2上每个过孔K对应的位置分别制造出第三凸块423。每个第三凸块423覆盖在基板422上对应的过孔K上并与所覆盖的过孔K电连接。
在步骤S30中，在所述第二连接层42中基板422的第二面M2安装所述第三连接层43，所述第三连接层43中的重布线层431靠近所述第二连接层42，以及将所述第三连接层43中重布线层431的布线434与所述第二连接层42中基板422上的多个过孔K电连接。同样，也可以将步骤S29中制造出的未完成封装结构固定安装到第三连接层43的重布线层431的表面，使每个所述第三凸块423电连接到第三连接层43的重布线层431表面裸露的布线434。而后对第三连接层43与第二连接层42之间的空间(也即基板422与重布线层431之间的空间)填充，形成第三填充层33。
在步骤S31中，至少对所述第三连接层43、所述第二连接层42和所述第一塑封层21进行塑封，形成至少用于包裹所述第三连接层43、所述第二连接层42和所述第一塑封层21的第三塑封层23，且所述第三连接层43中基板432的第二面被裸露出所述第三塑封层23。其中，由于步骤S28中已形成第二塑封层22，则可以如图5所示直接对步骤S30执行完所得到的未完成封装结构(也即第二塑封层22、第三连接层43、第三填充层33)进行塑封，形成第三塑封层33。第三塑封层23包裹第二塑封层22、第三填充层33和第三连接层43，并暴露出第三连接层43的基板432的第二面。
在步骤S32中，在基板432的第二面M2上每个过孔K对应的位置分别制造出第二凸块50，得到封装结构3。
其中，制造封装结构3的制造过程可以参见上述步骤S21-步骤S32。若封装结构3中连接层的层数为两个或大于3个，可以参照可以参照上述第二连接层、第三连接层的电连接的实现过程，继续进行其他连接层的电连接。其中，对于图3A、图3B所示的封装结构3，在制造过程中，每完成一层连接层的安装后均进行塑封。
在一种可能的实现方式中，在制造封装结构2或3的过程中，所述方法还包括：还可以对所述第一塑封层、第二塑封层和第三塑封层中的至少一个进行减薄处理，在形成了塑封层并进行减薄处理后再进行下一步骤，也可以完成整个封装结构制造后再进行针对塑封层的减薄处理。以减小封装结构的厚度，缩减封装结构的尺寸，使其可以安装的到给定空间更小的 电子设备中，扩大封装结构的使用范围。如图2A-图5中示出了减薄后的第一塑封层、第二塑封层、第三塑封层的厚度，其可以减薄至暴露出裸片的与设置有第一凸块的一面相对的另一面。
图6A-图6C示出根据本申请一实施例的又一种封装结构的结构示意图。如图6A-图6C所示，该封装结构4包括：第四塑封层24、至少两个裸片10、第一重布线层70、至少一个连接层、第四填充层34。封装结构4中可以如图6B所示包括一个第四连接层44。封装结构4中还可以如图6C所示包括两个连接层，如第四连接层44和第五连接层45。封装结构4中也可以如图6A所示包括多个连接层，如第四连接层44…连接层4m，其中，n-3等于封装结构4中连接层的层数。封装结构4与封装结构2的区别在于封装结构4中裸片和连接层之间增设了第一重布线层。使得封装结构4能够解决上述技术问题的前提下，由于第一重布线层可直接制备在各裸片具有第一凸块的一面，不仅能够进一步提高各裸片于第一重布线层之间的连接可靠性、提高封装结构整体的可靠性，还能够缩减封装结构的厚度。
如图6A-图6C所示，所述第四塑封层24用于至少部分包裹各每个所述裸片10，且每个所述裸片10的多个第一凸块101被暴露出所述第四塑封层24。
如图6A-图6C所示，所述第一重布线层70覆盖在所述第四塑封层24的暴露出每个所述裸片10的多个第一凸块101的第一面，且所述第一重布线层70中的布线与每个所述裸片10的多个第一凸块101电连接。
如图6A-图6C所示，每个所述连接层包括带有多个过孔的基板、以及覆盖在所述基板的第一面且与所述多个过孔电连接的重布线层(例如，如图6A、图6B、图6C中的第四连接层44，其包括重布线层441和基板442，基板442上设置有过孔K)，所述基板具有相对设置的所述第一面和(覆盖有重布线层的一面)第二面，且每个基板为玻璃基板。
如图6A-图6C所示，所述第四连接层44覆盖在所述第一重布线层70远离每个所述裸片10的一面，且所述第四连接层44的重布线层441靠近第一重布线层70。所述第四连接层44中重布线层441的布线与所述第一重布线层70的布线电连接。
如图6A-图6C所示，所述第四填充层34用于填充所述第四连接层44与所述第一重布线层70之间的空间，也即填充第一重布线层70与重布线层441之间的空间。
在一种可能的实现方式中，如图6C所示，所述至少一个连接层还包括：第五连接层45。第五连接层45，设置在所述第四连接层44中基板442的第二面，所述第五连接层45中的重布线层451靠近所述第四连接层44，且所述第五连接层45中重布线层451的布线与所述第四连接层44中基板442上的多个过孔K电连接。
其中，如图6A-图6C所示，所述封装结构4还包括多个第二凸块50(其设置位置与上文封装结构2、3中第二凸块的设置位置相似，可参考上文，此处不予赘述)。封装结构4的多个连接层中除设置有多个第二凸块50的连接层之外的其他连接层还包括多个第三凸块(如图6A、图6C中的第四连接层44包括多个第三凸块443)，每个第三凸块设置于所在连接层的基板的第二面，且每个第三凸块覆盖在基板上对应的过孔上并与所覆盖的过孔电连接。
在一种可能的实现方式中，所述封装结构4还包括填充在相邻的两个连接层之间的空间的第五填充层。例如，如图6C所示，所述封装结构4还包括第五填充层35。所述第五填充层35用于填充所述第四连接层44和所述第五连接层45之间的空间。也即，第五填充层35填充在重布线层451与基板442之间的空间。
图7A、图7B示出根据本申请一实施例的再一种封装结构的结构示意图。在一种可能的实现方式中，如图7A、图7B所示，所述封装结构5中的连接层为多个，其与封装结构4的区别在于所述封装结构5还可以包括对应于每个连接层的塑封层，对应于该连接层的塑封层用于包裹该连接层以及位于该连接层上方(该连接层的设置有裸片一方)的封装结构的其他部分。
例如，如图7A所示，封装结构5还可以包括第五塑封层25…第m塑封层2m。其中，m-3为封装结构5中连接层的层数，则塑封层的层数可以为m-2(包括第四塑封层和对应于每个连接层的塑封层)。则所述第五塑封层25至少用于包裹第四连接层44、所述第四填充层34、所述第一重布线层70和所述第四塑封层24，且所述第四连接层44中基板442的第二面被暴露出所述第五塑封层25。则所述第四连接层44、第四填充层34、所述第一重布线层70和所述第四塑封层24即为位于第四连接层44上方的封装结构的其他部分。继续参照第五塑封层25的塑封方式设置塑封层对“该连接层以及位于该连接层上方的封装结构的其他部分”进行塑封，直至设置所述第m塑封层2m，其用于包裹整个封装结构，且第m连接层4m的基板4m2的第二面被裸露出第m塑封层2m。
假定m为5，则封装结构5即为如图7B所示，该封装结构5还可以包括第五塑封层25和第六塑封层26。所述第五塑封层25至少用于包裹第四连接层44、所述第四填充层34、所述第一重布线层70和所述第四塑封层24，且所述第四连接层44中基板442的第二面被暴露出所述第五塑封层25。则所述第四连接层44、第四填充层34、所述第一重布线层70和所述第四塑封层24即为位于第四连接层44上方的封装结构的其他部分。所述第六塑封层26至少用于包裹第五连接层45、第四连接层44、所述第四填充层34、所述第一重布线层70和所述第四塑封层24，且所述第五连接层45中基板452的第二面被暴露出所述第六塑封层26。其中，第六塑封层26还可以包裹第五填充层35。则所述第五连接层45、第五填充层35、第四连接层44、所述第四填充层34、所述第一重布线层70和所述第四塑封层24即为位于第五连接层45上方的封装结构的其他部分。
这样，通过塑封层将“某一个连接层以及位于该连接层上方的封装结构的其他部分”塑封包裹在一个共同的空间内，可以增强封装结构5的可靠性和结构稳定性。
在一种可能的实现方式中，如图6A-图7B所示，至少一个所述裸片10的第二表面被暴露出所述封装结构4或5，每个所述裸片10具有相对设置的第一表面和第二表面，且每个所述裸片10的所述第一表面设置有多个第一凸块101。这样，由于尽可能的缩减了塑封层的厚度，可以减小封装结构5的厚度，缩减封装结构5的尺寸，使其可以安装的到给定空间更小的电子设备中，扩大封装结构的使用范围。
在一种可能的实现方式中，每个所述连接层中基板的热膨胀系数不完全相同或各不相同。且每个所述连接层中基板的热膨胀系数按照基板与所述第四塑封层24之间的距离由近到远的顺序依次增大。举例来说，假定裸片10的热膨胀系数a，该封装结构4或5后续所要连接的PCB的热膨胀系数为b(b＞a)。封装结构4或5需要设置3个连接层，第四连接层44、第五连接层45和第六连接层46，则可以设置第四连接层44、第五连接层45和第六连接层46中基板的CTE依次为w1、w2、w3，且a≤w1＜w2＜w3≤b。这样，可以设置靠近裸片10的第四连接层44中的基板442的CTE接近裸片10的CTE，解决了封装结构本身的可靠性应力问题，且可以设置靠近PCB的连接层(也即第六连接层)中基板的CTE接近PCB的 CTE，解决了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。并且通过各连接层具有不完全相同或完全不同的CTE的基板的设置，可以实现从裸片10到PCB之间的CTE不断递增，进一步提高了封装结构本身的可靠性，降低了封装结构与PCB之间焊接的可靠性风险，提高了封装结构与PCB之间的适配性。
本申请还提供一种用于制造上述图6A-图6C的封装结构4的制造方法，该方法的加工工艺简单且易于实现，可以快速地制造出封装结构4。图8示出根据本申请一实施例的又一种封装结构的制造方法的制造过程示意图。如图8所示，该方法包括步S41至步骤S51。其中，为清楚示意图6A-图6C的封装结构4的制造过程，图8中以制造图6C中所示出的封装结构4为示例进行过程示意，则需要制造两个连接层分别为第四连接层44和第五连接层45。制造过程为：
在步骤S41中，对至少两个裸片10进行塑封，形成第四塑封层24，所述第四塑封层24至少用于包裹每个所述裸片10且每个所述裸片10的多个第一凸块101被暴露出第四塑封层24。
在步骤S42中，在所述第四塑封层24暴露出每个所述裸片10的多个第一凸块101一面形成与每个裸片的多个第一凸块101电连接的第一重布线层70。其中，第一重布线层70远离裸片的一面还制造出裸露的布线(图中未标记)。
在步骤S43中，在第一重布线层70远离所述多个第一凸块101的一面的裸露的布线处分别制造出第四凸块701，以利用多个第四凸块701实现与后续连接层之间的电连接。
在步骤S44中，在提供的基板442上形成多个过孔K，所述基板442具有相对设置的第一面M1和第二面M2。
在步骤S45中，在所述基板442的第一面M1形成与所述基板442上的多个过孔K电连接的重布线层441，得到第四连接层44，该第四连接层44包括重布线层441以及基板442。其中，重布线层441的远离基板442的一面还制造出裸露的、用于与多个第四凸块701连接的布线444。
其中，可以参照制造第四连接层44的步骤S44和步骤S45，再继续制造出封装结构4的第五连接层，然后再执行步骤S46。也可以制造出第四连接层44之后即执行步骤S46，而后在后续需要使用对应的连接层之前参照第四连接层的制造过程(步骤S44和步骤S45)制造出对应的连接层。如，在步骤S49之前制造出第五连接层45。
在步骤S46中，将步骤S43制造的未完成封装结构固定安装到第四连接层44的重布线层441(也即在所述第一重布线层70远离所述第四塑封层24的一面安装所述第四连接层44)，并使所述第一重布线层70电连接到所述第四连接层44的重布线层441。其中，重布线层441上裸露的布线444与第一重布线层70的多个第四凸块701电连接。
在步骤S47中，对第四连接层44和所述第一重布线层70之间的空间(也即第一重布线层70与重布线层441之间的空间)进行填充，形成第四填充层34。
在步骤S48中，在所述第四连接层44的基板442的第二面M2上与所述第四连接层44的基板442中每个所述过孔K对应的位置分别形成第三凸块443，每个第三凸块443覆盖在基板442上对应的过孔K上并与所覆盖的过孔K电连接。
在步骤S49中，在所述第四连接层44中基板442的第二面安装第五连接层45，所述第五连接层45中的重布线层451靠近所述第四连接层44，以及将所述第五连接层45中重布线 层451的布线454与所述第四连接层44中基板442上的多个过孔K电连接。
在步骤S50中，而后对第五连接层45与第四连接层44之间的空间(也即基板442与重布线层451之间的空间)填充，形成第五填充层35。
在步骤S51中，在基板452的第二面M2上各过孔K对应的位置分别制造出第二凸块50，得到封装结构4。
其中，若封装结构4中连接层的层数大于2层，则在完成步骤S50之后，直接在基板452的第二面M2上各过孔K对应的位置分别制造出新的第三凸块，而后参照上述第四连接层和第五连接层的电连接的实现过程，继续进行其他连接层的电连接。
本申请还提供一种用于制造上述图7A-图7B的封装结构5的制造方法，其与上述制造图6A-图6C的封装结构4的制造过程相似。图9示出根据本申请一实施例的再一种封装结构的制造方法的制造过程示意图。如图9所示，制造上述图7A-图7B的封装结构5的制造方法可以包括步骤S61至步骤S73。其中，为清楚示意图7A-图7B的封装结构5的制造过程，图9中以制造图7B中所示出的封装结构5为示例进行过程示意。
在步骤S61-步骤S67与上述步骤S41-步骤S47的实现过程相似，可以参照步骤S41-步骤S17，此处不予赘述。
在步骤S68中，对第四连接层44、所述第四填充层34、第一重布线层70和第四塑封层24进行塑封，形成第五塑封层25，其中，所述第五塑封层25用于包裹第四连接层44、所述第四填充层34、第一重布线层70和第四塑封层24且所述第四连接层44中基板442的第二面M2被暴露出第五塑封层25。
在步骤S69中，在所述第四连接层44的基板442的第二面M2上与所述第四连接层44的基板442中各所述过孔K对应的位置分别形成第三凸块443。每个第三凸块443覆盖在基板442上对应的过孔K上并与所覆盖的过孔K电连接。
在步骤S70中，在所述第四连接层44中基板442的第二面安装第五连接层45，所述第五连接层45中的重布线层451靠近所述第四连接层44，以及将所述第五连接层45中重布线层451裸露的布线454与所述第四连接层44中基板442上的多个过孔K电连接。
在步骤S71中，而后对第五连接层45与第四连接层44之间的空间(也即基板442与重布线层451之间的空间)填充，形成第五填充层35。
在步骤S72中，对所述第五连接层45、所述第五填充层35、所述第四连接层44、所述第四填充层34、所述第一重布线层70和所述第四塑封层24进行塑封，形成第六塑封层26，且所述第五连接层45中基板452的第二面被暴露出所述第六塑封层26。也即对所述第五连接层45、所述第五填充层35和第五塑封层25进行塑封，形成第六塑封层26。
在步骤S73中，在基板452的第二面M2上各过孔K对应的位置分别制造出第二凸块50，得到封装结构5。
其中，制造封装结构5的制造过程可以参见上述步骤S61-步骤S73。若封装结构5中连接层的层数为两个或大于3个，可以参照上述第四连接层和第五连接层的电连接的实现过程，继续进行其他连接层的电连接。也即对于图7A、图7B所示的封装结构5，在制造过程中，每完成一层连接层的安装后均进行塑封。
在一种可能的实现方式中，在制造封装结构4或5的过程中，所述方法还可以包括：对所述第四塑封层、第五塑封层和/或第六塑封层进行减薄处理，可以在形成了塑封层并减薄后 再进行下一步骤，也可以完成整个封装结构制造后再进行针对“第五塑封层”、“第五塑封层和第四塑封层”、“第四塑封层、第五塑封层和第六塑封层”的减薄处理。以减小封装结构的厚度，缩减封装结构的尺寸，使其可以安装的到给定空间更小的电子设备中，扩大封装结构的使用范围。如图6A-图9中示出了减薄后的第四塑封层、第五塑封层、第六塑封层的厚度，其可以减薄至暴露出裸片的未设置有第一凸块的一面。
在本申请提供的封装结构制造方法中，可以在每完成一层连接层的安装后，就进行一次针对当前所制造的未完成封装结构的电测，以保证最终制造出的封装结构的良率。例如，在制造封装结构2时，可以在以下至少一个步骤之后进行一次电测：步骤S16、步骤S17、步骤S18。在制造封装结构3时，可以在以下至少一个步骤之后进行一次电测：步骤S26、步骤S29、步骤S32。在制造封装结构4时，可以在以下至少一个步骤之后进行一次电测：步骤S43、步骤S48、步骤S51。在制造封装结构5时，可以在以下至少一个步骤之后进行一次电测：步骤S63、步骤S69、步骤S73。
附图中的流程图和框图显示了根据本申请的多个实施例的装置、系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或指令的一部分，所述模块、程序段或指令的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。
也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行相应的功能或动作的硬件(例如电路或ASIC(Application Specific Integrated Circuit，专用集成电路))来实现，或者可以用硬件和软件的组合，如固件等来实现。
尽管在此结合各实施例对本发明进行了描述，然而，在实施所要求保护的本发明过程中，本领域技术人员通过查看所述附图、公开内容、以及所附权利要求书，可理解并实现所述公开实施例的其它变化。在权利要求中，“包括”(comprising)一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。单个处理器或其它单元可以实现权利要求中列举的若干项功能。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
以上已经描述了本申请的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (27)

  1. 一种封装结构，其特征在于，包括：第一塑封层、至少两个裸片、多个连接层和第一填充层，每个所述连接层包括带有多个过孔的基板、以及覆盖在所述基板的第一面且与所述多个过孔电连接的重布线层，所述基板具有相对设置的所述第一面和第二面，所述基板为玻璃基板，所述多个连接层包括第一连接层和第二连接层；
    所述第一塑封层用于至少部分包裹每个所述裸片，且每个所述裸片的多个第一凸块被暴露出所述第一塑封层；
    所述第一连接层设置在所述第一塑封层暴露出每个所述裸片的多个第一凸块的一面，所述第一连接层中的重布线层靠近所述第一塑封层，且每个所述裸片的多个第一凸块电连接到所述第一连接层中重布线层的布线，所述第一填充层用于填充所述第一连接层与每个所述裸片之间的空间；
    所述第二连接层设置在所述第一连接层中基板的第二面，所述第二连接层中的重布线层靠近所述第一连接层，且所述第一连接层中基板上的多个过孔与所述第二连接层中重布线层中的布线电连接。
  2. 根据权利要求1所述的封装结构，其特征在于，所述多个连接层还包括：
    第三连接层，设置在所述第二连接层中基板的第二面，所述第三连接层中的重布线层靠近所述第二连接层，且所述第三连接层中重布线层的布线与所述第二连接层中基板上的多个过孔电连接。
  3. 根据权利要求1或2所述的封装结构，其特征在于，所述封装结构还包括第二填充层和/或第三填充层，
    所述第二填充层用于填充所述第一连接层和所述第二连接层之间的空间；
    所述第三填充层用于填充所述第二连接层和所述第三连接层之间的空间。
  4. 根据权利要求1-3任意一项所述的封装结构，其特征在于，所述第一塑封层还用于包裹所述第一填充层和所述第一连接层，且所述第一连接层中基板的第二面被裸露出所述第一塑封层。
  5. 根据权利要求1-4任意一项所述的封装结构，其特征在于，所述封装结构还包括：第二塑封层和/或第三塑封层；
    所述第二塑封层至少用于包裹所述第二连接层和所述第一塑封层，且所述第二连接层中基板的第二面被裸露出所述第二塑封层；
    所述第三塑封层至少用于包裹所述第三连接层、所述第二连接层和所述第一塑封层，且所述第三连接层中的基板的第二面被裸露出所述第三塑封层。
  6. 根据权利要求1-5任意一项所述的封装结构，其特征在于，至少一个所述裸片的第二表面被暴露出所述封装结构，每个所述裸片具有相对设置的第一表面和第二表面，且每个所述裸片的所述第一表面设置有多个第一凸块。
  7. 根据权利要求1-6任意一项所述的封装结构，其特征在于，每个所述连接层中基板的热膨胀系数不同，且每个所述连接层中基板的热膨胀系数按照基板与所述第一塑封层之间的距离由近到远的顺序依次增大。
  8. 一种封装结构的制造方法，其特征在于，所述方法包括：
    在提供的多个基板上分别形成多个过孔，每个所述基板具有相对设置的第一面和第二面，每个所述基板为玻璃基板；
    在每个所述基板的第一面分别形成与所述基板上的多个过孔电连接的重布线层，得到多个连接层，每个所述连接层包括重布线层以及所述重布线层所覆盖的基板，所述多个连接层包括第一连接层和第二连接层；
    将至少两个裸片的多个第一凸块分别电连接到所述第一连接层中重布线层的布线；
    对每个所述裸片和所述第一连接层之间的空间进行填充，形成第一填充层；
    至少对每个所述裸片进行塑封，形成至少部分包裹每个所述裸片的第一塑封层，且每个所述裸片的多个第一凸块被暴露出所述第一塑封层；
    在所述第一连接层中基板的第二面安装所述第二连接层，所述第二连接层中的重布线层靠近所述第一连接层，以及将所述第二连接层中重布线层中的布线与所述第一连接层中基板上的多个过孔电连接。
  9. 根据权利要求8所述的方法，其特征在于，所述多个连接层还包括第三连接层，所述方法还包括：
    在所述第二连接层中基板的第二面安装所述第三连接层，所述第三连接层中的重布线层靠近所述第二连接层，以及将所述第三连接层中重布线层的布线与所述第二连接层中基板上的多个过孔电连接。
  10. 根据权利要求8或9所述的方法，其特征在于，所述所述第一塑封层还用于包裹所述第一填充层和所述第一连接层，且所述第一连接层中基板的第二面被裸露出所述第一塑封层。
  11. 根据权利要求8-10任意一项所述的方法，其特征在于，所述方法还包括以下至少一项操作：
    至少对所述第二连接层和所述第一塑封层进行塑封，形成至少用于包裹所述第二连接层和所述第一塑封层的第二塑封层，且所述第二连接层中基板的第二面被裸露出所述第二塑封层；
    至少对所述第三连接层、所述第二连接层和所述第一塑封层进行塑封，形成至少用于包裹所述第三连接层、所述第二连接层和所述第一塑封层的第三塑封层，且所述第三连接层中基板的第二面被裸露出所述第三塑封层。
  12. 根据权利要求8-11任意一项所述的方法，其特征在于，所述方法还包括以下至少一 项操作：
    对所述第一连接层和所述第二连接层之间的空间进行填充，形成第二填充层，所述第二塑封层还用于包裹所述第二填充层；
    对所述第二连接层和所述第三连接层之间的空间进行填充，形成第三填充层，所述第三塑封层还用于包裹所述第三填充层。
  13. 根据权利要求8-12任意一项所述的方法，其特征在于，所述方法还包括：
    对所述第一塑封层、所述第二塑封层和所述第三塑封层中的至少一个进行减薄处理。
  14. 根据权利要求8-13任意一项所述的方法，其特征在于，每个所述连接层中基板的热膨胀系数不同，且每个所述连接层中基板的热膨胀系数按照基板与每个所述裸片之间的距离由近到远的顺序依次增大。
  15. 一种封装结构，其特征在于，所述封装结构包括第四塑封层、至少两个裸片、第一重布线层、至少一个连接层和第四填充层，每个所述连接层包括带有多个过孔的基板、以及覆盖在所述基板的第一面且与所述多个过孔电连接的重布线层，所述基板具有相对设置的所述第一面和第二面，每个所述基板为玻璃基板，所述至少一个连接层包括第四连接层；
    所述第四塑封层用于至少部分包裹每个所述裸片，且每个所述裸片的多个第一凸块被暴露出所述第四塑封层；
    所述第一重布线层覆盖在所述第四塑封层的暴露出每个所述裸片的多个第一凸块的一面，且所述第一重布线层中的布线与每个所述裸片的多个第一凸块电连接；
    所述第四连接层设置在所述第一重布线层远离每个所述裸片的一面，所述第四连接层中的重布线层靠近所述第一重布线层，且所述第四连接层中重布线层的布线与所述第一重布线层的布线电连接；
    所述第四填充层用于填充所述第四连接层与所述第一重布线层之间的空间。
  16. 根据权利要求15所述的封装结构，其特征在于，所述至少一个连接层还包括：
    第五连接层，设置在所述第四连接层中基板的第二面，所述第五连接层中的重布线层靠近所述第四连接层，且所述第五连接层中重布线层的布线与所述第四连接层中基板上的多个过孔电连接。
  17. 根据权利要求15或16所述的封装结构，其特征在于，所述封装结构还包括：第五填充层，
    所述第五填充层用于填充所述第四连接层和所述第五连接层之间的空间。
  18. 根据权利要求15-17任意一项所述的封装结构，其特征在于，所述封装结构还包括：第五塑封层和/或第六塑封层；
    所述第五塑封层至少用于包裹所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层，且所述第四连接层中基板的第二面被暴露出所述第五塑封层；
    所述第六塑封层至少用于包裹所述第五连接层、所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层，且所述第五连接层中基板的第二面被暴露出所述第六塑封层。
  19. 根据权利要求15-18任意一项所述的封装结构，其特征在于，至少一个所述裸片的第二表面被暴露出所述封装结构，每个所述裸片具有相对设置的第一表面和第二表面，且每个所述裸片的所述第一表面设置有多个第一凸块。
  20. 根据权利要求15-19任意一项所述的封装结构，其特征在于，每个所述连接层中基板的热膨胀系数不同，且每个所述连接层中基板的热膨胀系数按照基板与所述第四塑封层之间的距离由近到远的顺序依次增大。
  21. 一种封装结构的制造方法，其特征在于，所述方法包括：
    对至少两个裸片进行塑封，形成用于至少部分包裹每个所述裸片的第四塑封层，且每个所述裸片的多个第一凸块被暴露出所述第四塑封层；
    在所述第四塑封层暴露出每个所述裸片的多个第一凸块的一面形成与每个所述裸片的芯多个第一凸块电连接的第一重布线层；
    在提供的至少一个基板上分别形成多个过孔，每个所述基板具有相对设置的第一面和第二面，每个所述基板为玻璃基板；
    在每个所述基板的第一面分别形成与所述基板上的多个过孔电连接的重布线层，得到至少一个连接层，每个所述连接层包括重布线层以及所述重布线层所覆盖的基板，所述至少一个连接层包括第四连接层；
    在所述第一重布线层远离所述第四塑封层的一面安装所述第四连接层，所述第四连接层中的重布线层靠近所述第四连接层，且所述第四连接层中重布线层的布线与所述第一重布线层的布线电连接；
    对所述第四连接层与所述第一重布线层之间的空间进行填充，形成第四填充层。
  22. 根据权利要求21所述的方法，其特征在于，所述至少一个连接层还包括第五连接层，所述方法还包括：
    在所述第四连接层中基板的第二面安装所述第五连接层，所述第五连接层中的重布线层靠近所述第四连接层，以及将所述第五连接层中重布线层的布线与所述第四连接层中基板上的多个过孔电连接。
  23. 根据权利要求21或22所述的方法，其特征在于，所述方法还包括：
    对所述第四连接层和所述第五连接层之间的空间进行填充，形成第五填充层。
  24. 根据权利要求21-23任意一项所述的方法，其特征在于，所述方法还包括以下至少一项操作：
    对所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层进行塑封， 形成用于包裹所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层的第五塑封层，且所述第四连接层中基板的第二面被暴露出所述第五塑封层；
    至少对所述第五连接层、所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层进行塑封，形成至少用于包裹所述第五连接层、所述第四连接层、所述第四填充层、所述第一重布线层和所述第四塑封层的第六塑封层，且所述第五连接层中基板的第二面被暴露出所述第六塑封层。
  25. 根据权利要求21-24任意一项所述的方法，其特征在于，所述方法还包括：
    对所述第四塑封层、第五塑封层和所述第六塑封层中的至少一个进行减薄处理。
  26. 根据权利要求21-25任意一项所述的方法，其特征在于，每个所述连接层中基板的热膨胀系数不同，且每个所述连接层中基板的热膨胀系数按照基板与所述第四塑封层之间的距离由近到远的顺序依次增大。
  27. 一种电子设备，其特征在于，包括：
    如权利要求1-7任意一项所述的封装结构、或者如权利要求15-20任意一项所述的封装结构；
    印制电路板PCB，所述封装结构与所述PCB电连接。
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CN107078118A (zh) * 2014-08-27 2017-08-18 思科技术公司 插入器到封装基板的耦合
CN110400781A (zh) * 2019-07-31 2019-11-01 苏州甫一电子科技有限公司 基于玻璃衬底的三维集成封装转接板及其制作方法
CN111987062A (zh) * 2019-05-22 2020-11-24 中芯长电半导体（江阴）有限公司 半导体封装结构及其制备方法

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CN103178047A (zh) * 2011-12-23 2013-06-26 新科金朋有限公司 半导体器件及其制作方法
CN107078118A (zh) * 2014-08-27 2017-08-18 思科技术公司 插入器到封装基板的耦合
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