WO2022242085A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022242085A1
WO2022242085A1 PCT/CN2021/132892 CN2021132892W WO2022242085A1 WO 2022242085 A1 WO2022242085 A1 WO 2022242085A1 CN 2021132892 W CN2021132892 W CN 2021132892W WO 2022242085 A1 WO2022242085 A1 WO 2022242085A1
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WIPO (PCT)
Prior art keywords
layer
area
pixel driving
display panel
display
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PCT/CN2021/132892
Other languages
English (en)
French (fr)
Inventor
方飞
刘珂
石领
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2022242085A1 publication Critical patent/WO2022242085A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.
  • FDC full-screen display camera
  • built-in pixel circuit the display quality inside the FDC area is poor.
  • the purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art, provide a display panel and a display device, and improve display quality.
  • a display panel including a display area and a peripheral area surrounding the display area; a binding area is provided on one side of the peripheral area; the display area includes an adjacent second A display area and a second display area; the light transmittance of the second display area is greater than the light transmittance of the first display area;
  • the display panel includes a plurality of pixel driving circuits, and includes data leads for loading data voltages to the pixel driving circuits;
  • the capacitance values of the storage capacitors of the pixel driving circuits sequentially connected to the same data lead line gradually change.
  • the capacitance value of the storage capacitor of each of the pixel driving circuits in the second display area and connected to the same data lead gradually decreases.
  • the display panel further includes scanning wires for loading scanning signals to the pixel driving circuit
  • the capacitance values of the storage capacitors of the respective pixel driving circuits sequentially connected to the same scanning wire are the same.
  • the storage capacitor of the pixel driving circuit includes multi-layer electrode plates sequentially stacked on one side of the substrate of the display panel;
  • the electrode plates of the odd-numbered layers are electrically connected to each other, and the electrode plates of the even-numbered layers are electrically connected to each other; the electrode plates of two adjacent layers overlap each other and are electrically insulated; the storage capacitor
  • the total overlapping area of the electrode plates is the sum of the overlapping areas between any two adjacent layers of the electrode plates;
  • the total overlapping area of the plates of the storage capacitors of the pixel driving circuits connected to the same data lead wire in the second display area decreases gradually.
  • the number of electrode plates of the storage capacitor of the pixel driving circuit is four layers.
  • the overlapping area between the electrode plates of the first layer and the electrode plates of the second layer is the first overlapping area; the electrode plates of the second layer and the electrode plates of the third layer The overlapping area between the electrode plates is the second overlapping area; the overlapping area between the electrode plates of the third layer and the electrode plates of the fourth layer is the third overlapping area;
  • the first overlapping area, the second overlapping area and the third At least one of the overlapping areas decreases gradually.
  • the pixel driving circuit includes a driving transistor for generating a driving current; the first layer electrode plate of the storage capacitor is multiplexed as the gate of the driving transistor;
  • the area of the first-layer electrode plates of the storage capacitors of the pixel driving circuits connected to the same data lead wire in the second display area remains unchanged.
  • the display panel includes a pixel driving area for setting each of the pixel driving circuits
  • the area of the pixel driving area in the second display area is smaller than the area of the pixel driving area in the first display area.
  • the display panel includes signal wires connecting adjacent pixel driving circuits
  • the material of the part of the signal line outside the pixel driving area is a transparent conductive material.
  • the display panel includes a base substrate, a semiconductor layer, a first gate layer, a second gate layer, a first source-drain metal layer, and a second source-drain metal layer that are sequentially stacked.
  • pixel electrode layer the display panel also includes a transparent wiring layer, the transparent wiring layer is located in the semiconductor layer, the first gate layer, the second gate layer, the first source-drain metal layer , between the second source-drain metal layer and any adjacent two layers in the pixel electrode layer;
  • the part of the wiring outside the pixel driving area is located in the transparent wiring layer.
  • a display panel which includes a base substrate, a driving circuit layer, and a pixel layer that are sequentially stacked;
  • the pixel layer is provided with sub-pixels, and the driving circuit layer is provided with a pixel driving circuit for driving the sub-pixels;
  • the driving circuit layer includes a thin film transistor and a storage capacitor;
  • the storage capacitor includes multilayer electrode plates stacked in sequence; the electrode plates of the odd-numbered layers are electrically connected to each other, and the electrode plates of the even-numbered layers are electrically connected to each other; the electrode plates of two adjacent layers are electrically connected to each other. overlap each other and are electrically insulated; at least part of the storage capacitor includes more than two layers of the electrode plates.
  • At least part of the storage capacitor includes four layers of the electrode plates.
  • At least part of the storage capacitor includes two layers of the electrode plates.
  • the display panel includes a display area and a peripheral area surrounding the display area; the display area includes an adjacent first display area and a second display area; the second display area The light transmittance is greater than the light transmittance of the first display area;
  • the first display area is provided with a first pixel drive circuit
  • the second display area is provided with a second pixel drive circuit.
  • the storage capacitor of the first pixel driving circuit includes two layers of electrode plates.
  • the storage capacitor of the second pixel driving circuit includes four layers of electrode plates.
  • the display panel includes a first pixel driving region for setting the first pixel driving circuit and a second pixel driving region for setting the second pixel driving circuit;
  • the area of the second pixel driving region is smaller than the area of the first pixel driving region.
  • the display panel includes signal wires connecting adjacent pixel driving circuits
  • the material of the part of the signal line outside the second pixel driving area is a transparent conductive material.
  • the display panel includes a base substrate, a semiconductor layer, a first gate layer, a second gate layer, a first source-drain metal layer, and a second source-drain metal layer that are sequentially stacked.
  • pixel electrode layer the display panel also includes a transparent wiring layer, the transparent wiring layer is located in the semiconductor layer, the first gate layer, the second gate layer, the first source-drain metal layer , between the second source-drain metal layer and any adjacent two layers in the pixel electrode layer;
  • the part of the signal wiring outside the second pixel driving area is located in the transparent wiring layer.
  • the driving circuit layer includes a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, and a second gate insulating layer stacked on one side of the substrate in sequence.
  • Two gate layers an interlayer dielectric layer, a first source-drain metal layer, a first planarization layer, a second source-drain metal layer, and a second planarization layer;
  • the driving circuit layer also includes a transparent wiring layer, and the transparent The wiring layer is disposed in the semiconductor layer, the first gate layer, the second gate layer, the first source-drain metal layer, the second source-drain metal layer and the pixel electrode layer Between any two adjacent layers;
  • the multi-layer electrode plates of the storage capacitor are respectively located on the first gate layer, the second gate layer, the first source-drain metal layer, the second source-drain metal layer, the transparent wiring Multiple layers of layers.
  • the driving circuit layer includes a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second Two gate layers, an interlayer dielectric layer, a first source-drain metal layer, a first planarization layer, a second source-drain metal layer and a second planarization layer;
  • the multi-layer electrode plates of the storage capacitor are respectively located in multiple layers of the first gate layer, the second gate layer, the first source-drain metal layer, and the second source-drain metal layer.
  • a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 3 is a partial cross-sectional structural schematic diagram of a display panel in an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display device in an embodiment of the present disclosure.
  • FIG. 5 is a schematic cross-sectional structure diagram of a storage capacitor in an embodiment of the present disclosure, in which only the electrical connections and overlapping positions of the four-layer electrode plates are shown.
  • FIG. 6 is a schematic cross-sectional structure diagram of a storage capacitor in an embodiment of the present disclosure, in which only the electrical connections and overlapping positions of four-layer electrode plates are shown.
  • FIG. 7 is a schematic diagram of a partial structure of a transparent wiring layer in a second display area in an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a partial structure of a transparent wiring layer and a first gate layer in a second display region in an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a partial structure of a transparent wiring layer and a second gate layer in a second display region in an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a partial structure of a transparent wiring layer and a second source-drain metal layer in a second display region in an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a pixel driving region of a polysilicon semiconductor layer in a second display region in an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a pixel driving region of the first gate layer in the second display region in an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a pixel driving region of the second gate layer in the second display region in an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a pixel driving region of the first source-drain metal layer in the second display region in an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a pixel driving region of a transparent wiring layer in a second display region in an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of a pixel driving region of a transparent wiring layer in the second display region in an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of a pixel driving region of the second display region of the second source and drain metal layer in an embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of an equivalent circuit of a pixel driving circuit in an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of the electrical connection relationship of the pixel driving circuit in the second display area in an embodiment of the present disclosure.
  • the shaded rectangle marked by Cst represents the capacitance value of the storage capacitor; the larger the rectangle, the larger the capacitance value.
  • FIG. 20 is a schematic structural diagram of a pixel driving region in an embodiment of the present disclosure.
  • PNL display panel
  • AA display area
  • BB peripheral area
  • B1 binding area
  • A1 first display area
  • C100 pixel drive circuit
  • C200 light-emitting element
  • C300 photosensitive component
  • F100 base substrate
  • F200 driving circuit layer
  • F300 pixel layer
  • Cst storage capacitor
  • CP1 first layer electrode plate
  • CP3, third layer electrode plate Four-layer electrode plate
  • Data data voltage
  • DataL data lead; GL, scan lead; GL1, first scan sub-lead; GL2, second scan sub-lead
  • Gate scan signal
  • EM light control signal
  • EML light Control lead
  • EML1 first light-emitting control sub-lead
  • EML2 second light-emitting control sub-lead
  • ReL reset lead
  • ReL1 first reset sub-lead
  • Reset reset signal
  • Vinit initialization Signal
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • FIG. 1 and FIG. 2 are top structural views of the display panel PNL provided by the present disclosure.
  • the display panel PNL may include a display area AA and a peripheral area BB surrounding the display area AA; the display area AA may include a first display area A1 and a second display area A2 disposed adjacently. Wherein, the light transmittance of the second display area A2 is greater than the light transmittance of the first display area A1.
  • FIG. 3 is a schematic diagram of a partial structure of the display panel PNL provided by the present disclosure.
  • the display panel can be provided with light-emitting elements C200 in both the first display area A1 and the second display area A2, so that both the first display area A1 and the second display area A2 can realize screen display.
  • a display device to which the display panel PNL is applied may include at least one photosensitive element C300.
  • the photosensitive component C300 can be provided in one-to-one correspondence with the second display area A2, and the photosensitive component C300 can face the corresponding second display area A2, so as to receive light transmitted from the second display area A2.
  • the photosensitive component C300 may have a photosensitive area for sensing light, and the orthographic projection of the photosensitive area on the base substrate F100 may be located in the second display area A2.
  • the photosensitive component C300 may be one or more light sensors, such as a camera, an optical fingerprint recognition chip, a light intensity sensor, and the like.
  • the photosensitive component C300 can be a camera, for example, a CCD (Charge Coupled Device) camera; in this way, the display device can realize off-screen photography and increase the screen-to-body ratio of the display device.
  • CCD Charge Coupled Device
  • the second display area A2 may be embedded in the first display area A1 , that is, the first display area A1 surrounds the second display area A2 .
  • the second display areas A2 may be scattered or adjacent to each other.
  • the second display area A2 may also be located on one side of the first display area A1; for example, the edge of the second display area A2 may partially overlap with the inner edge of the peripheral area BB, The second display area A2 is arranged at the edge of the display area AA.
  • any second display area A2 may be a circle, a square, a rhombus, a regular hexagon or other shapes.
  • the second display area A2 may be circular in shape.
  • the number of the second display area A2 can be one or more, whichever meets the configuration of the photosensitive component C300. In one embodiment of the present disclosure, the number of the second display area A2 is one. In this way, the display device may be provided with an under-screen photosensitive component C300, for example, an under-screen camera or an under-screen optical fingerprint recognition chip may be provided. In another embodiment of the present disclosure, there are multiple second display areas A2. In this way, the display device can be provided with multiple photosensitive components C300, and any two photosensitive components C300 can be the same or different. For example, referring to FIG. 2 , there are three second display areas A2 arranged adjacently.
  • the display device may be provided with different photosensitive components C300 corresponding to the three second display areas A2 one-to-one, for example, three different photosensitive components C300 are provided with an imaging camera, a depth-field camera, and an infrared camera.
  • the display panel is provided with a pixel driving circuit C100 for driving light-emitting elements, and an output terminal of the pixel driving circuit C100 is used to electrically connect with pixel electrodes of corresponding light-emitting elements.
  • the pixel driving circuit C100 can be distributed in the first display area A1 and the second display area A2, wherein the pixel driving circuit C100 in the first display area can be used to drive the light emitting element C200 in the first display area A1,
  • the pixel driving circuit C100 located in the second display area A2 can be used to drive the light emitting element C200 located in the second display area A2.
  • the light emitting element C200 may include a first light emitting element C201 located in the first display area A1 and a second light emitting element C202 located in the second display area A2;
  • the pixel driving circuit C100 may include a first light emitting element C201 for driving the first light emitting element C201.
  • the first pixel driving circuit C101 can be set in the first display area A1
  • the second pixel driving circuit C102 can be set in the second display area A2.
  • the display panel includes signal wires connected to the pixel driving circuit, so as to load corresponding signals to the pixel driving circuit.
  • these signal wires may include a scan lead GL for loading a scan signal Gate, a data lead DataL for loading a data voltage Data, a first power lead VDDL for loading a first power voltage VDD, and the like.
  • the display panel may also include other signal wires.
  • the signal routing of the display panel may also include a reset lead ReL for loading the reset signal Reset and a reset lead ReL for loading the initialization signal Vinit's initialization lead ViL.
  • the signal wiring of the display panel may further include light emission control leads EML for loading the light emission control signal EM.
  • the pixel driving circuit C100 may include a storage capacitor Cst, a data writing transistor and a driving transistor.
  • the driving transistor M1 can be loaded with the first power supply voltage VDD and output the driving current under the control of the storage capacitor Cst.
  • the data writing transistor M2 is capable of loading the data voltage Data and writing the data voltage Data into the storage capacitor Cst under the control of the scan signal Gate. Therefore, the data writing transistor M2 needs to be connected to the data voltage of the scan lead GL and the data lead DataL, so as to receive the scan signal Gate applied to the scan lead GL and the data voltage Data applied to the data lead DataL.
  • the extending direction of the data lines DataL may be defined as the row direction of the display panel PNL
  • the extending direction of the scanning lines GL may be defined as the column direction of the display panel PNL.
  • multiple pixel driving circuits C100 may be connected to one data lead DataL, and multiple pixel driving circuits C100 may be connected to one scanning lead GL. In this way, the display panel PNL can drive each pixel driving circuit C100 in a progressive scanning manner.
  • the peripheral area BB of the display panel PNL has a binding area B1 for electrically connecting with a driving chip or a circuit board to drive the display panel PNL. Further, the binding region is located at one end of the display panel PNL in the column direction. Furthermore, the second display area A2 is located at the end of the display area AA away from the binding area, and is set close to the edge or corner of the display area AA.
  • the display panel PNL may include a base substrate F100 , a driving circuit layer F200 , and a pixel layer F300 that are sequentially stacked.
  • the pixel driving circuit C100 may be disposed on the driving circuit layer F200
  • the light emitting element C200 may be disposed on the pixel layer F300.
  • the base substrate F100 may be a base substrate F100 of inorganic material, or may be a base substrate F100 of organic material.
  • the material of the substrate F100 may be glass materials such as soda-lime scanning lead GLass, quartz glass, sapphire glass, or stainless steel, aluminum, Metal materials such as nickel.
  • the material of the substrate F100 may be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyethersulfone (Polyether sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (Polycarbonate, PC), polyethylene terephthalate (Polyethylene terephthalate, PET), Polyethylene naphthalate (PEN) or a combination thereof.
  • the base substrate F100 may also be a flexible base substrate F100, for example, the material of the base substrate F100 may be polyimide (Polyimide, PI).
  • the base substrate F100 can also be a composite of multi-layer materials.
  • the base substrate F100 can include a bottom film layer (Bottom Film), a pressure-sensitive adhesive layer, A first polyimide layer and a second polyimide layer.
  • any pixel driving circuit C100 may include a transistor and a storage capacitor.
  • the transistor can be a thin film transistor, and the thin film transistor can be a top gate thin film transistor, a bottom gate thin film transistor or a double gate thin film transistor;
  • the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low temperature polysilicon semiconductor material materials, metal oxide semiconductor materials, organic semiconductor materials or other types of semiconductor materials;
  • the thin film transistors may be N-type thin film transistors or P-type thin film transistors.
  • the thin film transistor is a low temperature polysilicon transistor.
  • the types of any two transistors may be the same or different.
  • some transistors may be N-type transistors and some transistors may be P-type transistors.
  • the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be metal oxide semiconductor materials.
  • the transistor may have a first electrode, a second electrode, and a gate, and one of the first electrode and the second electrode may be a source of the transistor and the other may be a drain of the transistor. It can be understood that the source and the drain of the transistor are two opposite concepts that can be interchanged; when the working state of the transistor changes, for example, the direction of the current changes, the source and the drain of the transistor can be interchanged.
  • the driving circuit layer F200 may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a source-drain metal layer, a planarization layer and the like stacked between the base substrate F100 and the pixel layer F300.
  • Each thin film transistor and storage capacitor may be formed of film layers such as a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a source-drain metal layer. Wherein, the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the driving circuit layer F200 may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a source-drain metal layer that are sequentially stacked.
  • the thin film transistor is a top-gate thin film transistor.
  • the driving circuit layer F200 may include a gate layer, a gate insulating layer, a semiconductor layer, an interlayer dielectric layer, and a source-drain metal layer that are sequentially stacked, so that The formed thin film transistor is a bottom gate thin film transistor.
  • the driving circuit layer F200 can also adopt a double gate layer structure, that is, the gate layer can include a first gate layer and a second gate layer, and the gate insulating layer can include a layer for isolating the semiconductor layer and the first gate.
  • the driving circuit layer F200 may include a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate electrode insulating layer, second gate layer, interlayer dielectric layer and source-drain metal layer.
  • the driving circuit layer F200 may also adopt a dual source-drain metal layer structure, that is, the source-drain metal layer may include a first source-drain metal layer and a second source-drain metal layer, and the planarization layer may include a first planarization layer and a second source-drain metal layer. Two planarization layers; the first source-drain metal layer, the first planarization layer, the second source-drain metal layer, and the second planarization layer are sequentially stacked on one side of the base substrate.
  • the driving circuit layer F200 may include a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a first A source-drain metal layer, a first planarization layer, a second source-drain metal layer and a second planarization layer.
  • the driving circuit layer F200 may further include a passivation layer, and the passivation layer may be disposed on the surface of the source-drain metal layer away from the base substrate F100 to protect the source-drain metal layer.
  • the driving circuit layer F200 may further include a buffer material layer disposed between the base substrate F100 and the semiconductor layer, and the semiconductor layer, the gate layer, etc. are located on a side of the buffer material layer away from the base substrate F100 .
  • the material of the buffer material layer may be inorganic insulating materials such as silicon oxide and silicon nitride.
  • the buffer material layer can be a layer of inorganic material, or a layer of inorganic material stacked in multiple layers.
  • the driving circuit layer F200 may also include a transparent wiring layer.
  • part of the signal leads or part of the lead segments of the signal leads may be disposed on the transparent wiring layer, so as to increase the light transmittance of the second display area A2.
  • the pixel layer F300 may be disposed on a side of the driving circuit layer F200 away from the base substrate F100, and it may be disposed with a light emitting element C200 as a sub-pixel of the display panel PNL.
  • the light-emitting element C200 can be OLED (organic electroluminescent diode), Micro LED (micro light-emitting diode), Mini LED (miniature light-emitting diode), QD-OLED (quantum dot-organic electroluminescent diode) or other current-driven light emitting element.
  • OLED organic electroluminescent diode
  • Micro LED micro light-emitting diode
  • Mini LED miniature light-emitting diode
  • QD-OLED quantum dot-organic electroluminescent diode
  • the structure of the pixel layer is briefly introduced. It can be understood that the structure of the pixel layer may also be other structures, subject to the light emitting element C200 capable of providing current driving.
  • the pixel layer may include a pixel electrode layer, a pixel definition layer, a support pillar layer, an organic light-emitting functional layer and a common electrode layer which are stacked in sequence.
  • the pixel electrode layer has a plurality of pixel electrodes in the display area of the display panel;
  • the pixel definition layer has a plurality of penetrating pixel openings corresponding to the plurality of pixel electrodes in the display area, and any one of the pixel openings exposes the corresponding pixel electrode at least part of the area.
  • the support column layer includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer away from the base substrate F100, so as to support a fine metal mask (Fine Metal Mask, FMM) during the evaporation process.
  • the organic light emitting functional layer at least covers the pixel electrodes exposed by the pixel definition layer.
  • the organic light-emitting functional layer may include an organic electroluminescent material layer, and may include one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer or Various.
  • Each film layer of the organic light-emitting functional layer can be prepared by an evaporation process, and a fine metal mask or an open mask (Open Mask) can be used to define the pattern of each film layer during evaporation.
  • the common electrode layer can cover the organic light-emitting functional layer in the display area. In this way, the pixel electrode, the common electrode layer and the organic light-emitting functional layer located between the pixel electrode and the common electrode layer form an organic light-emitting diode, and any organic light-emitting diode can be used as a sub-pixel of the display panel.
  • the pixel layer F300 may further include a light extraction layer located on the side of the common electrode layer away from the base substrate F100, so as to enhance the light extraction efficiency of the organic light emitting diode.
  • the display panel may further include a thin film encapsulation layer.
  • the thin film encapsulation layer is disposed on the surface of the pixel layer F300 away from the base substrate F100, and may include alternately stacked inorganic encapsulation layers and organic encapsulation layers.
  • the inorganic encapsulation layer can effectively block moisture and oxygen from the outside, and prevent material degradation caused by water and oxygen intrusion into the organic light-emitting functional layer.
  • the edge of the inorganic encapsulation layer may be located in the peripheral area.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers, so as to realize planarization and weaken the stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.
  • the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer stacked on the side of the pixel layer away from the base substrate in sequence.
  • the display panel may further include a touch function layer, and the touch function layer is disposed on a side of the thin film encapsulation layer away from the base substrate for realizing touch operation of the display panel.
  • the display panel may further include an anti-reflection layer, which may be disposed on a side of the thin film encapsulation layer away from the pixel layer to reduce the reflection of the display panel on ambient light, thereby reducing the impact of ambient light on the display effect.
  • the anti-reflection layer may include a color filter layer and a black matrix layer that are stacked, so as to reduce the interference of ambient light while avoiding reducing the light transmittance of the display panel.
  • the antireflection layer may be a polarizer, such as a patterned coated circular polarizer. Further, the anti-reflection layer can be disposed on a side of the touch function layer away from the base substrate.
  • the structure of the display panel PNL in order to make the second display area A2 have greater light transmittance, the structure of the display panel PNL often leads to the setting or signal routing of the pixel driving circuit C100 in the second display area A2. There is a difference between the line and the first display area A1. On the one hand, this difference will cause a difference in the brightness of the light-emitting element C200 in the second display area A2 and the brightness of the light-emitting element C200 in the first display area A1. On the other hand, it will also cause As a result, there are large differences in the brightness of the light emitting elements C200 at different positions in the second display area A2.
  • the inventor has carried out a large number of tests, and in the tests, it was unexpectedly found that by adjusting the capacitance value of the storage capacitor Cst in the pixel drive circuit C100 (second pixel drive circuit C102) in the second display area A2 , the brightness of the light-emitting element C200 (second light-emitting element C202) in the second display area A2 can be adjusted, and the second display area A2 can be realized by adjusting the capacitance value of the storage capacitor Cst of the pixel driving circuit C100 in the second display area A2.
  • the inventors found that when the capacitance value of the storage capacitor Cst of the pixel driving circuit C100 in the second display area A2 is increased, the brightness value of the light emitting element C200 driven by the pixel driving circuit C100 can be increased; correspondingly, When the capacitance value of the storage capacitor Cst of the pixel driving circuit C100 in the second display area A2 is reduced, the brightness value of the light emitting element C200 driven by the pixel driving circuit C100 can be reduced. Based on this finding, referring to FIG.
  • the capacitance values of the storage capacitors of the pixel driving circuits C100 sequentially connected to the same data lead DataL change gradually.
  • the gradual change of the capacitance value of the storage capacitor Cst of the pixel driving circuit C100 in the second display area A2 can provide a gradual change trend for the luminance of the light emitting element C200 in the second display area A2; this gradual change trend can be compared with the second display area A2.
  • the gradient tendency of the brightness of the light emitting elements C200 originally existing in the display area A2 is canceled out, thereby making the brightness of the light emitting elements C200 in the second display area A2 uniform.
  • the display panel PNL can realize the uniform luminance of the light-emitting elements C200 in the first display area A1 and the second display area A2 through a compensation method more conveniently and better, Further, the display effect of the display panel PNL is improved.
  • the capacitance values of the storage capacitors Cst in the second display area A2 are the same; along the column direction and along the direction away from the binding area, each pixel driving circuit connected to the same data lead DataL in sequence The brightness of the light emitting element C200 driven by C100 increases sequentially. This results in non-uniform brightness of the light emitting element C200 in the second display area A2.
  • the capacitance values of the storage capacitors of the pixel driving circuits C100 connected to the same data lead DataL in the second display area gradually decrease.
  • the setting of the storage capacitor Cst in the technical solution of the present disclosure can provide a reverse gradient trend for the light-emitting brightness of the light-emitting elements C200 in the second display area A2, so that the brightness of each light-emitting element C200 in the second display area A2 Uniform brightness.
  • the capacitance values of the storage capacitors Cst in the second display area A2 are the same; they are sequentially connected to the same data lead DataL along the column direction and along the direction away from the binding area.
  • the light-emitting elements C200 driven by the respective pixel driving circuits C100 have their light-emitting luminances decrease sequentially. Then this related technical solution can be improved through the technical solution of the display panel provided in this disclosure, and then form another technical solution of this disclosure, and in this new technical solution, along the direction away from the binding area, in the second
  • the capacitance values of the storage capacitors of the pixel driving circuits C100 in the display area and connected to the same data lead line DataL gradually increase.
  • the display panel PNL includes a pixel driving area SubA for disposing pixel driving circuits C100 , and each pixel driving circuit C100 is provided in a one-to-one correspondence with each pixel driving area SubA.
  • the first electrode, the second electrode and the gate of each transistor of any one pixel driving circuit C100 are arranged in the corresponding pixel driving area SubA of the pixel driving circuit C100.
  • the area of the pixel driving area SubA in the second display area is smaller than the area of the pixel driving area SubA in the first display area.
  • the pixel driving circuit C100 in the second display area A2 can be compressed so as to reduce the area of its corresponding pixel driving area SubA, so as to prevent the pixel driving circuit C100 from blocking light and reduce the light transmittance of the second display area A2.
  • This setting method will cause the capacitance value of the storage capacitor Cst of the pixel driving circuit C100 in the second display area A2 to decrease, and then the voltage on the storage capacitor Cst will be easily affected by the scanning signal Gate that jumps on the scanning line GL.
  • this implementation mode tends to produce the following tendency: the voltage on the storage capacitor Cst in the second display area A2 (the gate voltage of the driving transistor M1) is affected by the scanning signal Gate that jumps on the scanning line GL and increases , so that the brightness of the light emitting element C200 in the second display area A2 is lower than the brightness of the light emitting element C200 in the first display area A1.
  • one or more of these tendencies can be weakened or eliminated by adjusting the capacitance value of the storage capacitor Cst in the second display area A2.
  • the trend of non-uniform brightness of the light emitting element C200 in the second display area A2 can be weakened by making the storage capacitor Cst successively decrease along the direction away from the binding area.
  • the pixel driving circuit C100 can be overcome by adjusting the capacitance value of the storage capacitor Cst in the second display area A2. Compression may have some or all of the negative effects.
  • the material of the part of the signal line outside the pixel driving area SubA is a transparent conductive material.
  • the transparent conductive material may be a transparent conductive metal oxide material, such as IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), and the like.
  • transparent conductive materials have a large square resistance; if the signal traces are made of transparent conductive materials, it will cause a large voltage drop during the transmission of the signal, which will intensify the intensity of the light-emitting elements in the second display area A2. Inhomogeneity of C200 brightness.
  • the data lead DataL is at least partly made of transparent conductive material in the second display area A2, which makes the data voltage Data have a larger voltage drop in the column direction; The actual data voltage Data received by the pixel driving circuit C100 in the fixed area is smaller and the brightness of the light emitting element is larger.
  • the brightness of the light-emitting element C200 in the second display area A2 can be made to have The trend of decreasing along the direction away from the binding region is opposite to the trend of the square resistance of the data lead DataL on the brightness of the light emitting element C200 , thereby producing a counteracting effect.
  • the technical solution of the present disclosure can not only realize the uniform brightness of the light-emitting element C200 in the second display area A2, but also use transparent conductive materials to prepare part of the lead segments of the signal leads in the second display area A2 to improve the brightness of the second display area A2. Transmittance.
  • the driving circuit layer may have a transparent wiring layer; in the second display area, the part of the signal wiring outside the pixel driving area SubA may be provided on the transparent wiring layer.
  • the driving circuit layer includes a semiconductor layer, a first gate layer, a second gate layer, a first source-drain metal layer, The second source-drain metal layer; the pixel layer is provided with a pixel electrode layer.
  • the display panel also includes a transparent wiring layer, and the transparent wiring layer is located at any adjacent two of the semiconductor layer, the first gate layer, the second gate layer, the first source-drain metal layer, the second source-drain metal layer, and the pixel electrode layer. between layers.
  • the part of the signal wiring outside the pixel driving area SubA is located in the transparent wiring layer.
  • the capacitance values of the storage capacitors of the respective pixel driving circuits C100 sequentially connected to the same scan lead GL are the same.
  • the design and manufacture of the pixel driving circuit C100 in the second display area A2 can be simplified, thereby reducing the cost of the display panel PNL.
  • the difference in luminance of the light-emitting element C200 in the second display area A2 along the row direction is small or basically no difference, so that the storage capacitor Cst of the pixel driving circuit C100 connected to the same scanning lead GL in the second display area A2 The same will not increase the brightness difference of the light emitting element C200 in the second display area A2.
  • the capacitance value of the storage capacitor Cst can be adjusted by adjusting the total overlapping area of the plates of the storage capacitor Cst.
  • the capacitance value of the storage capacitor Cst can be increased; conversely, when the total overlapping area of the plates of the storage capacitor Cst is reduced, the capacitance of the storage capacitor Cst can be increased. value decreases.
  • the storage capacitor of the pixel driving circuit C100 includes multilayer electrode plates sequentially stacked on one side of the substrate substrate of the display panel; wherein, the odd-numbered layer electrode plates are electrically connected to each other, and the even-number layer electrode plates are connected to each other. Electrically connected; two adjacent layers of electrode plates overlap each other and are electrically insulated; the total overlapping area of the electrode plates of the storage capacitor is the sum of the overlapping areas between any two adjacent layers of electrode plates.
  • the total overlapping area of the plates of the storage capacitors of the pixel driving circuits C100 connected to the same data lead DataL in the second display area gradually decreases; thus, along the direction away from the binding area In the direction of the second display area, the capacitance values of the storage capacitors of the respective pixel driving circuits C100 connected to the same data lead DataL gradually decrease.
  • the storage capacitor Cst may include four layers of electrode plates (CP1-CP4), so that the second display area A2 may be enlarged as much as possible.
  • the capacitance value of the storage capacitor Cst in the storage capacitor Cst prevents the storage capacitor Cst from being easily interfered by other signals because the capacitance value of the storage capacitor Cst is small. Further, referring to FIG. 5 and FIG. 6 , in the second display area A2, the storage capacitor Cst may include four layers of electrode plates (CP1-CP4), so that the second display area A2 may be enlarged as much as possible.
  • the capacitance value of the storage capacitor Cst in the storage capacitor Cst prevents the storage capacitor Cst from being easily interfered by other signals because the capacitance value of the storage capacitor Cst is small. Further, referring to FIG.
  • the area of the pixel driving region SubA in the second display area A2 is smaller than the area of the pixel driving area SubA in the first display area A1; in this case, the memory in the second display area A2
  • Capacitor Cst having four layers of electrode plates can reduce the difference between its capacitance value and the capacitance value of storage capacitor Cst in the first display area A1, which in turn facilitates making the light-emitting elements C200 in the first display area A1 and the second display area A2 The brightness difference is small.
  • the storage capacitor Cst in the first display area A1 may include two layers of electrode plates, for example, a first layer electrode plate CP1 located at the first gate layer and a second layer electrode plate CP2 located at the second gate layer ;
  • the electrode plate CP1 of the first layer and the electrode plate CP2 of the second layer overlap each other and are electrically insulated.
  • the storage capacitor Cst in the second display area A2 may include four layers of electrode plates, for example, a first layer electrode plate CP1 located at the first gate layer, a second layer electrode plate CP2 located at the second gate layer, and a second layer electrode plate CP2 located at the first gate layer.
  • the overlapping area between the first-layer electrode plate CP1 and the second-layer electrode plate CP2 is defined as the first overlapping area; the area between the second-layer electrode plate CP2 and the third-layer electrode plate CP3 The overlapping area is defined as the second overlapping area; the overlapping area between the electrode plate CP3 of the third layer and the electrode plate CP4 of the fourth layer is defined as the third overlapping area.
  • the storage capacitor Cst may only reduce the first overlapping area, the second overlapping area or the third overlapping area, or may reduce two of the three overlapping areas, Or all three overlapping areas are reduced.
  • the size of one or two layers of electrode plates can be reduced, or the size of one or two layers of electrode plates can be reduced. Adjust the position (as shown in Figure 5 and Figure 6, there are differences in the position of the electrode plates in Figure 5 and Figure 6), or implement the above two strategies at the same time, so as to reduce the overlap between two adjacent layers of electrode plates The area shall prevail.
  • the capacitance values of the storage capacitors of different pixel drive circuits C100 can also be adjusted in other ways, for example, the thickness of the insulating layer between the electrode plates of the storage capacitor, the dielectric constant of the insulating material can be adjusted And so on, subject to the capacitance value that can change the storage capacitor.
  • the pixel driving circuit C100 includes a driving transistor M1 for generating driving current; the first layer electrode plate CP1 of the storage capacitor is multiplexed as the gate of the driving transistor M1; direction, the area of the first-layer electrode plate CP1 of the storage capacitor of each pixel driving circuit C100 connected to the same data lead DataL in the second display area remains unchanged.
  • the performance of the driving transistor M1 of each pixel driving circuit C100 in the second display area A2 can be guaranteed to be unchanged, and the current characteristic of the driving transistor M1 can be changed to avoid increasing the brightness difference of the light emitting element C200 in the second display area A2.
  • An exemplary display panel PNL is provided as follows, in order to further explain and describe the specific structure, principle and effect of the display panel PNL of the present disclosure. It can be understood that the exemplary display panel PNL is only one of the specific feasible ways of the display panel PNL provided by the present disclosure, rather than a specific limitation on the display panel PNL of the present disclosure; the display panel PNL of the present disclosure can also It is exemplarily implemented in other ways than the display panel PNL.
  • the pixel driving circuit C100 may be a 7T1C structured pixel driving circuit C100, which may include a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, a first light emitting The control transistor M4, the second light emission control transistor M5, the first reset transistor M6, the second reset transistor M7 and the storage capacitor Cst.
  • the driving transistor M1 has a first electrode, a second electrode and a gate; wherein, the first electrode of the driving transistor M1 is connected to the first node N1, the second electrode of the driving transistor M1 is connected to the third node N3, and the gate of the driving transistor M1 is connected to The second node N2.
  • the data writing transistor M2 has a first electrode, a second electrode and a gate; wherein, the first electrode of the data writing transistor M2 is used to load the data voltage Data, and the second electrode of the data writing transistor M2 is connected to the first node N1, The gate of the data writing transistor M2 is used for loading the scan signal Gate.
  • the threshold compensation transistor M3 has a first electrode, a second electrode and a gate; wherein, the first electrode of the threshold compensation transistor M3 is connected to the second node N2, the second electrode of the threshold compensation transistor M3 is connected to the third node N3, and the threshold compensation transistor M3 The gate is used to load the scan signal Gate.
  • the first light emission control transistor M4 has a first electrode, a second electrode and a gate; wherein, the first electrode of the first light emission control transistor M4 is used to load the first power supply voltage VDD, and the second electrode of the first light emission control transistor M4 is connected to The first node N1 and the gate of the first light emission control transistor M4 are used for loading the light emission control signal EM.
  • the second light emission control transistor M5 has a first electrode, a second electrode and a gate; the first electrode of the second light emission control transistor M5 is connected to the third node N3, the second electrode of the second light emission control transistor M5 is connected to the fourth node N4, The gate of the second light emission control transistor M5 is used for loading the light emission control signal EM.
  • the first reset transistor M6 has a first electrode, a second electrode and a gate; wherein, the first electrode of the first reset transistor M6 is used to load the initialization signal Vinit, and the second electrode of the first reset transistor M6 is connected to the second node N2, The gate of the first reset transistor M6 is used for loading the reset signal Reset.
  • the second reset transistor M7 has a first electrode, a second electrode and a gate; wherein, the first electrode of the second reset transistor M7 is used to load the initialization signal Vinit, and the second electrode of the second reset transistor M7 is connected to the fourth node N4, The gate of the second reset transistor M7 is used for loading the scan signal Gate.
  • One end of the storage capacitor Cst is connected to the second node N2, and the other end is used to load the first power supply voltage VDD.
  • the pixel electrode of the light emitting element C200 may be connected to the fourth node N4, and the common electrode of the light emitting element C200 may be loaded with the second power supply voltage VSS.
  • the pixel driving circuit C100 can drive the light emitting element C200 connected to the pixel driving circuit C100 to emit light.
  • the capacitance values of the storage capacitors of the pixel driving circuits C100 connected to the same data lead DataL in the second display area gradually decrease.
  • the capacitance values of the storage capacitors of the respective pixel driving circuits C100 sequentially connected to the same scan lead GL are the same.
  • the exemplary display panel PNL includes a base substrate, a driving circuit layer and a pixel layer that are stacked in sequence.
  • the driving circuit layer includes a buffer material layer, a polysilicon semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, and a layer stacked sequentially on one side of the base substrate.
  • the pixel layer is provided with an organic electroluminescent diode as a light emitting element, and the pixel electrode of the organic electroluminescent diode is electrically connected to the pixel driving circuit C100 located in the driving circuit layer.
  • the scan leads GL include first scan sub-leads GL1 and second scan sub-leads GL2 that are alternately arranged and electrically connected in sequence.
  • the first scanning sub-lead GL1 is located in the pixel driving area SubA and is located in the first gate layer;
  • the second scanning sub-lead GL2 is located in the transparent wiring layer, and It is electrically connected to the first scanning sub-lead GL1 through a via hole.
  • the light emission control leads EML include first light emission control sub-leads EML1 and second light emission control sub-leads EML2 that are alternately arranged and electrically connected in sequence.
  • the first light emission control sub-lead EML1 is located in the pixel driving area SubA and is located in the first gate layer; referring to FIGS. 7, 8 and 15, the second light emission control sub-lead EML2 is located in the transparent wiring layer , and is electrically connected to the first light emission control sub-lead EML1 through a via hole.
  • the reset lead ReL includes a first reset sub-lead ReL1 and a second reset sub-lead ReL2 which are alternately arranged and electrically connected in sequence.
  • the first reset sub-lead ReL1 is located in the pixel driving area SubA and is located in the first gate layer; referring to FIG. 7 , FIG. 8 and FIG. 15 , the second reset sub-lead ReL2 is located in the transparent wiring layer, and It is electrically connected to the first reset sub-lead ReL1 through a via hole.
  • the initialization leads ViL include first initialization sub-leads ViL1 and second initialization sub-leads ViL2 that are alternately arranged and electrically connected in sequence.
  • the first initialization sub-lead ViL1 is located in the pixel driving area SubA and is located in the second gate layer; referring to FIG. 7, FIG. 9 and FIG. 15, the second initialization sub-lead ViL2 is located in the transparent wiring layer, and It is electrically connected to the first initialization sub-lead ViL1 through a via hole.
  • the first power supply voltage lead VDDL includes first power sub-leads VDDL1 and second power sub-leads VDDL2 that are arranged alternately and electrically connected in sequence.
  • the first power sub-lead VDDL1 is located in the pixel driving area SubA and is located in the second source-drain metal layer; referring to FIG. 7, FIG. 10 and FIG. 15, the second power sub-lead VDDL2 is located in the transparent wiring layer, And it is electrically connected to the first power supply sub-lead VDDL1 through the via hole.
  • FIG. 11 shows a schematic structural diagram of a polysilicon semiconductor layer in a pixel driving area SubA in the second display area A2.
  • the polysilicon semiconductor layer is provided with an active layer of the driving transistor M1, an active layer of the data writing transistor M2, an active layer of the threshold compensation transistor M3, and an active layer of the first light emission control transistor M4.
  • the active layer of the second light emission control transistor M5 the active layer of the first reset transistor M6 and the active layer of the second reset transistor M7
  • the conductive first conductive wiring PL1 the second conductive wiring PL2,
  • the active layer of any transistor includes a first electrode, a channel region and a second electrode connected in sequence.
  • the channel region maintains semiconductor properties
  • the first electrode, the second electrode, the first conductive wiring PL1 , the second conductive wiring PL2 , the third conductive wiring PL3 , and the fourth conductive wiring PL4 are conductive by doping.
  • 11 shows the channel region M1CNL of the driving transistor M1, the channel region M2CNL of the data writing transistor M2, the channel region (M3CNL1+M3CNL2) of the threshold compensation transistor M3, and the channel region M4CNL of the first light emission control transistor M4.
  • the positions of the channel region M5CNL of the second light emission control transistor M5 the channel region (M6CNL1+M6CNL2) of the first reset transistor M6, and the channel region M7CNL of the second reset transistor M7.
  • the channel region M2CNL of the data writing transistor M2 and the channel region M4CNL of the first light emission control transistor M4 are arranged along the column direction H2, and the channel region M4CNL of the first light emission control transistor M4 and the second light emission control transistor M5
  • the channel regions M5CNL are arranged along the row direction H1.
  • the row direction H1 includes the reversed first row direction H11 and the second row direction H12, wherein the channel region M5CNL of the second light emission control transistor M5 is located at the side of the channel region M4CNL of the first light emission control transistor M4
  • the first line is on the H11 side.
  • the column direction H2 includes a reverse first column direction H21 and a second column direction H22, wherein the channel region M4CNL of the first light emission control transistor M4 is located in the first column direction H21 of the channel region M2CNL of the data writing transistor M2. side.
  • the channel region M2CNL of the data writing transistor M2 and the channel region M4CNL of the first light emission control transistor M4 are arranged in sequence along the first column direction H21, and the two are electrically connected by a conductive first conductive wiring PL1 .
  • the first conductive wiring PL1 extends along the column direction H2, and it can be multiplexed as the second electrode of the data writing transistor M2 and the second electrode of the first light emission control transistor M4.
  • the first electrode of the data writing transistor M2 is located on the second column direction H22 side of the channel region M2CNL of the data writing transistor M2, and has a first bottom via area HA1, and the first bottom via area HA1 uses to be electrically connected to the data lead DataL through the via hole.
  • the first electrode of the first light emission control transistor M4 is located on the first column direction H21 side of the channel region M4CNL of the first light emission control transistor M4, and has a second bottom via area HA2, which is used for It is electrically connected with the first power supply voltage lead VDDL through the via hole.
  • One end of the channel region M1CNL of the driving transistor M1 is connected to the first conductive wiring PL1 and is located on the first row direction H11 side of the first conductive wiring PL1 .
  • the first conductive wiring PL1 can be used as a part of the first node N1 and multiplexed as the first electrode of the driving transistor M1.
  • the other end of the channel region M1CNL of the driving transistor M1 is connected to the conductorized second conductive wiring PL2, so that the second conductive wiring PL2 can be used as a part of the third node N3 and multiplexed as the second electrode of the driving transistor M1.
  • the second conductive wiring PL2 extends in the column direction H2 such that the channel region M1CNL of the driving transistor M1 is interposed between the first conductive wiring PL1 and the second conductive wiring PL2 .
  • One end of the second conductive wiring PL2 on the side of the first column direction H21 is connected to the channel region M5CNL of the second light emission control transistor M5, so that the second conductive wiring PL2 is multiplexed as the first electrode of the second light emission control transistor M5;
  • the second electrode of the second light emission control transistor M5 is located on the first column direction H21 side of the channel region M5CNL of the second light emission control transistor M5, and is provided with a third bottom via area HA3, which is used for It is electrically connected with the light emitting element C200 through the via hole.
  • One end of the second conductive wiring PL2 on the side of the second column direction H22 is connected to the channel region of the threshold compensation transistor M3 to be multiplexed as the second electrode of the threshold compensation transistor M3 .
  • the channel region of the threshold compensation transistor M3 includes the first channel region M3CNL1 of the threshold compensation transistor M3 and the second channel region M3CNL2 of the threshold compensation transistor M3, the first channel region M3CNL1 of the threshold compensation transistor M3 and the threshold compensation transistor M3
  • the second channel regions M3CNL2 are connected through the fourth conductive wiring PL4. Wherein, the fourth conductive wiring PL4 is bent, so that the second channel region M3CNL2 of the threshold compensation transistor M3 is disposed on the second column direction H22 side of the first channel region M3CNL1 of the threshold compensation transistor M3.
  • the gate of the threshold compensation transistor M3 may include a first gate of the threshold compensation transistor M3 overlapping with the first channel region M3CNL1 of the threshold compensation transistor M3 and a second channel region M3CNL2 of the threshold compensation transistor M3 overlapping.
  • the part of the scanning lead GL located in the first gate layer can extend along the row direction H1, and overlap with the first channel region M3CNL1 of the threshold compensation transistor M3 to be multiplexed as the first gate of the threshold compensation transistor M3; the scanning lead GL
  • the portion located on the first gate layer may also be provided with a protrusion extending along the column direction H2, and the protrusion overlaps the second channel region M3CNL2 of the threshold compensation transistor M3 to be multiplexed as a threshold compensation transistor
  • the second gate of M3. This arrangement can reduce the leakage current of the threshold compensation transistor M3 in the cut-off state, improve the voltage holding capacity of the storage capacitor Cst, and reduce the flicker risk of the display panel PNL when the display panel PNL is driven at a low frequency.
  • the first electrode of the threshold compensation transistor M3 is located on the side of the second row direction H12 of the second channel region M3CNL2 of the threshold compensation transistor M3, and is provided with a sixth bottom via area HA6, which is used for passing The via hole is electrically connected to the first electrode plate CP1 of the storage capacitor Cst. In this way, the first electrode of the threshold compensation transistor M3 and the first electrode plate CP1 of the storage capacitor Cst can serve as a part of the second node N2.
  • the channel region of the first reset transistor M6 is located on the second column direction H22 side of the channel region M3CNL of the threshold compensation transistor M3, and includes the first channel region M6CNL1 of the first reset transistor M6 and the first channel region M6CNL1 of the first reset transistor M6.
  • the second channel region M6CNL2, the first channel region M6CNL1 of the first reset transistor M6 and the second channel region M6CNL2 of the first reset transistor M6 are electrically connected through the third conductive wiring PL3.
  • the first channel region M6CNL1 of the first reset transistor M6 and the second channel region M6CNL2 of the first reset transistor M6 are sequentially arranged along the first row direction H11 .
  • the reset lead ReL located at the first gate layer may extend along the row direction H1 and overlap the first channel region M6CNL1 of the first reset transistor M6 and the second channel region M6CNL2 of the first reset transistor M6 .
  • the gate of the first reset transistor M6 includes a first gate of the first reset transistor and a second gate of the first reset transistor, and the overlapping portion of the reset lead ReL and the first channel region M6CNL1 of the first reset transistor M6 may be Multiplexed as the first gate of the first reset transistor, the overlapping portion of the reset lead ReL and the second channel region M6CNL2 of the first reset transistor M6 may be multiplexed as the second gate of the first reset transistor.
  • the second electrode of the first reset transistor M6 is multiplexed with the first electrode of the threshold compensation transistor M3, so that the first reset transistor M6 is connected to the second node N2. Since the first reset transistor M6 includes two sub-transistors in series, it has a low leakage current in the off state, which can improve the voltage holding capacity of the storage capacitor Cst and reduce the risk of flickering when the display panel PNL is driven at a low frequency .
  • the first electrode of the first reset transistor M6 is located on the side of the second electrode of the first reset transistor M6 in the first row direction H11, and can be multiplexed as the first electrode of the second reset transistor M7.
  • the first electrode of the first reset transistor M6 has a fifth bottom via area HA5, and the sixth bottom via area HA6 is used to electrically connect with the initialization lead ViL through a via hole, so that the initialization signal Vinit is loaded to the first reset transistor M6.
  • the first electrode and the first electrode of the second reset transistor M7 is used to electrically connect with the initialization lead ViL through a via hole, so that the initialization signal Vinit is loaded to the first reset transistor M6.
  • the channel region M7CNL of the second reset transistor M7 is located on the first column direction H21 side of the first electrode of the second reset transistor M7, and the second electrode of the second reset transistor M7 is located at the side of the channel region M7CNL of the second reset transistor M7.
  • the second electrode of the second reset transistor M7 is provided with a fourth bottom via area HA4, and the fourth bottom via area HA4 is used to electrically connect to the third bottom via area HA3 through via holes and other conductive structures.
  • FIG. 12 is a schematic structural diagram of the first gate layer in the pixel driving area SubA in the second display area A2.
  • the first gate layer in the second display area A2, is provided with the first reset sub-lead ReL1, the first scan sub-lead GL1, the first layer electrode plate CP1 and the first light emission control sub-lead in the pixel driving region SubA EML1, the first reset sub-lead ReL1, the first scan sub-lead GL1, the first layer electrode plate CP1 and the first light emission control sub-lead EML1 are arranged in sequence along the first column direction H21.
  • the first reset sub-lead ReL1 extends along the row direction H1 and overlaps with the first channel region M6CNL1 of the first reset transistor M6 and the second channel region M6CNL2 of the first reset transistor M6 in order to be multiplexed as the first The first gate of the reset transistor M6 and the second gate of the first reset transistor.
  • One end of the first reset sub-lead ReL1 in the second row direction H12 has the seventh bottom via area HA7
  • one end of the first reset sub-lead ReL1 in the first row direction H11 has the eighth bottom via area HA8, the seventh bottom via area HA7 and the eighth bottom via area HA8 are used to electrically connect with the second reset sub-lead ReL2 through via holes.
  • the first scanning sub-lead GL1 extends along the row direction H1 and sequentially intersects with the channel region M2CNL of the data writing transistor M2, the first channel region M3CNL1 of the threshold compensation transistor M3, and the channel region M7CNL of the second reset transistor M7. stacked, so as to be multiplexed as the gate of the data writing transistor M2, the first gate of the threshold compensation transistor M3 and the gate of the second reset transistor M7.
  • One end of the first scanning sub-lead GL1 in the second row direction H12 has the ninth bottom via area HA9
  • one end of the first scanning sub-lead GL1 in the first row direction H11 has the tenth bottom via area HA10
  • the first scanning sub-lead GL1 also has a protrusion extending toward the second column direction H22, and the protrusion overlaps the second channel region M3CNL2 of the threshold compensation transistor M3 to be multiplexed as the second gate of the threshold compensation transistor M3 .
  • the first light emission control sub-lead EML1 extends along the row direction H1 and overlaps with the channel region M4CNL of the first light emission control transistor M4 and the channel region M5CNL of the second light emission control transistor M5 in order to be multiplexed as the first light emission control sub-lead.
  • One end of the first light emission control sub-lead EML1 in the second row direction H12 has an eleventh bottom via area HA11
  • one end of the first light emission control sub-lead EML1 in the first row direction H11 has a twelfth bottom via area HA12, and a tenth bottom via area HA12.
  • the first bottom via area HA11 and the twelfth bottom via area HA12 are used for electrical connection with the second light emission control sub-lead EML2 through via holes.
  • the first-layer electrode plate CP1 overlaps the channel region M1CNL of the driving transistor M1, and has a thirteenth bottom via region HA13, which is used to communicate with the sixth bottom via hole and other conductive structures.
  • the via area HA6 is electrically connected. Further, in the row direction H1, the thirteenth bottom via area HA13 is located on the side of the first row direction H11 of the first layer electrode plate CP1; in the column direction H2, the thirteenth bottom via area HA13 is located in the first The second column direction H22 side of the layer electrode plate CP1.
  • FIG. 13 is a schematic structural diagram of the second gate layer in the pixel driving area SubA in the second display area A2.
  • the second gate layer is provided with the first initialization sub-lead ViL1 and the second-layer electrode plate CP2 in the pixel driving area SubA in the second display area A2; the first initialization sub-lead ViL1 and the second-layer electrode
  • the boards CP2 are arranged sequentially along the first column direction H21.
  • the two ends of the first initialization sub-lead ViL1 are respectively provided with the fourteenth bottom via area HA14 and the fifteenth bottom via area HA15, and the fourteenth bottom via area HA14 and the fifteenth bottom via area HA15 are respectively It is used to electrically connect with the second initialization sub-lead ViL2 through the via hole.
  • the fifteenth bottom via area HA15 is located at one end of the first initialization sub-lead ViL1 in the first row direction H11, and is also used to electrically connect with the fifth bottom via area HA5 through via holes and other conductive structures.
  • the second initialization sub-lead ViL2 extends along the row direction H1 and at least partially overlaps the third conductive wiring PL3 .
  • the second-layer electrode plate CP2 overlaps with the first-layer electrode plate CP1, and it has a notch that exposes the thirteenth via-hole area HA13, so that the thirteenth via-hole area HA13 can pass through the via located in the notch.
  • the holes are electrically connected to other conductive structures.
  • the side of the second row direction H12 of the second-layer electrode plate CP2 may at least partially overlap the first conductive wiring PL1, so as to provide electromagnetic shielding for the first conductive wiring PL1 and avoid the data voltage on the data lead DataL. The coupling effect of the Data jump on the first conductive wiring PL1.
  • the second-layer electrode plate CP2 may also be provided with an extension extending toward one side of the second column direction H22, and the extension may overlap the first scan sub-lead GL1.
  • the first source-drain metal layer is provided with a third-layer electrode plate CP3 and a fifth conductive wiring PL5 connected to the third-layer electrode plate CP3.
  • One end of the fifth conductive wiring PL5 in the second column direction H22 has a sixth top
  • the via hole area HB6, the sixth top via hole area HB6 and the sixth bottom via hole area HA6 are connected through via holes.
  • the orthographic projection of the overlapped portion of the fifth conductive wiring PL5 and the first scanning sub-lead GL1 on the second gate layer may be located in the extension of the third-layer electrode plate CP3.
  • the extension of the electrode plate CP2 on the second layer can shield the transition of the scanning signal Gate on the first scanning sub-lead GL1, so as to prevent the transition of the scanning signal Gate from being coupled to the electrode plate CP3 (second node N2) of the third layer and affecting Drives the gate voltage of transistor M1.
  • the second-layer electrode plate CP2 may be provided with a sixteenth bottom via area HA16 , and the sixteenth bottom via area HA16 is used for electrical connection with the fourth-layer electrode plate CP4 through via holes.
  • FIG. 14 shows a schematic structural view of the first source-drain metal layer in the pixel driving area SubA in the second display area A2.
  • the first source-drain metal layer may be provided with a first conductive part ML1, a second conductive part ML2, a third conductive part ML3, a fourth conductive part ML4,
  • the fifth conductive part ML5, the sixth conductive part ML6, the seventh conductive part ML7, the eighth conductive part ML8, the ninth conductive part ML9, and the fifth conductive wiring PL5, the sixth conductive wiring PL6, and the seventh conductive wiring PL7 are provided.
  • the first conductive portion ML1 overlaps the fourteenth bottom via area HA14 , which has a twenty-sixth bottom via area HA26 and a fourteenth top via area HB14 .
  • the fourteenth top via area HB14 is connected to the fourteenth bottom via area HA14 through vias.
  • the twenty-sixth bottom via area HA26 is used to connect to the second initialization sub-lead ViL2 through a via hole.
  • the twenty-sixth bottom via area HA26 and the fourteenth top via area HB14 may partially or completely overlap.
  • One end of the seventh conductive wiring PL7 in the second column direction H22 has the fifteenth top via area HB15 and the twenty-seventh bottom via area HA27, and the fifteenth top via area HB15 and the fifteenth bottom via area HA15 pass through Via connection: the twenty-seventh bottom via area HA27 is used to connect with the second initialization sub-lead ViL2 through a via.
  • the fifteenth top via area HB15 and the twenty-seventh bottom via area HA27 may partially or completely overlap.
  • the seventh conductive wiring PL7 extends along the column direction H2, and has a fifth top via area HB5 at one end in the first column direction H21, and the fifth top via area HB5 and the fifth bottom via area HA5 are connected by vias.
  • the second initialization sub-lead ViL2 can be electrically connected to the first initialization sub-lead ViL1 through the first conductive part ML1 and the seventh conductive wiring PL7, and the initialization signal Vinit loaded on the initialization lead ViL is loaded to the second reset.
  • the second conductive portion ML2 overlaps the seventh bottom via area HA7, which has a twentieth bottom via area HA20 and a seventh top via area HB7.
  • the seventh top via area HB7 and the seventh bottom via area HA7 are connected through via holes.
  • the twentieth via hole area HA20 is used to connect with the second reset sub-lead ReL2 through the via hole.
  • the twentieth bottom via area HA20 and the seventh top via area HB7 may partially or completely overlap.
  • the eighth conductive part ML8 overlaps with the eighth bottom via area HA8, and has the eighth top via area HB8 and the twenty-first bottom via area HA21, the eighth top via area HB8 and the eighth bottom via area HA8 is connected through a via hole; the twenty-first bottom via hole area HA21 is used to connect with the second reset sub-lead ReL2 through a via hole.
  • the eighth top via area HB8 and the twenty-first bottom via area HA21 may partially or completely overlap. In this way, the second reset sub-lead ReL2 can be electrically connected to the first reset sub-lead ReL1 through the transition of the second conductive part ML2 and the eighth conductive part ML8 .
  • the third conductive portion ML3 overlaps the first bottom via area HA1 , and has an eighteenth bottom via area HA18 and a first top via area HB1 .
  • the first top via area HB1 is connected to the first bottom via area HA1 through a via hole.
  • the eighteenth bottom via area HA18 is used to electrically connect with the data lead DataL through the via hole.
  • the eighteenth bottom via area HA18 and the first top via area HB1 may partially or completely overlap. In this way, the data line DataL can be connected to the first electrode of the data writing transistor M2 through the third conductive portion ML3, so that the data voltage Data applied on the data line DataL is applied to the first electrode of the data writing transistor M2.
  • the ninth conductive part ML9 overlaps the ninth bottom via area HA9 , which has a twenty-second bottom via area HA22 and a ninth top via area HB9 .
  • the ninth top via area HB9 and the ninth bottom via area HA9 are connected through via holes.
  • the twenty-second bottom via area HA22 is used to connect with the second scan sub-lead GL2 through the via hole.
  • the twenty-second bottom via area HA22 and the ninth top via area HB9 may partially or completely overlap.
  • the seventh conductive part ML7 overlaps with the tenth bottom via area HA10, and has the tenth top via area HB10 and the twenty-third bottom via area HA23, the tenth top via area HB10 and the tenth bottom via area HA10 is connected through a via hole; the twenty-third bottom via hole area HA23 is used to connect with the second scanning sub-lead GL2 through a via hole.
  • the tenth top via area HB10 and the tenth bottom via area HA10 may partially or completely overlap. In this way, the second scanning sub-lead GL2 can be electrically connected to the first scanning sub-lead GL1 through the transition of the seventh conductive part ML7 and the ninth conductive part ML9 .
  • the fifth conductive portion ML5 overlaps the eleventh bottom via area HA11 , which has a twenty-fourth bottom via area HA24 and an eleventh top via area HB11 .
  • the eleventh top via area HB11 and the eleventh bottom via area HA11 are connected through via holes.
  • the twenty-fourth bottom via area HA24 is used to connect with the second light emission control sub-lead EML2 through the via hole.
  • the twenty-fourth bottom via area HA24 and the eleventh top via area HB11 may partially or completely overlap.
  • the sixth conductive portion ML6 overlaps with the twelfth bottom via area HA12, and has a twelfth top via area HB12 and a twenty-fifth bottom via area HA25, the twelfth top via area HB12 and the twelfth via hole area
  • the bottom via hole area HA12 is connected through a via hole; the twenty-fifth bottom via hole area HA25 is used to connect with the second light emission control sub-lead EML2 through a via hole.
  • the twelfth top via area HB12 and the twenty-fifth bottom via area HA25 may partially or completely overlap. In this way, the second light emission control sub-lead EML2 can be electrically connected to the first light emission control sub-lead EML1 through the fifth conductive portion ML5 and the sixth conductive portion ML6.
  • the fourth conductive portion ML4 overlaps the second layer electrode plate CP2 and is connected to the sixth conductive wiring PL6.
  • the fourth conductive portion ML4 has a seventeenth bottom via area HA17 and a sixteenth top via area HB16 , and the sixteenth top via area HB16 and the sixteenth bottom via area HA16 are connected through via holes.
  • the seventeenth bottom via area HA17 is used to electrically connect with the first power supply voltage lead VDDL through the via hole.
  • the seventeenth bottom via area HA17 and the sixteenth top via area HB16 do not intersect.
  • the sixth conductive wiring PL6 is connected to the fourth conductive portion ML4 and is located on the first column direction H21 side of the fourth conductive portion ML4 .
  • One end of the sixth conductive wiring PL6 in the first column direction H21 has a second top via area HB2, and the second top via area HB2 is connected to the second bottom via area HA2 through via holes.
  • the first electrode of the first light emission control transistor M4 is electrically connected to the first power supply voltage lead VDDL through the sixth conductive wiring PL6 and the fourth conductive part ML4, so that the first power supply voltage VDD can be applied to the first light emission control transistor M4.
  • the electrode plate CP3 of the third layer overlaps with the electrode plate CP2 of the second layer, and has a thirteenth top via area HB13 overlapping with the thirteenth bottom via area HA13, and the thirteenth top via area HB13 overlaps with the tenth via hole area.
  • the triple-bottom via area HA13 is connected through via holes.
  • the first-layer electrode plate CP1 and the third-layer electrode plate CP3 are connected as a part of the second node N2.
  • the fifth conductive wiring PL5 is connected to the third-layer electrode plate CP3 and extends toward the second column direction H22; one end of the fifth conductive wiring PL5 in the second column direction H22 has a sixth top layer overlapping with the sixth bottom via area HA6.
  • the via hole area HB6, the sixth top via hole area HB6 and the sixth bottom via hole area HA6 are connected through via holes.
  • the third electrode plate CP3 is connected to the second electrode of the first reset transistor M6 and the first electrode of the threshold compensation transistor M3 through the fifth conductive wiring PL5.
  • Both ends of the eighth conductive wiring PL8 respectively have a fourth top via area HB4 overlapping with the fourth bottom via area HA4 and a third top via area HB3 intersecting with the third bottom via area HA3, and the fourth top via area HB3 overlaps with the third bottom via area HA3.
  • the top via area HB4 is connected to the fourth bottom via area HA4 through vias
  • the third top via area HB3 is connected to the third bottom via area HA3 through vias.
  • the second electrode of the second reset transistor M7 is connected to the second electrode of the second light emission control transistor M5 through the eighth conductive wiring PL8.
  • the eighth conductive wiring PL8 also has a first bottom via area HA19 close to the third top via area HB3, and the first bottom via area HA19 is used for electrically connecting with the light emitting element C200 through the via hole. Further, the first bottom via area HA19 and the third top via area HB3 may partially or completely overlap.
  • FIG. 15 and FIG. 16 show schematic structural diagrams of the transparent wiring layer in the second display area A2. It can be understood that, in the second display area A2, there may be certain differences in the wiring of the transparent wiring layer at different positions, as long as the required signal can be loaded to the pixel driving circuit.
  • the transparent wiring layer is provided with a second initialization sub-lead ViL2, a second reset sub-lead ReL2, a second scanning sub-lead GL2, and a second light emission control sub-lead EML2 in the second display area A2. , the data lead DataL, the second power sub-lead VDDL2 and so on.
  • the end of the second initialization sub-lead ViL2, the end of the second reset sub-lead ReL2, the end of the second scanning sub-lead GL2 and the end of the second light emission control sub-lead EML2 extend into the pixels of the second display area A2. in the driving region SubA, and connected to the corresponding wiring in the first source-drain metal layer through a via hole.
  • the second initialization sub-lead on the side of the second row direction H12 of the first initialization sub-lead ViL1 One end of the lead ViL2 in the first row direction H11 is provided with a twenty-sixth top via area HB26 overlapping with the twenty-sixth bottom via area HA26, and the twenty-sixth top via area HB26 is connected to the twenty-sixth via hole area HB26.
  • the bottom via area HA26 is connected through a via hole, which makes the second initialization sub-lead ViL2 electrically connected to the first initialization sub-lead ViL1; the second initialization sub-lead on the first row direction H11 side of the first initialization sub-lead ViL1
  • One end of the lead ViL2 in the second row direction H12 is provided with a twenty-seventh top via area HB27 overlapping with the twenty-seventh bottom via area HA27, and the twenty-seventh top via area HB27 is connected to the twenty-seventh via hole area HB27.
  • the bottom via area HA27 is connected through a via hole, which makes the second initialization sub-lead ViL2 electrically connected to the first initialization sub-lead ViL1.
  • the second initialization sub-leads ViL2 and the first initialization sub-leads ViL1 are arranged alternately and connected in sequence to form the initialization leads ViL.
  • the second reset sub-lead on the second row direction H12 side of the first reset sub-lead ReL1 Lead ReL2 one end of the first row direction H11 is provided with a twentieth top via area HB20 overlapping with the twentieth bottom via area HA20, the twentieth top via area HB20 and the twentieth bottom via area HA20 are connected through via holes, which makes the second reset sub-lead ReL2 electrically connected to the first reset sub-lead ReL1; the second reset sub-lead ReL2 on the first row direction H11 side of the first reset sub-lead ReL1, its One end of the second row direction H12 is provided with the twenty-first top via area HB21 overlapping with the twenty-first bottom via area HA21, the twenty-first top via area HB21 and the twenty-first bottom via area The HA21 are connected through via holes, which makes the second reset sub-lead ReL
  • the second scanning sub-lead on the side of the second row direction H12 of the first scanning sub-lead GL1 Lead GL2 one end of the first row direction H11 is provided with the twenty-second top via area HB22 overlapping with the twenty-second bottom via area HA22, the twenty-second top via area HB22 and the twenty-second
  • the bottom via hole area HA22 is connected through a via hole, which makes the second scanning sub-lead GL2 electrically connected to the first scanning sub-lead GL1; the second scanning sub-lead on the side of the first row direction H11 of the first scanning sub-lead GL1 Lead GL2, one end of the second row direction H12 is provided with the twenty-third top via area HB23 overlapping with the twenty-third bottom via area HA23, the twenty-third top via area HB23 is connected to the twenty
  • the first light emission controls the second light emission on the side of the second row direction H12 of the sub-lead EML1.
  • One end of the control sub-lead EML2 in the first row direction H11 is provided with a twenty-fourth top via area HB24 overlapping with the twenty-fourth bottom via area HA24, and the twenty-fourth top via area HB24 overlaps with the second Fourteen bottom via hole regions HA24 are connected through via holes, which makes the second light emission control sub-lead EML2 electrically connected to the first light emission control sub-lead EML1; the first row direction H11 side of the first light emission control sub-lead EML1
  • the second light emission control sub-lead EML2 one end of the second row direction H12 is provided with the twenty-fifth top via area HB25 overlapping with the twenty-fifth bottom via area HA25, the twenty-fifth top via area
  • the HB25 is connected to the twenty-fifth via hole region HA25 through a via hole, which makes the second light emission control sub-lead EML2 electrically connected to the first light emission control sub-le
  • the end of the second power supply sub-lead VDDL2 extends into the pixel driving area SubA in the second display area A2, and passes through the via hole and the second source-drain metal layer.
  • the first power supply sub-lead VDDL1 is connected.
  • the second power supply sub-lead VDDL2 on the second column direction H22 side of a pixel driving area SubA in the second display area A2 has a twenty-ninth bottom via area HA29 at one end in the first column direction H21;
  • the twenty-ninth bottom via area HA29 is used to connect with the first power supply sub-lead VDDL1 located in the second source-drain metal layer through a via hole;
  • the lead VDDL2 has a twenty-eighth bottom via area HA28 at one end of the second column direction H22, and the twenty-eighth bottom via area HA28 is used to pass through the via hole with the first power sub-lead VDDL1 located in the second source-drain metal layer. connect.
  • the second power supply sub-lead VDDL2 located on the side of the first column direction H21 of the pixel driving area SubA also has a seventeenth top end that overlaps the seventeenth bottom via area HA17 at one end in the second column direction H22.
  • the via hole area HB17, the seventeenth top via hole area HB17 and the seventeenth bottom via hole area HA17 are connected through via holes.
  • the data wire DataL is located in the transparent wiring layer and passes through the pixel driving area SubA along the column direction H2 .
  • the data lead DataL has an eighteenth top via area HB18 overlapping with the eighteenth bottom via area HA18 , and the eighteenth top via area HB18 is connected to the eighteenth bottom via area HA18 through a via.
  • FIG. 17 shows a schematic structural diagram of the second source-drain metal layer in a pixel driving area SubA in the second display area A2.
  • the second source-drain metal layer includes a tenth conductive part ML10 , an eleventh conductive part ML11 and a first power sub-lead VDDL1 in the pixel driving area SubA in the second display area A2 .
  • the eleventh conductive portion ML11 covers the eighteenth top via region HB18 so as to shield the interference of external signals on the data voltage Data.
  • the tenth conductive portion ML10 has a thirtieth top via area HB30 overlapping with the thirtieth bottom via area HA30 , and the thirtieth top via area HB30 is connected to the thirtieth bottom via area HA30 through a via.
  • the pixel electrode of the light emitting element C200 may be connected to the tenth conductive part ML10 through a via hole.
  • the first power supply sub-lead VDDL1 extends along the column direction H2, and has the twenty-ninth top via area HB29 overlapping with the twenty-ninth bottom via area HA29 and the twenty-eighth bottom via area HA28 at both ends.
  • the twenty-eighth top via area HB28 is connected to the twenty-eighth bottom via area HA28 through vias
  • the twenty-ninth top via area HB29 is connected to the twenty-ninth bottom via area HA29 through vias.

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Abstract

一种显示面板和显示装置，显示面板包括显示区（AA）和围绕显示区（AA）的外围区（BB）；外围区（BB）的一侧设置有绑定区（B1）；显示区（AA）包括相邻的第一显示区（A1）和第二显示区（A2）；第二显示区（A2）的透光率大于第一显示区（A1）的透光率。显示面板包括多个像素驱动电路（C100），以及包括用于向像素驱动电路（C100）加载数据电压的数据引线（DataL）；在第二显示区（A2），依次连接于同一数据引线（DataL）的各个像素驱动电路（C100）的存储电容（Cst）的电容值渐变。显示面板能够提高第二显示区（A2）的亮度均一性。

Description

显示面板和显示装置
交叉引用
本公开要求于2021年5月21日提交的申请号为202110558588.2、名称为“显示面板和显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板和显示装置。
背景技术
FDC(全屏显示摄像头)可分为像素电路内置法和外置法两种实现形式。像素电路内置时，FDC区域内部显示质量较差。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板和显示装置，提高显示质量。
根据本公开的第一个方面，提供一种显示面板，包括显示区和围绕所述显示区的外围区；所述外围区的一侧设置有绑定区；所述显示区包括相邻的第一显示区和第二显示区；所述第二显示区的透光率大于所述第一显示区的透光率；
所述显示面板包括多个像素驱动电路，以及包括用于向所述像素驱动电路加载数据电压的数据引线；
在所述第二显示区，依次连接于同一所述数据引线的各个所述像素驱动电路的存储电容的电容值渐变。
根据本公开的一种实施方式，沿远离所述绑定区的方向，在所述第二 显示区且连接于同一所述数据引线的各个所述像素驱动电路的存储电容的电容值逐渐减小。
根据本公开的一种实施方式，所述显示面板还包括用于向所述像素驱动电路加载扫描信号的扫描引线；
在所述第二显示区，依次连接于同一所述扫描引线的各个所述像素驱动电路的存储电容的电容值相同。
根据本公开的一种实施方式，所述像素驱动电路的存储电容包括依次层叠于所述显示面板的衬底基板一侧的多层电极板；
其中，第奇数层所述电极板之间相互电连接，第偶数层所述电极板之间相互电连接；相邻两层所述电极板之间相互交叠且电绝缘；所述存储电容的极板交叠总面积为任意相邻两层所述电极板之间的交叠面积之和；
沿远离所述绑定区的方向，在所述第二显示区且连接于同一所述数据引线的各个所述像素驱动电路的存储电容的极板交叠总面积逐渐减小。
根据本公开的一种实施方式，在所述第二显示区，所述像素驱动电路的存储电容的电极板的层数为四层。
根据本公开的一种实施方式，所述第一层电极板与所述第二层电极板之间的交叠面积为第一交叠面积；所述第二层电极板与所述第三层电极板之间的交叠面积为第二交叠面积；所述第三层电极板与所述第四层电极板之间的交叠面积为第三交叠面积；
沿远离所述绑定区的方向，在所述第二显示区且连接于同一所述数据引线的各个所述像素驱动电路的存储电容的第一交叠面积、第二交叠面积和第三交叠面积中的至少一个逐渐减小。
根据本公开的一种实施方式，所述像素驱动电路包括用于生成驱动电流的驱动晶体管；所述存储电容的第一层电极板复用为所述驱动晶体管的栅极；
沿远离所述绑定区的方向，在所述第二显示区且连接于同一所述数据引线的各个所述像素驱动电路的存储电容的第一层电极板的面积不变。
根据本公开的一种实施方式，所述显示面板包括用于设置各个所述像素驱动电路的像素驱动区域；
所述第二显示区中的所述像素驱动区域的面积，小于所述第一显示区 中的所述像素驱动区域的面积。
根据本公开的一种实施方式，所述显示面板包括连接相邻所述像素驱动电路的信号走线；
在所述第二显示区，所述信号走线位于所述像素驱动区域以外的部分的材料为透明导电材料。
根据本公开的一种实施方式，所述显示面板包括依次层叠设置的衬底基板、半导体层、第一栅极层、第二栅极层、第一源漏金属层、第二源漏金属层、像素电极层；所述显示面板还包括透明布线层，所述透明布线层位于所述半导体层、所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层和所述像素电极层中的任意相邻两层之间；
在所述第二显示区，所述走线位于所述像素驱动区域以外的部分位于所述透明布线层。
根据本公开的第二个方面，提供一种显示面板，所述显示面板包括依次层叠设置的衬底基板、驱动电路层和像素层；
所述像素层设置有子像素，所述驱动电路层设置有用于驱动所述子像素的像素驱动电路；所述驱动电路层包括薄膜晶体管和存储电容；
其中，所述存储电容包括依次层叠的多层电极板；第奇数层所述电极板之间相互电连接，第偶数层所述电极板之间相互电连接；相邻两层所述电极板之间相互交叠且电绝缘；至少部分所述存储电容包括多于两层的所述电极板。
根据本公开的一种实施方式，至少部分所述存储电容包括四层所述电极板。
根据本公开的一种实施方式，至少部分所述存储电容包括两层所述电极板。
根据本公开的一种实施方式，所述显示面板包括显示区和围绕所述显示区的外围区；所述显示区包括相邻的第一显示区和第二显示区；所述第二显示区的透光率大于所述第一显示区的透光率；
所述第一显示区设置有第一像素驱动电路，所述第二显示区设置有第二像素驱动电路。
根据本公开的一种实施方式，所述第一像素驱动电路的存储电容包括 两层电极板。
根据本公开的一种实施方式，所述第二像素驱动电路的存储电容包括四层电极板。
根据本公开的一种实施方式，所述显示面板包括用于设置所述第一像素驱动电路的第一像素驱动区域和用于设置所述第二像素驱动电路的第二像素驱动区域；
所述第二像素驱动区域的面积，小于所述第一像素驱动区域的面积。
根据本公开的一种实施方式，所述显示面板包括连接相邻所述像素驱动电路的信号走线；
在所述第二显示区，所述信号走线位于所述第二像素驱动区域以外的部分的材料为透明导电材料。
根据本公开的一种实施方式，所述显示面板包括依次层叠设置的衬底基板、半导体层、第一栅极层、第二栅极层、第一源漏金属层、第二源漏金属层、像素电极层；所述显示面板还包括透明布线层，所述透明布线层位于所述半导体层、所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层和所述像素电极层中的任意相邻两层之间；
在所述第二显示区，所述信号走线位于所述第二像素驱动区域以外的部分位于所述透明布线层。
根据本公开的一种实施方式，所述驱动电路层包括依次层叠于所述衬底基板一侧的半导体层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层、第一源漏金属层、第一平坦化层、第二源漏金属层和第二平坦化层；所述驱动电路层还包括透明布线层，所述透明布线层设置于所述半导体层、所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层和所述像素电极层中的任意相邻两层之间；
所述存储电容的多层电极板，分别位于所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层、所述透明布线层中的多层。
根据本公开的一种实施方式，所述驱动电路层包括依次层叠于所述衬底基板一侧的半导体层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、 第二栅极层、层间电介质层、第一源漏金属层、第一平坦化层、第二源漏金属层和第二平坦化层；
所述存储电容的多层电极板，分别位于所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层中的多层。
根据本公开的第三个方面，提供一种显示装置，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种实施方式中显示面板的结构示意图。
图2为本公开一种实施方式中显示面板的结构示意图。
图3为本公开一种实施方式中显示面板的局部剖视结构示意图。
图4为本公开一种实施方式中显示装置的剖视结构示意图。
图5为本公开一种实施方式中存储电容的剖视结构示意图，其中仅仅示意了四层电极板的电连接关系和交叠位置。
图6为本公开一种实施方式中存储电容的剖视结构示意图，其中仅仅示意了四层电极板的电连接关系和交叠位置。
图7为本公开一种实施方式中，透明布线层在第二显示区的局部结构示意图。
图8为本公开一种实施方式中，透明布线层和第一栅极层在第二显示区的局部结构示意图。
图9为本公开一种实施方式中，透明布线层和第二栅极层在第二显示区的局部结构示意图。
图10为本公开一种实施方式中，透明布线层和第二源漏金属层在第二显示区的局部结构示意图。
图11为本公开一种实施方式中，多晶硅半导体层在第二显示区的一个像素驱动区域的结构示意图。
图12为本公开一种实施方式中，第一栅极层在第二显示区的一个像素驱动区域的结构示意图。
图13为本公开一种实施方式中，第二栅极层在第二显示区的一个像素驱动区域的结构示意图。
图14为本公开一种实施方式中，第一源漏金属层在第二显示区的一个像素驱动区域的结构示意图。
图15为本公开一种实施方式中，透明布线层在第二显示区的一个像素驱动区域的结构示意图。
图16为本公开一种实施方式中，透明布线层在第二显示区的一个像素驱动区域的结构示意图。
图17为本公开一种实施方式中，第二源漏金属层在第二显示区的一个像素驱动区域的结构示意图。
图18为本公开一种实施方式中，像素驱动电路的等效电路示意图。
图19为本公开一种实施方式中，像素驱动电路在第二显示区的电连接关系原理示意图。其中，Cst所标示的具有阴影的矩形代表存储电容的电容值；该矩形越大，则表示电容值越大。
图20为本公开一种实施方式中，像素驱动区域的结构示意图。
附图标记说明：
PNL、显示面板；AA、显示区；BB、外围区；B1、绑定区；A1、第一显示区；A2、第二显示区；C100、像素驱动电路；C200、发光元件；C300、感光组件；F100、衬底基板；F200、驱动电路层；F300、像素层；Cst、存储电容；CP1、第一层电极板；CP2、第二层电极板；CP3、第三层电极板；CP4、第四层电极板；Data、数据电压；DataL、数据引线；GL、扫描引线；GL1、第一扫描子引线；GL2、第二扫描子引线；Gate、扫描信号；EM、发光控制信号；EML、发光控制引线；EML1、第一发光控制子引线；EML2、第二发光控制子引线；ReL、复位引线；ReL1、第一复位子引线；ReL2、第二复位子引线；Reset、复位信号；Vinit、初始化信号；ViL、初始化引线；ViL1、第一初始化子引线；ViL2、第二 初始化子引线；VDD、第一电源电压；VDDL、第一电源电压引线；VDDL1、第一电源子引线；VDDL2、第二电源子引线；VSS、第二电源电压；H1、行方向；H11、第一行方向；H12、第二行方向；H2、列方向；H21、第一列方向；H22、第二列方向；SubA、像素驱动区域；M1、驱动晶体管；M1CNL、驱动晶体管的沟道区；M2、数据写入晶体管；M2CNL、数据写入晶体管的沟道区；M3、阈值补偿晶体管；M3CNL1、阈值补偿晶体管的第一沟道区；M3CNL2、阈值补偿晶体管的第二沟道区；M4、第一发光控制晶体管；M4CNL、第一发光控制晶体管的沟道区；M5、第二发光控制晶体管；M5CNL、第二发光控制晶体管的沟道区；M6、第一复位晶体管；M6CNL1、第一复位晶体管的第一沟道区；M6CNL2、第一复位晶体管的第二沟道区；M7、第二复位晶体管；M7CNL、第二复位晶体管的沟道区；N1、第一节点；N2、第二节点；N3、第三节点；N4、第四节点；PL1、第一导电布线；PL2、第二导电布线；PL3、第三导电布线；PL4、第四导电布线；PL5、第五导电布线；PL6、第六导电布线；PL7、第七导电布线；PL8、第八导电布线；ML1、第一导电部；ML2、第二导电部；ML3、第三导电部；ML4、第四导电部；ML5、第五导电部；ML6、第六导电部；ML7、第七导电部；ML8、第八导电部；ML9、第九导电部；ML10、第十导电部；ML11、第十一导电部；HA1、第一底过孔区；HA2、第二底过孔区；HA3、第三底过孔区；HA4、第四底过孔区；HA5、第五底过孔区；HA6、第六底过孔区；HA7、第七底过孔区；HA8、第八底过孔区；HA9、第九底过孔区；HA10、第十底过孔区；HA11、第十一底过孔区；HA12、第十二底过孔区；HA13、第十三底过孔区；HA14、第十四底过孔区；HA15、第十五底过孔区；HA16、第十六底过孔区；HA17、第十七底过孔区；HA18、第十八底过孔区；HA19、第十九底过孔区；HA20、第二十底过孔区；HA21、第二十一底过孔区；HA22、第二十二底过孔区；HA23、第二十三底过孔区；HA24、第二十四底过孔区；HA25、第二十五底过孔区；HA26、第二十六底过孔区；HA27、第二十七底过孔区；HA28、第二十八底过孔区；HA29、第二十九底过孔区；HA30、第三十底过孔区；HB1、第一顶过孔区；HB2、第二顶过孔区；HB3、第三顶过孔区；HB4、第四顶过孔区；HB5、第 五顶过孔区；HB6、第六顶过孔区；HB7、第七顶过孔区；HB8、第八顶过孔区；HB9、第九顶过孔区；HB10、第十顶过孔区；HB11、第十一顶过孔区；HB12、第十二顶过孔区；HB13、第十三顶过孔区；HB14、第十四顶过孔区；HB15、第十五顶过孔区；HB16、第十六顶过孔区；HB17、第十七顶过孔区；HB18、第十八顶过孔区；HB19、第十九顶过孔区；HB20、第二十顶过孔区；HB21、第二十一顶过孔区；HB22、第二十二顶过孔区；HB23、第二十三顶过孔区；HB24、第二十四顶过孔区；HB25、第二十五顶过孔区；HB26、第二十六顶过孔区；HB27、第二十七顶过孔区；HB28、第二十八顶过孔区；HB29、第二十九顶过孔区；HB30、第三十顶过孔区。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开提供一种显示面板，以及提供一种包括该显示面板的显示装置。图1和图2为本公开提供的显示面板PNL的一种俯视结构图。参见图1和图2，显示面板PNL可以包括显示区AA和围绕显示区AA的外围区BB；显示区AA可以包括相邻设置的第一显示区A1和第二显示区A2。其中，第二显示区A2的透光率大于第一显示区A1的透光率。
图3为本公开提供的显示面板PNL的一种局部结构示意图。参见图3，显示面板在第一显示区A1和第二显示区A2内均可以设置有发光元件 C200，以便使得第一显示区A1和第二显示区A2均能够实现画面显示。
参见图4，应用该显示面板PNL的显示装置可以包括至少一个感光组件C300。其中，感光组件C300可以与第二显示区A2一一对应设置，且感光组件C300可以正对对应的第二显示区A2，以便接收从第二显示区A2透射的光线。感光组件C300可以具有用于感测光线的感光区域，感光区域在衬底基板F100上的正投影可以位于第二显示区A2内。感光组件C300可以为一个或者多个光线传感器，例如可以为摄像头、光学指纹识别芯片、光强传感器等。在一些实施方式中，感光组件C300可以为一摄像头，例如可以为一个CCD(电荷耦合器件)摄像头；如此，该显示装置可以实现屏下摄像，提高显示装置的屏占比。
可选地，参见图1和图2，第二显示区A2可以嵌于第一显示区A1中，即第一显示区A1环绕第二显示区A2。当第二显示区A2的数量为多个时，第二显示区A2可以分散设置，也可以相邻设置。当然地，在本公开的其他实施方式中，第二显示区A2也可以位于第一显示区A1的一侧；例如，第二显示区A2的边缘可以与外围区BB的内边缘部分交叠，使得第二显示区A2设置于显示区AA的边缘位置。
可选地，任意一个第二显示区A2的形状可以为圆形、方形、菱形、正六边形或者其他形状。在本公开的一种实施方式中，第二显示区A2的形状可以为圆形。
第二显示区A2的数量可以为一个，也可以为多个，以满足感光组件C300的设置为准。在本公开的一种实施方式中，第二显示区A2的数量为一个。如此，显示装置可以设置一个屏下感光组件C300，例如可以设置一个屏下摄像头或者屏下光学指纹识别芯片。在本公开的另一种实施方式中，第二显示区A2的数量为多个。如此，该显示装置可以设置多个感光组件C300，任意两个感光组件C300可以相同或者不相同。示例性地，参见图2，第二显示区A2的数量为三个且相邻设置。如此，显示装置可以设置有与三个第二显示区A2一一对应的不同的感光组件C300，例如设置有成像摄像头、深景摄像头、红外摄像头三种不同的感光组件C300。
参见图3，显示面板设置有用于驱动发光元件的像素驱动电路C100，像素驱动电路C100的输出端用于与对应的发光元件的像素电极电连接。
参见图3，像素驱动电路C100可以分布于第一显示区A1和第二显示区A2，其中，位于第一显示区的像素驱动电路C100可以用于驱动位于第一显示区A1的发光元件C200，位于第二显示区A2的像素驱动电路C100可以用于驱动位于第二显示区A2的发光元件C200。换言之，发光元件C200可以包括位于第一显示区A1的第一发光元件C201和位于第二显示区A2的第二发光元件C202；像素驱动电路C100可以包括用于驱动第一发光元件C201的第一像素驱动电路C101和用于驱动第二发光元件C202的第二像素驱动电路C102。第一像素驱动电路C101可以设置于第一显示区A1，第二像素驱动电路C102可以设置于第二显示区A2。
参见图19，显示面板包括与像素驱动电路连接的信号走线，以便向像素驱动电路加载相应的信号。参见图19，这些信号走线可以包括用于加载扫描信号Gate的扫描引线GL、用于加载数据电压Data的数据引线DataL、用于加载第一电源电压VDD的第一电源引线VDDL等。根据像素驱动电路C100的不同，显示面板还可以包括其他信号走线。例如，当像素驱动电路C100需要在复位信号Reset的控制下向某些节点加载初始化信号Vinit时，显示面板的信号走线还可以包括用于加载复位信号Reset的复位引线ReL和用于加载初始化信号Vinit的初始化引线ViL。再例如，当像素驱动电路C100需要在发光控制信号EM控制下才能够输出驱动电流时，显示面板的信号走线还可以包括用于加载发光控制信号EM的发光控制引线EML。
参见图18，像素驱动电路C100可以包括有存储电容Cst、数据写入晶体管和驱动晶体管。其中，驱动晶体管M1能够加载第一电源电压VDD并在存储电容Cst的控制下输出驱动电流。数据写入晶体管M2能够加载数据电压Data并在扫描信号Gate的控制下将数据电压Data写入至存储电容Cst。由此，数据写入晶体管M2需要与扫描引线GL和数据引线DataL数据电压连接，以便接收扫描引线GL上加载的扫描信号Gate和数据引线DataL上加载的数据电压Data。在本公开中，可以将数据引线DataL的延伸方向定义为显示面板PNL的行方向，将扫描引线GL的延伸方向定义为显示面板PNL的列方向。在本公开提供的显示面板PNL中，一个数据引线DataL上可以连接有多个像素驱动电路C100，一个扫描引线GL上可以 连接有多个像素驱动电路C100。如此，显示面板PNL可以通过逐行扫描的方式实现对各个像素驱动电路C100的驱动。
在本公开的一种实施方式中，参见图1，显示面板PNL的外围区BB具有绑定区B1，绑定区B1用于与驱动芯片或者电路板电连接，以便驱动该显示面板PNL。进一步地，绑定区位于显示面板PNL的列方向的一端。更进一步地，第二显示区A2位于显示区AA的远离绑定区的一端，且靠近显示区AA的边缘或者顶角处设置。
在膜层关系上，参见图3，显示面板PNL可以包括依次层叠设置的衬底基板F100、驱动电路层F200和像素层F300。其中，像素驱动电路C100可以设置于驱动电路层F200，发光元件C200可以设置于像素层F300。
衬底基板F100可以为无机材料的衬底基板F100，也可以为有机材料的衬底基板F100。举例而言，在本公开的一种实施方式中，衬底基板F100的材料可以为钠钙玻璃(soda-lime扫描引线GLass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板F100的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本公开的另一种实施方式中，衬底基板F100也可以为柔性衬底基板F100，例如衬底基板F100的材料可以为聚酰亚胺(Polyimide，PI)。衬底基板F100还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板F100可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
在驱动电路层F200中，任意一个像素驱动电路C100可以包括有晶体管和存储电容。进一步地，晶体管可以为薄膜晶体管，薄膜晶体管可以为顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。在本公开的一种实施 方式中，薄膜晶体管为低温多晶硅晶体管。
可以理解的是，像素驱动电路C100中的各个晶体管中，任意两个晶体管之间的类型可以相同或者不相同。示例性地，在一种实施方式中，在一个像素驱动电路C100中，部分晶体管可以为N型晶体管且部分晶体管可以为P型晶体管。再示例性地，在本公开的另一种实施方式中，在一个像素驱动电路C100中，部分晶体管的有源层的材料可以为低温多晶硅半导体材料，且部分晶体管的有源层的材料可以为金属氧化物半导体材料。
晶体管可以具有第一电极、第二电极和栅极，第一电极和第二电极中的一个可以为晶体管的源极且另一个可以为晶体管的漏极。可以理解的是，晶体管的源极和漏极为两个相对且可以相互转换的概念；当晶体管的工作状态改变时，例如电流方向改变时，晶体管的源极和漏极可以互换。
可选地，驱动电路层F200可以包括层叠于衬底基板F100和像素层F300之间的半导体层、栅极绝缘层、栅极层、层间电介质层、源漏金属层和平坦化层等。各个薄膜晶体管和存储电容可以由半导体层、栅极绝缘层、栅极层、层间电介质层、源漏金属层等膜层形成。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。举例而言，在本公开的一种实施方式中，驱动电路层F200可以包括依次层叠设置的半导体层、栅极绝缘层、栅极层、层间电介质层和源漏金属层，如此所形成的薄膜晶体管为顶栅型薄膜晶体管。再举例而言，在本公开的另一种实施方式中，驱动电路层F200可以包括依次层叠设置的栅极层、栅极绝缘层、半导体层、层间电介质层和源漏金属层，如此所形成的薄膜晶体管为底栅型薄膜晶体管。
可选地，驱动电路层F200还可以采用双栅极层结构，即栅极层可以包括第一栅极层和第二栅极层，栅极绝缘层可以包括用于隔离半导体层和第一栅极层的第一栅极绝缘层，以及包括用于隔离第一栅极层和第二栅极层的第二栅极绝缘层。举例而言，在本公开的一种实施方式中，驱动电路层F200可以包括依次层叠设置于衬底基板F100一侧的半导体层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层和源漏金属层。
可选地，驱动电路层F200还可以采用双源漏金属层结构，即源漏金 属层可以包括第一源漏金属层和第二源漏金属层，平坦化层包括第一平坦化层和第二平坦化层；第一源漏金属层、第一平坦化层、第二源漏金属层、第二平坦化层依次层叠设置于衬底基板的一侧。举例而言，在本公开的一种实施方式中，驱动电路层F200可以包括依次层叠设置于衬底基板F100一侧的半导体层、栅极绝缘层、栅极层、层间电介质层、第一源漏金属层、第一平坦化层、第二源漏金属层和第二平坦化层。
可选地，驱动电路层F200还可以包括有钝化层，钝化层可以设于源漏金属层远离衬底基板F100的表面，以便保护源漏金属层。
可选地，驱动电路层F200还可以包括设于衬底基板F100与半导体层之间的缓冲材料层，且半导体层、栅极层等均位于缓冲材料层远离衬底基板F100的一侧。缓冲材料层的材料可以为氧化硅、氮化硅等无机绝缘材料。缓冲材料层可以为一层无机材料层，也可以为多层层叠的无机材料层。
可选地，驱动电路层F200还可以包括有透明布线层。在第二显示区A2中，部分信号引线或者信号引线的部分引线段，可以设置于透明布线层，以便提高第二显示区A2的透光率。
可选地，像素层F300可以设置于驱动电路层F200远离衬底基板F100的一侧，其可以设置有发光元件C200作为显示面板PNL的子像素。其中，发光元件C200可以为OLED(有机电致发光二极管)、Micro LED(微发光二极管)、Mini LED(迷你发光二极管)、QD-OLED(量子点-有机电致发光二极管)或者其他电流驱动的发光元件。如下，以发光元件C200为有机电致发光二极管为例，对像素层的结构做简要介绍。可以理解的是，像素层的结构还可以为其他结构，以能够提供电流驱动的发光元件C200为准。
在该示例中，像素层可以包括依次层叠设置的像素电极层、像素定义层、支撑柱层、有机发光功能层和公共电极层。其中，像素电极层在显示面板的显示区具有多个像素电极；像素定义层在显示区具有与多个像素电极一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。支撑柱层在显示区包括多个支撑柱，且支撑柱位于像素定义层远离衬底基板F100的表面，以便在蒸镀制程中支撑精细金属掩模版(Fine Metal Mask，FMM)。有机发光功能层至少覆盖被像素定 义层所暴露的像素电极。其中，有机发光功能层可以包括有机电致发光材料层，以及可以包括有空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一种或者多种。可以通过蒸镀工艺制备有机发光功能层的各个膜层，且在蒸镀时可以采用精细金属掩模版或者开放式掩膜板(Open Mask)定义各个膜层的图案。公共电极层在显示区可以覆盖有机发光功能层。如此，像素电极、公共电极层和位于像素电极和公共电极层之间的有机发光功能层形成有机发电致光二极管，任意一个有机电致发光二极管可以作为显示面板的一个子像素。
在一些实施方式中，像素层F300还可以包括位于公共电极层远离衬底基板F100一侧的光取出层，以增强有机发光二极管的出光效率。
可选地，显示面板还可以包括薄膜封装层。薄膜封装层设于像素层F300远离衬底基板F100的表面，可以包括交替层叠设置的无机封装层和有机封装层。其中，无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵有机发光功能层而导致材料降解。可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间，以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的边缘，可以位于显示区的边缘和无机封装层的边缘之间。示例性地，薄膜封装层包括依次层叠于像素层远离衬底基板一侧的第一无机封装层、有机封装层和第二无机封装层。
可选地，显示面板还可以包括触控功能层，触控功能层设于薄膜封装层远离衬底基板的一侧，用于实现显示面板的触控操作。
可选地，显示面板还可以包括降反层，降反层可以设置于薄膜封装层远离像素层的一侧，用于降低显示面板对环境光线的反射，进而降低环境光线对显示效果的影响。在本公开的一种实施方式中，降反层可以包括层叠设置的彩膜层和黑矩阵层，如此可以在实现降低环境光线干扰的同时，可以避免降低显示面板的透光率。在本公开的另一种实施方式中，降反层可以为偏光片，例如可以为图案化的涂布型圆偏光片。进一步地，降反层可以设置于触控功能层远离衬底基板的一侧。
在本公开提供的显示面板PNL中，为了使得第二显示区A2具有更大的透光率，显示面板PNL的结构往往会导致位于第二显示区A2中的像素 驱动电路C100的设置或者信号走线与第一显示区A1中存在差异，这种差异一方面会导致第二显示区A2中发光元件C200的亮度与第一显示区A1中的发光元件C200的亮度存在差异，另一方面也会导致第二显示区A2中不同位置的发光元件C200的亮度存在较大差异。这两种差异(不均一)的存在，导致通过补偿的方式实现显示面板PNL的亮度均一性存在较大困难，且补偿效果欠佳。为了解决该问题，发明人进行了大量试验，且在试验中意外发现，通过调整第二显示区A2中的像素驱动电路C100(第二像素驱动电路C102)中的存储电容Cst的电容值的大小，可以调整第二显示区A2中的发光元件C200(第二发光元件C202)的亮度，进而可以通过对第二显示区A2中的像素驱动电路C100的存储电容Cst的电容值的调整来实现第二显示区A2中发光元件C200的亮度均一性。具体的，发明人发现，当增大第二显示区A2中的像素驱动电路C100的存储电容Cst的电容值时，该像素驱动电路C100驱动的发光元件C200的亮度值可以增大；相应的，当减小第二显示区A2中的像素驱动电路C100的存储电容Cst的电容值时，该像素驱动电路C100驱动的发光元件C200的亮度值可以减小。基于该发现，参见图19，本公开提供的显示面板PNL中，在该显示面板PNL的第二显示区A2中，依次连接于同一数据引线DataL的各个像素驱动电路C100的存储电容的电容值渐变。如此，第二显示区A2中像素驱动电路C100的存储电容Cst的电容值的渐变，可以对第二显示区A2中发光元件C200的发光亮度提供一种渐变趋势；这种渐变趋势可以与第二显示区A2中本来存在的发光元件C200的亮度渐变趋势相抵消，进而使得第二显示区A2中发光元件C200的亮度均一。进一步地，当第二显示区A2中的亮度均一后，显示面板PNL能够更方便且效果更佳的，通过补偿方法实现第一显示区A1和第二显示区A2中发光元件C200的亮度均一，进而提高显示面板PNL的显示效果。
示例性地，在一些相关技术中，第二显示区A2中的各个存储电容Cst的电容值相同；沿列方向且沿远离绑定区的方向，依次连接于同一数据引线DataL的各个像素驱动电路C100所驱动的发光元件C200，其亮度依次增大。这导致第二显示区A2中发光元件C200的亮度不均一。而在本公开的一种技术方案中，沿远离绑定区的方向，在第二显示区且连接于同一 数据引线DataL的各个像素驱动电路C100的存储电容的电容值逐渐减小。这样，本公开的该技术方案对存储电容Cst的设置可以为第二显示区A2中的发光元件C200发光亮度提供一种相反的渐变趋势，进而使得第二显示区A2中的各个发光元件C200的亮度均一。
可以理解的是，如果相关技术所采用的技术方案中，第二显示区A2中的各个存储电容Cst的电容值相同；沿列方向且沿远离绑定区的方向，依次连接于同一数据引线DataL的各个像素驱动电路C100所驱动的发光元件C200，其发光亮度依次减小。那么该相关技术方案可以通过本公开提供的显示面板的技术方案进行改良，进而形成本公开的另外一种技术方案，且在该新的技术方案中，沿远离绑定区的方向，在第二显示区且连接于同一数据引线DataL的各个像素驱动电路C100的存储电容的电容值逐渐增大。
在本公开中，参见图20，显示面板PNL包括用于设置像素驱动电路C100的像素驱动区域SubA，各个像素驱动电路C100与各个像素驱动区域SubA一一对应设置。任意一个像素驱动电路C100的各个晶体管的第一电极、第二电极和栅极等设置于该像素驱动电路C100对应的像素驱动区域SubA中。在本公开的一种实施方式中，第二显示区中的像素驱动区域SubA的面积，小于第一显示区中的像素驱动区域SubA的面积。换言之，第二显示区A2中的像素驱动电路C100可以被压缩，以便减小其对应的像素驱动区域SubA的面积，避免像素驱动电路C100遮光而降低第二显示区A2的透光率。这种设置方式，将会导致第二显示区A2中的像素驱动电路C100的存储电容Cst的电容值降低，进而使得存储电容Cst上的电压容易受到扫描引线GL上跳变的扫描信号Gate的影响，进而会产生如下趋势：第二显示区A2中的发光元件C200的亮度容易产生不均一、第二显示区A2和第一显示区A1中发光元件C200的亮度存在差异。示例性地，该种实施方式，容易产生如下趋势：第二显示区A2中存储电容Cst上的电压(驱动晶体管M1的栅极电压)受到扫描引线GL上跳变的扫描信号Gate影响而增大，进而使得第二显示区A2中发光元件C200的亮度低于第一显示区A1中发光元件C200的亮度。然而，在本公开中，通过对第二显示区A2中存储电容Cst的电容值的调整，可以对这些趋势中的 一种或者多种进行减弱或者消除。举例而言，可以通过使得存储电容Cst沿远离绑定区的方向依次减小的方式，减弱第二显示区A2中发光元件C200亮度不均一的趋势。这样，尽管本公开实施方式中采用了在第二显示区A2中压缩像素驱动电路C100的技术方案，但是可以通过对第二显示区A2中存储电容Cst的电容值的调整，克服像素驱动电路C100压缩可能产生的部分或者全部负面影响。
在本公开的一种实施方式中，在第二显示区A2，信号走线位于像素驱动区域SubA以外的部分的材料为透明导电材料。如此，既可以保证信号走线的通路，又可以避免信号走线遮光而降低第二显示区A2的透光率。进一步地，透明导电材料可以为透明导电金属氧化物材料，例如可以为IGZO(铟镓锌氧化物)、ITO(铟锡氧化物)等。在相关技术中，透明导电材料具有较大的方阻；如果信号走线部分采用透明导电材料，则会导致信号在传输过程中具有较大的压降，进而加剧第二显示区A2中发光元件C200亮度的不均一。例如，数据引线DataL在第二显示区A2区至少部分采用透明导电材料，这使得数据电压Data在列方向上具有较大的压降；相较于靠近绑定区的像素驱动电路C100，远离绑定区的像素驱动电路C100所接收到的实际数据电压Data更小且发光元件的亮度更大。然而，在本公开的实施方式中，可以通过在第二显示区A2中沿远离绑定区的方向依次减小存储电容Cst的设计方式，使得第二显示区A2中的发光元件C200的亮度具有沿远离绑定区的方向依次减小的趋势，该趋势与数据引线DataL的方阻对发光元件C200的亮度所产生的趋势相反，进而产生抵消效果。这样，本公开的技术方案既可以在第二显示区A2实现发光元件C200的亮度均一，又可以在第二显示区A2采用透明导电材料制备信号引线的部分引线段以提高第二显示区A2的透光率。
可选地，本公开的显示面板PNL中，驱动电路层中可以具有透明布线层；在第二显示区，信号走线位于像素驱动区域SubA以外的部分可以设置于该透明布线层。
示例性地，在本公开的一种实施方式中，驱动电路层包括依次层叠设置于衬底基板一侧的半导体层、第一栅极层、第二栅极层、第一源漏金属层、第二源漏金属层；像素层设置有像素电极层。显示面板还包括透明布 线层，透明布线层位于半导体层、第一栅极层、第二栅极层、第一源漏金属层、第二源漏金属层和像素电极层中的任意相邻两层之间。在第二显示区，信号走线位于像素驱动区域SubA以外的部分位于透明布线层。
在本公开的一种实施方式中，在第二显示区A2，依次连接于同一扫描引线GL的各个像素驱动电路C100的存储电容的电容值相同。这样，可以简化第二显示区A2中像素驱动电路C100的设计和制备，进而利于降低显示面板PNL的成本。另外，在测试中发现，第二显示区A2中发光元件C200沿行方向的亮度差异小或者基本无差异，因此使得第二显示区A2中同一扫描引线GL连接的像素驱动电路C100的存储电容Cst相同不会增大第二显示区A2中发光元件C200的亮度差异。
可选地，可以通过调整存储电容Cst的极板交叠总面积的方式来调整存储电容Cst的电容值。当增大存储电容Cst的极板交叠总面积时，可以使得存储电容Cst的电容值增大；反之，当减小存储电容Cst的极板交叠总面积时，可以使得存储电容Cst的电容值减小。
示例性地，像素驱动电路C100的存储电容包括依次层叠于显示面板的衬底基板一侧的多层电极板；其中，第奇数层电极板之间相互电连接，第偶数层电极板之间相互电连接；相邻两层电极板之间相互交叠且电绝缘；存储电容的极板交叠总面积为任意相邻两层电极板之间的交叠面积之和。
可选地，沿远离绑定区的方向，在第二显示区且连接于同一数据引线DataL的各个像素驱动电路C100的存储电容的极板交叠总面积逐渐减小；如此，沿远离绑定区的方向，在第二显示区且连接于同一数据引线DataL的各个像素驱动电路C100的存储电容的电容值逐渐减小。
在本公开的一种实施方式中，参见图5和图6，在第二显示区A2中，存储电容Cst可以包括四层电极板(CP1～CP4)，这样可以尽量增大第二显示区A2中的存储电容Cst的电容值，避免存储电容Cst的电容值较小而易受到其他信号的干扰。更进一步地，参见图20，第二显示区A2中的像素驱动区域SubA的面积小于第一显示区A1中的像素驱动区域SubA的面积；在这种情况下，第二显示区A2中的存储电容Cst具有四层电极板可以使得其电容值与第一显示区A1中的存储电容Cst的电容值的差异减小，进而利于使得第一显示区A1和第二显示区A2中的发光元件C200 的亮度差异小。示例性地，第一显示区A1中的存储电容Cst可以包括两层电极板，例如包括位于第一栅极层的第一层电极板CP1和位于第二栅极层的第二层电极板CP2；第一层电极板CP1和第二层电极板CP2之间相互交叠且电绝缘。第二显示区A2中的存储电容Cst可以包括四层电极板，例如包括位于第一栅极层的第一层电极板CP1、位于第二栅极层的第二层电极板CP2、位于第一源漏金属层的第三层电极板CP3和位于第二源漏金属层的第四层电极板CP4。相邻两层电极板之间相互交叠且电绝缘。其中，第一层电极板CP1与第三层电极板CP3之间通过过孔直接或者间接电连接；第二层电极板CP2和第四层电极板CP4之间通过过孔直接或者间接电连接。
在本公开中，将第一层电极板CP1与第二层电极板CP2之间的交叠面积定义为第一交叠面积；将第二层电极板CP2与第三层电极板CP3之间的交叠面积定义为第二交叠面积；将第三层电极板CP3与第四层电极板CP4之间的交叠面积定义为第三交叠面积。
在本公开的一种实施方式中，沿远离绑定区B1的方向，在第二显示区A2且连接于同一数据引线DataL的各个像素驱动电路C100的存储电容的第一交叠面积、第二交叠面积和第三交叠面积中的至少一个逐渐减小。例如，沿远离绑定区的方向，存储电容Cst可以仅减小第一交叠面积、第二交叠面积或者第三交叠面积，也可以减小这三个交叠面积中的两个，或者三个交叠面积均减小。
在本公开中，当减小相邻两层电极板之间的交叠面积时，既可以减小其中一层或者两层电极板本身的尺寸，也可以将其中一层或者两层电极板的位置进行调整(如图5和图6所示，图5和图6中电极板的位置存在差异)，或者如上两种策略同时实施，以能够减小相邻两层电极板之间的交叠面积为准。
可以理解的是，在本公开中，也可以采用其他方式调整不同像素驱动电路C100的存储电容的电容值，例如可以调整存储电容的电极板之间的绝缘层的厚度、绝缘材料的介电常数等等，以能够实现改变存储电容的电容值为准。
在本公开的一种实施方式中，像素驱动电路C100包括用于生成驱动 电流的驱动晶体管M1；存储电容的第一层电极板CP1复用为驱动晶体管M1的栅极；沿远离绑定区的方向，在第二显示区且连接于同一数据引线DataL的各个像素驱动电路C100的存储电容的第一层电极板CP1的面积不变。如此，可以保证第二显示区A2中各个像素驱动电路C100的驱动晶体管M1的性能不变，避免驱动晶体管M1电流特性改变而增大第二显示区A2中发光元件C200的亮度差异。
如下，提供一种示例性的显示面板PNL，以便对本公开的显示面板PNL的具体结构、原理和效果做进一步地解释和说明。可以理解的是，该示例性显示面板PNL仅仅为本公开提供的显示面板PNL的其中一种具体可行方式，而非对本公开的显示面板PNL的具体限定；本公开的显示面板PNL还可以通过该示例性地显示面板PNL以外的其他方式进行实施。
在该示例性地显示面板PNL中，参见图18，像素驱动电路C100可以为一个7T1C架构的像素驱动电路C100，其可以包括驱动晶体管M1、数据写入晶体管M2、阈值补偿晶体管M3、第一发光控制晶体管M4、第二发光控制晶体管M5、第一复位晶体管M6、第二复位晶体管M7和存储电容Cst。
驱动晶体管M1具有第一电极、第二电极和栅极；其中，驱动晶体管M1的第一电极连接第一节点N1，驱动晶体管M1的第二电极连接第三节点N3，驱动晶体管M1的栅极连接第二节点N2。
数据写入晶体管M2具有第一电极、第二电极和栅极；其中，数据写入晶体管M2的第一电极用于加载数据电压Data，数据写入晶体管M2的第二电极连接第一节点N1，数据写入晶体管M2的栅极用于加载扫描信号Gate。
阈值补偿晶体管M3具有第一电极、第二电极和栅极；其中，阈值补偿晶体管M3的第一电极连接第二节点N2，阈值补偿晶体管M3的第二电极连接第三节点N3，阈值补偿晶体管M3的栅极用于加载扫描信号Gate。
第一发光控制晶体管M4具有第一电极、第二电极和栅极；其中，第一发光控制晶体管M4的第一电极用于加载第一电源电压VDD，第一发光控制晶体管M4的第二电极连接第一节点N1，第一发光控制晶体管M4的栅极用于加载发光控制信号EM。
第二发光控制晶体管M5具有第一电极、第二电极和栅极；第二发光控制晶体管M5的第一电极连接第三节点N3，第二发光控制晶体管M5的第二电极连接第四节点N4，第二发光控制晶体管M5的栅极用于加载发光控制信号EM。
第一复位晶体管M6具有第一电极、第二电极和栅极；其中，第一复位晶体管M6的第一电极用于加载初始化信号Vinit，第一复位晶体管M6的第二电极连接第二节点N2，第一复位晶体管M6的栅极用于加载复位信号Reset。
第二复位晶体管M7具有第一电极、第二电极和栅极；其中，第二复位晶体管M7的第一电极用于加载初始化信号Vinit，第二复位晶体管M7的第二电极连接第四节点N4，第二复位晶体管M7的栅极用于加载扫描信号Gate。
存储电容Cst一端连接第二节点N2，另一端用于加载第一电源电压VDD。
该示例性地显示面板PNL中，发光元件C200的像素电极可以与第四节点N4连接，且发光元件C200的公共电极可以加载第二电源电压VSS。如此，像素驱动电路C100可以驱动与该像素驱动电路C100连接的发光元件C200发光。
在该示例性地实施方式中，沿远离绑定区的方向，在第二显示区且连接于同一数据引线DataL的各个像素驱动电路C100的存储电容的电容值逐渐减小。在第二显示区，依次连接于同一扫描引线GL的各个像素驱动电路C100的存储电容的电容值相同。
在膜层结构上，该示例性地显示面板PNL包括依次层叠设置的衬底基板、驱动电路层和像素层。其中，驱动电路层包括依次层叠于衬底基板一侧的缓冲材料层、多晶硅半导体层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层、第一源漏金属层、第一平坦化层、透明布线层、第三平坦化层、第二源漏金属层、第二平坦化层。像素层设置有作为发光元件的有机电致发光二极管，有机电致发光二极管的像素电极与位于驱动电路层的像素驱动电路C100电连接。
参见图8，在第二显示区A2，扫描引线GL包括交替设置且依次电连 接的第一扫描子引线GL1和第二扫描子引线GL2。其中，参见图8和图12，第一扫描子引线GL1位于像素驱动区域SubA且位于第一栅极层；参见图7、图8和图15，第二扫描子引线GL2位于透明布线层，且通过过孔与第一扫描子引线GL1电连接。
参见图8，在第二显示区A2，发光控制引线EML包括交替设置且依次电连接的第一发光控制子引线EML1和第二发光控制子引线EML2。其中，参见图8和图12，第一发光控制子引线EML1位于像素驱动区域SubA且位于第一栅极层；参见图7、图8和图15，第二发光控制子引线EML2位于透明布线层，且通过过孔与第一发光控制子引线EML1电连接。
参见图8，在第二显示区A2，复位引线ReL包括交替设置且依次电连接的第一复位子引线ReL1和第二复位子引线ReL2。其中，参见图8和图12，第一复位子引线ReL1位于像素驱动区域SubA且位于第一栅极层；参见图7、图8和图15，第二复位子引线ReL2位于透明布线层，且通过过孔与第一复位子引线ReL1电连接。
参见图9，在第二显示区A2，初始化引线ViL包括交替设置且依次电连接的第一初始化子引线ViL1和第二初始化子引线ViL2。其中，参见图9和图13，第一初始化子引线ViL1位于像素驱动区域SubA且位于第二栅极层；参见图7、图9和图15，第二初始化子引线ViL2位于透明布线层，且通过过孔与第一初始化子引线ViL1电连接。
参见图10，在第二显示区A2，第一电源电压引线VDDL包括交替设置且依次电连接的第一电源子引线VDDL1和第二电源子引线VDDL2。其中，参见图10和图17，第一电源子引线VDDL1位于像素驱动区域SubA且位于第二源漏金属层；参见图7、图10和图15，第二电源子引线VDDL2位于透明布线层，且通过过孔与第一电源子引线VDDL1电连接。
图11示出了多晶硅半导体层在第二显示区A2中的一个像素驱动区域SubA中的结构示意图。在一个像素驱动区域SubA中，多晶硅半导体层设置有驱动晶体管M1的有源层、数据写入晶体管M2的有源层、阈值补偿晶体管M3的有源层、第一发光控制晶体管M4的有源层、第二发光控制晶体管M5的有源层、第一复位晶体管M6的有源层和第二复位晶体管M7的有源层，以及设置有导体化的第一导电布线PL1、第二导电布线PL2、 第三导电布线PL3和第四导电布线PL4。其中，任意一个晶体管的有源层包括依次连接的第一电极、沟道区和第二电极。其中，沟道区保持半导体特性，第一电极、第二电极、第一导电布线PL1、第二导电布线PL2、第三导电布线PL3和第四导电布线PL4通过掺杂而导体化。图11示出了驱动晶体管M1的沟道区M1CNL、数据写入晶体管M2的沟道区M2CNL、阈值补偿晶体管M3的沟道区(M3CNL1+M3CNL2)、第一发光控制晶体管M4的沟道区M4CNL、第二发光控制晶体管M5的沟道区M5CNL、第一复位晶体管M6的沟道区(M6CNL1+M6CNL2)和第二复位晶体管M7的沟道区M7CNL的位置。
参见图11，数据写入晶体管M2的沟道区M2CNL和第一发光控制晶体管M4的沟道区M4CNL沿列方向H2排列，第一发光控制晶体管M4的沟道区M4CNL和第二发光控制晶体管M5的沟道区M5CNL沿行方向H1排列。在本公开中，行方向H1包括反向的第一行方向H11和第二行方向H12，其中，第二发光控制晶体管M5的沟道区M5CNL位于第一发光控制晶体管M4的沟道区M4CNL的第一行方向H11一侧。列方向H2包括反向的第一列方向H21和第二列方向H22，其中，第一发光控制晶体管M4的沟道区M4CNL位于数据写入晶体管M2的沟道区M2CNL的第一列方向H21一侧。
参见图11，数据写入晶体管M2的沟道区M2CNL和第一发光控制晶体管M4的沟道区M4CNL沿第一列方向H21依次排列，两者之间通过导体化的第一导电布线PL1电连接。第一导电布线PL1沿列方向H2延伸，其可以复用为数据写入晶体管M2的第二电极和第一发光控制晶体管M4的第二电极。相应的，数据写入晶体管M2的第一电极位于数据写入晶体管M2的沟道区M2CNL的第二列方向H22一侧，其具有第一底过孔区HA1，第一底过孔区HA1用于通过过孔与数据引线DataL电连接。第一发光控制晶体管M4的第一电极位于第一发光控制晶体管M4的沟道区M4CNL的第一列方向H21一侧，其具有第二底过孔区HA2，第二底过孔区HA2用于通过过孔与第一电源电压引线VDDL电连接。
驱动晶体管M1的沟道区M1CNL的一端与第一导电布线PL1连接，且位于第一导电布线PL1的第一行方向H11一侧。如此，第一导电布线 PL1可以作为第一节点N1的一部分，且复用为驱动晶体管M1的第一电极。驱动晶体管M1的沟道区M1CNL的另一端与导体化的第二导电布线PL2，如此，第二导电布线PL2可以作为第三节点N3节点的一部分，且复用为驱动晶体管M1的第二电极。第二导电布线PL2沿列方向H2延伸，使得驱动晶体管M1的沟道区M1CNL夹设于第一导电布线PL1和第二导电布线PL2之间。
第二导电布线PL2的第一列方向H21一侧的一端与第二发光控制晶体管M5的沟道区M5CNL连接，使得第二导电布线PL2复用为第二发光控制晶体管M5的第一电极；第二发光控制晶体管M5的第二电极位于第二发光控制晶体管M5的沟道区M5CNL的第一列方向H21一侧，且设置有第三底过孔区HA3，第三底过孔区HA3用于通过过孔与发光元件C200电连接。第二导电布线PL2的第二列方向H22一侧的一端与阈值补偿晶体管M3的沟道区连接，以复用为阈值补偿晶体管M3的第二电极。
阈值补偿晶体管M3的沟道区包括阈值补偿晶体管M3的第一沟道区M3CNL1和阈值补偿晶体管M3的第二沟道区M3CNL2，阈值补偿晶体管M3的第一沟道区M3CNL1和阈值补偿晶体管M3的第二沟道区M3CNL2之间通过第四导电布线PL4连接。其中，第四导电布线PL4呈弯折状，使的阈值补偿晶体管M3的第二沟道区M3CNL2设置于阈值补偿晶体管M3的第一沟道区M3CNL1的第二列方向H22一侧。这样，阈值补偿晶体管M3的栅极可以包括与阈值补偿晶体管M3的第一沟道区M3CNL1交叠的阈值补偿晶体管M3的第一栅极和与阈值补偿晶体管M3的第二沟道区M3CNL2交叠的阈值补偿晶体管M3的第二栅极。扫描引线GL位于第一栅极层的部分可以沿行方向H1延伸，且与阈值补偿晶体管M3的第一沟道区M3CNL1交叠以复用为阈值补偿晶体管M3的第一栅极；扫描引线GL位于第一栅极层的部分还可以设置有沿列方向H2方向延伸的凸出部，且该凸出部与阈值补偿晶体管M3的第二沟道区M3CNL2交叠，以复用为阈值补偿晶体管M3的第二栅极。这种设置方式，可以减小阈值补偿晶体管M3在截止状态下的漏电流，提高存储电容Cst的电压保持能力，减小显示面板PNL在低频驱动时的闪屏风险。
阈值补偿晶体管M3的第一电极位于阈值补偿晶体管M3的第二沟道 区M3CNL2的第二行方向H12一侧，且设置有第六底过孔区HA6，第六底过孔区HA6用于通过过孔与存储电容Cst的第一层电极板CP1电连接。如此，阈值补偿晶体管M3的第一电极和存储电容Cst的第一层电极板CP1可以作为第二节点N2节点的一部分。
第一复位晶体管M6的沟道区位于阈值补偿晶体管M3的沟道区M3CNL的第二列方向H22一侧，且包括第一复位晶体管M6的第一沟道区M6CNL1和第一复位晶体管M6的第二沟道区M6CNL2，第一复位晶体管M6的第一沟道区M6CNL1和第一复位晶体管M6的第二沟道区M6CNL2之间通过第三导电布线PL3电连接。其中，第一复位晶体管M6的第一沟道区M6CNL1和第一复位晶体管M6的第二沟道区M6CNL2沿第一行方向H11依次排列。如此，位于第一栅极层的复位引线ReL可以沿行方向H1延伸，且与第一复位晶体管M6的第一沟道区M6CNL1和第一复位晶体管M6的第二沟道区M6CNL2交叠。第一复位晶体管M6的栅极包括第一复位晶体管的第一栅极和第一复位晶体管的第二栅极，复位引线ReL与第一复位晶体管M6的第一沟道区M6CNL1交叠的部分可以复用为第一复位晶体管的第一栅极，复位引线ReL与第一复位晶体管M6的第二沟道区M6CNL2交叠的部分可以复用为第一复位晶体管的第二栅极。第一复位晶体管M6的第二电极和阈值补偿晶体管M3的第一电极复用，使得第一复位晶体管M6连接至第二节点N2。由于第一复位晶体管M6包括两个串联的子晶体管，因此其在截止状态下具有低的漏电流，这可以提高存储电容Cst的电压保持能力，减小显示面板PNL在低频驱动时的闪屏风险。
第一复位晶体管M6的第一电极位于第一复位晶体管M6的第二电极的第一行方向H11一侧，且可以复用为第二复位晶体管M7的第一电极。第一复位晶体管M6的第一电极具有第五底过孔区HA5，第六底过孔区HA6用于通过过孔与初始化引线ViL电连接，以便使得初始化信号Vinit加载至第一复位晶体管M6的第一电极和第二复位晶体管M7的第一电极。
第二复位晶体管M7的沟道区M7CNL位于第二复位晶体管M7的第一电极的第一列方向H21一侧，第二复位晶体管M7的第二电极位于第二复位晶体管M7的沟道区M7CNL的第一列方向H21一侧。第二复位晶体 管M7的第二电极设置有第四底过孔区HA4，第四底过孔区HA4用于通过过孔和其他导电结构电连接至第三底过孔区HA3。
图12为第一栅极层在第二显示区A2中的像素驱动区域SubA中的结构示意图。参见图12，第二显示区A2中，第一栅极层在像素驱动区域SubA设置有第一复位子引线ReL1、第一扫描子引线GL1、第一层电极板CP1和第一发光控制子引线EML1，第一复位子引线ReL1、第一扫描子引线GL1、第一层电极板CP1和第一发光控制子引线EML1沿第一列方向H21依次排列。
其中，第一复位子引线ReL1沿行方向H1延伸且依次与第一复位晶体管M6的第一沟道区M6CNL1和第一复位晶体管M6的第二沟道区M6CNL2交叠，以复用为第一复位晶体管M6的第一栅极和第一复位晶体管的第二栅极。第一复位子引线ReL1的第二行方向H12一端具有第七底过孔区HA7，第一复位子引线ReL1的第一行方向H11一端具有第八底过孔区HA8，第七底过孔区HA7和第八底过孔区HA8用于与第二复位子引线ReL2通过过孔电连接。
其中，第一扫描子引线GL1沿行方向H1延伸且依次与数据写入晶体管M2的沟道区M2CNL、阈值补偿晶体管M3的第一沟道区M3CNL1和第二复位晶体管M7的沟道区M7CNL交叠，以复用为数据写入晶体管M2的栅极、阈值补偿晶体管M3的第一栅极和第二复位晶体管M7的栅极。第一扫描子引线GL1的第二行方向H12一端具有第九底过孔区HA9，第一扫描子引线GL1的第一行方向H11一端具有第十底过孔区HA10，第九底过孔区HA9和第十底过孔区HA10用于与第二扫描子引线GL2通过过孔电连接。第一扫描子引线GL1还具有朝第二列方向H22延伸的突出部，该突出部与阈值补偿晶体管M3的第二沟道区M3CNL2交叠，以复用为阈值补偿晶体管M3的第二栅极。
其中，第一发光控制子引线EML1沿行方向H1延伸且依次与第一发光控制晶体管M4的沟道区M4CNL和第二发光控制晶体管M5的沟道区M5CNL交叠，以复用为第一发光控制晶体管M4的栅极和第二发光控制晶体管M5的栅极。第一发光控制子引线EML1的第二行方向H12一端具有第十一底过孔区HA11，第一发光控制子引线EML1的第一行方向H11 一端具有第十二底过孔区HA12，第十一底过孔区HA11和第十二底过孔区HA12用于与第二发光控制子引线EML2通过过孔电连接。
第一层电极板CP1与驱动晶体管M1的沟道区M1CNL交叠，其具有第十三底过孔区HA13，第十三底过孔区HA13用于通过过孔和其他导电结构与第六底过孔区HA6电连接。进一步地，在行方向H1上，第十三底过孔区HA13位于第一层电极板CP1的第一行方向H11一侧；在列方向H2上，第十三底过孔区HA13位于第一层电极板CP1的第二列方向H22一侧。
图13为第二栅极层在第二显示区A2中的像素驱动区域SubA中的结构示意图。参见图13，第二栅极层在第二显示区A2中的像素驱动区域SubA中，设置有第一初始化子引线ViL1和第二层电极板CP2；第一初始化子引线ViL1和第二层电极板CP2沿第一列方向H21依次排列。
其中，第一初始化子引线ViL1的两端分别设置有第十四底过孔区HA14和第十五底过孔区HA15，第十四底过孔区HA14和第十五底过孔区HA15分别用于通过过孔与第二初始化子引线ViL2电连接。更进一步地，第十五底过孔区HA15位于第一初始化子引线ViL1的第一行方向H11一端，还用于通过过孔和其他导电结构与第五底过孔区HA5电连接。进一步地，第二初始化子引线ViL2沿行方向H1延伸，且与第三导电布线PL3至少部分交叠。
第二层电极板CP2与第一层电极板CP1交叠设置，其具有暴露第十三底过孔区HA13的缺口部，这样可以使得第十三底过孔区HA13通过位于该缺口部的过孔与其他导电结构电连接。在该示例中，第二层电极板CP2的第二行方向H12一侧可以与第一导电布线PL1至少部分交叠，以对第一导电布线PL1提供电磁屏蔽，避免数据引线DataL上的数据电压Data跳变对第一导电布线PL1的耦合作用。第二层电极板CP2还可以设置有朝第二列方向H22一侧延伸的延伸部，该延伸部可以与第一扫描子引线GL1交叠。参见图14，第一源漏金属层设置有第三层电极板CP3以及与第三层电极板CP3连接的第五导电布线PL5，第五导电布线PL5的第二列方向H22一端具有第六顶过孔区HB6，第六顶过孔区HB6与第六底过孔区HA6之间通过过孔连接。其中，第五导电布线PL5与第一扫描子 引线GL1交叠的部分在第二栅极层上的正投影，可以位于第三层电极板CP3的延伸部内。如此，第二层电极板CP2的延伸部可以屏蔽第一扫描子引线GL1上扫描信号Gate的跳变，避免扫描信号Gate的跳变耦合至第三层电极板CP3(第二节点N2)而影响驱动晶体管M1的栅极电压。
参见图13，第二层电极板CP2可以设置有第十六底过孔区HA16，第十六底过孔区HA16用于通过过孔与第四层电极板CP4电连接。
图14示出了第一源漏金属层在第二显示区A2中的像素驱动区域SubA中的结构示意图。参见图14，第一源漏金属层在第二显示区A2中的像素驱动区域SubA中可以设置有第一导电部ML1、第二导电部ML2、第三导电部ML3、第四导电部ML4、第五导电部ML5、第六导电部ML6、第七导电部ML7、第八导电部ML8、第九导电部ML9，以及设置有第五导电布线PL5、第六导电布线PL6、第七导电布线PL7、第八导电布线PL8和第三层电极板CP3。
第一导电部ML1与第十四底过孔区HA14交叠，其具有第二十六底过孔区HA26和第十四顶过孔区HB14。第十四顶过孔区HB14与第十四底过孔区HA14之间通过过孔连接。第二十六底过孔区HA26用于通过过孔与第二初始化子引线ViL2连接。第二十六底过孔区HA26和第十四顶过孔区HB14可以部分或者全部重合。第七导电布线PL7的第二列方向H22一端具有第十五顶过孔区HB15和第二十七底过孔区HA27，第十五顶过孔区HB15与第十五底过孔区HA15通过过孔连接；第二十七底过孔区HA27用于通过过孔与第二初始化子引线ViL2连接。第十五顶过孔区HB15和第二十七底过孔区HA27可以部分或者全部重合。第七导电布线PL7沿列方向H2延伸，其第一列方向H21一端具有第五顶过孔区HB5，第五顶过孔区HB5与第五底过孔区HA5之间通过过孔连接。这样，第二初始化子引线ViL2可以通过第一导电部ML1、第七导电布线PL7转接而与第一初始化子引线ViL1电连接，且使得初始化引线ViL上加载的初始化信号Vinit加载至第二复位晶体管M7的第一电极和第一复位晶体管M6的第一电极。
第二导电部ML2与第七底过孔区HA7交叠，其具有第二十底过孔区HA20和第七顶过孔区HB7。第七顶过孔区HB7与第七底过孔区HA7之 间通过过孔连接。第二十底过孔区HA20用于通过过孔与第二复位子引线ReL2连接。第二十底过孔区HA20和第七顶过孔区HB7可以部分或者全部重合。第八导电部ML8与第八底过孔区HA8交叠，且具有第八顶过孔区HB8和第二十一底过孔区HA21，第八顶过孔区HB8与第八底过孔区HA8通过过孔连接；第二十一底过孔区HA21用于通过过孔与第二复位子引线ReL2连接。第八顶过孔区HB8和第二十一底过孔区HA21可以部分或者全部重合。这样，第二复位子引线ReL2可以通过第二导电部ML2、第八导电部ML8转接，而与第一复位子引线ReL1电连接。
第三导电部ML3与第一底过孔区HA1交叠，其具有第十八底过孔区HA18和第一顶过孔区HB1。第一顶过孔区HB1与第一底过孔区HA1之间通过过孔连接。第十八底过孔区HA18用于通过过孔与数据引线DataL电连接。第十八底过孔区HA18和第一顶过孔区HB1可以部分或者全部重合。这样，数据引线DataL可以通过第三导电部ML3与数据写入晶体管M2的第一电极连接，使得数据引线DataL上加载的数据电压Data加载至数据写入晶体管M2的第一电极。
第九导电部ML9与第九底过孔区HA9交叠，其具有第二十二底过孔区HA22和第九顶过孔区HB9。第九顶过孔区HB9与第九底过孔区HA9之间通过过孔连接。第二十二底过孔区HA22用于通过过孔与第二扫描子引线GL2连接。第二十二底过孔区HA22和第九顶过孔区HB9可以部分或者全部重合。第七导电部ML7与第十底过孔区HA10交叠，且具有第十顶过孔区HB10和第二十三底过孔区HA23，第十顶过孔区HB10与第十底过孔区HA10通过过孔连接；第二十三底过孔区HA23用于通过过孔与第二扫描子引线GL2连接。第十顶过孔区HB10与第十底过孔区HA10可以部分或者全部重合。这样，第二扫描子引线GL2可以通过第七导电部ML7、第九导电部ML9转接，而与第一扫描子引线GL1电连接。
第五导电部ML5与第十一底过孔区HA11交叠，其具有第二十四底过孔区HA24和第十一顶过孔区HB11。第十一顶过孔区HB11与第十一底过孔区HA11之间通过过孔连接。第二十四底过孔区HA24用于通过过孔与第二发光控制子引线EML2连接。第二十四底过孔区HA24和第十一顶过孔区HB11可以部分或者全部重合。第六导电部ML6与第十二底过 孔区HA12交叠，且具有第十二顶过孔区HB12和第二十五底过孔区HA25，第十二顶过孔区HB12与第十二底过孔区HA12通过过孔连接；第二十五底过孔区HA25用于通过过孔与第二发光控制子引线EML2连接。第十二顶过孔区HB12和第二十五底过孔区HA25可以部分或者全部重合。这样，第二发光控制子引线EML2可以通过第五导电部ML5、第六导电部ML6转接，而与第一发光控制子引线EML1电连接。
第四导电部ML4与第二层电极板CP2交叠且与第六导电布线PL6连接。其中，第四导电部ML4具有第十七底过孔区HA17和第十六顶过孔区HB16，第十六顶过孔区HB16与第十六底过孔区HA16之间通过过孔连接。第十七底过孔区HA17用于通过过孔与第一电源电压引线VDDL电连接。其中，第十七底过孔区HA17和第十六顶过孔区HB16不相交。第六导电布线PL6连接于第四导电部ML4，且位于第四导电部ML4的第一列方向H21一侧。第六导电布线PL6的第一列方向H21一端具有第二顶过孔区HB2，第二顶过孔区HB2通过过孔与第二底过孔区HA2连接。如此，第一发光控制晶体管M4的第一电极通过第六导电布线PL6、第四导电部ML4与第一电源电压引线VDDL电连接，使得第一电源电压VDD能够加载至第一发光控制晶体管M4的第一电极和第二层电极板CP2。
第三层电极板CP3与第二层电极板CP2交叠，且具有与第十三底过孔区HA13交叠的第十三顶过孔区HB13，第十三顶过孔区HB13与第十三底过孔区HA13之间通过过孔连接。如此，第一层电极板CP1和第三层电极板CP3连接，作为第二节点N2的一部分。第五导电布线PL5与第三层电极板CP3连接，且向第二列方向H22延伸；第五导电布线PL5的第二列方向H22一端具有与第六底过孔区HA6交叠的第六顶过孔区HB6，第六顶过孔区HB6与第六底过孔区HA6之间通过过孔连接。这样，第三层电极板CP3和第一复位晶体管M6的第二电极、阈值补偿晶体管M3的第一电极之间通过第五导电布线PL5连接。
第八导电布线PL8的两端分别具有与第四底过孔区HA4交叠的第四顶过孔区HB4和与第三底过孔区HA3交的的第三顶过孔区HB3，第四顶过孔区HB4与第四底过孔区HA4之间通过过孔连接，第三顶过孔区HB3与第三底过孔区HA3之间通过过孔连接。这样，使得第二复位晶体管M7 的第二电极与第二发光控制晶体管M5的第二电极之间通过第八导电布线PL8连接。第八导电布线PL8还具有靠近第三顶过孔区HB3的第一底过孔区HA19，第一底过孔区HA19用于通过过孔与发光元件C200电连接。进一步地，第一底过孔区HA19和第三顶过孔区HB3可以部分或者全部重合。
图15和图16示出了透明布线层在第二显示区A2的结构示意图。可以理解的是，在第二显示区A2，透明布线层在不同位置处的布线可以存在一定的差异，以能能够实现向像素驱动电路加载所需的信号为准。
参见图7、图15和图16，，透明布线层在第二显示区A2设置有第二初始化子引线ViL2、第二复位子引线ReL2、第二扫描子引线GL2、第二发光控制子引线EML2、数据引线DataL、第二电源子引线VDDL2等。
第二初始化子引线ViL2的端部、第二复位子引线ReL2的端部、第二扫描子引线GL2的端部和第二发光控制子引线EML2的端部伸入该第二显示区A2的像素驱动区域SubA中，且通过过孔与第一源漏金属层层中的对应的走线连接。
参见图7、图9、图14、图15和图16，在第二显示区A2中的一个像素驱动区域SubA中，第一初始化子引线ViL1的第二行方向H12一侧的第二初始化子引线ViL2，其第一行方向H11的一端设置有与第二十六底过孔区HA26交叠的第二十六顶过孔区HB26，第二十六顶过孔区HB26与第二十六底过孔区HA26之间通过过孔连接，这使得该第二初始化子引线ViL2与第一初始化子引线ViL1电连接；第一初始化子引线ViL1的第一行方向H11一侧的第二初始化子引线ViL2，其第二行方向H12的一端设置有与第二十七底过孔区HA27交叠的第二十七顶过孔区HB27，第二十七顶过孔区HB27与第二十七底过孔区HA27之间通过过孔连接，这使得该第二初始化子引线ViL2与第一初始化子引线ViL1电连接。如此，在第二显示区A2中，第二初始化子引线ViL2和第一初始化子引线ViL1交替设置且依次连接，以形成初始化引线ViL。
参见图7、图8、图14、图15和图16，在第二显示区A2中的一个像素驱动区域SubA中，第一复位子引线ReL1的第二行方向H12一侧的第二复位子引线ReL2，其第一行方向H11的一端设置有与第二十底过孔区 HA20交叠的第二十顶过孔区HB20，第二十顶过孔区HB20与第二十底过孔区HA20之间通过过孔连接，这使得该第二复位子引线ReL2与第一复位子引线ReL1电连接；第一复位子引线ReL1的第一行方向H11一侧的第二复位子引线ReL2，其第二行方向H12的一端设置有与第二十一底过孔区HA21交叠的第二十一顶过孔区HB21，第二十一顶过孔区HB21与第二十一底过孔区HA21之间通过过孔连接，这使得该第二复位子引线ReL2与第一复位子引线ReL1电连接。如此，在第二显示区A2中，第二复位子引线ReL2和第一复位子引线ReL1交替设置且依次连接，以形成复位引线ReL。
参见图7、图8、图14、图15和图16，在第二显示区A2中的一个像素驱动区域SubA中，第一扫描子引线GL1的第二行方向H12一侧的第二扫描子引线GL2，其第一行方向H11的一端设置有与第二十二底过孔区HA22交叠的第二十二顶过孔区HB22，第二十二顶过孔区HB22与第二十二底过孔区HA22之间通过过孔连接，这使得该第二扫描子引线GL2与第一扫描子引线GL1电连接；第一扫描子引线GL1的第一行方向H11一侧的第二扫描子引线GL2，其第二行方向H12的一端设置有与第二十三底过孔区HA23交叠的第二十三顶过孔区HB23，第二十三顶过孔区HB23与第二十三底过孔区HA23之间通过过孔连接，这使得该第二扫描子引线GL2与第一扫描子引线GL1电连接。如此，在第二显示区A2中，第二扫描子引线GL2和第一扫描子引线GL1交替设置且依次连接，以形成扫描引线GL。
参见图7、图8、图14、图15和图16，在第二显示区A2中的一个像素驱动区域SubA中，第一发光控制子引线EML1的第二行方向H12一侧的第二发光控制子引线EML2，其第一行方向H11的一端设置有与第二十四底过孔区HA24交叠的第二十四顶过孔区HB24，第二十四顶过孔区HB24与第二十四底过孔区HA24之间通过过孔连接，这使得该第二发光控制子引线EML2与第一发光控制子引线EML1电连接；第一发光控制子引线EML1的第一行方向H11一侧的第二发光控制子引线EML2，其第二行方向H12的一端设置有与第二十五底过孔区HA25交叠的第二十五顶过孔区HB25，第二十五顶过孔区HB25与第二十五底过孔区HA25之间通 过过孔连接，这使得该第二发光控制子引线EML2与第一发光控制子引线EML1电连接。如此，在第二显示区A2中，第二发光控制子引线EML2和第一发光控制子引线EML1交替设置且依次连接，以形成发光控制引线EML。
参见图10、图15、图16、图17，第二电源子引线VDDL2的端部伸入该第二显示区A2中的像素驱动区域SubA中，且通过过孔与第二源漏金属层中的第一电源子引线VDDL1连接。
其中，在第二显示区A2中的一个像素驱动区域SubA的第二列方向H22一侧的第二电源子引线VDDL2，其第一列方向H21的一端具有第二十九底过孔区HA29；第二十九底过孔区HA29用于与位于第二源漏金属层的第一电源子引线VDDL1通过过孔连接；位于该像素驱动区域SubA的第一列方向H21一侧的第二电源子引线VDDL2，其第二列方向H22一端具有第二十八底过孔区HA28，第二十八底过孔区HA28用于与位于第二源漏金属层的第一电源子引线VDDL1通过过孔连接。进一步地，位于该像素驱动区域SubA的第一列方向H21一侧的第二电源子引线VDDL2，其第二列方向H22一端还具有与第十七底过孔区HA17交叠的第十七顶过孔区HB17，第十七顶过孔区HB17与第十七底过孔区HA17之间通过过孔连接。
参见图10、图15和图16，在第二显示区A2中，数据引线DataL位于透明布线层且沿列方向H2穿过像素驱动区域SubA。其中，数据引线DataL具有与第十八底过孔区HA18交叠的第十八顶过孔区HB18，第十八顶过孔区HB18与第十八底过孔区HA18通过过孔连接。
图17示出了第二显示区A2中一个像素驱动区域SubA中的第二源漏金属层的结构示意图。参见图17，第二源漏金属层在第二显示区A2中的像素驱动区域SubA中包括第十导电部ML10、第十一导电部ML11和第一电源子引线VDDL1。其中，第十一导电部ML11覆盖第十八顶过孔区HB18，以便屏蔽外部信号对数据电压Data的干扰。第十导电部ML10具有与第三十底过孔区HA30交叠的第三十顶过孔区HB30，第三十顶过孔区HB30与第三十底过孔区HA30通过过孔连接。发光元件C200的像素电极可以通过过孔与第十导电部ML10连接。
第一电源子引线VDDL1沿列方向H2延伸，且两端分别具有与第二十九底过孔区HA29交叠的第二十九顶过孔区HB29和与第二十八底过孔区HA28交叠的第二十八顶过孔区HB28。其中，第二十八顶过孔区HB28与第二十八底过孔区HA28通过过孔连接，第二十九顶过孔区HB29与第二十九底过孔区HA29通过过孔连接。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (22)

  1. 一种显示面板，包括显示区和围绕所述显示区的外围区；所述外围区的一侧设置有绑定区；所述显示区包括相邻的第一显示区和第二显示区；所述第二显示区的透光率大于所述第一显示区的透光率；
    所述显示面板包括多个像素驱动电路，以及包括用于向所述像素驱动电路加载数据电压的数据引线；
    在所述第二显示区，依次连接于同一所述数据引线的各个所述像素驱动电路的存储电容的电容值渐变。
  2. 根据权利要求1所述的像素驱动电路，其中，沿远离所述绑定区的方向，在所述第二显示区且连接于同一所述数据引线的各个所述像素驱动电路的存储电容的电容值逐渐减小。
  3. 根据权利要求1所述的像素驱动电路，其中，所述显示面板还包括用于向所述像素驱动电路加载扫描信号的扫描引线；
    在所述第二显示区，依次连接于同一所述扫描引线的各个所述像素驱动电路的存储电容的电容值相同。
  4. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路的存储电容包括依次层叠于所述显示面板的衬底基板一侧的多层电极板；
    其中，第奇数层所述电极板之间相互电连接，第偶数层所述电极板之间相互电连接；相邻两层所述电极板之间相互交叠且电绝缘；所述存储电容的极板交叠总面积为任意相邻两层所述电极板之间的交叠面积之和；
    沿远离所述绑定区的方向，在所述第二显示区且连接于同一所述数据引线的各个所述像素驱动电路的存储电容的极板交叠总面积逐渐减小。
  5. 根据权利要求4所述的像素驱动电路，其中，在所述第二显示区，所述像素驱动电路的存储电容的电极板的层数为四层。
  6. 根据权利要求5所述的像素驱动电路，其中，所述第一层电极板与所述第二层电极板之间的交叠面积为第一交叠面积；所述第二层电极板与所述第三层电极板之间的交叠面积为第二交叠面积；所述第三层电极板与所述第四层电极板之间的交叠面积为第三交叠面积；
    沿远离所述绑定区的方向，在所述第二显示区且连接于同一所述数据引线的各个所述像素驱动电路的存储电容的第一交叠面积、第二交叠面积 和第三交叠面积中的至少一个逐渐减小。
  7. 根据权利要求5所述的像素驱动电路，其中，所述像素驱动电路包括用于生成驱动电流的驱动晶体管；所述存储电容的第一层电极板复用为所述驱动晶体管的栅极；
    沿远离所述绑定区的方向，在所述第二显示区且连接于同一所述数据引线的各个所述像素驱动电路的存储电容的第一层电极板的面积不变。
  8. 根据权利要求1所述的像素驱动电路，其中，所述显示面板包括用于设置各个所述像素驱动电路的像素驱动区域；
    所述第二显示区中的所述像素驱动区域的面积，小于所述第一显示区中的所述像素驱动区域的面积。
  9. 根据权利要求8所述的像素驱动电路，其中，所述显示面板包括连接相邻所述像素驱动电路的信号走线；
    在所述第二显示区，所述信号走线位于所述像素驱动区域以外的部分的材料为透明导电材料。
  10. 根据权利要求8所述的像素驱动电路，其中，所述显示面板包括依次层叠设置的衬底基板、半导体层、第一栅极层、第二栅极层、第一源漏金属层、第二源漏金属层、像素电极层；所述显示面板还包括透明布线层，所述透明布线层位于所述半导体层、所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层和所述像素电极层中的任意相邻两层之间；
    在所述第二显示区，所述走线位于所述像素驱动区域以外的部分位于所述透明布线层。
  11. 一种显示面板，其中，所述显示面板包括依次层叠设置的衬底基板、驱动电路层和像素层；
    所述像素层设置有子像素，所述驱动电路层设置有用于驱动所述子像素的像素驱动电路；所述驱动电路层包括薄膜晶体管和存储电容；
    其中，所述存储电容包括依次层叠的多层电极板；第奇数层所述电极板之间相互电连接，第偶数层所述电极板之间相互电连接；相邻两层所述电极板之间相互交叠且电绝缘；至少部分所述存储电容包括多于两层的所述电极板。
  12. 根据权利要求11所述的显示面板，其中，至少部分所述存储电容包括四层所述电极板。
  13. 根据权利要求11所述的显示面板，其中，至少部分所述存储电容包括两层所述电极板。
  14. 根据权利要求11所述的显示面板，其中，所述显示面板包括显示区和围绕所述显示区的外围区；所述显示区包括相邻的第一显示区和第二显示区；所述第二显示区的透光率大于所述第一显示区的透光率；
    所述第一显示区设置有第一像素驱动电路，所述第二显示区设置有第二像素驱动电路。
  15. 根据权利要求14所述的显示面板，其中，所述第一像素驱动电路的存储电容包括两层电极板。
  16. 根据权利要求14所述的显示面板，其中，所述第二像素驱动电路的存储电容包括四层电极板。
  17. 根据权利要求14所述的显示面板，其中，所述显示面板包括用于设置所述第一像素驱动电路的第一像素驱动区域和用于设置所述第二像素驱动电路的第二像素驱动区域；
    所述第二像素驱动区域的面积，小于所述第一像素驱动区域的面积。
  18. 根据权利要求17所述的显示面板，其中，所述显示面板包括连接相邻所述像素驱动电路的信号走线；
    在所述第二显示区，所述信号走线位于所述第二像素驱动区域以外的部分的材料为透明导电材料。
  19. 根据权利要求18所述的显示面板，其中，所述显示面板包括依次层叠设置的衬底基板、半导体层、第一栅极层、第二栅极层、第一源漏金属层、第二源漏金属层、像素电极层；所述显示面板还包括透明布线层，所述透明布线层位于所述半导体层、所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层和所述像素电极层中的任意相邻两层之间；
    在所述第二显示区，所述信号走线位于所述第二像素驱动区域以外的部分位于所述透明布线层。
  20. 根据权利要求11～19任意一项所述的显示面板，其中，所述驱动 电路层包括依次层叠于所述衬底基板一侧的半导体层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层、第一源漏金属层、第一平坦化层、第二源漏金属层和第二平坦化层；所述驱动电路层还包括透明布线层，所述透明布线层设置于所述半导体层、所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层和所述像素电极层中的任意相邻两层之间；
    所述存储电容的多层电极板，分别位于所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层、所述透明布线层中的多层。
  21. 根据权利要求11～19任意一项所述的显示面板，其中，所述驱动电路层包括依次层叠于所述衬底基板一侧的半导体层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层、层间电介质层、第一源漏金属层、第一平坦化层、第二源漏金属层和第二平坦化层；
    所述存储电容的多层电极板，分别位于所述第一栅极层、所述第二栅极层、所述第一源漏金属层、所述第二源漏金属层中的多层。
  22. 一种显示装置，包括权利要求1～21任意一项所述的显示面板。
PCT/CN2021/132892 2021-05-21 2021-11-24 显示面板和显示装置 WO2022242085A1 (zh)

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