WO2023123239A1 - 显示面板和电子设备 - Google Patents

显示面板和电子设备 Download PDF

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Publication number
WO2023123239A1
WO2023123239A1 PCT/CN2021/143227 CN2021143227W WO2023123239A1 WO 2023123239 A1 WO2023123239 A1 WO 2023123239A1 CN 2021143227 W CN2021143227 W CN 2021143227W WO 2023123239 A1 WO2023123239 A1 WO 2023123239A1
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WO
WIPO (PCT)
Prior art keywords
line
segment
section
transfer
column
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PCT/CN2021/143227
Other languages
English (en)
French (fr)
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WO2023123239A9 (zh
Inventor
王晓宵
李若湘
胡耀
李硕
王铸
郭丹
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/143227 priority Critical patent/WO2023123239A1/zh
Priority to CN202180004344.8A priority patent/CN116686421A/zh
Publication of WO2023123239A1 publication Critical patent/WO2023123239A1/zh
Publication of WO2023123239A9 publication Critical patent/WO2023123239A9/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present disclosure relates to the field of display technology, in particular, to a display panel and electronic equipment.
  • holes can be opened on the display screen, and photosensitive devices such as cameras and sensors can be installed in the hole-punched area.
  • photosensitive devices such as cameras and sensors
  • the size of the hole area is still relatively large, which is not conducive to the further improvement of the screen-to-body ratio of full-screen products.
  • the purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art, provide a display panel and an electronic device, and reduce the size of the opening area.
  • a display panel including an aperture area and a display area surrounding the aperture area; wherein, the display panel is provided with running lines extending along a first direction and running lines extending along a second direction. column alignment;
  • Some of the running lines are separated by the opening area into the first section of the running line and the second section of the running line corresponding to each other; Segment and column line second segment;
  • At least part of the first section of the column wiring is electrically connected to the corresponding second section of the column wiring through a corresponding transfer line located in the display area;
  • At least part of the first segment of the running line is electrically connected to the corresponding second segment of the running line through a corresponding transfer line located in the display area.
  • the column wiring includes a data wiring for loading driving data; part of the data wiring is separated by the opening area into the first segment of the data wiring and the data wiring corresponding to each other.
  • the first section of the data wiring is electrically connected to the corresponding second section of the data wiring through a corresponding column transfer wire located in the display area.
  • the column transfer wire includes a first segment of the column transfer wire, a second segment of the column transfer wire, and a third segment of the column transfer wire;
  • the first segment of the column transfer wire is electrically connected to the first segment of the data trace
  • the third segment of the column transfer wire is electrically connected to the second segment of the data trace.
  • the first segment of the column transfer wire and the third segment of the column transfer wire extend along the first direction; the second segment of the column transfer wire extends along the second direction;
  • the aperture area has a column axis extending along the second direction
  • Each of the first segments of the data traces located on one side of the column central axis is electrically connected to the column transfer wire located on the same side of the column central axis.
  • the column transfer line includes two parts respectively located on both sides of the column central axis;
  • Each of the row transfer wires located on the same side of the row central axis has its respective ends arranged in a straight line along the second direction.
  • the end of the first segment of the column transfer wire away from the second segment of the column transfer wire overlaps and is electrically connected to the corresponding first segment of the data trace
  • the column transfer wire The end of the third segment of the wire that is far away from the second segment of the column transfer wire overlaps and is electrically connected to the corresponding second segment of the data trace.
  • the column wiring further includes a driving power supply wiring extending along the second direction; the second segment of the column transfer wiring overlaps the driving power supply wiring.
  • the display area is provided with array-distributed pixel drive circuits; the pixel drive circuits are arranged into a plurality of pixel drive circuit rows and a plurality of pixel drive circuit columns;
  • the first sections of the two adjacent column transfer lines along the second direction are respectively located in the two adjacent rows of the pixel driving circuits;
  • the third sections of the two adjacent column transfer lines along the second direction are respectively located in the two adjacent rows of the pixel driving circuits;
  • the second segments of the two adjacent column transfer wires along the first direction are respectively located in the two adjacent columns of the pixel driving circuits.
  • the running lines include scanning lines for loading scanning signals; part of the scanning lines are separated by the opening area into the first segment of the scanning lines and the scanning lines corresponding to each other. the second segment of the line;
  • the first segment of the scan line is electrically connected to the corresponding second segment of the scan line through a corresponding row transfer line located in the display area.
  • At least part of the row transfer wires are first row transfer wires;
  • the third segment of the transfer line; the first segment of the row transfer line and the third segment of the row transfer line extend along the second direction; the second segment of the row transfer line extends along the first direction;
  • the first segment of the row transfer wire is electrically connected to the corresponding first segment of the scanning wire, and the third segment of the row transfer wire is electrically connected to the corresponding second segment of the scan wire.
  • the first segment of the row transfer wire of the first row transfer wire is electrically connected to the corresponding first segment of the scanning wire through its end, and the row of the first row transfer wire
  • the third segment of the transfer wire is electrically connected to the corresponding second segment of the scanning wire through its end.
  • some of the row transfer wires are second row transfer wires;
  • the second row transfer wires include the fourth segment of row transfer wires, the first segment of row transfer wires, The second section, the third section of the line transfer line and the fifth section of the row transfer line; the first section of the row transfer line and the third section of the row transfer line extend along the second direction; the fourth row of the row transfer line The segment, the second segment of the row transfer line, and the fifth segment of the row transfer line extend along the first direction;
  • the fourth segment of the row transfer line is electrically connected to the corresponding first segment of the scanning line through its end far away from the first segment of the row transfer line; the fifth segment of the row transfer line is away from the row.
  • the end of the third segment of the transfer wire is electrically connected to the corresponding second segment of the scanning wire.
  • the fourth segment of the row transfer line overlaps with the corresponding first segment of the scanning line; the fifth segment of the row transfer line overlaps the corresponding second segment of the scanning line. Segment overlap settings.
  • the display panel is provided with driving power traces extending along the second direction;
  • the first section of the row transfer line and the third section of the row transfer line overlap with the driving power supply line respectively.
  • the opening area has a row center axis extending along the first direction
  • the corresponding row transition lines are located on the same side of the row central axis.
  • the running lines further include reset control lines corresponding to the scanning lines and used for loading reset control signals; the reset control lines are connected to the corresponding scanning lines The loaded signals are consistent; part of the reset control wiring is separated by the opening area into a first section of the reset control wiring and a second section of the reset control wiring that correspond to each other;
  • the first section of the scan wiring and the corresponding first section of the reset control wiring are arranged in parallel, and are electrically connected to the same first section of the row transfer wiring;
  • the second section of the scan wiring is arranged in parallel with the corresponding second section of the reset control wiring, and is electrically connected to the same third section of the row transfer wiring.
  • the aperture area includes an aperture and an aperture packaging area surrounding the aperture
  • the opening packaging area is provided with a scanning transfer structure corresponding to the first section of the scanning line and the second section of the scanning line;
  • the first section of the scanning wiring and the corresponding first section of the reset control wiring are electrically connected to the corresponding scanning transfer structure
  • the second section of the scan wiring and the corresponding second section of the reset control wiring are electrically connected to the corresponding scan transfer structure.
  • the scanning wiring and the corresponding reset control wiring are arranged on the same conductive layer; the scanning wiring, the scanning transfer structure and the row transfer wiring are located on different conductive layer;
  • the first section of the scan line and the corresponding first section of the reset control line are electrically connected to the corresponding scan transfer structure through a via hole; the second section of the scan line is connected to the corresponding reset control line.
  • the second section of the control wiring is electrically connected to the corresponding scanning transfer structure through a via hole;
  • the scanning transfer structure corresponding to the first section of the scanning line is electrically connected to the row transfer line corresponding to the first section of the scanning line through a via hole;
  • the scan transition structure corresponding to the second section of the scan line is electrically connected to the row transition line corresponding to the second section of the scan line through a via hole.
  • the aperture area includes an aperture and an aperture packaging area surrounding the aperture
  • the traces include enable traces for loading enable signals
  • Some of the enabling traces are separated by the opening area into a first section of the enabling trace and a second section of the enabling trace;
  • the first segment of the enabling trace is electrically connected to the corresponding second segment of the enabling trace through a corresponding enabling routing wire provided in the aperture packaging area.
  • the display panel includes a first gate layer and a second gate layer stacked; the first gate layer is provided with a first electrode plate that enables wiring and storage capacitors ; The second gate layer is provided with a second electrode plate of the storage capacitor;
  • the enabling winding wire is disposed on the first gate layer and/or the second gate layer.
  • the aperture area includes an aperture and an aperture packaging area surrounding the aperture
  • the running lines include initialization lines for loading an initialization voltage; part of the initialization lines are separated by the opening area into a first section of initialization lines and a second section of initialization lines corresponding to each other;
  • the opening packaging area is provided with a reference voltage winding line surrounding the opening; the first section of each initialization wiring and the second section of each initialization wiring are electrically connected to the reference voltage winding line .
  • the transition lines include row transition lines and column transition lines
  • the row transfer line is used to electrically connect the corresponding first section of the running line to the second section of the running line;
  • the column transfer wire is used to electrically connect the corresponding first section of the column wiring to the second section of the column wiring;
  • the wiring space of the row transfer wires is located within the wiring space of the column transfer wires.
  • the row transfer lines are distributed on both sides of the opening area; along the first direction, the column transfer lines are distributed on the opening both sides of the area;
  • the column transfer line is connected to the corresponding column routing line through a column transfer via hole, and the row transfer line is connected to the corresponding row line through a row transfer via hole; the column transfer line
  • the distance between the via hole and the opening area is greater than the distance between the row transfer via hole and the opening area.
  • the transfer wires, the row wires and the column wires are disposed on different conductive layers.
  • the display panel includes a base substrate, a driving circuit layer, and a pixel layer that are sequentially stacked;
  • the driving circuit layer includes a first gate layer, a second gate layer and a metal wiring layer stacked on one side of the base substrate in sequence; the running lines are arranged on the first gate layer and the the second gate layer; the column wiring is arranged on the metal wiring layer;
  • the driving circuit layer also includes a transfer wiring layer; the transfer wiring layer is disposed on a side of the first gate layer away from the second gate layer, or is located on the metal wiring layer away from the first gate layer. One side of the second gate layer, or between two adjacent layers of the first gate layer, the second gate layer, and the metal wiring layer;
  • the transition line is disposed on the transition wiring layer.
  • the metal wiring layer includes a first source-drain metal layer
  • the transfer wiring layer includes a second source-drain metal layer located on a side of the first source-drain metal layer away from the base substrate; the transfer wire is disposed on the second source-drain metal layer.
  • the metal wiring layer includes a first source-drain metal layer and a second source-drain metal layer stacked on the side of the second gate layer away from the base substrate; Column wiring is arranged on the second source-drain metal layer;
  • the transfer wiring layer includes a third source-drain metal layer located on a side of the second source-drain metal layer away from the base substrate; the transfer line is disposed on the third source-drain metal layer.
  • the display area includes a transition area for arranging the transition lines, and a non-transition area surrounding the transition area;
  • the transfer wiring layer is provided with a column line resistance reducing structure corresponding to at least part of the column line; the column line resistance reducing structure passes through the corresponding column line Via electrical connections.
  • an electronic device including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of part of wiring on a display panel in an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of partial wiring of a display panel in a transition area in an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of partial wiring of a display panel in a transition area in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of partial wiring of a display panel in a transition area in an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of partial wiring of a display panel in a transition area in an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a partial distribution of row transfer lines in a transfer area in an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a partial distribution of column transfer wires in a transfer area in an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a pixel driving circuit in an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a semiconductor layer in a pixel driving region in an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a first gate layer in a pixel driving region in an exemplary embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a second gate layer in a pixel driving region in an exemplary embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of the first source-drain metal layer in the pixel driving region in an exemplary embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of the second source-drain metal layer of the pixel driving circuit in the pixel driving region in an exemplary embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a pixel driving region where the first source-drain metal layer is in the non-transition region in an exemplary embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of the second source-drain metal layer in the pixel driving region of the non-transition region in an exemplary embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a film layer structure of a display panel in an exemplary embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of the first source-drain metal layer, the second source-drain metal layer and part of the gate layer in the transfer region in an exemplary embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a pixel electrode layer, a first source-drain metal layer, a second source-drain metal layer, and a part of a gate layer in a transfer region in an exemplary embodiment of the present disclosure.
  • AA display area; A1, transition area; A2, non-transition area; BB, peripheral area; B1, binding area; CC, opening area; C1, opening packaging area; C2, opening; DH, second One direction; DV, second direction; DH1, first preset direction; DH2, second preset direction; Haxis, row central axis; Vaxis, column central axis; PDCA, pixel drive area; HPDC, pixel drive circuit row; VPDC, pixel drive circuit column; Gate, scanning signal; Reset, reset control signal; EM, enable signal; Vinit, initialization voltage; VDD, driving power supply voltage; VSS, public power supply voltage; Data, driving data; GL, scanning away GL1, the first section of the scan line; GL2, the second section of the scan line; RL, the reset control line; RL1, the first section of the reset control line; RL2, the second section of the reset control line; Can route; EML1, enable the first segment of the route; EML2, enable the second segment of the route; Vinit
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • FIG. 1 is a top structural diagram of a display panel provided by the present disclosure.
  • the display panel may include a hole area CC and a display area AA surrounding the hole area CC.
  • the opening area CC includes an opening C2 and an opening packaging area C1 surrounding the opening C2 for packaging.
  • the display area AA there are provided sub-pixels for displaying images and pixel driving circuits for driving the sub-pixels. Referring to Fig.
  • the display panel is also provided with a peripheral area BB surrounding the display area AA; a binding area B1 is provided at one end of the peripheral area BB, and the binding area B1 is used for connecting with external circuits (such as circuit boards, flexible circuit boards, Chip-on-chip, etc.) bonding connection.
  • external circuits such as circuit boards, flexible circuit boards, Chip-on-chip, etc.
  • the opening C2 makes it have greater light transmittance.
  • the opening may be a through hole penetrating the display panel, or a counterbore (a non-penetrating opening area of the display panel) for thinning or removing part of the film layer of the display panel, which is not specifically limited in the present disclosure.
  • a photosensitive component facing the opening C2 can be arranged behind the display panel; the photosensitive component can receive light from the front of the display panel through the opening C2.
  • the photosensitive component may be one or more light sensors, such as a camera, an optical fingerprint identification chip, a light intensity sensor, and the like.
  • the photosensitive component can be a camera, for example, a CCD (Charge Coupled Device) camera; in this way, the display device can realize off-screen photography and increase the screen-to-body ratio of the display device.
  • CCD Charge Coupled Device
  • the opening C2 may be circular; the opening sealing area C1 is a ring surrounding the opening C2, and its outer edge may be circular as a whole.
  • the outer edge of the hole packaging region C1 may be in the shape of a fold line in a part or in a microstructure, for example, in a part in a step shape.
  • the display panel may be provided with crack barrier dams, water and oxygen barriers and other structures, and may include organic or inorganic encapsulation structures, so as to encapsulate and protect the display area AA.
  • the shape of the opening C2 can also be other, such as rectangle, ellipse, etc., and the number of the opening C2 can be one or more.
  • the display area AA is provided with a data line DataL for providing driving data Data to the pixel driving circuit, and a scanning line GL for providing a scanning signal Gate to the pixel driving circuit.
  • the extending direction of the data line DataL intersects with the extending direction of the scanning line GL.
  • the extending direction of the data trace DataL may be defined as a second direction DV
  • the extending direction of the scanning trace GL may be defined as a first direction DH.
  • the first direction DH intersects with the second direction DV.
  • the first direction DH and the second direction DV are perpendicular to each other. It can be understood that the first direction DH may not be perpendicular to the second direction DV.
  • the opening area CC may be disposed at the end of the display area AA away from the binding area B1 .
  • the binding area B1 is located on one side of the display area AA, and the opening area CC is located away from the binding area B1.
  • the opening area CC may be disposed close to a corner of the display area AA, for example, disposed at a corner far away from the binding area B1 .
  • the direction of the opening area CC close to one of the top corners can be defined as the first preset direction DH1
  • the direction opposite to the first preset direction DH1 can be defined as the second preset direction DH2
  • a preset direction DH1 and a second preset direction DH2 are two different directions opposite to the first direction DH.
  • the display panel may be provided with running lines HL extending along the first direction DH, such as scanning lines GL for loading the scanning signal Gate to the pixel driving circuit, and reset control signals Reset for loading the pixel driving circuit.
  • the driving circuit layer is also provided with column wiring VL extending along the second direction DV, such as driving power supply wiring VDDL for loading driving power supply voltage VDD to the pixel driving circuit, and data wiring VDDL for loading driving data Data to the pixel driving circuit.
  • part of the traveling line HL is separated by the opening area CC into two corresponding sections, the first section of the traveling line HL1 and the second section of the traveling line HL2; wherein, the first section of the traveling line HL1 is set at the first section of the opening area CC.
  • the second segment HL2 of the running line is set on the side of the second preset direction DH2 of the opening area CC.
  • Part of the column wiring VL is separated by the opening area CC into two corresponding sections, the first section of the column wiring VL1 and the second section of the column wiring VL2.
  • the first section VL1 of the column wiring is arranged on the side of the opening area CC away from the binding area B1, and the second section VL2 of the column wiring is arranged on the side of the opening area CC close to the binding area B1.
  • the separated column traces VL and row traces HL need to be electrically connected through winding wires arranged in the hole packaging area C1 to ensure the continuity of signals on both sides of the hole area CC.
  • a transfer line TRL is provided in the display area AA. At least part of the first section VL1 of the column wiring is electrically connected to the corresponding second section VL2 of the column wiring through the corresponding transfer line TRL located in the open area CC; and/or, at least part of the first section HL1 of the line is connected to the corresponding line
  • the second line segment HL2 is electrically connected through the corresponding transition line TRL located in the open area CC.
  • the number of winding wires in the hole packaging area C1 can be reduced, thereby reducing the width of the hole packaging area C1, realizing the narrow frame of the hole area CC, further reducing the size of the hole area CC, and improving the electronic equipment. screen-to-body ratio and improved display quality.
  • the width of the hole packaging region C1 can be reduced to 0.5-0.6 mm.
  • part of the transfer line TRL can be used to ensure that at least some of the running lines HL that are cut off by the opening area CC ensure signal continuity, and the rest of the transfer line TRL can be used to enable the signal continuity of at least some of the running lines HL that are cut off by the opening area CC.
  • At least part of the column wiring VL ensures signal continuity.
  • part of the transfer line TRL is used to electrically connect the first segment of the row line HL1 to the corresponding second segment of the row line HL2
  • the rest of the transfer line TRL is used to connect the first segment of the column line VL1 to the corresponding second segment of the column line.
  • VL2 is electrically connected.
  • all the transfer lines TRL can be used to make at least some of the running lines HL that are cut off by the opening area CC ensure signal continuity, or all the transfer lines TRL can be used to make the signal continuity by the opening area CC
  • the isolated at least part of the column wiring VL ensures signal continuity.
  • the display panel of the present disclosure is further introduced and illustrated from the perspective of film layers as follows.
  • the display panel of the present disclosure includes a base substrate BP, a driving circuit layer F100 and a pixel layer F200 stacked in sequence.
  • the pixel layer is provided with light-emitting elements serving as sub-pixels
  • the driving circuit layer is provided with a pixel driving circuit for driving the sub-pixels.
  • the base substrate BP may be a base substrate of an inorganic material, or may be a base substrate of an organic material.
  • the material of the base substrate BP can be glass materials such as soda-lime glass, quartz glass, sapphire glass, or can be stainless steel, aluminum, nickel, etc. metallic material.
  • the material of the base substrate BP can be polymethyl methacrylate (Polymethyl methacrylate, PMMA), polyvinyl alcohol (Polyvinyl alcohol, PVA), polyvinyl phenol (Polyvinyl phenol, PVP), polyethersulfone (Polyether sulfone, PES), polyimide, polyamide, polyacetal, polycarbonate (Polycarbonate, PC), polyethylene terephthalate (Polyethylene terephthalate, PET), Polyethylene naphthalate (PEN) or a combination thereof.
  • the base substrate BP may also be a flexible base substrate, for example, the material of the base substrate BP may include polyimide (PI).
  • the driving circuit layer F100 is provided with a pixel driving circuit for driving sub-pixels.
  • any pixel driving circuit may include a transistor and a storage capacitor.
  • the transistor can be a thin film transistor, and the thin film transistor can be selected from top gate thin film transistor, bottom gate thin film transistor or double gate thin film transistor;
  • the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low temperature polysilicon Semiconductor materials, metal oxide semiconductor materials, organic semiconductor materials or other types of semiconductor materials; the thin film transistors may be N-type thin film transistors or P-type thin film transistors.
  • the types of any two transistors may be the same or different.
  • some transistors may be N-type transistors and some transistors may be P-type transistors.
  • the material of the active layer of some transistors may be low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be metal oxide semiconductor materials.
  • the thin film transistor is a low temperature polysilicon transistor. In some other embodiments of the present disclosure, some of the thin film transistors are low temperature polysilicon transistors, and some of the thin film transistors are metal oxide transistors.
  • the transistor may have a first terminal, a second terminal and a control terminal, one of which may be the source of the transistor and the other may be the drain of the transistor, and the control terminal may be the gate of the transistor. It can be understood that the source and the drain of the transistor are two opposite concepts that can be interchanged; when the working state of the transistor changes, for example, the direction of the current changes, the source and the drain of the transistor can be interchanged.
  • the driving circuit layer may include a plurality of conductive layers, so as to arrange the routing lines HL, column routing VL, transfer wire TRL and the like.
  • the row wires, the column wires and the transition wires may be respectively disposed on different conductive layers.
  • the driving circuit layer may include a gate layer (for example, a stacked first gate layer and a second gate layer) and a metal wiring layer stacked on one side of the substrate in sequence, and the gate
  • the electrode layer is used to set the row lines
  • the metal wiring layer is used to arrange the column lines
  • the driving circuit layer also includes a transfer wiring layer; the transfer wiring layer is arranged on the side of the first gate layer away from the second gate layer, or Located on the side of the metal wiring layer away from the second gate layer, or between two adjacent layers of the first gate layer, the second gate layer, and the metal wiring layer; the transfer line is arranged on the transfer wiring layer. In this way, it can be ensured that the column trace VL, the travel trace HL, and the transfer trace TRL avoid each other.
  • the metal wiring layer includes a first source-drain metal layer; the transfer wiring layer includes a second source-drain metal layer located on the side of the first source-drain metal layer away from the substrate; the transfer wire is arranged on the second source-drain metal layer metal layer.
  • each conductive layer of the driving circuit layer includes the first gate layer, the second gate layer, the first source-drain metal layer, and the second source-drain metal layer that are sequentially arranged on one side of the substrate; On the first source-drain metal layer, the transfer line is arranged on the second source-drain metal layer.
  • the metal wiring layer includes a first source-drain metal layer and a second source-drain metal layer stacked on the side of the second gate layer away from the substrate; the column wiring is arranged on the second source-drain metal layer
  • the transfer wiring layer includes a third source-drain metal layer located on the side of the second source-drain metal layer away from the base substrate; the transfer wire is arranged on the third source-drain metal layer.
  • each conductive layer of the driving circuit layer includes the first gate layer, the second gate layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain layer arranged on one side of the substrate in sequence.
  • the display area AA includes a transition area A1 for laying the transition line TRL, and a non-transition area A2 surrounding the transition area A1 .
  • the transfer wiring layer is provided with a column line resistance reduction structure VLD corresponding to at least part of the column line VL (for example, the driving power line resistance reduction structure VDDLD in FIG. line resistance reducing structure DataLD); the column line resistance reducing structure VLD is electrically connected to the corresponding column line VL through via holes.
  • the column line resistance reducing structure VLD is arranged in the same extending direction as the corresponding column line and overlapped, and is electrically connected through a plurality of via holes.
  • the transfer wiring layer may also be provided with a routing line resistance-reducing structure corresponding to at least part of the column routing VL, and the routing line resistance-reducing structure and the corresponding routing line VL are electrically connected through the via hole. connect.
  • the resistance-reducing structure of the running line can adjust the load of the running line, so that the load uniformity of the running line is improved, and the problem of inconsistency of the load of different running lines caused by the lack of sub-pixels in the opening area is alleviated.
  • the driving circuit layer may also include other film layers, for example, may include film layers such as a semiconductor layer, an insulating layer, a passivation layer, and a planarization layer.
  • the semiconductor layer may be a polysilicon semiconductor layer (such as a low-temperature polysilicon semiconductor layer), or a metal oxide semiconductor layer (such as an IGZO layer), or may include stacked polysilicon semiconductor layers and metal oxide semiconductor layers.
  • the lamination relationship of each film layer can be determined according to the film layer structure of the thin film transistor.
  • the semiconductor layer can be used to form the active layer of the transistor; the gate layer can be used to form the gate layer wiring such as scanning wiring and reset control wiring, and can also be used to form the gate of the transistor.
  • the source-drain metal layer can be used to form the wiring of the source-drain metal layer such as data leads and power leads, and can also be used to form part of the electrode plates of the storage capacitor.
  • the film layer structure of the driving circuit layer will be explained and illustrated exemplarily.
  • the driving circuit layer F100 of this example may include a semiconductor layer Poly, a first gate insulating layer GI1, a first gate layer G1, a second gate insulating layer stacked between the base substrate BP and the pixel layer F200.
  • These film layers can form various transistors, storage capacitors, column wiring, row wiring and transfer wiring, etc.
  • the driving circuit layer F100 may further include a passivation layer, and the passivation layer may be disposed on the surface of the source-drain metal layer away from the base substrate BP, so as to protect the source-drain metal layer.
  • the passivation layer may include a first passivation layer disposed on the surface of the first source-drain metal layer and a second passivation layer disposed on the surface of the second source-drain metal layer.
  • the driving circuit layer F100 may further include a buffer material layer Buff disposed between the base substrate BP and the semiconductor layer Poly, and the semiconductor layer Poly, the gate layer, etc. are located on the buffer material layer Buff away from the base substrate BP. side.
  • the material of the buffer material layer may be inorganic insulating materials such as silicon oxide and silicon nitride.
  • the buffer material layer can be a layer of inorganic material, or a layer of inorganic material stacked in multiple layers.
  • the pixel layer F200 may be provided with light-emitting elements distributed in an array as sub-pixels, and each light-emitting element emits light under the control of the pixel driving circuit.
  • the light-emitting element can be an organic electroluminescent diode (OLED), a micro light-emitting diode (Micro LED), a quantum dot-organic electroluminescent diode (QD-OLED), a quantum dot light-emitting diode (QLED) or other types of light-emitting elements.
  • the light-emitting element is an organic light-emitting diode (OLED)
  • the display panel is an OLED display panel.
  • a possible structure of the pixel layer is exemplarily introduced as follows, taking the light-emitting element as an organic electroluminescence diode as an example.
  • the pixel layer F200 can be disposed on the side of the driving circuit layer F100 away from the base substrate BP, which can include a pixel electrode layer Ano, a pixel definition layer PDL, and a supporting post layer (as shown in FIG. 16 ). Not shown in ), the organic light-emitting functional layer EL and the common electrode layer COM.
  • the pixel electrode layer Ano has a plurality of pixel electrodes in the display area of the display panel;
  • the pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes in the display area, and any pixel opening exposes the corresponding At least a partial area of the pixel electrode.
  • the support column layer includes a plurality of support columns in the display area, and the support columns are located on the surface of the pixel definition layer PDL away from the base substrate BP, so as to support a fine metal mask (Fine Metal Mask, FMM) during the evaporation process.
  • the organic light emitting functional layer EL covers at least the pixel electrodes exposed by the pixel definition layer PDL.
  • the organic light-emitting functional layer EL may include an organic electroluminescent material layer, and may include one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. or multiple.
  • Each film layer of the organic light-emitting functional layer EL can be prepared by an evaporation process, and a fine metal mask or an open mask (Open Mask) can be used to define the pattern of each film layer during evaporation.
  • the common electrode layer COM may cover the organic light emitting functional layer EL in the display area. In this way, the pixel electrode, the common electrode layer COM and the organic light-emitting functional layer EL between the pixel electrode and the common electrode layer COM form an organic light-emitting diode, and any organic light-emitting diode can be used as a sub-pixel of the display panel.
  • the pixel layer F200 may further include a light extraction layer located on the side of the common electrode layer COM away from the base substrate BP, so as to enhance the light extraction efficiency of the organic light emitting diode.
  • the display panel may further include a thin film encapsulation layer TFE.
  • the thin film encapsulation layer TFE is disposed on the surface of the pixel layer F200 away from the base substrate BP, and may include alternately stacked inorganic encapsulation layers and organic encapsulation layers.
  • the inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the organic light-emitting functional layer EL to cause material degradation.
  • the edge of the inorganic encapsulation layer may be located in the peripheral region.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers, so as to realize planarization and weaken the stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.
  • the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer stacked on the side of the pixel layer F200 away from the base substrate BP in sequence. It can be understood that the thin film encapsulation layer TFE also encapsulates the display area AA in the opening encapsulation area C1 to protect each sub-pixel in the display area and prevent water and oxygen from invading the display area AA from the opening C2.
  • the display panel may further include a touch function layer TS, and the touch function layer TS is disposed on a side of the thin film encapsulation layer TFE away from the base substrate BP for realizing touch operation of the display panel.
  • the touch function layer TS is disposed on a side of the thin film encapsulation layer TFE away from the base substrate BP for realizing touch operation of the display panel.
  • the display panel may further include an anti-reflection layer, which may be disposed on a side of the thin film encapsulation layer away from the pixel layer to reduce the reflection of the display panel on ambient light, thereby reducing the impact of ambient light on the display effect.
  • the anti-reflection layer may include a color filter layer and a black matrix layer that are stacked, so as to reduce the interference of ambient light while avoiding reducing the light transmittance of the display panel.
  • the antireflection layer may be a polarizer, such as a patterned coated circular polarizer. Further, the antireflection layer can be disposed on the side of the touch function layer away from the base substrate BP.
  • the transition line TRL may include a row transition line HTRL for making the signal of the row line HL continuous, and a column transition line for making the signal of the column line VL continuous.
  • VTRL a row transition line HTRL for making the signal of the row line HL continuous
  • VTRL a column transition line for making the signal of the column line VL continuous.
  • the first section VL1 of the column wiring is electrically connected with the corresponding second section VL2 of the column wiring through the corresponding column transfer line VTRL; the first section HL1 of the running line is connected to the corresponding second section HL2 of the running line through the corresponding row switching line HTRL is electrically connected.
  • the column transition line VTRL is arranged farther from the hole area CC.
  • the wiring space of the row transition line HTRL is located within the wiring space of the column transition line VTRL.
  • the row transition line HTRL may also be farther away from the hole region CC.
  • the row transition line HTRL is electrically connected to the corresponding row line HL through the row transition via
  • the column line VTRL is electrically connected to the corresponding column trace VL through the column transition via.
  • the row transfer via is formed in the insulating layer adjacent to the transfer wiring layer and overlaps the row transfer wire HTRL
  • the column transfer via is formed in the insulating layer adjacent to the transfer wiring layer and overlaps the column transfer wire HTML overlaps.
  • the distance between the column transfer vias and the opening area is greater than the distance between the row transfer vias and the opening area.
  • the row transition lines are distributed on both sides of the opening area; along the first direction, the column transition lines are distributed on the opening both sides of the hole area.
  • the row transfer line HTRL can be divided into two different types: the first row transfer line H1TRL and the second row transfer line H2TRL.
  • the row transfer line HTRL may only include the first row transfer line H1TRL or only the second row transfer line H2TRL, or may include both the first row transfer line H1TRL and the second row transfer line H2TRL.
  • the first line transfer line H1TRL may include the first segment HTRL1 of the row transfer line connected in sequence, the second segment HTRL2 of the row transfer line and the third segment HTRL3 of the row transfer line; wherein, the first segment HTRL1 of the row transfer line
  • the third section HTRL3 of the and row transfer line extends along the second direction DV
  • the second section HTRL2 of the row transfer line extends along the first direction DH.
  • the first segment HTRL1 of the row transfer line is electrically connected to the first segment HL1 of the corresponding travel line
  • the third segment HTRL3 of the row transfer line is electrically connected to the second segment HL2 of the corresponding travel line.
  • the first line transfer line H1TRL is electrically connected to the first segment HL1 of the corresponding travel line through the first segment HTRL1 of the row transfer line, for example, the end of the first segment HTRL1 of the row transfer line far away from the second segment HTRL2 of the row transfer line is connected to the corresponding
  • the first segment of the running line is electrically connected to HL1.
  • the first row transfer wire H1TRL is electrically connected to the corresponding travel line second segment HL2 through the row transfer wire third segment HTRL3, for example, the end of the row transfer wire third segment HTRL3 away from the row transfer wire second segment HTRL2 is electrically connected to the corresponding travel line.
  • the second segment of the line HL2 is electrically connected.
  • the second section HTRL2 of the row transfer line can be arranged on the side of the opening area CC close to or away from the binding area B1.
  • each row transfer line HTRL is the first row transfer line H1TRL.
  • the second line transfer line H2TRL includes the fourth segment HTRL4 of the row transfer line, the first segment HTRL1 of the row transfer line, the second segment HTRL2 of the row transfer line, the third segment HTRL3 of the row transfer line and the row
  • the fifth segment HTRL5 of the line transfer line; the first segment HTRL1 of the row transfer line and the third segment HTRL3 of the row transfer line extend along the second direction DV; the fourth segment HTRL4 of the row transfer line, the second segment HTRL2 of the row transfer line, and the fifth row transfer line Segment HTRL5 extends along a first direction DH.
  • the second row transfer wire H2TRL is electrically connected to the corresponding first segment HL1 of the travel line through the fourth segment HTRL4 of the row transfer wire, for example, the end of the first segment HTRL1 of the row transfer wire far away from the end of the row transfer wire HTRL4 is connected to the corresponding travel line.
  • the first section HL1 of the line is electrically connected;
  • the second line transfer line H2TRL is electrically connected to the corresponding second section HL2 of the line through the fifth section HTRL5 of the line line, for example, the fifth section HTRL5 of the line line is far away from the third section of the line line line
  • the end of HTRL3 is electrically connected to the corresponding second segment HL2 of the running line.
  • some of the row transfer lines HTRL are the first row transfer lines H1TRL, and the rest of the row transfer lines HTRL are the second row transfer lines H2TRL. Further, along the second direction DV, the first segment HL1 of the running line corresponding to the second row of transfer line H2TRL is set close to the middle of the opening area CC, and the first segment of each running line HL1 corresponding to the first row of transfer line H1TRL is close to The ends of the open area CC are provided.
  • all the row transition lines HTRL may be the second row transition lines H2TRL.
  • the opening area CC has a row central axis Haxis extending along the first direction DH, and the row central axis Haxis passes through the geometric center of the opening area CC.
  • the row transfer line HTRL corresponding to the first segment HL1 of each running line located on one side of the row central axis Haxis is located on the same side of the row central axis Haxis.
  • the running line HL located on the side of the central axis Haxis of the row close to the binding area B1 of the binding area, the second section HTRL2 of the row transfer line connected to it is located on the side of the opening area CC close to the binding area B1 of the binding area;
  • the running line HL located on the side of the central axis Haxis away from the binding area B1 is connected to the second segment of the row transfer line HTRL2 located on the side of the opening area CC away from the binding area B1.
  • the row transition line electrically connected to the first segment HL1 of the travel line far away from the row central axis Haxis The second stage HTRL2 is set close to the opening area CC. In other words, on the same side of the row center axis Haxis, the farther the distance between the first segment HL1 of the travel line and the row center axis Haxis is, the closer the second segment HTRL2 of the row transfer line electrically connected to the first segment HL1 of the travel line is to the opening Zone CC settings.
  • the first row of transfer wires H1TRL is in the shape of a square to form an accommodating space.
  • the first row transfer line H1TRL connected by the first section HL1 of two adjacent travel lines the first row transfer line H1TRL connected by the first segment HL1 of the travel line far away from the row central axis Haxis is located near the row central axis Haxis In the accommodating space of the first row of transfer line H1TRL connected to the first section HL1 of the walking line.
  • the running line HL includes the scanning line GL; a part of the scanning line GL is separated by the opening area CC into the corresponding first section GL1 of the scanning line located on both sides of the opening area CC and the second segment of the scan line GL2.
  • the first section GL1 of the scanning line is located on the side of the first predetermined direction DH1 of the opening area CC
  • the second section GL2 of the scanning line is located on the side of the second predetermined direction DH2 of the opening area CC.
  • the corresponding first section GL1 of the scanning line and the second section GL2 of the scanning line are electrically connected through the corresponding row transfer line HTRL.
  • the driving circuit layer includes a first gate layer G1 , a second gate layer G1 , a first source-drain metal layer SD1 and a second source-drain metal layer SD2 which are stacked in sequence.
  • the scan line GL is set on G1
  • the row transfer line HTRL is set on SD2.
  • the first source-drain metal layer SD1 is provided with a scan transfer structure GD corresponding to the first segment GL1 of the scan line and the second segment GL2 of the scan line.
  • the scanning transfer structure GD corresponding to the first section GL1 of the scanning line is electrically connected to the first section GL1 of the scanning line through a via hole, for example, the scanning transfer structure GD corresponding to the first section GL1 of the scanning line is connected to the first section of the scanning line GL1.
  • the end of a segment of GL1 (the end near the opening area CC) is electrically connected through the via hole.
  • the scanning transfer structure GD corresponding to the second section GL2 of the scanning line is electrically connected to the second section GL2 of the scanning line through a via hole, for example, the scanning transfer structure GD corresponding to the second section GL2 of the scanning line is connected to the second section GL2 of the scanning line.
  • the ends of the two segments GL2 are electrically connected through via holes.
  • the row transfer line HTRL corresponding to the scanning line GL has one end electrically connected to the scanning transfer structure GD corresponding to the first section GL1 of the scanning line through a via hole, and the other end is electrically connected to the scanning transfer structure GD corresponding to the second section GL2 of the scanning line. Structures GD are electrically connected through vias.
  • the first segment of the scanning line GL1 and the second segment of the scanning line GL2 may also be electrically connected through a routing wire disposed in the opening packaging area C1 .
  • the fourth segment HTRL4 of the row transfer line overlaps the corresponding first segment GL1 of the scanning line
  • the fifth segment HTRL5 of the row transfer line overlaps the corresponding The GL2 overlap setting of the second section of the scan line.
  • the fourth section HTRL4 of the row transfer line and the corresponding first section GL1 of the scanning line extend substantially parallel and side by side along the first direction DH, and the overlapping part of the orthographic projection of the two on the base substrate BP is along the first direction DH extension;
  • the fifth segment HTRL5 of the row transfer line and the corresponding second segment GL2 of the scanning line extend along the first direction DH substantially parallel and side by side, and the overlapping part of the orthogonal projection of the two on the base substrate BP is along the first direction
  • the direction DH extends. In this way, the interference received by the second-row transfer line H2TRL can be reduced.
  • the running lines HL include the enabling lines EML; part of the enabling lines EML are separated by the opening area CC into corresponding enabling lines located on both sides of the opening area CC.
  • the first segment of the enabling trace EML1 is located on the side of the first predetermined direction DH1 of the opening area CC, and the second segment of the enabling trace EML2 is located on the side of the second preset direction DH2 of the opening area CC.
  • the corresponding first section EML1 of the enabling wiring and the second section EML2 of the enabling wiring are electrically connected through the corresponding row transition line HTRL.
  • the connection between the first segment of the enabling trace EML1 and the corresponding second segment of the enabling trace EML2 may also be through Wired electrical connections can be made.
  • the display panel includes a stacked first gate layer and a second gate layer; the first gate layer is provided with a first electrode plate that enables wiring EML and a storage capacitor; the second gate layer is provided with a storage The second electrode plate of the capacitor; wherein, the enabling winding wire is arranged on the first gate layer and/or the second gate layer.
  • each enabling winding wire can be alternately arranged in the first gate layer and the second gate layer, so as to reduce the distance between adjacent enabling winding wires and further reduce the opening
  • the width of the packaging area C1 realizes a smaller frame of the opening in the screen.
  • the first source-drain metal layer SD1 can be provided in the open-hole packaging area C1 to correspond to the first section EML1 of the enabling wiring and the second section EML2 of the enabling wiring.
  • the enable winding wire (not shown in Figure 17 and Figure 18) corresponding to the first section EML1 of the enabling wiring and the second section EML2 of the enabling wiring, and the two ends of which are respectively connected to the first section of the enabling wiring through via holes.
  • the enabling transition structure EMD corresponding to the segment EML1 is electrically connected to the enabling transition structure EMD corresponding to the second segment EML2 of the enabling trace.
  • the running line HL includes the initialization line VinitL; wherein, a part of the initialization line VinitL is separated by the opening area CC into a corresponding first segment of the initialization line located on both sides of the opening area CC and initialize the second segment of the trace.
  • the corresponding first section of the initialization wiring and the second section of the initialization wiring are electrically connected through a row transition line HTRL.
  • initialization line VinitL disconnected by the hole area CC can also adopt other methods to keep the signal continuous.
  • initialization voltage buses may be arranged on both sides of the display area AA in the first direction DH, and the two ends of the initialization line VinitL are respectively electrically connected to the initialization voltage buses on both sides.
  • both ends of the initialization line VinitL not separated by the opening area CC can be loaded with the initialization voltage Vinit through the initialization voltage bus, and the first section of the initialization line and the second section of the initialization line can respectively pass through the adjacent initialization voltage bus Obtain the initialization voltage Vinit.
  • the opening packaging area C1 is provided with a reference voltage winding line VinitER surrounding the opening C2; the first segment of each initialization wiring (not shown in FIG. Out) and the second segment of each initialization line (not shown in FIG. 17 and FIG. 18 ) are electrically connected to the reference voltage winding line VinitER.
  • VinitER the reference voltage winding line
  • the running line HL includes a reset control wiring RL; wherein, a part of the reset control wiring RL is separated by the opening area CC into corresponding reset control wirings located on both sides of the opening area CC
  • the first section RL1 and the second section RL2 of the reset control line are electrically connected through a row transfer line HTRL.
  • the first section RL1 of the reset control wiring and the second section RL2 of the reset control wiring may also be electrically connected through a winding wire arranged in the opening packaging area C1. .
  • the signal of one of the reset control lines RL is the same as that of the scan line GL (for example, it is at a high level and at a low level at the same time).
  • the scan lines GL and the reset control lines RL loaded with the same signal can be used as the scan lines GL and the reset control lines RL corresponding to each other.
  • the first section GL1 of the scan line and the first section RL1 of the corresponding reset control line are arranged side by side, and are electrically connected to the first section HTRL1 of the same row of transfer lines; the second section GL2 of the scan line is connected to the corresponding reset control line.
  • the second segment RL2 of the line is arranged side by side, and is electrically connected to the third segment HTRL3 of the transfer line in the same row. In this way, it is not necessary to set up a special row transfer line HTRL for the continuity of the signal of the reset control line RL, thereby reducing the number of row transfer lines HTRL, reducing the size of the wiring space of the row transfer lines HTRL, and improving the uniformity of the display panel. sex.
  • the opening packaging area C1 is provided with a scanning transfer structure GD corresponding to the first section GL1 of the scanning line and the second section GL2 of the scanning line;
  • the first section GL1 of the scan line and the first section RL1 of the corresponding reset control line are electrically connected to the corresponding scan transfer structure GD;
  • the second section GL2 of the scan line and the second section RL2 of the corresponding reset control line are connected to the corresponding
  • the scanning transfer structure GD is electrically connected.
  • the scan line GL and the corresponding reset control line RL are arranged on the same conductive layer, for example, both are located on the first gate layer; the scan line GL, the scan transfer structure GD and the row transfer line HTRL are located on different conductive layers. layer.
  • the first section GL1 of the scan line and the first section RL1 of the corresponding reset control line are electrically connected to the corresponding scan transfer structure GD through the via hole;
  • the second section GL2 of the scan line and the second section of the corresponding reset control line RL2 is electrically connected to the corresponding scanning transition structure GD through the via hole;
  • the scanning transition structure GD corresponding to the first section of the scanning line GL1 is electrically connected to the row transition line HTRL corresponding to the first section of the scanning line GL1 through the via hole ;
  • the scanning transfer structure GD corresponding to the second section of the scanning line GL2 is electrically connected to the row transfer line HTRL corresponding to the second section of the scanning line GL2 through a via hole.
  • the running lines HL include an initialization line VinitL, a scanning line GL, a reset control line RL and an enabling line EML.
  • the first section of the initialization line and the second section of the initialization line are respectively electrically connected to the adjacent initialization voltage bus, and the first section of the initialization line and the second section of the initialization line are electrically connected to the adjacent initialization voltage bus.
  • the two segments are not electrically connected through the row transition line HTRL located in the display area AA.
  • the reference voltage winding line VinitER surrounding the opening C2 is set in the opening packaging area C1, and the ends of the first section of the initialization line and the second section of the initialization line near the opening area CC are connected with the reference voltage winding line Wire VinitER electrical connections.
  • the enabling traces EML separated by the opening area CC the first section EML1 of the enabling wiring and the corresponding second section EML2 of the enabling wiring are electrically connected through the enabling routing wire located in the opening packaging area C1.
  • the first segment GL1 of the scan line and the first segment RL1 of the reset control line loaded with the same signal are electrically connected to the first segment HTRL1 of the same row transfer line
  • the second section GL2 of the scanning line loaded with the same signal and the second section RL2 of the reset control line are electrically connected to the third section HTRL3 of the same row transfer line, so that the first section GL1 of the scanning line loaded with the same signal, the scanning line
  • the second section GL2, the first section RL1 of the reset control wiring, and the second section RL2 of the reset control wiring are electrically connected through the same row of transfer wires HTRL.
  • the first section HTRL1 of the row transition line and the third section HTRL3 of the row transition line overlap with the driving power supply line VDDL respectively.
  • the first section HTRL1 of the row transfer line can be arranged in parallel with one of the driving power supply lines VDDL (in different film layers and in the same extending direction), and the first section HTRL1 of the row transfer line and the driving power supply line VDDL are on the substrate substrate.
  • the overlapping portion of the orthographic projection on BP may extend along the second direction DV.
  • the third section HTRL3 of the row transfer line can be arranged in parallel with one of the driving power supply lines VDDL (in different film layers and in the same extension direction), and the third section HTRL3 of the row transfer line and the driving power supply line VDDL are on the substrate BP
  • the coincident portion of the orthographic projection of can extend along the second direction DV.
  • the driving power trace VDDL can provide a certain signal shielding effect for the row transfer wire HTRL, and reduce the crosstalk of the internal signal of the display panel to the row transfer wire HTRL.
  • the width of each row transfer line HTRL can be determined as required, so that the loads of each row line HL are as close as possible to improve the uniformity of the display panel. In this way, the widths of any two row transfer lines HTRL may be the same or different.
  • the column transfer line VTRL may include a first segment of the column transfer line VTRL1, a second segment of the column transfer line VTRL2, and a third segment of the column transfer line VTRL3; , the first segment VTRL1 of the column transfer line and the third segment VTRL3 of the column transfer line extend along the first direction DH, and the second segment VTRL2 of the column transfer line extends along the second direction DV.
  • the column transition line VTRL is electrically connected to the corresponding first segment VL1 of the column line through the first section VTRL1 of the column line, and the column line VTRL is electrically connected to the second section VL2 of the corresponding column line through the third section VTRL3 of the column line.
  • the second segment VTRL2 of the column transfer line can be disposed on one side of the opening area CC in the first preset direction DH1 or the second preset direction DH2.
  • the open area CC includes a column axis Vaxis extending along the second direction DV, and the column axis Vaxis passes through the geometric center of the open area CC.
  • the running line HL located on the side of the first preset direction DH1 of the column central axis Vaxis, the second section VTRL2 of the column transfer line connected to it is located on the side of the first preset direction DH1 of the opening area CC; located on the column central axis
  • the running line HL on the side of the second preset direction DH2 of the Vaxis is connected to the second segment VTRL2 of the column transition line on the side of the second preset direction DH2 of the opening area CC.
  • the column transition line connected to the first segment VL1 of the column line far away from the column central axis Vaxis The second section of VTRL2 is set far away from the opening area CC. In other words, on the same side of the column central axis Vaxis, the farther the distance between the first segment VL1 of the column trace and the column central axis Vaxis is, the farther away the second segment VTRL2 of the column transfer line connected to the first segment VL1 of the column trace is. Hole area CC.
  • Such setting can make the lengths of the second section VTRL2 of each column transfer line close to each other, reduce the signal difference between each column line VL, and further facilitate the debugging of the display panel.
  • the column transfer line VTRL can also be arranged in other ways, for example, in the second segment VTRL2 of the column transfer line connected by the first segment VL1 of two adjacent column lines, the column line far away from the column central axis Vaxis
  • the second segment VTRL2 of the column transfer line connected to the first segment VL1 is set close to the opening area CC.
  • the column wiring VL includes the driving power wiring VDDL; part of the driving power wiring VDDL is separated by the opening area CC into the corresponding first section of the driving power wiring VDDL1 and the driving power wiring
  • the second section VDDL2 the first section VDDL1 of the driving power line is located on the side of the opening area CC away from the binding area B1, and the second section of the driving power line VDDL2 is located on the side of the opening area CC close to the binding area B1; that is The corresponding first segment VDDL1 of the driving power trace and the second segment VDDL2 of the driving power trace are respectively located on both sides of the opening area CC.
  • the first section VDDL1 of the driving power line is electrically connected to the corresponding second section VDDL2 of the driving power line through the column transfer line VTRL.
  • other conductive layers of the driving circuit layer may be provided with conductive structures electrically connected to the driving power line VDDL, such as the second electrode plate of the storage capacitor; one of these conductive structures arranged in a row can be connected to each other, for example, the second electrode plates of the storage capacitors of adjacent pixel driving circuits in a row can be connected to each other.
  • the driving power supply voltage VDD can have a gridded signal path.
  • the electrical connection between the first section VDDL1 of the driving power supply line and the second section VDDL2 of the driving power supply line may not be electrically connected through the column transfer line VTRL, but through the gridded connection of the driving power supply voltage VDD.
  • the signal path is used to obtain the driving power supply voltage VDD. In this way, the wiring quantity and wiring space of the column transfer line VTRL can be reduced.
  • the column wiring VL includes the data wiring DataL; wherein, part of the data wiring DataL is separated by the opening area CC into the corresponding first section of the data wiring DataL1 and the second section of the data wiring.
  • Section DataL2; the first section DataL1 of the data line is located on the side of the opening area CC away from the binding area B1, and the second section DataL2 of the data line is located on the side of the opening area CC close to the binding area B1; that is, the corresponding data line
  • the first section DataL1 of the line and the second section DataL2 of the data line are respectively located on both sides of the opening area CC.
  • the corresponding first segment DataL1 of the data trace and the second segment DataL2 of the data trace are electrically connected through the corresponding column transfer line VTRL.
  • the column wiring VL includes a driving power supply wiring VDDL and a data wiring DataL.
  • the driving power lines VDDL separated by the opening area CC the first section VDDL1 of the driving power line and the second section VDDL2 of the driving power line are not electrically connected through the column transfer line VTRL located in the display area AA. It is not electrically connected through the routing wire located in the hole packaging area C1.
  • the first section of the data line DataL1 and the corresponding second section of the data line DataL2 are electrically connected through the column transfer line VTRL located in the display area AA.
  • the second segment VTRL2 of the column transition line connected to the first segment DataL1 of two adjacent data lines the second segment VTRL2 of the column transition line connected to the first segment DataL1 of the data line far away from the column central axis Vaxis CC setting away from the hole opening area.
  • the end of the first segment VTRL1 of the column transfer wire away from the second segment VTRL2 of the column transfer wire overlaps and is electrically connected to the corresponding first segment VL1 of the column routing wire.
  • the end of the third segment VTRL3 of the column transition line away from the second segment VTRL2 of the column transition line overlaps and is electrically connected to the corresponding second segment VL2 of the column routing line.
  • the end of the first section VTRL1 of the column transfer line is electrically connected to the corresponding first section VL1 of the column line through the via hole
  • the end of the third section VTRL3 of the column line is connected to the second section of the corresponding column line through the via hole.
  • VL2 is electrically connected.
  • the column transfer line VTRL includes two parts respectively located on both sides of the column axis Vaxis; each column transfer line VTRL located on the same side of the column axis Vaxis, which The respective end portions are arranged linearly along the second direction DV.
  • the ends of the first segment VTRL1 of each column transfer line and the ends of the third segment VTRL3 of each column transfer line are arranged in a straight line along the second direction DV;
  • the first segment VTRL1 of the column transfer line It can be electrically connected to the first section VL1 of the corresponding column wiring through the via hole located at its end or non-end, and the third section VTRL3 of the column transfer line can be connected to the corresponding column wiring through the via hole located at its end or non-end
  • the second segment VL2 is electrically connected. In this way, it can be ensured that the impact of the column transfer line VTRL on the visual effect around the opening area CC is more uniform.
  • the second segment VTRL2 of the column transfer line overlaps with the driving power line VDDL.
  • the second segment VTRL2 of the column transfer line and the driving power line VDDL extend along the second direction DV, and the orthographic projections of the two on the base substrate BP extend along the second direction DV.
  • the driving power line VDDL can provide a signal shielding effect for the driving data Data loaded on the second segment VTRL2 of the column transfer line, and improve the stability of the driving data Data.
  • the display area AA is provided with array-distributed pixel driving circuits; the pixel driving circuits are arranged as a plurality of pixel driving circuit rows HPDC and a plurality of pixel driving circuit columns VPDC.
  • any pixel driving circuit row HPDC includes pixel driving circuits sequentially arranged along the first direction;
  • any pixel driving circuit column VPDC includes pixel driving circuits sequentially arranged along the second direction.
  • each row transition line second section HTRL2 located on the same side of the row central axis Haxis is divided into a plurality of row transition line second sections.
  • the second segment group of each line transfer line includes a plurality of adjacent second segment HTRL2 of row transfer lines, for example, including 2 to 4 adjacent second segment HTRL2 of row transfer lines; the second segment of each row transfer line
  • the segment groups are arranged to overlap with the same pixel driving circuit row HPDC, and the second segment groups of adjacent row transfer lines are respectively arranged to overlap with two adjacent pixel driving circuit rows HPDC.
  • each group of the second section HTRL2 of row transition lines includes three second sections of row transition lines HTRL2.
  • the first row transfer line H1TRL is composed of a first section of the row transfer line HTRL1 , a second section of the row transfer line HTRL2 and a third section of the row transfer line HTRL3 . Then the first section HTRL1 of the row transfer line and the third row transfer line can be determined according to the end positions of the first segment HL1 of the travel line and the second segment HL2 of the travel line corresponding to the first row transfer line H1TRL close to the opening area CC. The position of segment HTRL3, and then determine the length of the second segment HTRL2 of the line transfer line.
  • the end of the first section HL1 of the running line close to the open area CC can be connected to the end of the first section HTRL1 of the row transfer line close to the open area CC; the end of the second section HL2 of the running line close to the open area CC It can be connected with the end of the second section HTRL2 of the row transfer line close to the opening area CC.
  • the first segment HTRL1 of the row transition line and the third segment HTRL3 of the row transition line extend along the second direction DV and overlap with the column VPDC of the pixel driving circuit.
  • each pixel driving circuit column VPDC there is no first segment HTRL1 of a plurality of row transfer lines extending in parallel or a third segment HTRL3 of a plurality of row transfer lines extending in parallel.
  • the wiring area of each pixel driving circuit column VPDC only overlaps with the first segment HTRL1 of the row transition line or the third segment HTRL3 of the row transition line.
  • the first section HTRL1 of the row transition line and the third section HTRL3 of the row transition line overlap with the driving power line VDDL in the pixel driving circuit column VPDC. It can be understood that, in the wiring space of the pixel driving circuit column VPDC, there may be two first segment HTRL1 or third segment HTRL3 of the row transfer line located on both sides of the row central axis Haxis.
  • the plurality of pixel driving circuit columns VPDC may not be separated from each other by the pixel driving circuit column VPDC.
  • the second segment HTRL2 of each row transfer line is sequentially numbered in a direction away from the row central axis Haxis, and the number of the second segment HTRL2 of the row transfer line closest to the row central axis Haxis is Connect the second segment of HTRL2 for the first row, and the rest are analogous.
  • the first segment HTRL1 of the line transfer line connected to the second segment HTRL2 of the i-th line transfer line as HTRL1(i)
  • the second row transfer line H2TRL is composed of the row transfer line fourth section HTRL4, the row transfer line first segment HTRL1, and the row transfer line second segment HTRL2 connected in sequence. 1.
  • the first segment HTRL1 of each of the row transfer lines HTRL can be arranged in a one-to-one correspondence with a plurality of adjacent pixel drive circuit columns VPDC.
  • the third section HTRL3 of each row transfer line HTRL of these row transfer lines HTRL can be arranged in a one-to-one correspondence with a plurality of adjacent pixel driving circuit columns VPDC.
  • the first segments VTRL1 of the two adjacent column transition lines along the second direction DV are respectively located in two adjacent pixel drive circuit rows HPDC;
  • the third segment VTRL3 of the two column transfer lines is respectively located in two adjacent pixel drive circuit rows HPDC;
  • the second segment VTRL2 of the two adjacent column transfer lines along the first direction DH is respectively located in two adjacent pixels
  • the driving circuit is listed in VPDC. In this way, the wiring space of the column transfer line VTRL can be reduced.
  • the width of each column transfer line VTRL can be determined as required, so that the loads of each column line VL are as close as possible to improve the uniformity of the display panel. In this way, the widths of any two column transfer lines VTRL may be the same or different.
  • the display panel of this example is provided with an opening area CC near a corner of the display area AA, and the opening area CC includes an opening C2 and an opening packaging area C1 surrounding the opening C2.
  • the display area AA Around the opening area CC, the display area AA has a transition area A1, which is used for laying transition lines TRL.
  • the display area AA also includes a non-transition area A2 surrounding the transition area A1.
  • the display panel of this example includes a base substrate BP, a driving circuit layer F100 and a pixel layer F200 which are stacked in sequence.
  • the driving circuit layer F100 includes buffer material layer Buff, semiconductor layer Poly, first gate insulating layer GI1, first gate layer G1, second gate insulating layer GI2, second gate layer G2, The interlayer dielectric layer ILD, the first source-drain metal layer SD1, the first planarization layer PLN1, the second source-drain metal layer SD2 and the second planarization layer PLN2; the pixel layer is provided with an OLED as a sub-pixel.
  • the display area AA is provided with array-distributed pixel driving circuits.
  • the pixel driving circuit has a 7T1C architecture, including a capacitance reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and an electrode reset transistor T7 and storage capacitor Cst.
  • the source of the driving transistor T3, the drain of the first light emission control transistor T5, and the drain of the data writing transistor T4 are electrically connected to each other, and the drain of the driving transistor T3 and the source of the threshold compensation transistor T2 ,
  • the source of the second light emission control transistor T6 is electrically connected to each other, the gate T3G of the driving transistor T3, the first electrode plate CP1 of the storage capacitor, the drain of the threshold compensation transistor T2, and the drain of the capacitor reset transistor T1 are electrically connected to each other.
  • the driving transistor T3 is configured to output a driving current to control the brightness of the OLED under the control of the voltage on the gate T3G of the driving transistor T3.
  • the source of the data writing transistor T4 is used to load the driving data Data
  • the gate T4G of the data writing transistor T4 is used to load the scanning signal Gate
  • the data writing transistor T4 is configured to output the driving data Data to Data is written to the drain of transistor T4.
  • the gate T2G of the threshold compensation transistor T2 is used for loading the scanning signal Gate, and is configured to be turned on in response to the scanning signal Gate, so as to compensate the threshold voltage of the driving transistor T3.
  • the gate T1G of the capacitor reset transistor T1 is used to load the reset control signal Reset
  • the source of the capacitor reset transistor T1 is used to load the initialization voltage Vinit
  • the capacitor reset transistor T1 is configured to supply the drain of the capacitor reset transistor T1 in response to the reset control signal Reset Pole load initialization voltage Vinit.
  • the source of the electrode reset transistor T7 is used to load the initialization voltage Vinit
  • the gate T7G of the electrode reset transistor T7 is used to load the reset control signal Reset, and is configured to load the initialization voltage to the drain of the electrode reset transistor T7 in response to the reset control signal Reset Vinit.
  • the source of the first light emission control transistor T5 is used to load the driving power supply voltage VDD
  • the gate T5G of the first light emission control transistor T5 is used to load the enable signal EM
  • the gate T6G of the second light emission control transistor T6 is used to load the enable signal.
  • signal EM; the first light emission control transistor T5 and the second light emission control transistor T6 are used to be turned on in response to the enable signal EM.
  • the second electrode plate CP2 of the storage capacitor is used to load the driving power supply voltage VDD.
  • the pixel electrode of the OLED can be electrically connected to the drain of the second light emission control transistor T6, and the common electrode can be loaded with a common power supply voltage VSS.
  • the reset control signal Reset loaded by the capacitor reset transistor T1 of the pixel drive circuit in the upper row is the same as the scan signal Gate loaded by the pixel drive circuit in the next row (both high level or low level at the same time). level), the scanning signal Gate loaded by the pixel driving circuit in the upper row is the same as the reset control signal Reset loaded by the electrode reset transistor T7 of the pixel driving circuit in the lower row.
  • the reset control signal Reset loaded by the capacitor reset transistor T1 of the pixel drive circuit can be used as the reset control signal Reset of the pixel drive circuit, that is, the reset control wiring RL connected to the capacitor reset transistor T1 is used as the row The reset control wiring RL connected to the pixel driving circuit. In this way, the electrode reset transistor T7 of the pixel driving circuit in the previous row can be connected to the reset control wiring RL of the pixel driving circuit in the next row.
  • the main area where transistors of the pixel driving circuit are arranged can be defined as the pixel driving area PDCA of the pixel driving circuit, and most transistors of the pixel driving circuit are arranged in the corresponding pixel driving area PDCA.
  • the pixel driving area PDCA can be defined as a rectangular area, and the capacitance reset transistor T1 to the second light emission control transistor T6 of the pixel driving circuit are arranged in the corresponding pixel driving area PDCA, and The electrode reset transistor T7 of the pixel driving circuit is arranged in the pixel driving area PDCA corresponding to the pixel driving circuit of the next row.
  • the pixel driving area PDCA includes seven transistors including the capacitance reset transistor T1 ⁇ the electrode reset transistor T7, among which the capacitance reset transistor T1 ⁇ the second light emission control transistor T6 belong to the pixel driving circuit corresponding to the pixel driving area PDCA, and the electrode The reset transistor T7 belongs to the pixel driving circuit of the upper row.
  • the material of the active layer 200 can be polysilicon, which can change the conductivity at different positions through processes such as doping, thereby forming multiple channel regions and conductive segments.
  • the active layer 200 can be formed with the channel region T1Act of the capacitance reset transistor T1, the channel region T2Act of the threshold compensation transistor T2, and the channel region of the driving transistor T3.
  • a first conductive segment PL1 , a second conductive segment PL2 , a third conductive segment PL3 , a fourth conductive segment PL4 , a fifth conductive segment PL5 , a sixth conductive segment PL6 and a seventh conductive segment PL7 are formed.
  • the first conductive segment PL1 is connected to one end of the channel region T4Act of the data writing transistor T4 as the source of the data writing transistor T4, and is provided with a first bottom via area HA1 for electrically connecting with the data line DataL .
  • the second conductive segment PL2 is connected to the other end of the channel region T4Act of the data writing transistor T4, and is connected to one end of the channel region T3Act of the driving transistor T3 and one end of the channel region T5Act of the first light emission control transistor T5, so that The drain of the data writing transistor T4, the source of the driving transistor T3, and the drain of the first light emission control transistor T5 are electrically connected to each other.
  • the third conductive segment PL3 is connected to the other end of the first light emission control transistor T5 as the source of the first light emission control transistor T5, and is provided with a fourth bottom via area HA4 for electrically connecting with the driving power line VDDL.
  • the fourth conductive segment PL4 is electrically connected to the other end of the channel region T3Act of the driving transistor T3, one end of the channel region T2Act of the threshold compensation transistor T2, and one end of the channel region T6Act of the second light emission control transistor T6, so that the driving transistor The drain of T3, the source of the threshold compensation transistor T2, and the source of the second light emission control transistor T6 are electrically connected.
  • the fifth conductive segment PL5 is electrically connected to one end of the channel region T7Act of the electrode reset transistor T7 , and is provided with a fifth bottom via region HA5 for electrically connecting to the first source-drain metal layer SD1 .
  • the sixth conductive segment PL6 is electrically connected to the other end of the channel region T2Act of the threshold compensation transistor T2 and one end of the channel region T1Act of the capacitance reset transistor T1, for making the drain of the capacitance reset transistor T1 and the drain of the threshold compensation transistor T2 Pole electrical connection.
  • a third bottom via area HA3 for electrically connecting with the first source-drain metal layer SD1 is disposed on the sixth conductive segment PL6 .
  • the seventh conductive segment PL7 is electrically connected to the other end of the channel region T1Act of the capacitance reset transistor T1 of the pixel driving circuit, and is electrically connected to the other end of the channel region T7Act of the electrode reset transistor T7 of the pixel driving circuit of the previous row.
  • a second bottom via area HA2 for electrically connecting with the first source-drain metal layer SD1 is disposed on the seventh conductive segment PL7 .
  • the channel region T1Act of the capacitor reset transistor T1 includes two sub-channel regions electrically connected to each other, so that the capacitor reset transistor T1 includes two sub-transistors connected in series.
  • the channel region T2Act of the threshold compensation transistor T2 includes two sub-channel regions electrically connected to each other, so that the threshold compensation transistor T2 includes two sub-transistors connected in series. In this way, the leakage of the first electrode plate CP1 of the storage capacitor can be reduced, and the voltage holding capacity of the pixel driving circuit can be improved.
  • the first gate layer is provided with a scanning line GL extending along a first direction DH, a reset control line RL and an enabling line EML, and a first electrode plate CP1 provided with a storage capacitor.
  • the first electrode plate CP1 overlaps with the channel region T3Act of the driving transistor T3 to be multiplexed as the gate T3G of the driving transistor T3.
  • the first electrode plate CP1 of the storage capacitor is provided with a sixth bottom via region HA6 for electrically connecting with the first source-drain metal layer SD1.
  • the overlapping part of the reset control trace RL and the channel region T1Act of the capacitor reset transistor T1 can be used as the gate T1G of the capacitor reset transistor T1; wherein, the reset control trace RL has two regions respectively connected to the channel region T1 of the capacitor reset transistor T1 The two sub-channel regions of the region T1Act overlap and serve as the gates of the two sub-transistors of the capacitive reset transistor T1 respectively.
  • the overlapping portion of the reset control line RL and the channel region T7Act of the electrode reset transistor T7 serves as the gate T7G of the electrode reset transistor T7 .
  • the overlapping part of the scanning line GL and the channel area T4Act of the data writing transistor T4 is used as the gate T4G of the data writing transistor T4, and the part of the overlapping part of the scanning line GL and the channel area T2Act of the threshold compensation transistor T2
  • the scanning line GL may have a side branch portion overlapping with a sub-channel region of the channel region T2Act of the threshold compensation transistor T2, so as to be multiplexed as a gate of a sub-transistor of the threshold compensation transistor T2 .
  • the overlapping part of the enabling wiring EML and the channel region T5Act of the first light emitting control transistor T5 is multiplexed as the gate T5G of the first light emitting controlling transistor T5;
  • the overlapping portion of the channel region T6Act is multiplexed as the gate T6G of the second light emission control transistor T6.
  • the gate T1G of the capacitance reset transistor T1 of the PCD in the current row and the gate T7G of the electrode reset transistor T7 of the PCD in the next row are arranged in a straight line along the first direction DH, and the gate T4G of the data write transistor T4 and the threshold
  • the gates of one sub-transistor of the compensation transistor T2 are linearly arranged along the first direction DH.
  • the gate T5G of the first light emission control transistor T5 and the gate T6G of the second light emission control transistor T6 are linearly arranged along the first direction DH.
  • the second gate layer includes an initialization wiring VinitL extending along the first direction DH, and an eighth bottom via area HA8 for electrically connecting with the first source-drain metal layer SD1 is provided on the initialization wiring VinitL.
  • the second gate layer is also provided with the second electrode plate CP2 of the storage capacitor, and the second electrode plate CP2 of the storage capacitor is provided with a gap exposing the sixth bottom via region HA6 so that the sixth bottom via region HA6 can be connected with the first The source-drain metal layer SD1 is electrically connected.
  • the second electrode plate CP2 of the storage capacitor overlaps the first electrode plate CP1 of the storage capacitor to form the storage capacitor Cst.
  • the second electrode plate CP2 of the storage capacitor is provided with a seventh bottom via area HA7 for electrically connecting with the driving power supply line VDDL.
  • the second electrode plate CP2 of the storage capacitor also has a connection line extending along the first direction DH, so that the second electrode plates CP2 of the storage capacitors of the pixel driving circuits arranged adjacently in one row can be electrically connected to each other.
  • the second electrode plates CP2 of the storage capacitors sequentially connected along the first direction DH can serve as the signal channel of the driving power supply voltage VDD along the first direction DH, and are electrically connected to the driving power supply line VDDL along the second direction DV. In this way, the signal channels driving the power supply voltage VDD can be meshed.
  • the first source-drain metal layer SD1 includes the data wiring DataL and the driving power supply wiring VDDL extending along the second direction DV, and includes the first conductive structure ML1, the second conductive structure ML2 and the third conductive structure. Structure ML3.
  • the second source-drain metal layer SD2 is provided with a fourth conductive structure ML4.
  • the data line DataL has a first top via area HB1, the first top via area HB1 overlaps with the first bottom via area HA1 and is connected through a via, so that the data line DataL and the data writing transistor T4 The source electrical connection.
  • the driving power line VDDL has a fourth top via area HB4 and a seventh top via area HB7; the fourth top via area HB4 overlaps with the fourth bottom via area HA4 and is connected through a via, so that the driving power line
  • the line VDDL is electrically connected to the source of the first light emission control transistor T5; the seventh top via region HB7 overlaps with the seventh bottom via region HA7 and is connected through a via, so that the driving power supply line VDDL and the first storage capacitor
  • the two electrode plates CP2 are electrically connected.
  • the first conductive structure ML1 has a second top via area HB2 and an eighth top via area HB8; the second top via area HB2 overlaps with the second bottom via area HA2 and is connected by a via, and the eighth top via The area HB8 overlaps with the eighth bottom via area HA8 and is connected through vias.
  • the initialization line VinitL is electrically connected to the source of the capacitance reset transistor T1 and the source of the electrode reset transistor T7 through the first conductive structure ML1 .
  • the second conductive structure ML2 has a third top via region HB3 and a sixth top via region HB6; the third top via region HB3 overlaps with the third bottom via region HA3 and is connected by a via; the sixth top via The region HB6 overlaps with the sixth bottom via region HA6 and is connected through a via.
  • the drain of the threshold compensation transistor T2 is electrically connected to the first electrode plate CP1 of the storage capacitor through the second conductive structure ML2 .
  • the third conductive structure ML3 has a fifth top via area HB5 and a ninth bottom via area HA9 ; the fourth conductive structure ML4 is provided with a ninth top via area HB9 and a tenth bottom via area HA10 .
  • the fifth top via area HB5 overlaps with the fifth bottom via area HA5 and is connected through vias
  • the ninth top via area HB9 overlaps with the ninth bottom via area HA9 and is connected through vias
  • the tenth bottom via area HA9 overlaps and is connected through vias.
  • the hole area HA10 is used for electrical connection with the pixel electrode of the OLED. In this way, the OLED is electrically connected to the drain of the second light emission control transistor T6 through the fourth conductive structure ML4 and the third conductive structure ML3.
  • FIG. 14 and FIG. 15 show schematic structural diagrams of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 in the non-transition area A2.
  • the data line DataL is further provided with an eleventh bottom via area HA11
  • the driving power line VDDL is also provided with a twelfth bottom via area HA12.
  • the second source-drain metal layer SD2 is also provided with a data line resistance-reducing structure DataLD extending along the second direction DV and a driving power line resistance-reducing structure VDDLD; wherein, the data line resistance reduction structure DataLD is provided with an eleventh top pass Hole area HB11, the eleventh top via area HB11 overlaps with the eleventh bottom via area HA11 and is connected through vias, so that the data line resistance reducing structure DataLD and the corresponding data line DataL are connected in parallel, thereby reducing data Impedance of trace DataL.
  • the drive power trace resistance reduction structure VDDLD is provided with a twelfth top via area HB12, the twelfth top via area HB12 overlaps with the twelfth bottom via area HA12 and is connected through via holes, so that the drive power traces
  • the resistance-reducing structure VDDLD is connected in parallel with the corresponding driving power trace VDDL, thereby reducing the impedance of the driving power trace VDDL.
  • FIG. 17 shows a schematic diagram of a partial structure of the first source-drain metal layer SD1 , the second source-drain metal layer SD2 and part of gate traces in the transition area A1 .
  • FIG. 18 shows a schematic diagram of the partial structure of the first source-drain metal layer SD1, the second source-drain metal layer SD2, the pixel electrode layer and part of the gate wiring in the transition area A1.
  • the pixel electrode R of the red sub-pixel, the pixel electrode G of the green sub-pixel, and the pixel electrode B of the blue sub-pixel are distributed in the display area.
  • the first source-drain metal layer SD1 is provided with a scan transfer structure GD, and the scan transfer structure GD is connected to the via hole.
  • the scanning line GL of the previous pixel driving circuit row HPDC (for example, the first section of the scanning line GL1 or the second section of the scanning line GL2) is connected, and is connected to the reset control line RL of the next pixel driving circuit row HPDC through a via hole (the first section RL1 of the reset control line or the second section RL2 of the reset control line) is connected, and connected to the row transfer line HTRL through the via hole, so that the scanning line GL of the previous pixel driving circuit line HPDC and the next pixel
  • the reset control wire RL of the driving circuit row HPDC (as the reset control wire RL corresponding to the scanning wire GL in the previous pixel driving circuit row HPDC) is electrically connected through the row transfer wire HTRL.
  • the pixel driving circuit closest to the opening region CC in the isolated pixel driving circuit row HPDC may be defined as the innermost pixel driving circuit.
  • An auxiliary area may be disposed on the side of the innermost pixel driving circuit close to the hole packaging area C1, and the scan transfer structure GD is disposed in the auxiliary area.
  • the first section GL1 or the second section GL2 of the scanning line of the pixel driving circuit row HPDC needs to extend into the auxiliary area along the first direction DH so as to be electrically connected to the scanning transfer structure GD.
  • the reset control wiring RL of the next pixel driving circuit row HPDC also needs to extend into the auxiliary area so as to be electrically connected to the scan transfer structure GD.
  • the line section along the second direction DV can be overlapped with the drive power line VDDL, so as to shield the driving data Data and other signals by means of the drive power line VDDL, and reduce the reception of the line line HTRL. crosstalk. Further, in the row transition line HTRL, the line segment along the second direction DV may not overlap with the data line DataL.
  • the first source-drain metal layer SD1 may also be provided with an enabling transition structure EMD in the auxiliary region, and the enabling transition structure EMD is electrically connected to the enabling wiring EML through a via hole.
  • an enabling routing line (not shown in FIG. 17 and FIG. 18 ) may be provided, and the enabling routing line may be disposed on one of the first gate layer and the second gate layer. layer or two layers, so that the first section EML1 of the enabling line is electrically connected to the second section EML2 of the enabling line.
  • the enabling routing wire may be electrically connected to the enabling transfer structure EMD through a via hole.
  • the enabling winding wires are alternately arranged on the first gate layer and the second gate layer.
  • a reference voltage winding line VinitER surrounding the hole C2 is provided in the hole packaging area C1, and a connection part protruding toward the auxiliary area is provided on the reference voltage winding line VinitER, and the connection part is connected to the initialization circuit through the via hole.
  • the first section of the line or the second section of the initialization line (the first section of the initialization line or the second section of the initialization line is not shown in Figure 17 and Figure 18) is electrically connected, so that the first section of each initialization line and each initialization line
  • the second section of the wiring is electrically connected through the reference voltage winding line VinitER, thereby reducing the difference in the initialization voltage Vinit on both sides of the opening area CC, and improving the uniformity of the display panel.

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Abstract

一种显示面板和电子设备，属于显示技术领域。显示面板包括开孔区(CC)和围绕开孔区(CC)的显示区(AA)；其中，显示面板设置有沿第一方向(DH)延伸的行走线(HL)和沿第二方向(DV)延伸的列走线(VL)；部分行走线(HL)被开孔区(CC)隔断为相互对应的行走线第一段(HL1)和行走线第二段(HL2)；部分列走线(VL)被开孔区(CC)隔断为相互对应的列走线第一段(VL1)和列走线第二段(VL2)；至少部分列走线第一段(VL1)与对应的列走线第二段(VL2)通过位于显示区(AA)的对应的转接线（VTRL）电连接；和/或，至少部分行走线第一段(HL1)与对应的行走线第二段(HL2)通过位于显示区(AA)的对应的转接线（HTRL）电连接。显示面板能够减小开孔区(CC)的尺寸。

Description

显示面板和电子设备 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板和电子设备。
背景技术
在全面屏产品中，可以在显示屏幕上开孔，并将摄像头、传感器等感光设备安装在打孔区域。然而，开孔区的尺寸依旧比较大，不利于全面屏产品的屏占比的进一步提升。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板和电子设备，减小开孔区的尺寸。
根据本公开的一个方面，提供一种显示面板，包括开孔区和围绕所述开孔区的显示区；其中，所述显示面板设置有沿第一方向延伸的行走线和沿第二方向延伸的列走线；
部分所述行走线被所述开孔区隔断为相互对应的行走线第一段和行走线第二段；部分所述列走线被所述开孔区隔断为相互对应的列走线第一段和列走线第二段；
至少部分所述列走线第一段与对应的所述列走线第二段通过位于所述显示区的对应的转接线电连接；
和/或，至少部分所述行走线第一段与对应的所述行走线第二段通过位于所述显示区的对应的转接线电连接。
根据本公开的一种实施方式，所述列走线包括用于加载驱动数据的数据走线；部分所述数据走线被所述开孔区隔断为相互对应的数据走线第一段和数据走线第二段；
所述数据走线第一段与对应的所述数据走线第二段通过位于所述显示区的对应的列转接线电连接。
根据本公开的一种实施方式，所述列转接线包括依次连接的列转接线第一段、列转接线第二段和列转接线第三段；
所述列转接线第一段与所述数据走线第一段电连接，所述列转接线第三段与所述数据走线第二段电连接。
根据本公开的一种实施方式，所述列转接线第一段和所述列转接线第三段沿所述第一方向延伸；所述列转接线第二段沿所述第二方向延伸；
所述开孔区具有沿所述第二方向延伸的列中轴线；
位于所述列中轴线一侧的各个所述数据走线第一段，其所电连接的所述列转接线位于所述列中轴线的同一侧。
根据本公开的一种实施方式，所述列转接线包括分别位于所述列中轴线两侧的两部分；
位于所述列中轴线同一侧的各个所述列转接线，其各个端部沿所述第二方向直线排列。
根据本公开的一种实施方式，所述列转接线第一段远离所述列转接线第二段的端部与对应的所述数据走线第一段交叠且电连接，所述列转接线第三段远离所述列转接线第二段的端部与对应的所述数据走线第二段交叠且电连接。
根据本公开的一种实施方式，所述列走线还包括沿所述第二方向延伸的驱动电源走线；所述列转接线第二段与所述驱动电源走线交叠。
根据本公开的一种实施方式，所述显示区设置有阵列分布的像素驱动电路；所述像素驱动电路排列为多个像素驱动电路行和多个像素驱动电路列；
沿所述第二方向相邻的两个列转接线第一段，分别位于相邻的两个所述像素驱动电路行中；
沿所述第二方向相邻的两个列转接线第三段，分别位于相邻的两个所述像素驱动电路行中；
沿所述第一方向相邻的两个列转接线第二段，分别位于相邻的两个所述像素驱动电路列中。
根据本公开的一种实施方式，所述行走线包括用于加载扫描信号的扫描走线；部分所述扫描走线被所述开孔区隔断为相互对应的扫描走线第一段和扫描走线第二段；
所述扫描走线第一段与对应的所述扫描走线第二段通过位于所述显示区的对应的行转接线电连接。
根据本公开的一种实施方式，至少部分所述行转接线为第一行转接线；所述第一行转接线包括依次连接的行转接线第一段、行转接线第二段、和行转接线第三段；所述行转接线第一段和所述行转接线第三段沿所述第二方向延伸；所述行转接线第二段沿所述第一方向延伸；
所述行转接线第一段与对应的所述扫描走线第一段电连接，所述行转接线第三段与对应的所述扫描走线第二段电连接。
根据本公开的一种实施方式，所述第一行转接线的行转接线第一段通过其端部与对应的所述扫描走线第一段电连接，所述第一行转接线的行转接线第三段通过其端部与对应的所述扫描走线第二段电连接。
根据本公开的一种实施方式，部分所述行转接线为第二行转接线；所述第二行转接线包括依次连接的行转接线第四段、行转接线第一段、行转接线第二段、行转接线第三段和行转接线第五段；所述行转接线第一段和所述行转接线第三段沿所述第二方向延伸；所述行转接线第四段、行转接线第二段、行转接线第五段沿所述第一方向延伸；
所述行转接线第四段通过其远离所述行转接线第一段的端部与对应的所述扫描走线第一段电连接；所述行转接线第五段通过其远离所述行转接线第三段的端部与对应的所述扫描走线第二段电连接。
根据本公开的一种实施方式，所述行转接线第四段与对应的所述扫描走线第一段交叠设置；所述行转接线第五段与对应的所述扫描走线第二段交叠设置。
根据本公开的一种实施方式，所述显示面板设置有沿所述第二方向延伸的驱动电源走线；
所述行转接线第一段和所述行转接线第三段分别与所述驱动电源走线交叠。
根据本公开的一种实施方式，所述开孔区具有沿所述第一方向延伸的 行中轴线；
位于所述行中轴线一侧的各个所述扫描走线第一段，其所对应的所述行转接线位于所述行中轴线的同一侧。
根据本公开的一种实施方式，所述行走线还包括与所述扫描走线对应且用于加载复位控制信号的复位控制走线；所述复位控制走线与对应的所述扫描走线所加载的信号一致；部分所述复位控制走线被所述开孔区隔断为相互对应的复位控制走线第一段和复位控制走线第二段；
所述扫描走线第一段与对应的所述复位控制走线第一段并列设置，且电连接至同一所述行转接线第一段；
所述扫描走线第二段与对应的所述复位控制走线第二段并列设置，且电连接至同一所述行转接线第三段。
根据本公开的一种实施方式，所述开孔区包括开孔和围绕所述开孔的开孔封装区；
所述开孔封装区设置有与所述扫描走线第一段和所述扫描走线第二段一一对应的扫描转接结构；
所述扫描走线第一段和对应的所述复位控制走线第一段与对应的所述扫描转接结构电连接；
所述扫描走线第二段和对应的所述复位控制走线第二段与对应的所述扫描转接结构电连接。
根据本公开的一种实施方式，所述扫描走线和对应的所述复位控制走线设置于同一导电层；所述扫描走线、所述扫描转接结构和所述行转接线位于不同的导电层；
所述扫描走线第一段和对应的所述复位控制走线第一段，通过过孔与对应的所述扫描转接结构电连接；所述扫描走线第二段和对应的所述复位控制走线第二段，通过过孔与对应的所述扫描转接结构电连接；
所述扫描走线第一段对应的所述扫描转接结构，通过过孔与所述扫描走线第一段对应的行转接线电连接；
所述扫描走线第二段对应的所述扫描转接结构，通过过孔与所述扫描走线第二段对应的行转接线电连接。
根据本公开的一种实施方式，所述开孔区包括开孔和围绕所述开孔的 开孔封装区；
所述行走线包括用于加载使能信号的使能走线；
部分所述使能走线被所述开孔区隔断为相互对应的使能走线第一段和使能走线第二段；
所述使能走线第一段与对应的所述使能走线第二段通过设置于所述开孔封装区的对应的使能绕设线电连接。
根据本公开的一种实施方式，所述显示面板包括层叠设置的第一栅极层和第二栅极层；所述第一栅极层设置有使能走线和存储电容的第一电极板；所述第二栅极层设置有所述存储电容的第二电极板；
其中，所述使能绕设线设置于所述第一栅极层和/或所述第二栅极层。
根据本公开的一种实施方式，所述开孔区包括开孔和围绕所述开孔的开孔封装区；
所述行走线包括用于加载初始化电压的初始化走线；部分所述初始化走线被所述开孔区隔断为相互对应的初始化走线第一段和初始化走线第二段；
所述开孔封装区设置有一个环绕所述开孔的参考电压绕设线；各个所述初始化走线第一段和各个所述初始化走线第二段与所述参考电压绕设线电连接。
根据本公开的一种实施方式，所述转接线包括行转接线和列转接线；
所述行转接线用于使得对应的所述行走线第一段和所述行走线第二段电连接；
所述列转接线用于使得对应的所述列走线第一段和所述列走线第二段电连接；
所述行转接线的布线空间，位于所述列转接线的布线空间以内。
根据本公开的一种实施方式，沿所述第二方向，所述行转接线分布于所述开孔区的两侧；沿所述第一方向，所述列转接线分布于所述开孔区的两侧；
所述列转接线与对应的所述列走线之间通过列转接过孔连接，所述行转接线与对应的所述行走线之间通过行转接过孔连接；所述列转接过孔与所述开孔区的距离，大于所述行转接过孔与所述开孔区的距离。
根据本公开的一种实施方式，所述转接线、所述行走线和所述列走线设置于不同的导电层。
根据本公开的一种实施方式，所述显示面板包括依次层叠设置的衬底基板、驱动电路层和像素层；
所述驱动电路层包括依次层叠设置于所述衬底基板一侧的第一栅极层、第二栅极层和金属布线层；所述行走线布设于所述第一栅极层和所述第二栅极层；所述列走线布设于所述金属布线层；
所述驱动电路层还包括转接布线层；所述转接布线层设置于所述第一栅极层远离所述第二栅极层的一侧，或者位于所述金属布线层远离所述第二栅极层的一侧，或者位于所述第一栅极层、所述第二栅极层、所述金属布线层的相邻两层之间；
所述转接线设置于所述转接布线层。
根据本公开的一种实施方式，所述金属布线层包括第一源漏金属层；
所述转接布线层包括位于所述第一源漏金属层远离所述衬底基板一侧的第二源漏金属层；所述转接线设置于所述第二源漏金属层。
根据本公开的一种实施方式，所述金属布线层包括层叠设置于所述第二栅极层远离所述衬底基板一侧的第一源漏金属层和第二源漏金属层；所述列走线设置于所述第二源漏金属层；
所述转接布线层包括位于所述第二源漏金属层远离所述衬底基板一侧的第三源漏金属层；所述转接线设置于所述第三源漏金属层。
根据本公开的一种实施方式，所述显示区包括用于布设所述转接线的转接区，以及围绕所述转接区的非转接区；
在所述非转接区，所述转接布线层设置有与至少部分所述列走线对应的列走线降阻结构；所述列走线降阻结构与对应的所述列走线通过过孔电连接。
根据本公开的第二个方面，提供一种电子设备，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一种实施方式中，显示面板上的部分走线示意图。
图2为本公开的一种实施方式中，显示面板在转接区的部分走线示意图。
图3为本公开的一种实施方式中，显示面板在转接区的部分走线示意图。
图4为本公开的一种实施方式中，显示面板在转接区的部分走线示意图。
图5为本公开的一种实施方式中，显示面板在转接区的部分走线示意图。
图6为本公开的一种实施方式中，行转接线在转接区局部的分布示意图。
图7为本公开的一种实施方式中，列转接线在转接区局部的分布示意图。
图8为本公开的一种示例实施方式中，像素驱动电路的原理示意图。
图9为本公开的一种示例实施方式中，半导体层在像素驱动区的结构示意图。
图10为本公开的一种示例实施方式中，第一栅极层在像素驱动区的结构示意图。
图11为本公开的一种示例实施方式中，第二栅极层在像素驱动区的结构示意图。
图12为本公开的一种示例实施方式中，第一源漏金属层在像素驱动区的结构示意图。
图13为本公开的一种示例实施方式中，像素驱动电路的第二源漏金属层在像素驱动区的结构示意图。
图14为本公开的一种示例实施方式中，第一源漏金属层在非转接区的像素驱动区的结构示意图。
图15为本公开的一种示例实施方式中，第二源漏金属层在非转接区的像素驱动区的结构示意图。
图16为本公开的一种示例实施方式中，显示面板的膜层结构示意图。
图17为本公开的一种示例实施方式中，第一源漏金属层、第二源漏金属层和部分栅极层，在转接区的结构示意图。
图18为本公开的一种示例实施方式中，像素电极层、第一源漏金属层、第二源漏金属层和部分栅极层，在转接区的结构示意图。
附图标记说明：
AA、显示区；A1、转接区；A2、非转接区；BB、外围区；B1、绑定区；CC、开孔区；C1、开孔封装区；C2、开孔；DH、第一方向；DV、第二方向；DH1、第一预设方向；DH2、第二预设方向；Haxis、行中轴线；Vaxis、列中轴线；PDCA、像素驱动区；HPDC、像素驱动电路行；VPDC、像素驱动电路列；Gate、扫描信号；Reset、复位控制信号；EM、使能信号；Vinit、初始化电压；VDD、驱动电源电压；VSS、公共电源电压；Data、驱动数据；GL、扫描走线；GL1、扫描走线第一段；GL2、扫描走线第二段；RL、复位控制走线；RL1、复位控制走线第一段；RL2、复位控制走线第二段；EML、使能走线；EML1、使能走线第一段；EML2、使能走线第二段；VinitL、初始化走线；DataL、数据走线；DataL1、数据走线第一段；DataL2、数据走线第二段；VDDL、驱动电源走线；VDDL1、驱动电源走线第一段；VDDL2、驱动电源走线第二段EMD、使能转接结构；GD、扫描转接结构；VinitER、参考电压绕设线；HL、行走线；HL1、行走线第一段；HL2、行走线第二段；VL、列走线；VL1、列走线第一段；VL2、列走线第二段；TRL、转接线；HTRL、行转接线；H1TRL、第一行转接线；H2TRL、第二行转接线；HTRL1、行转接线第一段；HTRL2、行转接线第二段；HTRL3、行转接线第三段；HTRL4、行转接线第四段；HTRL5、行转接线第五段；VTRL、列转接线；VTRL1、列转接线第一段；VTRL2、列转接线第二段；VTRL3、列转接线第三段。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本公开提供一种显示面板以及应用该显示面板的电子设备。图1为本公开提供的显示面板的一种俯视结构图。参见图1，显示面板可以包括开孔区CC和围绕开孔区CC的显示区AA。其中，开孔区CC包括开孔C2和围绕开孔C2以进行封装的开孔封装区C1。在显示区AA中，设置有用于显示画面的子像素以及驱动子像素的像素驱动电路。参见图1，显示面板还设置有围绕显示区AA的外围区BB；在外围区BB的其中一端设置有绑定区B1，绑定区B1用于与外部电路(例如电路板、柔性电路板、覆晶薄膜等)绑定连接。
在本公开提供的显示面板中，开孔C2使得其具有较大的透光率。该开孔可以为贯穿显示面板的通孔，也可以为对显示面板的部分膜层进行减薄或者去除的沉孔(非贯穿显示面板的开孔区)，本公开对此不做特殊的 限定。本公开的电子设备可以在显示面板后方设置正对开孔C2的感光组件；感光组件可以通过开孔C2接收显示面板前方的光线。感光组件可以为一个或者多个光线传感器，例如可以为摄像头、光学指纹识别芯片、光强传感器等。在一些实施方式中，感光组件可以为一摄像头，例如可以为一个CCD(电荷耦合器件)摄像头；如此，该显示装置可以实现屏下摄像，提高显示装置的屏占比。
在本公开的一种实施方式中，开孔C2可以为圆形；开孔封装区C1为环绕开孔C2的环形，其外侧边缘整体上可以呈圆形。可以理解的是，开孔封装区C1的外侧边缘在局部或者微观结构上，可以呈现折线状，例如局部呈现台阶状。在开孔封装区C1中，显示面板可以设置有裂纹阻挡坝、水氧阻挡墙等结构，以及可以包括有机或者无机的封装结构，以便对显示区AA进行封装保护。开孔C2的形状还可以为其他，比如矩形、椭圆形等，开孔C2的个数可以为一个或多个。
在本公开提供的显示面板中，显示区AA设置有用于向像素驱动电路提供驱动数据Data的数据走线DataL，以及设置有用于向像素驱动电路提供扫描信号Gate的扫描走线GL。数据走线DataL延伸的方向和扫描走线GL的延伸方向相交。在本公开的一种实施方式中，可以将数据走线DataL延伸的方向定义为第二方向DV，将扫描走线GL的延伸方向定义为第一方向DH。其中，第一方向DH与第二方向DV相交。在一些实施方式中，第一方向DH与第二方向DV相互垂直。可以理解的是，第一方向DH与第二方向DV也可以不垂直。
在本公开的一种实施方式中，参见图1，开孔区CC可以设置于显示区AA远离绑定区B1的一端。换言之，沿第二方向DV，绑定区B1位于显示区AA的一侧，开孔区CC远离绑定区B1设置。
在本公开的一种实施方式中，参见图1，开孔区CC可以靠近显示区AA的一个顶角设置，例如设置在远离绑定区B1的一个顶角处。沿第一方向DH，可以将开孔区CC靠近其中一个顶角的方向定义为第一预设方向DH1，将与第一预设方向DH1反向的方向定义为第二预设方向DH2；第一预设方向DH1和第二预设方向DH2为第一方向DH上相反的两个不同方向。
参见图1，显示面板可以设置有沿第一方向DH延伸的行走线HL，例如用于向像素驱动电路加载扫描信号Gate的扫描走线GL、用于向像素驱动电路加载复位控制信号Reset的复位控制走线RL、用于向像素驱动电路加载使能信号EM的使能走线EML、用于向像素驱动电路加载初始化电压Vinit的初始化走线VinitL等中的一种或者多种。驱动电路层还设有沿第二方向DV延伸的列走线VL，例如用于向像素驱动电路加载驱动电源电压VDD的驱动电源走线VDDL、用于向像素驱动电路加载驱动数据Data的数据走线DataL等中的一种或者多种。
参见图1，部分行走线HL被开孔区CC隔断为对应的行走线第一段HL1和行走线第二段HL2两段；其中，行走线第一段HL1设置于开孔区CC的第一预设方向DH1一侧；行走线第二段HL2设置于开孔区CC的第二预设方向DH2一侧。部分列走线VL被开孔区CC隔断为对应的列走线第一段VL1和列走线第二段VL2两段。其中，列走线第一段VL1设置于开孔区CC远离绑定区B1的一侧，列走线第二段VL2设置于开孔区CC靠近绑定区B1的一侧。在相关技术中，被隔断的列走线VL和行走线HL需要通过设置于开孔封装区C1中的绕接线进行电连接，以保证开孔区CC两侧的信号的连续性。然而，这导致开孔封装区C1中需要绕设过多的绕接线而具有较大的宽度。这使得开孔C1需要设置较大的边框且开孔区CC具有较大的尺寸，不利于显示面板的屏占比的提升，也不利于显示画面质量的提高。
参见图2～图5，在本公开的显示面板中，在显示区AA设置有转接线TRL。至少部分列走线第一段VL1与对应的列走线第二段VL2通过位于开孔区CC的对应的转接线TRL电连接；和/或，至少部分行走线第一段HL1与对应的行走线第二段HL2通过位于开孔区CC的对应的转接线TRL电连接。这样，可以减少开孔封装区C1中绕设线的数量，进而减小开孔封装区C1的宽度，实现开孔区CC的窄边框化，进而减小开孔区CC的尺寸，提高电子设备的屏占比和提高显示质量。在一些实施方式中，可以使得开孔封装区C1的宽度减小至0.5～0.6毫米。
在本公开的一种实施方式中，部分转接线TRL可以用于使得被开孔区CC隔断的至少部分行走线HL保证信号连续，且其余转接线TRL可以 用于使得被开孔区CC隔断的至少部分列走线VL保证信号连续。换言之，部分转接线TRL用于使得行走线第一段HL1与对应的行走线第二段HL2电连接，其余转接线TRL用于使得列走线第一段VL1与对应的列走线第二段VL2电连接。当然的，在本公开的其他实施方式中，全部转接线TRL可以用于使得被开孔区CC隔断的至少部分行走线HL保证信号连续，或者全部转接线TRL可以用于使得被开孔区CC隔断的至少部分列走线VL保证信号连续。
如下，从膜层的角度对本公开的显示面板进一步的介绍和说明。
参见图16，本公开的显示面板包括依次层叠设置的衬底基板BP、驱动电路层F100和像素层F200。其中，像素层设置有作为子像素的发光元件，驱动电路层设置有用于驱动子像素的像素驱动电路。
衬底基板BP可以为无机材料的衬底基板，也可以为有机材料的衬底基板。举例而言，在本公开的一种实施方式中，衬底基板BP的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。在本公开的另一种实施方式中，衬底基板BP的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，PMMA)、聚乙烯醇(Polyvinyl alcohol，PVA)、聚乙烯基苯酚(Polyvinyl phenol，PVP)、聚醚砜(Polyether sulfone，PES)、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，PEN)或其组合。在本公开的另一种实施方式中，衬底基板BP也可以为柔性衬底基板，例如衬底基板BP的材料可以包括聚酰亚胺(polyimide，PI)。
驱动电路层F100设置有用于驱动子像素的像素驱动电路。在驱动电路层F100中，任意一个像素驱动电路可以包括有晶体管和存储电容。进一步地，晶体管可以为薄膜晶体管，薄膜晶体管可以选自顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。
可以理解的是，像素驱动电路中的各个晶体管中，任意两个晶体管之 间的类型可以相同或者不相同。示例性地，在一种实施方式中，在一个像素驱动电路中，部分晶体管可以为N型晶体管且部分晶体管可以为P型晶体管。再示例性地，在本公开的另一种实施方式中，在一个像素驱动电路中，部分晶体管的有源层的材料可以为低温多晶硅半导体材料，且部分晶体管的有源层的材料可以为金属氧化物半导体材料。在本公开的一些实施方式中，薄膜晶体管为低温多晶硅晶体管。在本公开的另外一些实施方式中，部分薄膜晶体管为低温多晶硅晶体管，部分薄膜晶体管为金属氧化物晶体管。
晶体管可以具有第一端、第二端和控制端，第一端和第二端中的一个可以为晶体管的源极且另一个可以为晶体管的漏极，控制端可以为晶体管的栅极。可以理解的是，晶体管的源极和漏极为两个相对且可以相互转换的概念；当晶体管的工作状态改变时，例如电流方向改变时，晶体管的源极和漏极可以互换。
在本公开提供的显示面板中，驱动电路层可以包括多个导电层，以便布设行走线HL、列走线VL和转接线TRL等走线。在一些实施方式中，行走线、列走线和转接线可以分别设置于不同的导电层。
在本公开的一种实施方式中，驱动电路层可以包括依次层叠设置于衬底基板一侧的栅极层(例如层叠的第一栅极层和第二栅极层)和金属布线层，栅极层用于设置行走线，金属布线层用于布设列走线；驱动电路层还包括转接布线层；转接布线层设置于第一栅极层远离第二栅极层的一侧，或者位于金属布线层远离第二栅极层的一侧，或者位于第一栅极层、第二栅极层、金属布线层的相邻两层之间；转接线设置于转接布线层。这样，可以保证列走线VL、行走线HL和转接线TRL相互避让。
作为一种示例，金属布线层包括第一源漏金属层；转接布线层包括位于第一源漏金属层远离衬底基板一侧的第二源漏金属层；转接线设置于第二源漏金属层。如此，驱动电路层的各个导电层，包括依次设置于衬底基板一侧的第一栅极层、第二栅极层、第一源漏金属层和第二源漏金属层；列走线设置于第一源漏金属层，转接线设置于第二源漏金属层。
作为另一种示例，金属布线层包括层叠设置于第二栅极层远离衬底基板一侧的第一源漏金属层和第二源漏金属层；列走线设置于第二源漏金属 层；转接布线层包括位于第二源漏金属层远离衬底基板一侧的第三源漏金属层；转接线设置于第三源漏金属层。如此，驱动电路层的各个导电层，包括依次设置于衬底基板一侧的第一栅极层、第二栅极层、第一源漏金属层、第二源漏金属层和第三源漏金属层；列走线设置于第二源漏金属层，转接线设置于第三源漏金属层。
在一些实施方式中，参见图1，显示区AA包括用于布设转接线TRL的转接区A1，以及围绕转接区A1的非转接区A2。参见图15，在非转接区A2，转接布线层设置有与至少部分列走线VL对应的列走线降阻结构VLD(例如图15中的驱动电源走线降阻结构VDDLD、数据走线降阻结构DataLD)；列走线降阻结构VLD与对应的列走线VL通过过孔电连接。进一步地，列走线降阻结构VLD与对应的列走线延伸方向相同且交叠设置，且通过多个过孔电连接。
当然的，在本公开的一些实施方式中，转接布线层还可以设置有与至少部分列走线VL对应的行走线降阻结构，行走线降阻结构与对应的行走线VL通过过孔电连接。行走线降阻结构可以调节行走线的负载，使得行走线的负载均一性提高，减弱因开孔区缺失子像素而导致的不同行走线负载不一致的问题。
驱动电路层还可以包括有其他膜层，例如可以包括有半导体层、绝缘层、钝化层和平坦化层等膜层。半导体层可以为多晶硅半导体层(例如低温多晶硅半导体层)，也可以为金属氧化物半导体层(例如IGZO层)，亦或可以包括层叠的多晶硅半导体层和金属氧化物半导体层等。各个膜层的层叠关系可以根据薄膜晶体管的膜层结构确定。在驱动电路层中，半导体层可以用于形成晶体管的有源层；栅极层可以用于形成扫描走线、复位控制走线等栅极层走线，也可以用于形成晶体管的栅极，还可以用于形成存储电容的部分或者全部电极板；源漏金属层可以用于形成数据引线、电源引线等源漏金属层走线，也可以用于形成存储电容的部分电极板。
如下，以驱动电路层包括两层栅极层和两层源漏金属层为例，对驱动电路层的膜层结构做示例性地解释和说明。
参见图16，该示例的驱动电路层F100可以包括层叠于衬底基板BP和像素层F200之间的半导体层Poly、第一栅极绝缘层GI1、第一栅极层 G1、第二栅极绝缘层GI2、第二栅极层G2、层间电介质层ILD、第一源漏金属层SD1、第一平坦化层PLN1、第二源漏金属层SD2和第二平坦化层PLN2等。这些膜层可以形成各个晶体管、存储电容、列走线、行走线和转接线等。其中，晶体管的沟道区形成于半导体层Poly，存储电容的第一电极板形成于第一栅极层，存储电容的第二电极板形成于第二栅极层。在一些示例中，驱动电路层F100还可以包括有钝化层，钝化层可以设于源漏金属层远离衬底基板BP的表面，以便保护源漏金属层。例如，钝化层可以包括设于第一源漏金属层表面的第一钝化层和设置于第二源漏金属层表面的第二钝化层。
在一些示例中，驱动电路层F100还可以包括设于衬底基板BP与半导体层Poly之间的缓冲材料层Buff，且半导体层Poly、栅极层等均位于缓冲材料层Buff远离衬底基板BP的一侧。缓冲材料层的材料可以为氧化硅、氮化硅等无机绝缘材料。缓冲材料层可以为一层无机材料层，也可以为多层层叠的无机材料层。
像素层F200可以设置有阵列分布的作为子像素的发光元件，且各个发光元件在像素驱动电路的控制下发光。在本公开中，发光元件可以为有机电致发光二极管(OLED)、微发光二极管(Micro LED)、量子点-有机电致发光二极管(QD-OLED)、量子点发光二极管(QLED)或者其他类型的发光元件。示例性地，在本公开的一种实施方式中，发光元件为有机电致发光二极管(OLED)，则该显示面板为OLED显示面板。如下，以发光元件为有机电致发光二极管为例，对像素层的一种可行结构进行示例性的介绍。
可选地，参见图16，像素层F200可以设置于驱动电路层F100远离衬底基板BP的一侧，其可以包括依次层叠设置的像素电极层Ano、像素定义层PDL、支撑柱层(图16中未示出)、有机发光功能层EL和公共电极层COM。其中，像素电极层Ano在显示面板的显示区具有多个像素电极；像素定义层PDL在显示区具有与多个像素电极一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。支撑柱层在显示区包括多个支撑柱，且支撑柱位于像素定义层PDL远离衬底基板BP的表面，以便在蒸镀制程中支撑精细金属掩模版(Fine Metal  Mask，FMM)。有机发光功能层EL至少覆盖被像素定义层PDL所暴露的像素电极。其中，有机发光功能层EL可以包括有机电致发光材料层，以及可以包括有空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一种或者多种。可以通过蒸镀工艺制备有机发光功能层EL的各个膜层，且在蒸镀时可以采用精细金属掩模版或者开放式掩膜板(Open Mask)定义各个膜层的图案。公共电极层COM在显示区可以覆盖有机发光功能层EL。如此，像素电极、公共电极层COM和位于像素电极和公共电极层COM之间的有机发光功能层EL形成有机发电致光二极管，任意一个有机电致发光二极管可以作为显示面板的一个子像素。
在一些实施方式中，像素层F200还可以包括位于公共电极层COM远离衬底基板BP一侧的光取出层，以增强有机发光二极管的出光效率。
可选地，显示面板还可以包括薄膜封装层TFE。薄膜封装层TFE设于像素层F200远离衬底基板BP的表面，可以包括交替层叠设置的无机封装层和有机封装层。其中，无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵有机发光功能层EL而导致材料降解。可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间，以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的边缘，可以位于显示区的边缘和无机封装层的边缘之间。示例性地，薄膜封装层TFE包括依次层叠于像素层F200远离衬底基板BP一侧的第一无机封装层、有机封装层和第二无机封装层。可以理解的是，薄膜封装层TFE在开孔封装区C1也对显示区AA进行封装，以保护显示区中的各个子像素，避免水氧从开孔C2处入侵显示区AA。
可选地，显示面板还可以包括触控功能层TS，触控功能层TS设于薄膜封装层TFE远离衬底基板BP的一侧，用于实现显示面板的触控操作。
可选地，显示面板还可以包括降反层，降反层可以设置于薄膜封装层远离像素层的一侧，用于降低显示面板对环境光线的反射，进而降低环境光线对显示效果的影响。在本公开的一种实施方式中，降反层可以包括层叠设置的彩膜层和黑矩阵层，如此可以在实现降低环境光线干扰的同时，可以避免降低显示面板的透光率。在本公开的另一种实施方式中，降反层可以为偏光片，例如可以为图案化的涂布型圆偏光片。进一步地，降反层 可以设置于触控功能层远离衬底基板BP的一侧。
在本公开的一些实施方式中，参见图2～图5，转接线TRL可以包括用于使得行走线HL信号连续的行转接线HTRL，以及包括用于使得列走线VL信号连续的列转接线VTRL。其中，列走线第一段VL1与对应的列走线第二段VL2通过对应的列转接线VTRL电连接；行走线第一段HL1与对应的行走线第二段HL2通过对应的行转接线HTRL电连接。
在本公开的一种实施方式中，相较于行转接线HTRL，列转接线VTRL远离开孔区CC设置。换言之，行转接线HTRL的布线空间，位于列转接线VTRL的布线空间以内。当然的，在本公开的其他实施方式中，相较于列转接线VTRL，也可以使得行转接线HTRL更远离开孔区CC。
在本公开的一种实施方式中，行转接线HTRL通过行转接过孔与对应的行走线HL电连接，列接线VTRL通过列转接过孔与对应的列走线VL电连接。其中，行转接过孔形成于与转接布线层相邻的绝缘层且与行转接线HTRL交叠；列转接过孔形成于与转接布线层相邻的绝缘层且与列转接线HTRL交叠。所述列转接过孔与所述开孔区的距离，大于所述行转接过孔与所述开孔区的距离。
在本公开的一种实施方式中，沿所述第二方向，所述行转接线分布于所述开孔区的两侧；沿所述第一方向，所述列转接线分布于所述开孔区的两侧。
在一些实施方式中，根据行转接线HTRL的走线方式，行转接线HTRL可以分为第一行转接线H1TRL和第二行转接线H2TRL两种不同的类型。在本公开的显示面板中，行转接线HTRL可以仅仅包括第一行转接线H1TRL或者仅仅包括第二行转接线H2TRL，也可以同时包括第一行转接线H1TRL和第二行转接线H2TRL。
参见2和图3，第一行转接线H1TRL可以包括依次连接的行转接线第一段HTRL1、行转接线第二段HTRL2和行转接线第三段HTRL3；其中，行转接线第一段HTRL1和行转接线第三段HTRL3沿第二方向DV延伸，行转接线第二段HTRL2沿第一方向DH延伸。行转接线第一段HTRL1与对应的行走线第一段HL1电连接，行转接线第三段HTRL3与对应的行走线第二段HL2电连接。换言之，第一行转接线H1TRL通过行转接线第 一段HTRL1与对应的行走线第一段HL1电连接，例如通过行转接线第一段HTRL1远离行转接线第二段HTRL2的端部与对应的行走线第一段HL1电连接。第一行转接线H1TRL通过行转接线第三段HTRL3与对应的行走线第二段HL2电连接，例如通过行转接线第三段HTRL3远离行转接线第二段HTRL2的端部与对应的行走线第二段HL2电连接。行转接线第二段HTRL2可以设置于开孔区CC靠近或者远离绑定区B1的一侧。
在本公开的一种实施方式中，参见图2和图3，各个行转接线HTRL均为第一行转接线H1TRL。
参见图4和图5，第二行转接线H2TRL包括依次连接的行转接线第四段HTRL4、行转接线第一段HTRL1、行转接线第二段HTRL2、行转接线第三段HTRL3和行转接线第五段HTRL5；行转接线第一段HTRL1和行转接线第三段HTRL3沿第二方向DV延伸；行转接线第四段HTRL4、行转接线第二段HTRL2、行转接线第五段HTRL5沿第一方向DH延伸。第二行转接线H2TRL通过行转接线第四段HTRL4与对应的行走线第一段HL1电连接，例如通过行转接线第四段HTRL4远离行转接线第一段HTRL1的端部与对应的行走线第一段HL1电连接；第二行转接线H2TRL通过行转接线第五段HTRL5与对应的行走线第二段HL2电连接，例如通过行转接线第五段HTRL5远离行转接线第三段HTRL3的端部与对应的行走线第二段HL2电连接。
在本公开的另一种实施方式中，参见图4和图5，部分行转接线HTRL为第一行转接线H1TRL，且其余部分的行转接线HTRL为第二行转接线H2TRL。进一步地，沿第二方向DV，第二行转接线H2TRL所对应的行走线第一段HL1靠近开孔区CC的中部设置，第一行转接线H1TRL所对应的各个行走线第一段HL1靠近开孔区CC的端部设置。
当然的，在本公开的其他实施方式中，全部行转接线HTRL可以均为第二行转接线H2TRL。
在本公开的一种实施方式中，参见图2～图5，开孔区CC具有沿第一方向DH延伸的行中轴线Haxis，行中轴线Haxis穿过开孔区CC的几何中心。位于行中轴线Haxis一侧的各个行走线第一段HL1，其所对应的行转接线HTRL位于行中轴线Haxis的同一侧。换言之，位于行中轴线Haxis 靠近绑定区绑定区B1一侧的行走线HL，其所连接的行转接线第二段HTRL2位于开孔区CC靠近绑定区绑定区B1的一侧；位于行中轴线Haxis远离绑定区B1一侧的行走线HL，其所连接的行转接线第二段HTRL2位于开孔区CC远离绑定区B1的一侧。
在一种示例中，在相邻两个行走线第一段HL1所电连接的行转接线第二段HTRL2中，远离行中轴线Haxis的行走线第一段HL1所电连接的行转接线第二段HTRL2靠近开孔区CC设置。换言之，在行中轴线Haxis的同一侧，行走线第一段HL1与行中轴线Haxis的距离越远，则该行走线第一段HL1所电连接的行转接线第二段HTRL2越靠近开孔区CC设置。
在一种示例中，参见图2～图3，第一行转接线H1TRL呈凵字型而形成容置空间。在相邻两个行走线第一段HL1所连接的第一行转接线H1TRL中，远离行中轴线Haxis的行走线第一段HL1所连接的第一行转接线H1TRL位于靠近行中轴线Haxis的行走线第一段HL1所连接的第一行转接线H1TRL的容置空间内。
在本公开的一种实施方式中，行走线HL包括扫描走线GL；其中部分扫描走线GL被开孔区CC隔断为对应的且位于开孔区CC两侧的扫描走线第一段GL1和扫描走线第二段GL2。扫描走线第一段GL1位于开孔区CC的第一预设方向DH1一侧，扫描走线第二段GL2位于开孔区CC的第二预设方向DH2一侧。对应的扫描走线第一段GL1和扫描走线第二段GL2之间通过对应的行转接线HTRL电连接。
在一种示例中，驱动电路层包括依次层叠设置的第一栅极层G1、第二栅极层G1、第一源漏金属层SD1和第二源漏金属层SD2。其中扫描走线GL设置于G1，行转接线HTRL设置于SD2。参见图17，在开孔封装区C1，第一源漏金属层SD1设置有与扫描走线第一段GL1、扫描走线第二段GL2对应的扫描转接结构GD。扫描走线第一段GL1对应的扫描转接结构GD与该扫描走线第一段GL1通过过孔电连接，例如扫描走线第一段GL1对应的扫描转接结构GD与该扫描走线第一段GL1的末端(靠近开孔区CC的一端)通过过孔电连接。扫描走线第二段GL2对应的扫描转接结构GD与该扫描走线第二段GL2通过过孔电连接，例如扫描走线第二段GL2对应的扫描转接结构GD与该扫描走线第二段GL2的末端(靠近 开孔区CC的一端)通过过孔电连接。该扫描走线GL对应的行转接线HTRL，其一端与扫描走线第一段GL1对应的扫描转接结构GD通过过孔电连接，另一端与扫描走线第二段GL2对应的扫描转接结构GD通过过孔电连接。
当然的，在本公开的另外一种实施方式中，扫描走线第一段GL1和扫描走线第二段GL2之间也可以通过设置于开孔封装区C1中的绕设线电连接。
在本公开的一种实施方式中，在第二行转接线H2TRL中，行转接线第四段HTRL4与对应的扫描走线第一段GL1交叠设置，行转接线第五段HTRL5与对应的扫描走线第二段GL2交叠设置。换言之，行转接线第四段HTRL4与对应的扫描走线第一段GL1的基本平行且并列的沿第一方向DH延伸，两者在衬底基板BP上的正投影的重叠部分沿第一方向DH延伸；行转接线第五段HTRL5与对应的扫描走线第二段GL2的基本平行且并列的沿第一方向DH延伸，两者在衬底基板BP上的正投影的重叠部分沿第一方向DH延伸。这样，可以减小第二行转接线H2TRL所受到的干扰。
在本公开的一种实施方式中，行走线HL包括使能走线EML；其中部分使能走线EML被开孔区CC隔断为对应的且位于开孔区CC两侧的使能走线第一段EML1和使能走线第二段EML2。使能走线第一段EML1位于开孔区CC的第一预设方向DH1一侧，使能走线第二段EML2位于开孔区CC的第二预设方向DH2一侧。对应的使能走线第一段EML1和使能走线第二段EML2之间通过对应的行转接线HTRL电连接。
当然的，在本公开的另外一种实施方式中，使能走线第一段EML1和对应的使能走线第二段EML2之间也可以通过设置于开孔封装区C1中的对应的使能绕设线电连接。进一步地，显示面板包括层叠设置的第一栅极层和第二栅极层；第一栅极层设置有使能走线EML和存储电容的第一电极板；第二栅极层设置有存储电容的第二电极板；其中，使能绕设线设置于第一栅极层和/或第二栅极层。
在一种示例中，各个使能绕设线可以交替的设置有第一栅极层和第二栅极层中，以便减小相邻使能绕设线之间的间距，进一步减小开孔封装区 C1的宽度，实现屏内开孔的更小边框。
在一种示例中，参见图17和图18，第一源漏金属层SD1在开孔封装区C1中可以设置有与使能走线第一段EML1、使能走线第二段EML2对应设置的使能转接结构EMD；使能走线第一段EML1的末端(靠近开孔区CC的一端)通过过孔与对应的使能转接结构EMD电连接；使能走线第二段EML2的末端(靠近开孔区CC的一端)通过过孔与对应的使能转接结构EMD电连接。与使能走线第一段EML1、使能走线第二段EML2对应的使能绕设线(图17和图18中未示出)，两端分别通过过孔与使能走线第一段EML1对应的使能转接结构EMD、使能走线第二段EML2对应的使能转接结构EMD电连接。
在本公开的一些实施方式中，行走线HL包括初始化走线VinitL；其中，其中部分初始化走线VinitL被开孔区CC隔断为对应的且位于开孔区CC两侧的初始化走线第一段和初始化走线第二段。对应的初始化走线第一段和初始化走线第二段之间通过行转接线HTRL电连接。
当然的，被开孔区CC断开的初始化走线VinitL也可以采用其他方式保持信号连续。举例而言，可以在显示区AA的第一方向DH两侧分别布设初始化电压总线，初始化走线VinitL的两端分别与两侧的初始化电压总线电连接。这样，没有被开孔区CC隔断的初始化走线VinitL的两端均可以通过初始化电压总线加载初始化电压Vinit，初始化走线第一段和初始化走线第二段可以分别通过相邻的初始化电压总线获得初始化电压Vinit。在一种实施方式中，参见图17和图18，开孔封装区C1设置有一个环绕开孔C2的参考电压绕设线VinitER；各个初始化走线第一段(图17和图18中未示出)和各个初始化走线第二段(图17和图18中未示出)与参考电压绕设线VinitER电连接。这样，可以减小初始化走线第一段和初始化走线第二段上的压降，进而利于显示面板的均一性。
在本公开的一些实施方式中，行走线HL包括复位控制走线RL；其中，其中部分复位控制走线RL被开孔区CC隔断为对应的且位于开孔区CC两侧的复位控制走线第一段RL1和复位控制走线第二段RL2。对应的复位控制走线第一段RL1和复位控制走线第二段RL2之间通过行转接线HTRL电连接。当然的，在本公开的另外一种实施方式中，复位控制走线 第一段RL1和复位控制走线第二段RL2之间也可以通过设置于开孔封装区C1中的绕设线电连接。
在一些实施方式中，在与扫描走线GL相邻的复位控制走线RL中，其中一个复位控制走线RL的信号与该扫描走线GL相同(例如同时为高电平、同时为低电平)，可以将加载相同信号的扫描走线GL和复位控制走线RL作为相互对应的扫描走线GL和复位控制走线RL。此时，扫描走线第一段GL1与对应的复位控制走线第一段RL1并列设置，且电连接至同一行转接线第一段HTRL1；扫描走线第二段GL2与对应的复位控制走线第二段RL2并列设置，且电连接至同一行转接线第三段HTRL3。如此可以无需额外为复位控制走线RL的信号连续而设置专门的行转接线HTRL，进而可以减少行转接线HTRL的数量，减小行转接线HTRL的布线空间的大小，利于提高显示面板的均一性。
在本公开的一种实施方式中，参见图17和图18，开孔封装区C1设置有与扫描走线第一段GL1和扫描走线第二段GL2一一对应的扫描转接结构GD；扫描走线第一段GL1和对应的复位控制走线第一段RL1与对应的扫描转接结构GD电连接；扫描走线第二段GL2和对应的复位控制走线第二段RL2与对应的扫描转接结构GD电连接。
示例性地，扫描走线GL和对应的复位控制走线RL设置于同一导电层，例如都位于第一栅极层；扫描走线GL、扫描转接结构GD和行转接线HTRL位于不同的导电层。扫描走线第一段GL1和对应的复位控制走线第一段RL1，通过过孔与对应的扫描转接结构GD电连接；扫描走线第二段GL2和对应的复位控制走线第二段RL2，通过过孔与对应的扫描转接结构GD电连接；扫描走线第一段GL1对应的扫描转接结构GD，通过过孔与扫描走线第一段GL1对应的行转接线HTRL电连接；扫描走线第二段GL2对应的扫描转接结构GD，通过过孔与扫描走线第二段GL2对应的行转接线HTRL电连接。
作为一种示例，参见图1，行走线HL包括初始化走线VinitL、扫描走线GL、复位控制走线RL和使能走线EML。其中，被开孔区CC隔断的初始化走线VinitL中，初始化走线第一段和初始化走线第二段分别与相邻的初始化电压总线电连接，初始化走线第一段和初始化走线第二段之间 不通过位于显示区AA的行转接线HTRL进行电连接。参见图17，开孔封装区C1中设置有环绕开孔C2的参考电压绕设线VinitER，初始化走线第一段和初始化走线第二段靠近开孔区CC的端部与参考电压绕设线VinitER电连接。被开孔区CC隔断的使能走线EML中，使能走线第一段EML1和对应的使能走线第二段EML2通过位于开孔封装区C1的使能绕设线电连接。被开孔区CC隔断的扫描走线GL和复位控制走线RL中，加载相同信号的扫描走线第一段GL1和复位控制走线第一段RL1电连接至同一行转接线第一段HTRL1，加载相同信号的扫描走线第二段GL2和复位控制走线第二段RL2电连接至同一行转接线第三段HTRL3，以使得加载相同信号的扫描走线第一段GL1、扫描走线第二段GL2、复位控制走线第一段RL1和复位控制走线第二段RL2通过同一行转接线HTRL电连接。
进一步地，参见图2，扫描走线第一段GL1与开孔区CC的行中轴线Haxis越远，则与扫描走线第一段GL1连接的行转接线HTRL的行转接线第二段HTRL2与开孔区CC越近。这样，可以有效地减小行转接线HTRL的布线空间的大小。
在本公开的一种实施方式中，行转接线第一段HTRL1和行转接线第三段HTRL3分别与驱动电源走线VDDL交叠。换言之，行转接线第一段HTRL1可以与其中一个驱动电源走线VDDL并行设置(处于不同的膜层且延伸方向一致)，行转接线第一段HTRL1与该驱动电源走线VDDL在衬底基板BP上的正投影的重合部分，可以沿第二方向DV延伸。行转接线第三段HTRL3可以与其中一个驱动电源走线VDDL并行设置(处于不同的膜层且延伸方向一致)，行转接线第三段HTRL3与该驱动电源走线VDDL在衬底基板BP上的正投影的重合部分，可以沿第二方向DV延伸。这样，驱动电源走线VDDL可以为行转接线HTRL提供一定的信号屏蔽效果，减小显示面板内部信号对行转接线HTRL的串扰。
在一些实施方式中，可以根据需要确定各个行转接线HTRL的宽度，以使得各个行走线HL的负载尽量接近，提高显示面板的均一性。这样，任意两个行转接线HTRL的宽度可以相同，也可以不相同。
在本公开的一些实施方式中，参见图2～图5，列转接线VTRL可以包 括依次连接的列转接线第一段VTRL1、列转接线第二段VTRL2和列转接线第三段VTRL3；其中，列转接线第一段VTRL1和列转接线第三段VTRL3沿第一方向DH延伸，列转接线第二段VTRL2沿第二方向DV延伸。列转接线VTRL通过列转接线第一段VTRL1与对应的列走线第一段VL1电连接，列转接线VTRL通过列转接线第三段VTRL3与对应的列走线第二段VL2电连接。列转接线第二段VTRL2可以设置于开孔区CC的第一预设方向DH1或者第二预设方向DH2一侧。
在一种示例中，开孔区CC包括沿第二方向DV延伸的列中轴线Vaxis，列中轴线Vaxis穿过开孔区CC的几何中心。其中，位于列中轴线Vaxis第一预设方向DH1一侧的行走线HL，其所连接的列转接线第二段VTRL2位于开孔区CC的第一预设方向DH1一侧；位于列中轴线Vaxis的第二预设方向DH2一侧的行走线HL，其所连接的列转接线第二段VTRL2位于开孔区CC的第二预设方向DH2的一侧。
在一种示例中，在相邻两个列走线第一段VL1所连接的列转接线第二段VTRL2中，远离列中轴线Vaxis的列走线第一段VL1所连接的列转接线第二段VTRL2远离开孔区CC设置。换言之，在列中轴线Vaxis的同一侧，列走线第一段VL1与列中轴线Vaxis的距离越远，则该列走线第一段VL1所连接的列转接线第二段VTRL2越远离开孔区CC。如此设置，可以使得各个列转接线第二段VTRL2的长度接近，减小各个列走线VL之间的信号差异，进而利于显示面板的调试。当然的，列转接线VTRL也可以采用其他的布设方式，例如，在相邻两个列走线第一段VL1所连接的列转接线第二段VTRL2中，远离列中轴线Vaxis的列走线第一段VL1所连接的列转接线第二段VTRL2靠近开孔区CC设置。
在本公开的一种实施方式中，列走线VL包括驱动电源走线VDDL；其中部分驱动电源走线VDDL被开孔区CC隔断为对应的驱动电源走线第一段VDDL1和驱动电源走线第二段VDDL2，驱动电源走线第一段VDDL1位于开孔区CC远离绑定区B1的一侧，驱动电源走线第二段VDDL2位于开孔区CC靠近绑定区B1的一侧；即对应的驱动电源走线第一段VDDL1和驱动电源走线第二段VDDL2分别位于开孔区CC的两侧。其中，驱动电源走线第一段VDDL1与对应的驱动电源走线第二段VDDL2 之间通过列转接线VTRL电连接。当然的，在本公开的其他实施方式中，驱动电路层的其他导电层可以设置有与驱动电源走线VDDL电连接的导电结构，例如存储电容的第二电极板；同行设置的这些导电结构之间可以相互连接，例如同行相邻的像素驱动电路的存储电容的第二电极板可以相互连接。这样，可以使得驱动电源电压VDD具有网格化的信号通路。在这种情形下，驱动电源走线第一段VDDL1和驱动电源走线第二段VDDL2之间可以不通过列转接线VTRL进行电连接，而是通过接入驱动电源电压VDD的网格化的信号通路而获得驱动电源电压VDD。这样，可以减小列转接线VTRL的布线数量和布线空间。
在本公开的一种实施方式中，列走线VL包括数据走线DataL；其中，其中部分数据走线DataL被开孔区CC隔断为对应的数据走线第一段DataL1和数据走线第二段DataL2；数据走线第一段DataL1位于开孔区CC远离绑定区B1的一侧，数据走线第二段DataL2位于开孔区CC靠近绑定区B1的一侧；即对应的数据走线第一段DataL1和数据走线第二段DataL2分别位于开孔区CC的两侧。对应的数据走线第一段DataL1和数据走线第二段DataL2之间通过对应的列转接线VTRL电连接。
作为一种示例，参见图1，列走线VL包括驱动电源走线VDDL和数据走线DataL。其中，被开孔区CC隔断的驱动电源走线VDDL中，驱动电源走线第一段VDDL1和驱动电源走线第二段VDDL2之间不通过位于显示区AA的列转接线VTRL电连接，也不通过位于开孔封装区C1的绕设线电连接。参见图2～图4，被开孔区CC隔断的数据走线DataL中，数据走线第一段DataL1和对应的数据走线第二段DataL2通过位于显示区AA的列转接线VTRL电连接。进一步地，在相邻两个数据走线第一段DataL1所连接的列转接线第二段VTRL2中，远离列中轴线Vaxis的数据走线第一段DataL1所连接的列转接线第二段VTRL2远离开孔区CC设置。
在本公开的一种实施方式中，参见图3和图5，列转接线第一段VTRL1远离列转接线第二段VTRL2的端部与对应的列走线第一段VL1交叠且电连接，列转接线第三段VTRL3远离列转接线第二段VTRL2的端部与对应的列走线第二段VL2交叠且电连接。换言之，列转接线第一段VTRL1的端部通过过孔与对应的列走线第一段VL1电连接，列转接线第三段 VTRL3的端部通过过孔与对应的列走线第二段VL2电连接。这样，可以减小不同的列转接线VTRL之间的长度差异，进而减小各个列走线VL的阻抗差异，提高开孔区CC两侧的信号均一性。在一种示例中，各个列转接线第一段VTRL1的长度基本相同。
在本公开的另一种实施方式中，参见图2和图4，列转接线VTRL包括分别位于列中轴线Vaxis两侧的两部分；位于列中轴线Vaxis同一侧的各个列转接线VTRL，其各个端部沿第二方向DV直线排列。换言之，在列中轴线Vaxis的同一侧，各个列转接线第一段VTRL1的端部和各个列转接线第三段VTRL3的端部沿第二方向DV呈直线排列；列转接线第一段VTRL1可以通过位于其端部或者非端部的过孔与对应列走线第一段VL1电连接，列转接线第三段VTRL3可以通过位于其端部或者非端部的过孔与对应列走线第二段VL2电连接。这样，可以保证列转接线VTRL对开孔区CC周围的视觉效果的影响更为均一。
在本公开的一种实施方式中，列转接线第二段VTRL2与驱动电源走线VDDL交叠设置。换言之，列转接线第二段VTRL2与驱动电源走线VDDL沿第二方向DV延伸，且两者在衬底基板BP上的正投影沿第二方向DV延伸。如此，驱动电源走线VDDL可以为列转接线第二段VTRL2上加载的驱动数据Data提供信号屏蔽效果，提高驱动数据Data的稳定性。
参见图6和图7，显示区AA设置有阵列分布的像素驱动电路；像素驱动电路排列为多个像素驱动电路行HPDC和多个像素驱动电路列VPDC。其中，任意一个像素驱动电路行HPDC包括沿第一方向依次排列的各个像素驱动电路；任意一个像素驱动电路列VPDC包括沿第二方向依次排列的各个像素驱动电路。
在本公开的一些实施方式中，在各个行转接线HTRL的行转接线第二段HTRL2中，位于行中轴线Haxis同一侧的各个行转接线第二段HTRL2分为多个行转接线第二段组，每个行转接线第二段组包括相邻的多个行转接线第二段HTRL2，例如包括2～4个相邻的行转接线第二段HTRL2；每个行转接线第二段组与同一像素驱动电路行HPDC交叠设置，且相邻的行转接线第二段组分别与相邻的两个像素驱动电路行HPDC交叠设置。示例性地，参见图6，每个行转接线第二段HTRL2组包括三个行转接线第二 段HTRL2。
参见图2和图3，在本公开的一种实施方式中，第一行转接线H1TRL由行转接线第一段HTRL1、行转接线第二段HTRL2和行转接线第三段HTRL3组成。则可以根据与该第一行转接线H1TRL对应的行走线第一段HL1、行走线第二段HL2的靠近开孔区CC的端部位置确定行转接线第一段HTRL1和行转接线第三段HTRL3的位置，进而确定行转接线第二段HTRL2的长度。具体的，行走线第一段HL1靠近开孔区CC的端部可以与行转接线第一段HTRL1靠近开孔区CC的端部连接；行走线第二段HL2靠近开孔区CC的端部可以与行转接线第二段HTRL2靠近开孔区CC的端部连接。其中，行转接线第一段HTRL1和行转接线第三段HTRL3沿第二方向DV延伸，且与像素驱动电路列VPDC交叠。在每个像素驱动电路列VPDC的布线处中，不设置并列延伸的多个行转接线第一段HTRL1或者并列延伸的多个行转接线第三段HTRL3。换言之，在行中轴线Haxis的同一侧，每个像素驱动电路列VPDC的布线区域仅仅与一个行转接线第一段HTRL1或者行转接线第三段HTRL3交叠。进一步地，行转接线第一段HTRL1和行转接线第三段HTRL3与该像素驱动电路列VPDC中的驱动电源走线VDDL交叠设置。可以理解的是，在像素驱动电路列VPDC的布线空间中，可以设置有两个且位于行中轴线Haxis两侧的两个行转接线第一段HTRL1或者行转接线第三段HTRL3。
根据行走线第一段HL1和行走线第二段HL2的端部的不同，相邻两个行转接线第一段HTRL1或者相邻两个行转接线第三段HTRL3之间可以间隔有一个或者多个像素驱动电路列VPDC，也可以不间隔像素驱动电路列VPDC。
示例性地，在行中轴线Haxis的同一侧，将各个行转接线第二段HTRL2沿远离行中轴线Haxis的方向依次进行编号，最靠近行中轴线Haxis的行转接线第二段HTRL2的编号为第1个行转接线第二段HTRL2，其余依次类推。将第i个行转接线第二段HTRL2所连接的行转接线第一段HTRL1记为HTRL1(i)，将第i个行转接线第二段HTRL2所连接的行转接线第三段HTRL3记为HTRL3(i)。那么，HTRL1(1)与HTRL1(2)之间间隔5个不设置行转接线第一段HTRL1的像素驱动电路列VPDC；HTRL1(2) 与HTRL1(3)之间间隔3个不设置行转接线第一段HTRL1的像素驱动电路列VPDC；HTRL1(3)与HTRL1(4)之间间隔3个不设置行转接线第一段HTRL1的像素驱动电路列VPDC；HTRL1(4)与HTRL1(5)之间、HTRL1(5)与HTRL1(6)之间、HTRL1(6)与HTRL1(7)之间、HTRL1(7)与HTRL1(8)之间、HTRL1(8)与HTRL1(9)之间均间隔1个不设置行转接线第一段HTRL1的像素驱动电路列VPDC。相应的，相邻的行转接线第三段HTRL3之间也可以呈现相同的规律，例如与行转接线第一段HTRL1沿列中轴线Vaxis对称。
参见图4和图5，在本公开的一种实施方式中，第二行转接线H2TRL由依次连接的行转接线第四段HTRL4、行转接线第一段HTRL1、行转接线第二段HTRL2、行转接线第三段HTRL3和行转接线第五段HTRL5组成。这些行转接线HTRL的各个行转接线第一段HTRL1可以与相邻的多个像素驱动电路列VPDC一一对应设置。相应的，这些行转接线HTRL的各个行转接线第三段HTRL3可以与相邻的多个像素驱动电路列VPDC一一对应设置。
在一些实施方式中，参见图7，沿第二方向DV相邻的两个列转接线第一段VTRL1，分别位于相邻的两个像素驱动电路行HPDC中；沿第二方向DV相邻的两个列转接线第三段VTRL3，分别位于相邻的两个像素驱动电路行HPDC中；沿第一方向DH相邻的两个列转接线第二段VTRL2，分别位于相邻的两个像素驱动电路列VPDC中。这样，可以减小列转接线VTRL的布线空间。
在一些实施方式中，可以根据需要确定各个列转接线VTRL的宽度，以使得各个列走线VL的负载尽量接近，提高显示面板的均一性。这样，任意两个列转接线VTRL的宽度可以相同，也可以不相同。
如下，以一种具体的示例为例，对本公开的显示面板的结构、原理和效果做进一步地解释和说明。可以理解的是，该示例实施方式中所提供的具体的结构仅仅为本公开的一种示例，本公开的显示面板还可以呈现其他结构。
参见图1，该示例的显示面板在显示区AA的一个顶角附近设置有开孔区CC，开孔区CC包括开孔C2和围绕开孔C2的开孔封装区C1。在开 孔区CC周围，显示区AA具有转接区A1，转接区A1用于布设转接线TRL。显示区AA还包括围绕转接区A1的非转接区A2。
在膜层结构上，参见图16，该示例的显示面板包括依次层叠设置的衬底基板BP、驱动电路层F100和像素层F200。其中，驱动电路层F100包括依次层叠设置的缓冲材料层Buff、半导体层Poly、第一栅极绝缘层GI1、第一栅极层G1、第二栅极绝缘层GI2、第二栅极层G2、层间电介质层ILD、第一源漏金属层SD1、第一平坦化层PLN1、第二源漏金属层SD2和第二平坦化层PLN2；像素层设置有作为子像素的OLED。
该示例的显示面板中，显示区AA设置有阵列分布的像素驱动电路。参见图8，像素驱动电路为7T1C架构，包括电容复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、电极复位晶体管T7和存储电容Cst。参见图8～图15，驱动晶体管T3的源极、第一发光控制晶体管T5的漏极、数据写入晶体管T4的漏极相互电连接，驱动晶体管T3的漏极、阈值补偿晶体管T2的源极、第二发光控制晶体管T6的源极相互电连接，驱动晶体管T3的栅极T3G、存储电容的第一电极板CP1、阈值补偿晶体管T2的漏极、电容复位晶体管T1的漏极相互电连接。驱动晶体管T3被配置为，在驱动晶体管T3的栅极T3G上的电压的控制下，输出驱动电流以控制OLED的亮度。数据写入晶体管T4的源极用于加载驱动数据Data，数据写入晶体管T4的栅极T4G用于加载扫描信号Gate；数据写入晶体管T4被配置为，响应扫描信号Gate而输出驱动数据Data至数据写入晶体管T4的漏极。阈值补偿晶体管T2的栅极T2G用于加载扫描信号Gate，被配置为响应扫描信号Gate而导通，以便对驱动晶体管T3的阈值电压进行补偿。电容复位晶体管T1的栅极T1G用于加载复位控制信号Reset，电容复位晶体管T1的源极用于加载初始化电压Vinit，电容复位晶体管T1被配置为响应复位控制信号Reset而向电容复位晶体管T1的漏极加载初始化电压Vinit。电极复位晶体管T7的源极用于加载初始化电压Vinit，电极复位晶体管T7的栅极T7G用于加载复位控制信号Reset，被配置为响应复位控制信号Reset而向电极复位晶体管T7的漏极加载初始化电压Vinit。第一发光控制晶体管T5的源极用于加载驱动电源电压VDD，第一发光控制晶体管 T5的栅极T5G用于加载使能信号EM，第二发光控制晶体管T6的栅极T6G用于加载使能信号EM；第一发光控制晶体管T5和第二发光控制晶体管T6用于，响应使能信号EM而导通。存储电容的第二电极板CP2用于加载驱动电源电压VDD。OLED的像素电极可以与第二发光控制晶体管T6的漏极电连接，公共电极可以加载公共电源电压VSS。在阵列分布的像素驱动电路中，上一行像素驱动电路的电容复位晶体管T1所加载的复位控制信号Reset与下一行像素驱动电路所加载的扫描信号Gate相同(同时为高电平或者同时为低电平)，上一行像素驱动电路所加载的扫描信号Gate与下一行像素驱动电路的电极复位晶体管T7所加载的复位控制信号Reset相同。在本公开中，可以将像素驱动电路的电容复位晶体管T1所加载的复位控制信号Reset作为该像素驱动电路的复位控制信号Reset，即将电容复位晶体管T1所连接连接的复位控制走线RL作为该行像素驱动电路所连接的复位控制走线RL。这样，上一行的像素驱动电路的电极复位晶体管T7可以连接至下一行像素驱动电路的复位控制走线RL。
在本公开中，可以将布设像素驱动电路的各个晶体管的主要范围定义为该像素驱动电路的像素驱动区PDCA，像素驱动电路的大多数晶体管布设于对应的像素驱动区PDCA中。在该示例中，参见图9～图15，可以将像素驱动区PDCA定义为一个矩形区域，像素驱动电路的电容复位晶体管T1～第二发光控制晶体管T6布设于对应的像素驱动区PDCA中，且该像素驱动电路的电极复位晶体管T7布设于下一行的像素驱动电路对应的像素驱动区PDCA中。根据该定义方式，像素驱动区PDCA中包括电容复位晶体管T1～电极复位晶体管T7等七个晶体管，其中电容复位晶体管T1～第二发光控制晶体管T6属于该像素驱动区PDCA对应的像素驱动电路，电极复位晶体管T7属于上一行的像素驱动电路。
在该示例的显示面板中，有源层200的材料可以为多晶硅，其可以通过掺杂等工艺改变不同位置处的导电性能，进而形成多个沟道区和导电段。举例而言，如图9所示，在任意一个像素驱动电路中，有源层200可以形成有电容复位晶体管T1的沟道区T1Act、阈值补偿晶体管T2的沟道区T2Act、驱动晶体管T3的沟道区T3Act、数据写入晶体管T4的沟道区T4Act、第一发光控制晶体管T5的沟道区T5Act、第二发光控制晶体管T6的沟道 区T6Act、电极复位晶体管T7的沟道区T7Act，以及形成有第一导电段PL1、第二导电段PL2、第三导电段PL3、第四导电段PL4、第五导电段PL5、第六导电段PL6、第七导电段PL7。其中，第一导电段PL1连接数据写入晶体管T4的沟道区T4Act的一端以作为数据写入晶体管T4的源极，其设置有用于与数据走线DataL电连接的第一底过孔区HA1。第二导电段PL2连接数据写入晶体管T4的沟道区T4Act的另一端，且与驱动晶体管T3的沟道区T3Act的一端、第一发光控制晶体管T5的沟道区T5Act的一端连接，以使得数据写入晶体管T4的漏极、驱动晶体管T3的源极、第一发光控制晶体管T5的漏极相互电连接。第三导电段PL3连接第一发光控制晶体管T5的另一端以作为第一发光控制晶体管T5的源极，且设置有用于与驱动电源走线VDDL电连接的第四底过孔区HA4。第四导电段PL4与驱动晶体管T3的沟道区T3Act的另一端、阈值补偿晶体管T2的沟道区T2Act的一端、第二发光控制晶体管T6的沟道区T6Act的一端电连接，以使得驱动晶体管T3的漏极、阈值补偿晶体管T2的源极、第二发光控制晶体管T6的源极电连接。第五导电段PL5与电极复位晶体管T7的沟道区T7Act的一端电连接，且设置有用于与第一源漏金属层SD1电连接的第五底过孔区HA5。
第六导电段PL6与阈值补偿晶体管T2的沟道区T2Act的另一端和电容复位晶体管T1的沟道区T1Act的一端电连接，用于使得电容复位晶体管T1的漏极和阈值补偿晶体管T2的漏极电连接。第六导电段PL6上设置有用于与第一源漏金属层SD1电连接的第三底过孔区HA3。第七导电段PL7与该像素驱动电路的电容复位晶体管T1的沟道区T1Act的另一端电连接，且与上一行像素驱动电路的电极复位晶体管T7的沟道区T7Act的另一端电连接。第七导电段PL7上设置有用于与第一源漏金属层SD1电连接的第二底过孔区HA2。
参见图9，电容复位晶体管T1的沟道区T1Act包括相互电连接的两个亚沟道区，以使得电容复位晶体管T1包括串联的两个亚晶体管。阈值补偿晶体管T2的沟道区T2Act包括相互电连接的两个亚沟道区，以使得阈值补偿晶体管T2包括串联的两个亚晶体管。如此，可以减小存储电容的第一电极板CP1的漏电，提高像素驱动电路的电压保持能力。
参见图10，第一栅极层设置有沿第一方向DH延伸的扫描走线GL、复位控制走线RL和使能走线EML，以及设置有存储电容的第一电极板CP1，存储电容的第一电极板CP1与驱动晶体管T3的沟道区T3Act交叠以复用为驱动晶体管T3的栅极T3G。其中，存储电容的第一电极板CP1设置有用于与第一源漏金属层SD1电连接的第六底过孔区HA6。
复位控制走线RL与电容复位晶体管T1的沟道区T1Act交叠的部分可以作为电容复位晶体管T1的栅极T1G；其中，复位控制走线RL具有两个区域分别与电容复位晶体管T1的沟道区T1Act的两个亚沟道区交叠，分别作为电容复位晶体管T1的两个亚晶体管的栅极。复位控制走线RL与电极复位晶体管T7的沟道区T7Act交叠的部分作为电极复位晶体管T7的栅极T7G。扫描走线GL与数据写入晶体管T4的沟道区T4Act交叠的部分作为数据写入晶体管T4的栅极T4G，扫描走线GL与阈值补偿晶体管T2的沟道区T2Act交叠的部分组委阈值补偿晶体管T2的栅极T2G。参见图10，扫描走线GL可以具有一个侧枝部，侧枝部与阈值补偿晶体管T2的沟道区T2Act的一个亚沟道区交叠，以复用为阈值补偿晶体管T2的一个亚晶体管的栅极。使能走线EML与第一发光控制晶体管T5的沟道区T5Act交叠的部分，复用为第一发光控制晶体管T5的栅极T5G；使能走线EML与第二发光控制晶体管T6的沟道区T6Act交叠的部分，复用为第二发光控制晶体管T6的栅极T6G。参见图10，当前行的PCD的电容复位晶体管T1的栅极T1G与下一行的PCD的电极复位晶体管T7的栅极T7G沿第一方向DH直线排列，数据写入晶体管T4的栅极T4G和阈值补偿晶体管T2的一个亚晶体管的栅极沿第一方向DH直线排列。第一发光控制晶体管T5的栅极T5G和第二发光控制晶体管T6的栅极T6G沿第一方向DH直线排列。
参见图11，第二栅极层包括沿第一方向DH方向延伸的初始化走线VinitL，初始化走线VinitL上设置有用于与第一源漏金属层SD1电连接的第八底过孔区HA8。第二栅极层还设置有存储电容的第二电极板CP2，存储电容的第二电极板CP2设置有暴露第六底过孔区HA6的缺口以使得第六底过孔区HA6能够与第一源漏金属层SD1电连接。存储电容的第二电极板CP2与存储电容的第一电极板CP1交叠以形成存储电容Cst。其中， 存储电容的第二电极板CP2上设置有用于与驱动电源走线VDDL电连接的第七底过孔区HA7。存储电容的第二电极板CP2还具有沿第一方向DH延伸的连接线，以使得同行相邻设置的像素驱动电路的存储电容的第二电极板CP2可以相互电连接。这样，沿第一方向DH依次连接的存储电容的第二电极板CP2可以作为第一方向DH的驱动电源电压VDD信号通道，且与沿第二方向DV的驱动电源走线VDDL电连接。这样，可以使得驱动电源电压VDD的信号通道网格化。
参见图12和图13，第一源漏金属层SD1包括沿第二方向DV延伸的数据走线DataL和驱动电源走线VDDL，以及包括第一导电结构ML1、第二导电结构ML2和第三导电结构ML3。第二源漏金属层SD2设置有第四导电结构ML4。其中，数据走线DataL具有第一顶过孔区HB1，第一顶过孔区HB1与第一底过孔区HA1交叠且通过过孔连接，以使得数据走线DataL与数据写入晶体管T4的源极电连接。驱动电源走线VDDL具有第四顶过孔区HB4和第七顶过孔区HB7；第四顶过孔区HB4与第四底过孔区HA4交叠且通过过孔连接，以使得驱动电源走线VDDL与第一发光控制晶体管T5的源极电连接；第七顶过孔区HB7与第七底过孔区HA7交叠且通过过孔连接，以使得驱动电源走线VDDL与存储电容的第二电极板CP2电连接。第一导电结构ML1具有第二顶过孔区HB2和第八顶过孔区HB8；第二顶过孔区HB2与第二底过孔区HA2交叠且通过过孔连接，第八顶过孔区HB8与第八底过孔区HA8交叠且通过过孔连接，如此，初始化走线VinitL通过第一导电结构ML1与电容复位晶体管T1的源极、电极复位晶体管T7的源极电连接。第二导电结构ML2具有第三顶过孔区HB3和第六顶过孔区HB6；第三顶过孔区HB3与第三底过孔区HA3交叠且通过过孔连接，第六顶过孔区HB6与第六底过孔区HA6交叠且通过过孔连接，如此，阈值补偿晶体管T2的漏极通过第二导电结构ML2与存储电容的第一电极板CP1电连接。第三导电结构ML3具有第五顶过孔区HB5和第九底过孔区HA9；第四导电结构ML4设置有第九顶过孔区HB9和第十底过孔区HA10。第五顶过孔区HB5与第五底过孔区HA5交叠且通过过孔连接，第九顶过孔区HB9与第九底过孔区HA9交叠且通过过孔连接，第十底过孔区HA10用于与OLED的像素电极电连接。这样，OLED通过 第四导电结构ML4、第三导电结构ML3电连接至第二发光控制晶体管T6的漏极。
图14和图15示出了第一源漏金属层SD1和第二源漏金属层SD2在非转接区A2的结构示意图。其中，在非转接区A2，数据走线DataL还设置有第十一底过孔区HA11，驱动电源走线VDDL还设置有第十二底过孔区HA12。第二源漏金属层SD2还设置有沿第二方向DV延伸的数据走线降阻结构DataLD和驱动电源走线降阻结构VDDLD；其中，数据走线降阻结构DataLD设置有第十一顶过孔区HB11，第十一顶过孔区HB11与第十一底过孔区HA11交叠且通过过孔连接，以使得数据走线降阻结构DataLD和对应的数据走线DataL并联，进而降低数据走线DataL的阻抗。驱动电源走线降阻结构VDDLD设置有第十二顶过孔区HB12，第十二顶过孔区HB12与第十二底过孔区HA12交叠且通过过孔连接，以使得驱动电源走线降阻结构VDDLD与对应的驱动电源走线VDDL并联，进而降低驱动电源走线VDDL的阻抗。
图17示出了第一源漏金属层SD1、第二源漏金属层SD2和部分栅极走线在转接区A1的局部结构示意图。图18示出了、第一源漏金属层SD1、第二源漏金属层SD2、像素电极层和部分栅极走线在转接区A1的局部结构示意图。在图18中，红色子像素的像素电极R、绿色子像素的像素电极G、蓝色子像素的像素电极B分布于显示区。
参见图17和图18，在该示例的显示面板中，在靠近开孔封装区C1的一侧，第一源漏金属层SD1设置有扫描转接结构GD，扫描转接结构GD通过过孔与上一像素驱动电路行HPDC的扫描走线GL(例如扫描走线第一段GL1或者扫描走线第二段GL2)连接，且通过过孔与下一像素驱动电路行HPDC的复位控制走线RL(复位控制走线第一段RL1或者复位控制走线第二段RL2)连接，并通过过孔与行转接线HTRL连接，进而使得上一个像素驱动电路行HPDC的扫描走线GL、下一个像素驱动电路行HPDC的复位控制走线RL(作为上一个像素驱动电路行HPDC中的扫描走线GL对应的复位控制走线RL)通过行转接线HTRL电连接。
在该示例中，被隔断的像素驱动电路行HPDC中最靠近开孔区CC的像素驱动电路可以定义为最内侧的像素驱动电路。在最内侧的像素驱动电 路靠近开孔封装区C1一侧可以设置有辅助区，扫描转接结构GD设置于辅助区内。像素驱动电路行HPDC的扫描走线第一段GL1或者扫描走线第二段GL2需要沿第一方向DH延伸至辅助区内以便与扫描转接结构GD电连接。相应的，下一像素驱动电路行HPDC的复位控制走线RL也需要延伸至辅助区内以便与扫描转接结构GD电连接。
参见图17，行转接线HTRL中，沿第二方向DV的走线段可以与驱动电源走线VDDL交叠设置，以便借助驱动电源走线VDDL屏蔽驱动数据Data等信号，减少行转接线HTRL收到的串扰。进一步地，行转接线HTRL中，沿第二方向DV的走线段可以不与数据走线DataL交叠。
在该示例中，第一源漏金属层SD1在辅助区内还可以设置有使能转接结构EMD，使能转接结构EMD通过过孔与使能走线EML电连接。在开孔封装区C1中，可以设置有使能绕设线(图17和图18中未示出)，使能绕设线可以设置于第一栅极层和第二栅极层中的一层或者两层，以使得使能走线第一段EML1和使能走线第二段EML2电连接。其中，使能绕设线可以通过过孔与使能转接结构EMD电连接。在本公开的一种实施方式中，使能绕设线交替的设置于第一栅极层和第二栅极层。
在该示例中，开孔封装区C1中设置有环绕开孔C2的参考电压绕设线VinitER，参考电压绕设线VinitER上设置有朝向辅助区突出的连接部，连接部通过过孔与初始化走线第一段或者初始化走线第二段(图17和图18中未示出初始化走线第一段或者初始化走线第二段)电连接，以使得各个初始化走线第一段和各个初始化走线第二段通过参考电压绕设线VinitER电连接，进而减小开孔区CC两侧的初始化电压Vinit差异，提高显示面板的均一性。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (29)

  1. 一种显示面板，包括开孔区和围绕所述开孔区的显示区；其中，所述显示面板设置有沿第一方向延伸的行走线和沿第二方向延伸的列走线；所述第一方向和所述第二方向相交；
    部分所述行走线被所述开孔区隔断为相互对应的行走线第一段和行走线第二段；部分所述列走线被所述开孔区隔断为相互对应的列走线第一段和列走线第二段；
    至少部分所述列走线第一段与对应的所述列走线第二段通过位于所述显示区的对应的转接线电连接；
    和/或，至少部分所述行走线第一段与对应的所述行走线第二段通过位于所述显示区的对应的转接线电连接。
  2. 根据权利要求1所述的显示面板，其中，所述列走线包括用于加载驱动数据的数据走线；部分所述数据走线被所述开孔区隔断为相互对应的数据走线第一段和数据走线第二段；
    所述数据走线第一段与对应的所述数据走线第二段通过位于所述显示区的对应的列转接线电连接。
  3. 根据权利要求2所述的显示面板，其中，所述列转接线包括依次连接的列转接线第一段、列转接线第二段和列转接线第三段；
    所述列转接线第一段与所述数据走线第一段电连接，所述列转接线第三段与所述数据走线第二段电连接。
  4. 根据权利要求3所述的显示面板，其中，所述列转接线第一段和所述列转接线第三段沿所述第一方向延伸；所述列转接线第二段沿所述第二方向延伸；
    所述开孔区具有沿所述第二方向延伸的列中轴线；位于所述列中轴线一侧的各个所述数据走线第一段，其所电连接的所述列转接线位于所述列中轴线的同一侧。
  5. 根据权利要求4所述的显示面板，其中，所述列转接线包括分别位于所述列中轴线两侧的两部分；
    位于所述列中轴线同一侧的各个所述列转接线，其各个端部沿所述第 二方向直线排列。
  6. 根据权利要求3所述的显示面板，其中，所述列转接线第一段远离所述列转接线第二段的端部与对应的所述数据走线第一段交叠且电连接，所述列转接线第三段远离所述列转接线第二段的端部与对应的所述数据走线第二段交叠且电连接。
  7. 根据权利要求3所述的显示面板，其中，所述列走线还包括沿所述第二方向延伸的驱动电源走线；所述列转接线第二段与所述驱动电源走线交叠。
  8. 根据权利要求3所述的显示面板，其中，所述显示区设置有阵列分布的像素驱动电路；所述像素驱动电路排列为多个像素驱动电路行和多个像素驱动电路列；
    沿所述第二方向相邻的两个列转接线第一段，分别位于相邻的两个所述像素驱动电路行中；
    沿所述第二方向相邻的两个列转接线第三段，分别位于相邻的两个所述像素驱动电路行中；
    沿所述第一方向相邻的两个列转接线第二段，分别位于相邻的两个所述像素驱动电路列中。
  9. 根据权利要求1所述的显示面板，其中，所述行走线包括用于加载扫描信号的扫描走线；部分所述扫描走线被所述开孔区隔断为相互对应的扫描走线第一段和扫描走线第二段；
    所述扫描走线第一段与对应的所述扫描走线第二段通过位于所述显示区的对应的行转接线电连接。
  10. 根据权利要求9所述的显示面板，其中，至少部分所述行转接线为第一行转接线；所述第一行转接线包括依次连接的行转接线第一段、行转接线第二段、和行转接线第三段；所述行转接线第一段和所述行转接线第三段沿所述第二方向延伸；所述行转接线第二段沿所述第一方向延伸；
    所述行转接线第一段与对应的所述扫描走线第一段电连接，所述行转接线第三段与对应的所述扫描走线第二段电连接。
  11. 根据权利要求10所述的显示面板，其中，所述第一行转接线的行转接线第一段通过其端部与对应的所述扫描走线第一段电连接，所述第 一行转接线的行转接线第三段通过其端部与对应的所述扫描走线第二段电连接。
  12. 根据权利要求9所述的显示面板，其中，部分所述行转接线为第二行转接线；所述第二行转接线包括依次连接的行转接线第四段、行转接线第一段、行转接线第二段、行转接线第三段和行转接线第五段；所述行转接线第一段和所述行转接线第三段沿所述第二方向延伸；所述行转接线第四段、行转接线第二段、行转接线第五段沿所述第一方向延伸；
    所述行转接线第四段通过其远离所述行转接线第一段的端部与对应的所述扫描走线第一段电连接；所述行转接线第五段通过其远离所述行转接线第三段的端部与对应的所述扫描走线第二段电连接。
  13. 根据权利要求12所述的显示面板，其中，所述行转接线第四段与对应的所述扫描走线第一段交叠设置；所述行转接线第五段与对应的所述扫描走线第二段交叠设置。
  14. 根据权利要求10～13任意一项所述的显示面板，其中，所述显示面板设置有沿所述第二方向延伸的驱动电源走线；
    所述行转接线第一段和所述行转接线第三段分别与所述驱动电源走线交叠。
  15. 根据权利要求9～13任意一项所述的显示面板，其中，所述开孔区具有沿所述第一方向延伸的行中轴线；
    位于所述行中轴线一侧的各个所述扫描走线第一段，其所对应的所述行转接线位于所述行中轴线的同一侧。
  16. 根据权利要求10～13任意一项所述的显示面板，其中，所述行走线还包括与所述扫描走线对应且用于加载复位控制信号的复位控制走线；所述复位控制走线与对应的所述扫描走线所加载的信号一致；部分所述复位控制走线被所述开孔区隔断为相互对应的复位控制走线第一段和复位控制走线第二段；
    所述扫描走线第一段与对应的所述复位控制走线第一段并列设置，且电连接至同一所述行转接线第一段；
    所述扫描走线第二段与对应的所述复位控制走线第二段并列设置，且电连接至同一所述行转接线第三段。
  17. 根据权利要求16所述的显示面板，其中，所述开孔区包括开孔和围绕所述开孔的开孔封装区；
    所述开孔封装区设置有与所述扫描走线第一段和所述扫描走线第二段一一对应的扫描转接结构；
    所述扫描走线第一段和对应的所述复位控制走线第一段与对应的所述扫描转接结构电连接；
    所述扫描走线第二段和对应的所述复位控制走线第二段与对应的所述扫描转接结构电连接。
  18. 根据权利要求17所述的显示面板，其中，所述扫描走线和对应的所述复位控制走线设置于同一导电层；所述扫描走线、所述扫描转接结构和所述行转接线位于不同的导电层；
    所述扫描走线第一段和对应的所述复位控制走线第一段，通过过孔与对应的所述扫描转接结构电连接；所述扫描走线第二段和对应的所述复位控制走线第二段，通过过孔与对应的所述扫描转接结构电连接；
    所述扫描走线第一段对应的所述扫描转接结构，通过过孔与所述扫描走线第一段对应的行转接线电连接；
    所述扫描走线第二段对应的所述扫描转接结构，通过过孔与所述扫描走线第二段对应的行转接线电连接。
  19. 根据权利要求1所述的显示面板，其中，所述开孔区包括开孔和围绕所述开孔的开孔封装区；
    所述行走线包括用于加载使能信号的使能走线；
    部分所述使能走线被所述开孔区隔断为相互对应的使能走线第一段和使能走线第二段；
    所述使能走线第一段与对应的所述使能走线第二段通过设置于所述开孔封装区的对应的使能绕设线电连接。
  20. 根据权利要求19述的显示面板，其中，所述显示面板包括层叠设置的第一栅极层和第二栅极层；所述第一栅极层设置有使能走线和存储电容的第一电极板；所述第二栅极层设置有所述存储电容的第二电极板；
    其中，所述使能绕设线设置于所述第一栅极层和/或所述第二栅极层。
  21. 根据权利要求1所述的显示面板，其中，所述开孔区包括开孔和 围绕所述开孔的开孔封装区；
    所述行走线包括用于加载初始化电压的初始化走线；部分所述初始化走线被所述开孔区隔断为相互对应的初始化走线第一段和初始化走线第二段；
    所述开孔封装区设置有一个环绕所述开孔的参考电压绕设线；各个所述初始化走线第一段和各个所述初始化走线第二段与所述参考电压绕设线电连接。
  22. 根据权利要求1所述的显示面板，其中，所述转接线包括行转接线和列转接线；
    所述行转接线用于使得对应的所述行走线第一段和所述行走线第二段电连接；
    所述列转接线用于使得对应的所述列走线第一段和所述列走线第二段电连接；
    所述行转接线的布线空间，位于所述列转接线的布线空间以内。
  23. 根据权利要求22所述的显示面板，其中，沿所述第二方向，所述行转接线分布于所述开孔区的两侧；沿所述第一方向，所述列转接线分布于所述开孔区的两侧；
    所述列转接线与对应的所述列走线之间通过列转接过孔连接，所述行转接线与对应的所述行走线之间通过行转接过孔连接；所述列转接过孔与所述开孔区的距离，大于所述行转接过孔与所述开孔区的距离。
  24. 根据权利要求1所述的显示面板，其中，所述转接线、所述行走线和所述列走线设置于不同的导电层。
  25. 根据权利要求24所述的显示面板，其中，所述显示面板包括依次层叠设置的衬底基板、驱动电路层和像素层；
    所述驱动电路层包括依次层叠设置于所述衬底基板一侧的第一栅极层、第二栅极层和金属布线层；所述行走线布设于所述第一栅极层和所述第二栅极层；所述列走线布设于所述金属布线层；
    所述驱动电路层还包括转接布线层；所述转接布线层设置于所述第一栅极层远离所述第二栅极层的一侧，或者位于所述金属布线层远离所述第二栅极层的一侧，或者位于所述第一栅极层、所述第二栅极层、所述金属 布线层的相邻两层之间；
    所述转接线设置于所述转接布线层。
  26. 根据权利要求25所述的显示面板，其中，所述金属布线层包括第一源漏金属层；
    所述转接布线层包括位于所述第一源漏金属层远离所述衬底基板一侧的第二源漏金属层；所述转接线设置于所述第二源漏金属层。
  27. 根据权利要求25所述的显示面板，其中，所述金属布线层包括层叠设置于所述第二栅极层远离所述衬底基板一侧的第一源漏金属层和第二源漏金属层；所述列走线设置于所述第二源漏金属层；
    所述转接布线层包括位于所述第二源漏金属层远离所述衬底基板一侧的第三源漏金属层；所述转接线设置于所述第三源漏金属层。
  28. 根据权利要求25所述的显示面板，其中，所述显示区包括用于布设所述转接线的转接区，以及围绕所述转接区的非转接区；
    在所述非转接区，所述转接布线层设置有与至少部分所述列走线对应的列走线降阻结构；所述列走线降阻结构与对应的所述列走线通过过孔电连接。
  29. 一种电子设备，包括权利要求1～28任意一项所述的显示面板。
PCT/CN2021/143227 2021-12-30 2021-12-30 显示面板和电子设备 WO2023123239A1 (zh)

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KR20180049296A (ko) * 2016-10-31 2018-05-11 엘지디스플레이 주식회사 관통 홀을 구비한 평판 표시장치
CN108735094A (zh) * 2018-07-25 2018-11-02 武汉华星光电技术有限公司 显示面板
CN109541867A (zh) * 2018-12-28 2019-03-29 厦门天马微电子有限公司 一种显示面板和显示装置
CN111697040A (zh) * 2020-06-15 2020-09-22 合肥维信诺科技有限公司 一种显示面板及显示装置
CN212725309U (zh) * 2020-09-30 2021-03-16 合肥维信诺科技有限公司 阵列基板和显示面板
CN112542092A (zh) * 2020-12-08 2021-03-23 合肥维信诺科技有限公司 显示面板和显示装置
CN113160743A (zh) * 2021-02-24 2021-07-23 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001075112A (ja) * 1999-08-31 2001-03-23 Optrex Corp 液晶表示パネル
KR20180049296A (ko) * 2016-10-31 2018-05-11 엘지디스플레이 주식회사 관통 홀을 구비한 평판 표시장치
CN108735094A (zh) * 2018-07-25 2018-11-02 武汉华星光电技术有限公司 显示面板
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CN113160743A (zh) * 2021-02-24 2021-07-23 合肥维信诺科技有限公司 阵列基板、显示面板及显示装置

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