WO2022242048A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2022242048A1
WO2022242048A1 PCT/CN2021/128698 CN2021128698W WO2022242048A1 WO 2022242048 A1 WO2022242048 A1 WO 2022242048A1 CN 2021128698 W CN2021128698 W CN 2021128698W WO 2022242048 A1 WO2022242048 A1 WO 2022242048A1
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Prior art keywords
light
pixel
sub
layer
transmitting
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Application number
PCT/CN2021/128698
Other languages
English (en)
French (fr)
Inventor
陈友春
郭丹
李硕
高洪成
鲍建东
王计伟
郭胜
侯鹏
刘月
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/800,045 priority Critical patent/US20240179989A1/en
Priority to JP2022558517A priority patent/JP2024519232A/ja
Priority to EP21926068.4A priority patent/EP4123716A4/en
Priority to KR1020237002619A priority patent/KR20240009381A/ko
Publication of WO2022242048A1 publication Critical patent/WO2022242048A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/047—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04112—Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode, organic light-emitting diode
  • OLED Organic Light Emitting Diode, organic light-emitting diode
  • At least one embodiment of the present disclosure provides a display substrate, the display substrate has a plurality of sub-pixels arranged in an array, and includes a base substrate, a driving circuit layer disposed on the base substrate, a driving circuit layer disposed on the driving circuit layer
  • the pixel defining layer on the side away from the base substrate, the light-emitting device layer, and the black matrix layer arranged on the side of the light-emitting device layer away from the base substrate, wherein each of the plurality of sub-pixels includes a A pixel driving circuit in the driving circuit layer and a light emitting device disposed in the light emitting device layer, the pixel driving circuit is configured to drive the light emitting device, the pixel defining layer includes a plurality of sub-pixel openings, the The light-emitting device includes a first electrode layer, a light-emitting material layer, and a second electrode layer that are sequentially stacked in a direction away from the base substrate, and the pixel defining layer is arranged on the side of the first electrode
  • the black matrix layer has A plurality of first light-transmitting openings of the light-emitting device exposing the plurality of sub-pixels, at least one of the plurality of first light-transmitting openings has an arc-shaped edge in a direction perpendicular to the board surface of the base substrate , at least some of the plurality of sub-pixel openings correspond one-to-one with the plurality of first light-transmitting openings and at least partially overlap each other.
  • the planar shape of at least one of the plurality of first light-transmitting openings is an ellipse, half Oval, circular, semicircular, racetrack or semi-racetrack.
  • the plane shape of at least one of the plurality of sub-pixel openings is ellipse, semi-ellipse, Circular, semicircular, racetrack or semi-racetrack.
  • the sub-pixel opening in a corresponding sub-pixel opening and a first light-transmitting opening, in a direction parallel to the plate surface of the base substrate, the sub-pixel opening
  • the plane shape of is the same as the plane shape of the first light-transmitting opening.
  • the orthographic projection of the sub-pixel opening on the base substrate is located within the orthographic projection of the first light transmission opening on the base substrate.
  • the edge of the orthographic projection of the sub-pixel opening on the base substrate and the edge of the orthographic projection of the first light-transmitting opening on the base substrate The minimum distance of the edge is 1 ⁇ m-3 ⁇ m.
  • the first electrode layer includes a main body part and a connection part, the connection part is configured to be electrically connected to the pixel driving circuit, at least part of the main body part is covered by The sub-pixel opening is exposed; in a direction parallel to the board surface of the base substrate, the planar shape of the main body part is at least partially the same as the planar shape of the sub-pixel opening.
  • the orthographic projection of the sub-pixel opening on the base substrate is located within the orthographic projection of the main body portion on the base substrate.
  • the minimum difference between the edge of the orthographic projection of the sub-pixel opening on the base substrate and the edge of the orthographic projection of the main body on the base substrate is The distance is 1 ⁇ m-5 ⁇ m.
  • the orthographic projection of the first light-transmitting opening corresponding to the sub-pixel opening on the base substrate is located on the base substrate of the main body. in the orthographic projection of .
  • the orthographic projection of the main body on the base substrate is located on the base substrate where the first light-transmitting opening corresponding to the sub-pixel opening is located. in the orthographic projection of .
  • the display substrate provided in at least one embodiment of the present disclosure further includes a color filter layer, and the color filter layer includes a plurality of color filter patterns, and the plurality of color filter patterns are respectively arranged in the plurality of first light-transmitting openings. .
  • the black matrix layer further has a plurality of second light-transmitting openings, and the plurality of second light-transmitting openings are respectively arranged on the plurality of first light-transmitting openings.
  • the driving circuit layer includes a plurality of light-transmitting parts; at least part of the plurality of second light-transmitting openings are set in one-to-one correspondence with at least part of the plurality of light-transmitting parts, configured to be transparent to the substrate
  • the surface of the base substrate exposes light in a predetermined range of angles.
  • the second light-transmitting The planar size of the opening is smaller than the planar size of the light-transmitting portion.
  • the orthographic projection of the second light-transmitting opening on the base substrate is the same as that of the light-transmitting opening. Orthographic projections of the light portions on the substrate substrate at least partially overlap.
  • the plurality of sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels
  • the first light-transmitting opening of the light-emitting device exposing the red sub-pixels is substantially shaped like
  • the first ellipse, the first light-transmitting opening of the light-emitting device exposing the green sub-pixel is basically a second ellipse, the length of the major axis of the second ellipse is smaller than the length of the major axis of the first ellipse , the length of the minor axis of the second ellipse is smaller than the length of the minor axis of the first ellipse; or, the first light-transmitting opening of the light-emitting device exposing the green sub-pixel is basically semi-elliptical, and the exposed
  • the first light-transmitting opening of the light-emitting device of the blue sub-pixel is basically in the shape of
  • the first light-transmitting opening of the light-emitting device exposing the red sub-pixel includes opposite first and second arc-shaped edges and The first point and the second point at the intersection position of the arc-shaped edge and the second arc-shaped edge, the first point and the second point are opposite; the first light-transmitting opening of the light-emitting device exposing the blue sub-pixel Including the opposite third arc edge and fourth arc edge and the third tip and fourth tip at the intersection position of the third arc edge and the fourth arc edge, the third tip and the first arc edge The four points are facing each other; and the first light-transmitting opening exposing the light-emitting device of the green sub-pixel includes a fifth arc edge and a fifth point located at one end of the fifth arc edge.
  • the subpixel opening corresponding to the green subpixel includes a sixth arc edge and a sixth tip located at one end of the sixth arc edge, and the green subpixel
  • the main body portion of the first electrode layer of the light emitting device includes a seventh arc-shaped edge, and the seventh arc-shaped edge does not include a tip.
  • the plurality of sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels
  • the first light-transmitting opening of the light-emitting device exposing the red sub-pixels is substantially shaped like
  • the first racetrack shape, the first light-transmitting opening of the light-emitting device exposing the green sub-pixel is basically in the second racetrack shape, and the length of the long axis of the second racetrack shape is smaller than the length of the long axis of the first racetrack shape , the length of the minor axis of the second racetrack shape is less than the length of the minor axis of the first racetrack shape; or, the first light-transmitting opening of the light-emitting device exposing the green sub-pixel is basically half racetrack-shaped, and the exposed
  • the first light-transmitting opening of the light-emitting device of the blue sub-pixel is basically in the shape of a third racetrack, the length of the long axis of the first racetrack shape
  • one red sub-pixel, two green sub-pixels and one blue sub-pixel form a pixel unit, and the plurality of pixel units formed by the plurality of sub-pixels are arranged on the substrate Arranged in an array on the base substrate.
  • At least one embodiment of the present disclosure provides a display device, and the display device includes the display substrate provided by the embodiments of the present disclosure.
  • the display device provided by at least one embodiment of the present disclosure further includes a textured touch surface and an image sensor array, wherein the image sensor array is disposed on a side of the driving circuit layer away from the light emitting device layer, and includes a plurality of an image sensor, the plurality of image sensors configured to receive light emitted from the plurality of light emitting devices in the light emitting device layer and reflected to the plurality of image sensors through the textures on the textured touch surface for use in collection of textures.
  • FIG. 1 is a schematic partial cross-sectional view of a display substrate
  • FIG. 2 is a schematic plan view of a sub-pixel opening of a pixel defining layer of a display substrate and a sub-pixel light exit opening of a black matrix layer;
  • FIG. 3 is a partial cross-sectional schematic diagram of a display substrate provided by at least one embodiment of the present disclosure
  • 4A is a schematic plan view of a sub-pixel opening of a pixel defining layer of a display substrate, a first light-transmitting opening of a black matrix layer, and a first electrode layer of a light-emitting device according to at least one embodiment of the present disclosure;
  • 4B is another schematic plan view of a sub-pixel opening of a pixel defining layer of a display substrate, a first light-transmitting opening of a black matrix layer, and a first electrode layer of a light-emitting device according to at least one embodiment of the present disclosure;
  • FIG. 5 is a schematic cross-sectional view of another part of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6 is a plane layout diagram of multiple sub-pixels of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 7 is a planar layout diagram of multiple first light-transmitting openings of the black matrix layer corresponding to multiple sub-pixels of the display substrate in FIG. 6;
  • FIG. 8A is another layout diagram of a plurality of sub-pixels of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 8B is a planar layout diagram of multiple first light-transmitting openings of the black matrix layer corresponding to multiple sub-pixels of the display substrate in FIG. 8A;
  • FIG. 9 is another planar arrangement diagram of a plurality of sub-pixels of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a plan layout diagram of multiple first light-transmitting openings of the black matrix layer corresponding to the multiple sub-pixels of the display substrate in FIG. 9;
  • FIG. 11A is yet another planar arrangement diagram of a plurality of sub-pixels of a display substrate provided by at least one embodiment of the present disclosure
  • Figure 11B is a planar arrangement diagram of multiple first light-transmitting openings of the black matrix layer corresponding to multiple sub-pixels of the display substrate in Figure 11A;
  • FIG. 12 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 13 is a schematic plan view of a black matrix layer and a color filter layer of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 14A is a schematic diagram of a pixel driving circuit of a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 14B is a schematic diagram of another pixel driving circuit of a display substrate provided by at least one embodiment of the present disclosure.
  • 15 to 21B are partial plan views of each functional layer of a display substrate provided by at least one embodiment of the present disclosure and a partial plan view of each functional layer stacked in sequence;
  • Fig. 22 is a schematic cross-sectional view of a display device provided by at least one embodiment of the present disclosure.
  • COE Cross film On Encapsulation
  • FIG. 1 shows a schematic partial cross-sectional view of an exemplary display substrate using COE technology.
  • the pixel defining layer E has a sub-pixel opening E1, the sub-pixel opening E1 exposes the anode D of the light-emitting device, and the light-emitting layer B1 and the cathode B2 of the light-emitting device are formed in the sub-pixel opening E1 and on the anode D, within the range defined by the sub-pixel opening E1 Inside, the light-emitting layer B1 is in contact with the anode D, and the light-emitting layer B1 can be jointly driven by the anode D and the cathode B2 to emit light.
  • the area defined by the sub-pixel opening E1 is the effective light-emitting area of the sub-pixel.
  • the encapsulation layer F is disposed on the light-emitting device, and the black matrix layer C is disposed on the encapsulation layer F.
  • the black matrix layer C has a sub-pixel light-emitting opening C1 for exposing the effective light-emitting area of the sub-pixel, so that the light emitted by the light-emitting device of the sub-pixel shoot.
  • a color filter A is formed in the light output opening C1 of the sub-pixel, and the color of the color filter A is the same as that of the light emitted by the light-emitting layer of the light-emitting device, thereby improving the light output purity of the display substrate and increasing the light extraction rate of the display substrate;
  • the light-emitting layer of the light-emitting device emits white light, and after the color filter A is added, monochromatic light can be formed.
  • FIG. 2 shows a schematic plan view of a sub-pixel opening of a pixel defining layer corresponding to a sub-pixel of an exemplary display substrate and a sub-pixel light outlet opening of a black matrix layer.
  • the pixel defining layer E The plane shape of the area defined by the sub-pixel opening E1 of the black matrix layer C is hexagonal in plan, and correspondingly, the plane shape of the area defined by the sub-pixel light outlet opening C1 of the black matrix layer C is also hexagonal.
  • the sub-pixel light exit opening C1 of the black matrix layer C in the display substrate adopting COE technology is relatively small, for example, on the order of ⁇ *10 2 , in the current sub-pixel arrangement, for example, when there are red sub-pixel, green In the sub-pixel arrangement of the color sub-pixel, at the hexagonal sub-pixel light outlet opening C1, when the display substrate is exposed to external light (such as a point light source), monochromatic light (red, green, blue, etc.) will inevitably be generated.
  • the shapes and sizes of the sub-pixel openings E1 of the pixel defining layer E corresponding to different color sub-pixels are usually different, wherein the sub-pixel with a narrower opening size Diffraction phenomena produced by pixels and sub-pixels with shorter aperture sizes are more serious, and these diffraction phenomena further aggravate the degree of color separation.
  • the color separation phenomenon refers to that when the display substrate is in the off-screen state, under external light (such as a point light source, a line light source), the reflected light takes on a color (such as red, green, etc.). and blue) separation phenomenon.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate has a plurality of sub-pixels arranged in an array, and includes a base substrate, a driving circuit layer disposed on the base substrate, and a driving circuit layer disposed on the driving circuit layer.
  • each of the plurality of sub-pixels includes a pixel driving circuit arranged in the driving circuit layer and a device
  • the pixel drive circuit is configured to drive the light-emitting device
  • the pixel defining layer includes a plurality of sub-pixel openings
  • the light-emitting device includes a first electrode layer and a light-emitting material that are sequentially stacked in a direction away from the substrate layer and the second electrode layer
  • the pixel defining layer is arranged on the side of the first electrode layer away from the base substrate, and the plurality of sub-pixel openings respectively expose the first electrode layer of the light-emitting device of the plurality of sub-pixels
  • the black matrix layer has A plurality of first light-transmitting openings of the light-emitting
  • At least one of the plurality of first light-transmitting openings has an arc-shaped edge, and the arc-shaped edge can reduce or even eliminate external light passing through the first light-transmitting opening of the black matrix layer. Diffraction at the edge causes color separation on the display substrate, thereby improving the display effect of the display substrate.
  • FIG. 3 shows a schematic cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate has a plurality of sub-pixels arranged in an array.
  • the substrate includes a base substrate 101, a driving circuit layer 102 disposed on the base substrate 101, a light emitting device layer disposed on a side of the driving circuit layer 102 away from the base substrate 101, and a light emitting device layer disposed on a side far away from the base substrate 101.
  • the black matrix layer 113 on the side.
  • each sub-pixel includes a pixel driving circuit disposed in the driving circuit layer 102 and a light emitting device EM disposed in the light emitting device layer, and the pixel driving circuit is configured to drive the light emitting device EM.
  • the black matrix layer 113 has a plurality of first light-transmitting openings 1131 that respectively expose the light-emitting devices EM of a plurality of sub-pixels in a direction perpendicular to the board surface of the base substrate 101 (that is, in the vertical direction in the figure), so as to respectively transmit The light emitted by the light emitting device EM of multiple sub-pixels.
  • FIG. 1 first light-transmitting openings 1131 that respectively expose the light-emitting devices EM of a plurality of sub-pixels in a direction perpendicular to the board surface of the base substrate 101 (that is, in the vertical direction in the figure), so as to respectively transmit The light emitted by the light emitting device EM of multiple sub-pixels.
  • FIG. 4A shows a schematic plan view of the first light-transmitting opening 1131, that is, a schematic plan view in a direction parallel to the board surface of the base substrate 101.
  • at least one first light-transmitting opening 1131 With curved edges, for example, each of the first light-transmitting openings 1131 has curved edges.
  • the planar shape of at least one first light transmission opening 1131 (for example, each first light transmission opening 1131 ) It is basically oval (or called mango-shaped), semi-elliptical, circular, semi-circular, racetrack-shaped (in the case shown in the figure) or semi-racetrack-shaped or other shapes or deformed shapes thereof.
  • the racetrack shape refers to a shape similar to a racetrack formed by a rectangle and two circular arcs on opposite sides of the rectangle. A straight edge and two arcs set opposite each other.
  • the mango shape can be regarded as a deformed shape of an ellipse, with two arc-shaped edges facing each other. For details, refer to FIGS. 6 and 7 described later.
  • the pixel driving circuit of each sub-pixel includes structures such as at least one thin film transistor TFT and a storage capacitor Cst.
  • the thin film transistor TFT includes an active layer 1021, a gate 1022, a source 1023, a drain 1024, and the like.
  • the source 1023 of the thin film transistor TFT is electrically connected to the first electrode layer 104 of the light emitting device EM.
  • the storage capacitor Cst includes a first capacitor electrode C1 and a second capacitor electrode C2.
  • the first capacitor electrode C1 of the storage capacitor Cst is disposed on the same layer as the gate 1022 of the thin film transistor TFT.
  • the pixel driving circuit can be formed into a structure such as 2T1C (two thin film transistors and one storage capacitor), 6T1C (six thin film transistors and one storage capacitor), thereby including a plurality of thin film transistors.
  • the stacked structure is similar or the same.
  • FIG. 3 only shows the thin film transistor directly connected to the light emitting device.
  • the thin film transistor may be a driving thin film transistor or a light emitting control thin film transistor.
  • set in the same layer means that two functional layers or structural layers are formed in the same layer and with the same material in the hierarchical structure of the display substrate, that is, in the manufacturing process, the two The functional layer or structural layer can be formed from the same material layer, and the required pattern and structure can be formed through the same patterning process.
  • the display panel may further include a buffer layer 103 disposed on the base substrate 101, a first gate insulating layer 1024 disposed on the active layer 1021, a first gate insulating layer 1024 disposed on the gate 1022 and a first capacitor electrode
  • the second gate insulating layer 1025 on C1 the interlayer insulating layer 1026 arranged on the second capacitive electrode CE2, the passivation layer 1027 arranged on the source electrode 1023 and the drain electrode 1024, and the planar layer arranged on the passivation layer 1027 layer 109 and other structures.
  • the display substrate may further include a pixel defining layer 108 disposed on the side of the driving circuit layer 102 away from the base substrate 101, for example, the pixel defining layer 108 is disposed on the planarization layer 109, the pixel defining layer 108 includes a plurality of sub-pixel openings 1081, the light-emitting device EM includes a first electrode layer 104, a light-emitting material layer 105, and a second electrode layer 106 that are sequentially stacked in a direction away from the base substrate 101, and the pixel The defining layer 108 is disposed on a side of the first electrode layer 104 away from the substrate 101 , and the plurality of sub-pixel openings 1081 respectively expose the first electrode layer 104 of the light-emitting devices EM of the plurality of sub-pixels.
  • the plurality of sub-pixel openings 1081 correspond to the plurality of first light-transmitting openings 1131 one by one and overlap at least partially.
  • the light emitted by the light emitting device EM can exit through the first light-transmitting opening 1131 to achieve a display effect.
  • the planar shape of at least one sub-pixel opening 1081 is substantially elliptical (or mango-shaped), semi-elliptical. shape, circle, semicircle, racetrack shape (similarity shown in the figure) or half racetrack shape or its deformed shapes.
  • the sub-pixel opening 1081 in a corresponding sub-pixel opening 1081 and a first light-transmitting opening 1131, in a direction parallel to the plate surface of the base substrate 101, the sub-pixel opening 1081
  • the planar shape of the first light-transmitting opening 1131 is the same as the planar shape of the first light-transmitting opening 1131 , and both are racetrack-shaped in the figure.
  • the orthographic projection of the sub-pixel opening 1081 on the base substrate 101 is located within the orthographic projection of the first light-transmitting opening 1131 on the base substrate 101; that is, the sub-pixel
  • the planar size of the opening 1081 is smaller than the planar size of the first light-transmitting opening 1131 .
  • the luminescent material layer 105 Since the luminescent material layer 105 is in contact with the first electrode layer 104 within the range defined by the sub-pixel opening 1081, the luminescent material layer 105 can be jointly driven by the first electrode layer 104 and the second electrode layer 106 to emit light, thus, the sub-pixel
  • the area defined by the opening 1081 is the effective light emitting area of the sub-pixel.
  • the planar shape of the sub-pixel opening 1081 By designing the planar shape of the sub-pixel opening 1081 to be substantially the same as the planar shape of the first light-transmitting opening 1131, and the planar size of the sub-pixel opening 1081 is smaller than the planar size of the first light-transmitting opening 1131, the effective light emission of the sub-pixel The area is fully exposed by the first light-transmitting opening 1131, and the light emitted by the light-emitting device of the sub-pixel can be fully emitted from the first light-transmitting opening 1131, so that the display substrate can make full use of the light emitted by the light-emitting device of the sub-pixel to display, improving Display the light output rate of the substrate to save energy consumption.
  • the minimum distance between the edge of the orthographic projection of the subpixel opening 1081 on the base substrate 101 and the edge of the orthographic projection of the first light-transmitting opening 1131 on the base substrate 101 D1 is 1 ⁇ m-3 ⁇ m, for example, 1.5 ⁇ m, 2 ⁇ m or 2.5 ⁇ m, etc., that is, the sub-pixel opening 1081 shrinks 1 ⁇ m-3 ⁇ m relative to the first light-transmitting opening 1131, so that the effective light-emitting area defined by the sub-pixel opening 1081 is fully covered.
  • the first light-transmitting opening 1131 is exposed.
  • the first electrode layer 104 includes a main body portion 1041 and a connection portion 1042, the connection portion 1042 is configured to be electrically connected to the pixel driving circuit, and at least part of the main body portion 1041 is covered.
  • the pixel opening 1081 is exposed.
  • the planar shape of the main body portion 1041 is the same as the planar shape of the sub-pixel opening 1081 .
  • the orthographic projection of the sub-pixel opening 1081 on the base substrate 101 is located within the orthographic projection of the main body portion 1041 on the base substrate 101 .
  • the shape and size of the main body portion 1041 exposed by the sub-pixel opening 1081 are equal to the shape and size of the sub-pixel opening 1081, so in the manufacturing process, the effective light-emitting area of each sub-pixel can be obtained by designing the size of the sub-pixel opening 1081,
  • the larger main body portion 1041 also leaves room for possible positional deviations of the sub-pixel openings 1081 during the manufacturing process.
  • the minimum distance D2 between the edge of the orthographic projection of the sub-pixel opening 1081 on the base substrate 101 and the edge of the orthographic projection of the main body portion 1041 on the base substrate 101 is 1 ⁇ m ⁇ 5 ⁇ m, such as 2.5 ⁇ m, 3 ⁇ m or 3.5 ⁇ m, etc., that is, the sub-pixel opening 1081 is retracted by 1 ⁇ m-5 ⁇ m relative to the main body portion 1041 .
  • the orthographic projection of the first light-transmitting opening 1131 corresponding to the sub-pixel opening 1081 on the base substrate 101 is located at the orthographic projection of the main body portion 1041 on the base substrate 101 Inside, that is, in a direction parallel to the board surface of the base substrate 101 , the planar dimensions of the main body portion 1041 , the first light-transmitting opening 1131 and the sub-pixel opening 1081 gradually decrease.
  • the design is beneficial to improving the preparation yield of the display substrate, increasing the light extraction rate of the display substrate, and reducing or even eliminating the phenomenon of color separation of the display substrate.
  • the orthographic projection of the main body portion 1041 on the base substrate 101 is located at the front of the first light-transmitting opening 1131 corresponding to the sub-pixel opening 1081 on the base substrate 101. inside the projection.
  • the shape of the first light-transmitting opening 1131 is basically the same as that of the main body portion 1041, and the first light-transmitting opening 1131 expands outward relative to the main body portion 1041.
  • the display substrate may further include structures such as spacers 107 disposed on the pixel defining layer 108 and encapsulation layers EN disposed on the light emitting devices EM of the sub-pixels, for example,
  • the encapsulation layer EN may include multiple sub-encapsulation layers to improve its encapsulation effect.
  • the encapsulation layer EN may be a composite encapsulation layer including a first inorganic encapsulation layer 110 , a second organic encapsulation layer 111 and a third inorganic encapsulation layer 112 .
  • the first inorganic encapsulation layer 110 and the second inorganic encapsulation layer 112 can be formed of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc.
  • the first organic encapsulation layer 111 can be formed of polyimide (PI), epoxy Formed of organic materials such as resins.
  • PI polyimide
  • the composite encapsulation layer can form multiple protections for the functional structure on the display panel, and has a better encapsulation effect.
  • the display substrate may further include a connection electrode 1043 through which the first electrode layer 104 of the light emitting device EM of the sub-pixel is electrically connected to the source electrode 1023 of the thin film transistor TFT. connect.
  • a connection electrode 1043 through which the first electrode layer 104 of the light emitting device EM of the sub-pixel is electrically connected to the source electrode 1023 of the thin film transistor TFT. connect.
  • another planarization layer 1091 is formed on the connection electrode 1043 , and at this time, the pixel defining layer 108 is disposed on the planarization layer 1091 .
  • FIG. 5 for other structures, reference may be made to the description of the display substrate shown in FIG. 3 and FIG. 4A , which will not be repeated here.
  • the base substrate 101 may include a flexible insulating material such as polyimide (PI) or a rigid insulating material such as a glass substrate.
  • the base substrate 101 may be a laminated structure in which multiple flexible layers and multiple barrier layers are alternately arranged.
  • the flexible layer may include polyimide
  • the barrier layer may include inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the buffer layer 103 may include inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride.
  • the active layer 1021 can be made of materials such as polysilicon and metal oxide
  • the first gate insulating layer 1024 and the second gate insulating layer 1025 can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride
  • the gate 1022 and the first Capacitive electrode C1 can be made of metal materials such as copper, aluminum, titanium, cobalt, etc., for example, can be formed into a single-layer structure or a multi-layer structure, such as multi-layer structures such as titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, and the second capacitance electrode C2 Copper, aluminum, titanium, cobalt and other metal or alloy materials can be used
  • the interlayer insulating layer 1026 can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride
  • the passivation layer 1027 can be made of silicon oxide, silicon nitride or
  • the source-drain electrodes 1023 and 1024 can be made of metal materials such as copper, aluminum, titanium, cobalt, etc., for example, can be formed into a single-layer structure or a multi-layer structure, such as a multi-layer structure such as titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, the first
  • the electrode layer 104 is, for example, an anode layer, and includes metal oxides such as ITO, IZO, or metals such as Ag, Al, Mo, or alloys thereof.
  • the material of the luminescent material layer 105 can be an organic luminescent material.
  • the material of the luminescent material layer 105 can be a luminescent material that can emit light of a certain color (such as red light, blue light, or green light, etc.) according to requirements.
  • the second electrode layer 106 is, for example, a cathode layer, including metals such as Mg, Ca, Li or Al or alloys thereof, or metal oxides such as IZO and ZTO, or PEDOT/PSS (poly 3,4-ethylenedioxythiophene/poly Styrene sulfonate) and other organic materials with conductive properties.
  • the planarization layer 109 (and the planarization layer 1091 ), the pixel defining layer 108 and the spacers 107 can be made of organic insulating materials such as polyimide. The embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • the display substrate may further include a color filter layer 114, and the color filter layer 114 includes a plurality of color filter patterns 1141, and the plurality of color filter patterns 1141 are respectively arranged on a plurality of first transparent layers.
  • the light emitted by the light emitting device EM of the sub-pixel can pass through the color filter pattern 1141 to be emitted, so as to improve the purity of the emitted light.
  • the display substrate may further include a protective cover 115 disposed on the black matrix layer 113 and the color filter layer 114 to protect the structure of the display substrate.
  • the protective cover 115 may be a glass cover, which may be bonded to the display substrate through an optically transparent adhesive (not shown in the figure).
  • the black matrix layer 113 can also have a plurality of second light-transmitting openings 1132, and the plurality of second light-transmitting openings 1132 are respectively arranged between the plurality of first light-transmitting openings 1131.
  • the driving circuit layer includes a plurality of light-transmitting parts 1020; at least part of the second light-transmitting openings 1132 are provided in one-to-one correspondence with at least part of the plurality of light-transmitting parts 1020, and are configured to be transparent to the board surface of the base substrate 101 in a predetermined shape. Light in the angular range, for example, passes through the ray L shown in the figure.
  • the light L can pass through the display substrate from the display side (upper side in the figure) of the display substrate to reach the non-display side (lower side in the figure) of the display substrate, for the photosensitive device that may be provided on the non-display side of the display substrate (such as image sensors, etc.) for photosensitive operations.
  • the photosensitive device that may be provided on the non-display side of the display substrate (such as image sensors, etc.) for photosensitive operations.
  • the plurality of light-transmitting parts 1020 include a light-transmitting insulating material
  • the light-transmitting insulating material includes transparent parts of insulating layers such as the first gate insulating layer 1024, the second gate insulating layer 1025, the interlayer insulating layer 1026, and the passivation layer 1027.
  • Optical insulating material is preferably transparent to the first gate insulating layer 1024, the second gate insulating layer 1025, the interlayer insulating layer 1026, and the passivation layer 1027.
  • the planar size of the second light-transmitting opening 1132 is smaller than that of the light-transmitting opening 1132 .
  • the plane size of the light part 1020 will be introduced in detail later.
  • the orthographic projection of the second light-transmitting opening 1132 on the base substrate 101 is the same as that of the light-transmitting portion 1020 on the base substrate 101
  • the orthographic projections on , at least partially overlap, are detailed later.
  • the plurality of sub-pixels of the display substrate include red sub-pixel R, green sub-pixel G and blue sub-pixel B
  • the pixel defining layer includes red sub-pixel opening 11, green sub-pixel
  • the opening 12 and the blue sub-pixel opening 13 the light-emitting devices EM of the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B are respectively formed in the red sub-pixel opening 11, the green sub-pixel opening 12 and the blue sub-pixel opening 11 of the pixel defining layer.
  • the sub-pixel opening 13 In the sub-pixel opening 13.
  • FIG. 7 shows a plurality of first light-transmitting openings 1131 of the black matrix layer 113 corresponding to a plurality of sub-pixels in FIG. 6.
  • the opening 1131 is basically in the shape of a first ellipse 11-1 (or mango shape, formed by two symmetrical circular arcs), and the first light-transmitting opening 1131 exposing the light-emitting device of the green sub-pixel G is basically in the shape of a second ellipse 12-1.
  • the length L2 of the major axis of the second ellipse 12-1 is less than the length L1 of the major axis of the first ellipse 11-1, and the length W2 of the minor axis of the second ellipse 12-1 is less than
  • the first light-transmitting opening 1131 of the light-emitting device exposing the blue sub-pixel B is basically the third ellipse 13-1, and the long axis of the third ellipse 13-1
  • the length L3 of the third ellipse is smaller than the length L1 of the major axis of the first ellipse 11-1, and the length W3 of the minor axis of the third ellipse 13-1 is greater than the length L1 of the minor axis of the first ellipse.
  • the first light-transmitting opening 1131 of the light-emitting device EM exposing the red sub-pixel R has the same shape as the red sub-pixel opening 11 of the pixel defining layer corresponding to the red sub-pixel R, and the red sub-pixel
  • the plane size of the pixel opening 11 is smaller than the plane size of the first light-transmitting opening 1131 of the light-emitting device EM exposing the red sub-pixel R; the first light-transmitting opening 1131 of the light-emitting device EM exposing the green sub-pixel G corresponds to the green sub-pixel G
  • the shape of the green sub-pixel opening 12 of the pixel defining layer is the same, and the planar size of the green sub-pixel opening 12 is smaller than the planar size of the first light-transmitting opening 1131 of the light-emitting device EM exposing the green sub-pixel G;
  • the shape of the first light-transmitting opening 1131 of the light-emitting device EM is the same shape as the red sub-
  • the Lab value is 7.68, and the display substrate in six
  • the Lab value is 28.3, and the lower the Lab value, the less color separation occurs on the display substrate. It can be seen that the display substrate provided by the embodiment of the present disclosure obviously weakens the color separation. Shows the degree of color separation from the substrate.
  • the green subpixel opening 12 of the pixel defining layer corresponding to the green subpixel G is basically semi-elliptical, exposing the first transparent portion of the light emitting device of the green subpixel G.
  • the light opening 1311 is also substantially semi-elliptical 12-2, ie half of an ellipse.
  • the length L21 of the semi-ellipse 12-2 is less than the length L1 of the major axis of the first ellipse 11-1
  • the width W21 of the semi-ellipse 12-2 is less than or equal to the length of the minor axis of the first ellipse 11-1 W1.
  • the first light-transmitting openings 1311 and sub-pixel openings of other sub-pixels in this example are the same as those in FIG. 6 and FIG. 7 , and will not be repeated here.
  • one red sub-pixel R, two green sub-pixels G and one blue sub-pixel B form a pixel unit, and multiple pixel units composed of multiple sub-pixels are
  • the base substrate 101 is arranged in an array.
  • a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B can also form a pixel unit, and multiple pixel units composed of multiple sub-pixels are arrayed on the base substrate 101 Arrangement, the embodiment of the present disclosure does not limit the specific form of the pixel unit.
  • a plurality of sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, and the first transparent portion of the light-emitting device of the red sub-pixel R is exposed.
  • the light opening 1131 is basically in the shape of a first racetrack 21-1, and the first light-transmitting opening 1131 exposing the light-emitting device of the green sub-pixel G is basically in the shape of a half-racetrack 22-1, for example, the length L5 of the half-racetrack shape 22-1 is less than the first The length L4 of the long axis of a racetrack shape, the width W5 of the semi-racetrack shape 22-1 is greater than or equal to the length W4 of the short axis of the first racetrack shape; the first light-transmitting opening 1131 of the light emitting device exposing the blue sub-pixel B is basically Be the third runway shape 23-1, the length L6 of the long axis of the third runway shape 23-1 is less than the length L4 of the long axis of the first runway shape 21-1, the length W6 of the minor axis of the third runway shape 23-1 It is longer than the length W4 of the minor axis of the first runway shape 21-1.
  • the first light-transmitting opening 1131 of the light-emitting device exposing the green sub-pixel G is basically in the shape of a second racetrack 22-2, and the second racetrack shape 22-2
  • the length L7 of the major axis is less than the length L4 of the major axis of the first racetrack shape 21-1
  • the length W7 of the minor axis of the second racetrack shape 22-2 is less than or equal to the length W4 of the minor axis of the first racetrack shape 21-1
  • the green sub-pixel opening 22 of the pixel defining layer corresponding to the green sub-pixel G also has a second racetrack shape.
  • the first light-transmitting opening 1311 and sub-pixel openings of other sub-pixels in this example are the same as those in FIG. 9 and FIG. 10 , and will not be repeated here.
  • one red sub-pixel R, two green sub-pixels G and one blue sub-pixel B form a pixel unit, and multiple pixel units composed of multiple sub-pixels are
  • the base substrate 101 is arranged in an array.
  • a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B can also form a pixel unit, and multiple pixel units composed of multiple sub-pixels are arrayed on the base substrate 101 Arrangement, the embodiment of the present disclosure does not limit the specific form of the pixel unit.
  • FIG. 12 shows a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • one red sub-pixel R, two green sub-pixels G and one blue sub-pixel Pixel B forms a pixel unit
  • the first light-transmitting opening 1131 of the black matrix layer corresponding to each sub-pixel, the sub-pixel opening 1081 of the pixel defining layer, and the main body portion 1041 of the first electrode layer 104 are all oval (or called mango shape).
  • the first light-transmitting opening 1131 of the light-emitting device exposing the red sub-pixel includes opposite first arc-shaped edge RL1 and second arc-shaped edge RL2 and between the first arc-shaped edge RL1 and the second arc-shaped edge RL1 and the second arc-shaped edge
  • the first tip RO1 and the second tip RO2 at the intersection position of the shape edge RL2, the first tip RO1 and the second tip RO2 face each other, thereby forming a mango shape.
  • the first light-transmitting opening 1131 of the light-emitting device exposing the blue sub-pixel includes the opposite third arc-shaped edge BL1 and the fourth arc-shaped edge BL2 and the intersection position of the third arc-shaped edge BL1 and the fourth arc-shaped edge BL2
  • the third tip BO1 is opposite to the fourth tip BO2
  • the third tip BO1 is opposite to the fourth tip BO2.
  • the first light-transmitting opening 1131 of the light-emitting device exposing the green sub-pixel includes a fifth arc-shaped edge GL1 and a fifth tip GO1 located at one end of the fifth arc-shaped edge GL1 .
  • both the first light-transmitting opening of the light-emitting device exposing the red sub-pixel and the first light-transmitting opening of the light-emitting device exposing the blue sub-pixel have two opposite pointed ends, and the first light-transmitting opening of the light emitting device of the green sub-pixel is exposed.
  • the light-transmitting opening has only one tip; this arrangement reduces the degree of color separation of the display substrate.
  • the formed tip may not have a pointed shape, but the curvature of the tip is changed relative to the curvature of the arc edge, for example, the curvature Create mutations at the tip.
  • the green subpixel opening 12 of the pixel defining layer corresponding to the green subpixel G includes a sixth arc edge GL3 and a sixth tip GO3 located at one end of the sixth arc edge GL3, as shown in FIG. 12 , the main body of the first electrode layer of the light emitting device of the green sub-pixel includes a seventh arc-shaped edge GL4 , and the seventh arc-shaped edge GL4 does not include a tip.
  • This setting can reduce the degree of color separation of the display substrate at the green sub-pixel.
  • the black matrix layer includes a plurality of second light-transmitting openings 1132
  • the driving circuit layer includes a plurality of light-transmitting parts 1020
  • one second light-transmitting opening 1132 corresponds to one light-transmitting part 1020
  • the planar size of the second light-transmitting opening 1132 is smaller than the planar size of the light-transmitting portion 1020 .
  • the orthographic projection of the second light-transmitting opening 1132 on the base substrate 101 is the same as that of the light-transmitting portion 1020 on the base substrate 101 Orthographic projections of at least partially overlap, for example, the orthographic projection of the second light-transmitting opening 1132 on the base substrate 101 is located inside the orthographic projection of the light-transmitting portion 1020 on the base substrate 101 .
  • the light L can pass through the second light-transmitting opening 1132 and the light-transmitting portion 1020 from the display side (upper side in the figure) of the display substrate to the non-display side of the display substrate in sequence (the upper side in the figure).
  • the lower side of the display substrate for photosensitive devices (such as image sensors, etc.) that may be provided on the non-display side of the display substrate to perform photosensitive operations.
  • the driving circuit layer 102 includes a first signal line S1 and a second signal line S2 arranged in parallel and arranged periodically, and the first signal line S1 and the second signal line S2 It is configured to provide different electrical signals to the plurality of sub-pixels SP.
  • the orthographic projections of the plurality of second light-transmitting openings 1132 on the base substrate 101 are respectively located in the orthographic projection of a first signal line S1 on the base substrate 101 and the first signal line S1 closest to the first signal line S1. Between the orthographic projections of the two signal lines S2 on the base substrate 101 .
  • the first signal line S1 is an emission control signal line EMT
  • the second signal line is a reset voltage line VNT, which will be described in detail later.
  • the formed signal lines may not be straight lines, for example, have uneven parts.
  • the first signal line S1 and the second signal line The two signal lines S2 being "parallel to each other" may mean that the angle formed between the extension directions of the first signal line S1 and the second signal line S2 is within a range of 15 degrees, but not necessarily parallel in the strict sense.
  • the driving circuit layer may also include third signal lines S3 and fourth signal lines S4 arranged in parallel with each other and arranged periodically, and the third signal lines S3 and fourth signal lines S4 are connected with the first signal lines respectively.
  • the orthographic projections of are respectively located between the orthographic projection of a third signal line S3 on the base substrate 101 and the orthographic projection of a fourth signal line S4 adjacent to the third signal line on the base substrate 101 .
  • the third signal line S3 is the first power line VDD1
  • the fourth signal line S4 is the data line DT, which will be described in detail later.
  • the first signal line S1, the second signal line S2, the third signal line S3, and the fourth signal line S4 define a plurality of first regions RG, that is, the region circled by a dotted line in the figure.
  • the orthographic projections of the plurality of second light-transmitting openings 1032 on the base substrate 101 are respectively located within the orthographic projections of the plurality of first regions RG on the base substrate 101 .
  • FIG. 13 shows a partial plan view of the black matrix layer and the color filter layer of the display substrate, and shows a plurality of first light transmission openings 1131, a plurality of second light transmission openings 1132 and a plurality of color filter patterns 1141 floor plan.
  • the plurality of color filter patterns 1141 include a first color filter pattern that at least partially overlaps with a light-emitting device of a first sub-pixel (for example, a red sub-pixel).
  • 1141A and a second color filter pattern 1141B at least partially overlapping with the light emitting device of the second sub-pixel (for example, the green sub-pixel).
  • the planar shape of the first color filter pattern 1141A is different from the planar shape of the second color filter pattern 1141B, and the area of the first color filter pattern 1141A is larger than that of the second color filter pattern 1141B area.
  • the plane shape of the first color filter pattern 1141A is basically a rectangle, for example, a rectangle with a gap
  • the plane shape of the second color filter pattern 1141B is basically a semi-ellipse.
  • the areas of the first color filter pattern 1141A and the second color filter pattern 1141B are respectively larger than the area of the first light transmission opening 1131 covered by them, so as to fully realize the light filtering effect.
  • the ratio of the area of the first color filter pattern 1141A to the area of the second color filter pattern 1141B ranges from (1 ⁇ 1.5):1, such as 1.2:1 or 1.4:1.
  • the plurality of color filter patterns 1141 further include a third sub-pixel (such as a blue sub-pixel) that at least partially overlaps a light-emitting device.
  • a third sub-pixel such as a blue sub-pixel
  • Three-color film pattern 1141C In the direction parallel to the board surface of the base substrate 101, the planar shape of the third color filter pattern 1141C is different from the planar shapes of the first color filter pattern 1141A and the second color filter pattern 1141B, and the area of the third color filter pattern 1141C It is larger than the area of the first color filter pattern 1141A and the area of the second color filter pattern 1141B.
  • the planar shape of the third color filter pattern 1141C is irregular, so as to fully realize the light filtering effect.
  • the ratio range of the area of the first color filter pattern 1141A, the area of the second color filter pattern 1141B and the area of the third color filter pattern 1141C is (1-1.5):1:(1-1.6 ), such as 1.2:1:1.1 or 1.4:1:1.3, etc.
  • the plurality of color filter patterns 1141 further include a fourth pixel that at least partially overlaps with a light emitting device of a fourth sub-pixel (such as a green sub-pixel).
  • Color filter pattern 1141D In the direction parallel to the board surface of the base substrate 101, the planar shape of the fourth color filter pattern 1141D is basically the same as that of the second color filter pattern 1141B, and the area of the fourth color filter pattern 1141D is basically equal to that of the second color filter pattern. The area of pattern 1141D.
  • the planar shape of the fourth color filter pattern 1141D is basically semi-elliptical, and its area is basically equal to the area of the second color filter pattern 1141D, for example, the area of the fourth color filter pattern 1141D is equal to the area of the second color filter pattern 1141D.
  • the difference is not more than 10% of the area of the second color filter pattern 1141D.
  • the black matrix layer 113 can absorb light incident on the display substrate, reduce the reflectivity of the display substrate to external light, and improve the display effect of the display substrate; by covering the black matrix layer 113 with a color filter layer 114.
  • the color filter layer 114 can perform secondary absorption on the light incident on the display substrate, so as to further reduce the reflectivity of the display substrate to external light and improve the display effect of the display substrate.
  • the fourth color filter pattern 1141D partially overlaps the fourth light-transmitting sub-opening 1132D.
  • the lateral dimension 1141A ⁇ 1 of the first color filter pattern 1141A corresponding to the first sub-pixel P1 is 27 ⁇ m ⁇ 33 ⁇ m, such as 28 ⁇ m, 29 ⁇ m or 30 ⁇ m, etc., and the vertical dimension 1141A ⁇ 2 30 ⁇ m to 35 ⁇ m, such as 32 ⁇ m, 33 ⁇ m or 34 ⁇ m, etc.
  • the lateral dimension 1141B-1 of the second color filter pattern 1141B corresponding to the second sub-pixel P2 is 20 ⁇ m-25 ⁇ m, such as 21 ⁇ m, 22 ⁇ m or 23 ⁇ m, etc., and the vertical dimension 1141B-2 23 ⁇ m to 28 ⁇ m, such as 25 ⁇ m, 26 ⁇ m or 27 ⁇ m, etc.
  • the lateral dimension 1141C ⁇ 1 of the third color filter pattern 1141C corresponding to the third sub-pixel P3 is 32 ⁇ m ⁇ 38 ⁇ m, such as 34 ⁇ m
  • the minimum distance between the edges of the plurality of color filter patterns 1141 and the edges of the plurality of second light-transmitting openings 1132 is 1 ⁇ m-5 ⁇ m.
  • the minimum distance between the edges of the second light-transmitting opening 1132 is 1 ⁇ m-5 ⁇ m, so as to prevent the color filter pattern 1141 from filtering the light passing through the second light-transmitting opening 1132 .
  • the planar shape of the color filter pattern 1141 is different from that of the subpixel opening 1081 .
  • at least part of the edges of the plurality of second light-transmitting openings 1132 are parallel to at least part of the edges of the adjacent color filter patterns 1141.
  • part of the edge of the second light transmission opening 1132 is parallel to the part of the edge of the adjacent color filter pattern 1141 .
  • the sub-pixel uses a 7T1C pixel driving circuit to drive the light emitting device EM.
  • FIG. 14A shows a circuit diagram of a 7T1C pixel circuit.
  • the pixel circuit includes a driving circuit 122 , a data writing circuit 126 , a compensation circuit 128 , a storage circuit 127 , a first light emission control circuit 123 , a second light emission control circuit 124 and a reset circuit 129 .
  • the driving circuit 122 includes a control terminal 131, a first terminal 132 and a second terminal 133, which are configured to control the driving current flowing through the light emitting device EM, and the control terminal 131 of the driving circuit 122 is connected to the first node N1, and the driving circuit The first end 132 of the driving circuit 122 is connected to the second node N2, and the second end 133 of the driving circuit 122 is connected to the third node N3.
  • the data writing circuit 126 includes a control terminal, a first terminal and a second terminal, the control terminal is configured to receive the first scan signal, the first terminal is configured to receive the data signal, and the second terminal is connected to the first terminal of the drive circuit 122 132 (the second node N2 ), and is configured to write the data signal into the first terminal 132 of the driving circuit 122 in response to the first scan signal Ga1 .
  • the first end of the data writing circuit 126 is connected to the data line 12 to receive the data signal, and the control end is connected to the scan line 11 to receive the first scan signal Ga1.
  • the data writing circuit 126 can be turned on in response to the first scan signal Ga1, so that the data signal can be written into the first terminal 132 (the second node N2) of the driving circuit 122, and the data signal can be Stored in the storage circuit 127, for example, the driving current for driving the light-emitting device EM to emit light can be generated according to the data signal during the light-emitting phase.
  • the compensation circuit 128 includes a control terminal, a first terminal and a second terminal. 133 is electrically connected, and the compensation circuit is configured to perform threshold compensation on the driving circuit 120 in response to the second scan signal.
  • the storage circuit 127 is electrically connected to the control terminal 131 of the driving circuit 122 and the first voltage terminal VDD, and configured to store the data signal written by the data writing circuit 126 .
  • the compensation circuit 128 can be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing circuit 126 can be stored in the storage circuit 127 .
  • the compensation circuit 128 can electrically connect the control terminal 131 and the second terminal 133 of the driving circuit 122, so that the relevant information of the threshold voltage of the driving circuit 122 can also be stored in the memory.
  • the stored data signal and the threshold voltage can be used to control the driving circuit 122 during the light-emitting phase, so that the output of the driving circuit 122 is compensated.
  • the first light emission control circuit 123 is connected to the first terminal 132 (second node N2) of the drive circuit 122 and the first voltage terminal VDD, and is configured to switch the first voltage terminal VDD to the first voltage terminal VDD in response to the first light emission control signal.
  • the power supply voltage is applied to the first terminal 132 of the driving circuit 122 .
  • the first light emission control circuit 123 is connected to the first light emission control terminal EM1 , the first voltage terminal VDD and the second node N2 .
  • the second light emission control circuit 124 is connected to the second light emission control terminal EM2, the first terminal 510 of the light emitting device EM, and the second terminal 132 of the driving circuit 122, and is configured to respond to the second light emission control signal so that the driving current can be controlled by Applied to the light emitting device EM.
  • the second light-emitting control circuit 123 is turned on in response to the second light-emitting control signal provided by the second light-emitting control terminal EM2, so that the driving circuit 122 can apply a driving current to the light-emitting device EM through the second light-emitting control circuit 123 In order to make it emit light; and in the non-light-emitting period, the second light-emitting control circuit 123 is turned off in response to the second light-emitting control signal, so as to prevent current from flowing through the light-emitting device EM and make it emit light, which can improve the contrast of the corresponding display device.
  • the second light emission control circuit 124 can also be turned on in response to the second light emission control signal, so that the reset circuit can be combined to reset the driving circuit 122 and the light emitting device EM.
  • the second light emission control signal EM2 may be the same as or different from the first light emission control signal EM1 , for example, the two may be connected to the same or different signal output terminals.
  • the reset circuit 129 is connected to the reset voltage terminal Vinit and the first terminal 134 (fourth node N4) of the light emitting device EM, and is configured to apply a reset voltage to the first terminal 134 of the light emitting device EM in response to a reset signal.
  • the reset signal may also be applied to the control terminal 131 of the driving circuit, that is, the first node N1.
  • the reset signal is the second scan signal, and the reset signal may also be other signals synchronized with the second scan signal, which is not limited in the embodiments of the present disclosure. For example, as shown in FIG.
  • the reset circuit 129 is respectively connected to the first terminal 134 of the light emitting device EM, the reset voltage terminal Vinit and the reset control terminal Rst (reset control line).
  • the reset circuit 129 can be turned on in response to the reset signal, so that the reset voltage can be applied to the first end 134 and the first node N1 of the light emitting device EM, so that the driving circuit 122, the compensation circuit 128 and the light emitting The device EM performs a reset operation, eliminating the effects of the previous light-emitting phase.
  • the light emitting device EM includes a first end 134 and a second end 135, the first end 134 of the light emitting device EM is configured to receive a driving current from the second end 133 of the driving circuit 122, and the second end 135 of the light emitting device EM is configured to communicate with The second voltage terminal VSS is connected.
  • the first end 134 of the light emitting device EM may be connected to the third node N3 through the second light emitting circuit 124 .
  • Embodiments of the present disclosure include, but are not limited to, this scenario.
  • the light-emitting device EM can be various types of OLEDs, such as top emission, bottom emission, double-side emission, etc., which can emit red light, green light, blue light, or white light, etc.
  • the first electrode layer and the second electrode layer of the OLED are respectively used as the first end 134 and the second end 135 of the light emitting device.
  • the embodiments of the present disclosure do not limit the specific structure of the light emitting device.
  • the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent the actual components, but represent the relevant circuit connections in the circuit diagram. meeting point.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the signal can also represent the first scanning signal terminal and the second scanning signal terminal
  • Rst can represent both the reset control terminal and the reset signal
  • the symbol Vinit can represent both the reset voltage terminal and the reset voltage
  • the symbol VDD can represent the second A voltage terminal can also represent the first power supply voltage
  • the symbol VSS can represent both the second voltage terminal and the second power supply voltage.
  • FIG. 14B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 14A .
  • the pixel circuit includes: first to seventh transistors T1 , T2 , T3 , T4 , T5 , T6 , T7 and a storage capacitor Cst.
  • the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.
  • the driving circuit 122 may be implemented as a first transistor T1.
  • the gate of the first transistor T1 serves as the control terminal 131 of the drive circuit 122 and is connected to the first node N1;
  • the first pole of the first transistor T1 serves as the first terminal 132 of the drive circuit 122 and is connected to the second node N2;
  • the second pole of the transistor T1 serves as the second terminal 133 of the driving circuit 122 and is connected to the third node N3.
  • the data writing circuit 126 may be implemented as a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, and the first pole of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal , the second pole of the second transistor T2 is connected to the first terminal 132 (second node N2 ) of the driving circuit 122 .
  • the second transistor T2 is a P-type transistor, such as a thin film transistor whose active layer is low-temperature doped polysilicon.
  • the compensation circuit 128 may be implemented as a third transistor T3.
  • the gate of the third transistor T3 is configured to be connected to the second scan line (second scan signal terminal Ga2) to receive the second scan signal, and the first pole of the third transistor T3 is connected to the control terminal 131 of the drive circuit 122 (the first node N1) is connected, and the second pole of the third transistor T3 is connected to the second terminal 133 (third node N3) of the driving circuit 122 .
  • the storage circuit 127 can be implemented as a storage capacitor Cst, the storage capacitor Cst includes a first capacitor electrode C1 and a second capacitor electrode C2, the first capacitor electrode C1 is connected to the first voltage terminal VDD, and the The second capacitive electrode C2 is connected to the control terminal 131 of the driving circuit 122 .
  • the first light emission control circuit 123 may be realized as a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the first light emission control line (the first light emission control terminal EM1) to receive the first light emission control signal, and the first pole of the fourth transistor T4 is connected to the first voltage terminal VDD to receive the first power supply voltage, the second pole of the fourth transistor T4 is connected to the first terminal 132 (second node N2 ) of the driving circuit 122 .
  • the light-emitting device EM can be specifically implemented as a light-emitting diode (OLED), and its first electrode layer (here, the anode) is connected to the fourth node N4 and is configured to be connected from the second terminal 133 of the driving circuit 122 through the second light-emitting control circuit 124.
  • the second electrode layer (here, the cathode) of the light emitting device EM is configured to be connected to the second voltage terminal VSS to receive the second power supply voltage.
  • the second voltage terminal can be grounded, that is, VSS can be 0V.
  • the second light emission control circuit 124 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second light emission control line (second light emission control terminal EM2) to receive the second light emission control signal, and the first pole of the fifth transistor T5 is connected to the second terminal 133 of the driving circuit 122 (third light emission control terminal EM2). node N3), and the second pole of the fifth transistor T5 is connected to the first terminal 134 (fourth node N4) of the light emitting device EM.
  • the reset circuit 129 may include a first reset circuit configured to apply a first reset voltage Vini1 to the first node N1 in response to a first reset signal Rst1 and a second reset circuit configured to The second reset voltage Vini2 is applied to the fourth node N4 in response to the second reset signal Rst2.
  • the first reset circuit is implemented as a sixth transistor T6, and the second reset circuit is implemented as a seventh transistor T7.
  • the gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset signal Rst1, and the first electrode of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1.
  • the second pole of the six-transistor T6 is configured to be connected to the first node N1.
  • the gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset signal Rst2, and the first electrode of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2.
  • the second pole of the seven transistor T7 is configured to be connected to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the embodiments of the present disclosure in order to distinguish the two poles of the transistor except the gate, it is directly described that one pole is the first pole and the other pole is the second pole.
  • the first signal line S1 is the light emission control line EMT, which is used to transmit the first light emission control signal EM1 and the second light emission control signal EM2;
  • the second signal line S2 is the reset voltage line VNT, which is used to transmit the above light emission control signal EM2.
  • the side of the reset voltage line VNT away from the light emission control line EMT further has a reset control line RST for transmitting the above-mentioned first reset signal Rst1 and second reset signal Rst2.
  • FIG. 15 shows a schematic diagram of the semiconductor layer of the display substrate, and the semiconductor layer is used to form the active layers of the thin film transistors T1-T7 of the pixel driving circuit of multiple sub-pixels.
  • FIG. 12 shows two rows of sub-pixels The pixel driving circuit, the pixel driving circuit of the four directly adjacent sub-pixels (namely the first sub-pixel 100a, the second sub-pixel 100b, the third sub-pixel 100c and the fourth sub-pixel 100d) is used as an example to introduce, in the figure
  • the dotted line box in the shows the area where the pixel driving circuit of each sub-pixel is located, and the embodiments of the present disclosure are not limited to this layout.
  • a first gate insulating layer is further disposed on the semiconductor layer, which is not shown in the figure, and reference may be made to the first gate insulating layer 1024 in FIG. 3 or FIG. 5 .
  • FIG. 16A shows a schematic diagram of the first gate metal layer of the display substrate, and the first gate metal layer is disposed on the first gate insulating layer.
  • FIG. 16B shows a schematic diagram of the first gate metal layer and the semiconductor layer stack of the display substrate. .
  • the first gate metal layer includes a plurality of emission control lines EMT, a plurality of reset control lines RST, a plurality of scanning lines GATE, and a plurality of first capacitor electrodes C1 of storage capacitors Cst, for example
  • the emission control line EMT, the reset control line RST, the scan line GATE, and the overlapping portion of the first capacitor electrode C1 of the storage capacitor Cst and the active layer of the thin film transistors T1 - T7 constitute the gates of the thin film transistors T1 - T7 .
  • a plurality of emission control lines EMT, a plurality of reset control lines RST, and a plurality of scanning lines GATE are respectively electrically connected to the plurality of rows of sub-pixels in one-to-one correspondence to provide corresponding electrical signals.
  • a second gate insulating layer is further disposed on the first gate metal layer, which is not shown in the figure, and reference may be made to the second gate insulating layer 1025 in FIG. 3 and FIG. 5 .
  • FIG. 17A shows a schematic diagram of the second gate metal layer of the display substrate, the second gate metal layer is disposed on the second gate insulating layer, and FIG. 17B shows the connection between the second gate metal layer of the display substrate and the first gate metal layer and Schematic diagram of a semiconductor layer stack.
  • the second gate metal layer includes a second capacitor electrode C2 of a storage capacitor Cst and a plurality of reset voltage lines VNT.
  • the second capacitor electrode C2 of the storage capacitor Cst at least partially overlaps the first capacitor electrode C1 to form a capacitor.
  • Multiple reset voltage lines VNT are electrically connected to multiple rows of sub-pixels in one-to-one correspondence to provide corresponding electrical signals.
  • an interlayer insulating layer is further disposed on the second gate metal layer, which is not shown in the figure, and reference may be made to the interlayer insulating layer 1026 in FIG. 3 and FIG. 5 .
  • Fig. 18A shows a schematic diagram of the first source-drain metal layer of the display substrate, the first source-drain metal layer is disposed on the interlayer insulating layer, and Fig. 18B shows the first source-drain metal layer and the second gate metal layer of the display substrate layer, the first gate metal layer and the schematic diagram of the semiconductor layer stack.
  • the first source-drain metal layer includes a plurality of first power supply lines VDD1 .
  • the plurality of first power supply lines VDD1 are respectively electrically connected to multiple columns of sub-pixels in one-to-one correspondence to provide the first power supply voltage.
  • the first source-drain metal layer further includes the plurality of data lines DT. The multiple data lines DT are electrically connected to multiple columns of sub-pixels in one-to-one correspondence to provide data signals.
  • the first source-drain metal layer further includes a plurality of connecting electrodes CL for connecting the second capacitor electrode C2 and the first pole of the third transistor T3, or connecting the first pole of the sixth transistor T6 and the reset voltage line VNT, Or connect the second electrode of the fifth transistor T5 to the first electrode layer of the light emitting device and the like.
  • a passivation layer and a planarization layer are further disposed on the first source-drain metal layer, which are not shown in the figure, and reference may be made to the passivation layer 1027 and the planarization layer 1091 in FIG. 3 and FIG. 5 .
  • FIG. 19A shows a schematic diagram of the second source and drain metal layer of the display substrate.
  • the second source and drain metal layer is disposed on the planarization layer 1091.
  • FIG. 19B shows the connection between the second source and drain metal layer of the display substrate and the first source and drain metal layer.
  • the second source-drain metal layer includes a second power line VDD2, and the second power line VDD2 is in a grid shape.
  • the second power line VDD2 is electrically connected to the first power line VDD1 to effectively It helps to reduce the resistance on the power line to reduce the voltage drop of the power line, and helps to uniformly deliver the first power supply voltage to each sub-pixel of the display substrate.
  • the second source-drain metal layer may further include a connecting electrode 1043 for connecting the first electrode layer of the light emitting device and the first electrode of the first transistor T1.
  • the second power line VDD2 at least partially overlaps with the main body portion 1042 of the first electrode layer 104 .
  • FIG. 20 shows a schematic plan view of the planarization layer.
  • the first electrode layer 104 is connected to the connection electrode 1043 through the via hole VA in the planarization layer 109 .
  • multiple via holes VA of the planarization layer 109 corresponding to multiple sub-pixels in the same row are not on a straight line.
  • a first sub-pixel such as a red sub-pixel
  • a second sub-pixel such as a green sub-pixel
  • a third sub-pixel such as a blue sub-pixel
  • a fourth sub-pixel for example, a green sub-pixel
  • the routing of the pixel driving circuit can be avoided to a larger light-transmitting area, forming a sufficient area of the light-transmitting portion.
  • FIG. 21A shows a schematic diagram of the first electrode material layer of the display substrate, and the first electrode material layer is disposed on the passivation layer 109.
  • FIG. 21B shows the first electrode material layer and the second source-drain metal layer of the display substrate, A schematic diagram of the first source-drain metal layer, the second gate metal layer, the first gate metal layer and the semiconductor layer stack.
  • the first electrode material layer includes the first electrode layers of the light-emitting devices EM of multiple sub-pixels, and the first electrode layers of the light-emitting devices EM of multiple sub-pixels pass through a plurality of planarization layers 109 respectively.
  • the via hole VA is connected to the connection electrode 1043 .
  • the light emitting material layer of the light emitting device EM is disposed on the first electrode layer, and the second electrode layer is disposed on the light emitting material layer.
  • FIG. 22 shows a schematic cross-sectional view of the display device.
  • the display device includes a display substrate provided by an embodiment of the present disclosure.
  • the display substrate shown in 3 is taken as an example.
  • the display device further includes a textured touch surface S and an image sensor array 30 , for example, the surface of the protective cover 115 is realized as the textured touch surface S.
  • the image sensor array is arranged on the side of the driving circuit layer 102 away from the light-emitting device layer, and includes a plurality of image sensors 31 (one is shown in the figure as an example), and the plurality of image sensors 31 are configured to receive multiple images from the light-emitting device layer.
  • the light emitted by each light emitting device EM and reflected by the textures (such as fingerprints, palmprints, etc.) on the textured touch surface S to the plurality of image sensors 31 is used for texture collection.
  • the black matrix layer includes a plurality of second light-transmitting openings 1132
  • the driving circuit layer includes a plurality of light-transmitting portions 1020
  • one second light-transmitting opening 1132 corresponds to one light-transmitting portion 1020.
  • the sensor 31 is configured to receive reflections emitted from multiple light-emitting devices EM in the light-emitting device layer and reflected by the texture on the textured touch surface S, and pass through multiple second light-transmitting openings 1132 of the black matrix layer 113 and the driving circuit layer.
  • Light from the plurality of light-transmitting parts 1020 reaches the plurality of image sensors 31 for texture collection. Therefore, through the plurality of second light-transmitting openings 1132 and the plurality of light-transmitting portions 1020 , the plurality of image sensors 31 can fully receive the light reflected by the texture, thereby improving the speed and accuracy of texture recognition.
  • the display device provided by the embodiments of the present disclosure may also have other structures, for details, reference may be made to related technologies, which will not be repeated here.

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Abstract

一种显示基板和显示装置，显示基板，该显示基板具有阵列排布的多个子像素，且包括衬底基板(101)、设置在衬底基板(101)上的驱动电路层(102)、设置在驱动电路层(102)的远离衬底基板(101)一侧的像素界定层(108)、发光器件层以及设置在发光器件层远离衬底基板(101)一侧的黑矩阵层(113)，多个子像素的每个包括设置在驱动电路层(102)中的像素驱动电路以及设置在发光器件层中的发光器件(EM)，像素驱动电路配置为驱动发光器件(EM)，黑矩阵层(113)具有在垂直于衬底基板(101)的板面的方向上分别暴露多个子像素的发光器件(EM)的多个第一透光开口(1031)，像素界定层(108)包括多个子像素开口(1081)，至少部分子像素开口(1081)与多个第一透光开口(1031)一一对应且至少部分重叠，多个第一透光开口(1031)中的至少一个具有弧形边缘。该显示基板具有更好的显示效果。

Description

显示基板以及显示装置
本申请要求于2021年5月19日递交的国际申请第PCT/CN2021/094676号的优先权以及2021年6月29日递交的中国专利申请第202110726472.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示基板以及显示装置。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)显示装置具有自发光、对比度高、清晰度高、视角宽、功耗低、响应速度快、以及制造成本低等一系列优势，已经成为新一代显示装置的重点发展方向之一，因此受到越来越多的关注。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有阵列排布的多个子像素，且包括衬底基板、设置在所述衬底基板上的驱动电路层、设置在所述驱动电路层的远离所述衬底基板一侧的像素界定层、发光器件层以及设置在所述发光器件层远离所述衬底基板一侧的黑矩阵层，其中，所述多个子像素的每个包括设置在所述驱动电路层中的像素驱动电路以及设置在所述发光器件层中的发光器件，所述像素驱动电路配置为驱动所述发光器件，所述像素界定层包括多个子像素开口，所述发光器件包括在远离所述衬底基板的方向上依次叠层设置的第一电极层、发光材料层和第二电极层，所述像素界定层设置在所述第一电极层的远离所述衬底基板的一侧，且所述多个子像素开口分别暴露所述多个子像素的发光器件的第一电极层，所述黑矩阵层具有在垂直于所述衬底基板的板面的方向上分别暴露所述多个子像素的发光器件的多个第一透光开口，所述多个第一透光开口中的至少一个具有弧形边缘，在垂直于所述衬底 基板的板面的方向上，至少部分所述多个子像素开口与多个第一透光开口一一对应且至少部分重叠。
例如，本公开至少一实施例提供的显示基板中，在平行于所述衬底基板的板面的方向上，所述多个第一透光开口中的至少一个的平面形状呈椭圆形、半椭圆形、圆形、半圆形、跑道形或者半跑道形。
例如，本公开至少一实施例提供的显示基板中，在平行于所述衬底基板的板面的方向上，所述多个子像素开口中的至少一个的平面形状呈椭圆形、半椭圆形、圆形、半圆形、跑道形或者半跑道形。
例如，本公开至少一实施例提供的显示基板中，在对应的一个子像素开口和一个第一透光开口中，在平行于所述衬底基板的板面的方向上，所述子像素开口的平面形状与所述第一透光开口的平面形状相同。
例如，本公开至少一实施例提供的显示基板中，所述子像素开口在所述衬底基板上的正投影位于所述第一透光开口在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述子像素开口在所述衬底基板上的正投影的边缘与所述第一透光开口在所述衬底基板上的正投影的边缘的最小距离为1μm-3μm。
例如，本公开至少一实施例提供的显示基板中，所述第一电极层包括主体部和连接部，所述连接部配置为与所述像素驱动电路电连接，所述主体部的至少部分被所述子像素开口暴露；在平行于所述衬底基板的板面的方向上，所述主体部的平面形状与所述子像素开口的平面形状至少部分相同。
例如，本公开至少一实施例提供的显示基板中，所述子像素开口在所述衬底基板上的正投影位于所述主体部在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述子像素开口在所述衬底基板上的正投影的边缘与所述主体部在所述衬底基板上的正投影的边缘的最小距离为1μm-5μm。
例如，本公开至少一实施例提供的显示基板中，与所述子像素开口对应设置的第一透光开口在所述衬底基板上的正投影位于所述主体部在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板中，所述主体部在所述衬底基板上的正投影位于与所述子像素开口对应设置的第一透光开口在所述衬底基板上的正投影内。
例如，本公开至少一实施例提供的显示基板还包括彩膜层，所述彩膜层包括多个彩膜图案，所述多个彩膜图案分别设置在所述多个第一透光开口中。
例如，本公开至少一实施例提供的显示基板中，所述黑矩阵层还具有多个第二透光开口，所述多个第二透光开口分别设置在所述多个第一透光开口之间，所述驱动电路层包括多个透光部分；至少部分所述多个第二透光开口与至少部分所述多个透光部分一一对应设置，配置为可透过与所述衬底基板的板面呈预定角度范围的光。
例如，本公开至少一实施例提供的显示基板中，在对应设置的第二透光开口和透光部分中，在平行于所述衬底基板的板面的方向上，所述第二透光开口的平面尺寸小于所述透光部分的平面尺寸。
例如，本公开至少一实施例提供的显示基板中，在对应设置的第二透光开口和透光部分中，所述第二透光开口在所述衬底基板上的正投影与所述透光部分在所述衬底基板上的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，暴露所述红色子像素的发光器件的第一透光开口基本呈第一椭圆形，暴露所述绿色子像素的发光器件的第一透光开口基本呈第二椭圆形，所述第二椭圆形的长轴的长度小于所述第一椭圆形的长轴的长度，所述第二椭圆形的短轴的长度小于所述第一椭圆形的短轴的长度；或者，暴露所述绿色子像素的发光器件的第一透光开口基本呈半椭圆形，以及暴露所述蓝色子像素的发光器件的第一透光开口基本呈第三椭圆形，所述第三椭圆形的长轴的长度小于所述第一椭圆形的长轴的长度，所述第三椭圆形的短轴的长度大于所述第一椭圆形的短轴的长度。
例如，本公开至少一实施例提供的显示基板中，暴露所述红色子像素的发光器件的第一透光开口包括相对的第一弧形边缘和第二弧形边缘以及在所述第一弧形边缘和所述第二弧形边缘相交位置的第一尖端和第二尖端，所述第一尖端和所述第二尖端相对；暴露所述蓝色子像素 的发光器件的第一透光开口包括相对的第三弧形边缘和第四弧形边缘以及在所述第三弧形边缘和所述第四弧形边缘相交位置第三尖端和第四尖端，所述第三尖端和所述第四尖端相对；以及暴露所述绿色子像素的发光器件的第一透光开口包括第五弧形边缘以及位于所述第五弧形边缘一端的第五尖端。
例如，本公开至少一实施例提供的显示基板中，所述绿色子像素对应的子像素开口包括第六弧形边缘以及位于所述第六弧形边缘一端的第六尖端，所述绿色子像素的发光器件的第一电极层的主体部包括第七弧形边缘，所述第七弧形边缘不包括尖端。
例如，本公开至少一实施例提供的显示基板中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，暴露所述红色子像素的发光器件的第一透光开口基本呈第一跑道形，暴露所述绿色子像素的发光器件的第一透光开口基本呈第二跑道形，所述第二跑道形的长轴的长度小于所述第一跑道形的长轴的长度，所述第二跑道形的短轴的长度小于所述第一跑道形的短轴的长度；或者，暴露所述绿色子像素的发光器件的第一透光开口基本呈半跑道形，以及暴露所述蓝色子像素的发光器件的第一透光开口基本呈第三跑道形，所述第三跑道形的长轴的长度小于所述第一跑道形的长轴的长度，所述第三跑道形的短轴的长度大于所述第一跑道形的短轴的长度。
例如，本公开至少一实施例提供的显示基板中，一个红色子像素、两个绿色子像素和一个蓝色子像素组成一个像素单元，所述多个子像素组成的多个像素单元在所述衬底基板上阵列排布。
本公开至少一实施例提供一种显示装置，该显示装置包括本公开实施例提供的显示基板。
例如，本公开至少一实施例提供的显示装置还包括纹路触摸表面以及图像传感器阵列，其中，所述图像传感器阵列设置在所述驱动电路层的远离所述发光器件层的一侧，包括多个图像传感器，所述多个图像传感器配置为可接收从所述发光器件层中的多个发光器件发出的且经在所述纹路触摸表面的纹路反射至所述多个图像传感器的光以用于纹路采集。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的部分截面示意图；
图2为一种显示基板的像素界定层的子像素开口和黑矩阵层的子像素出光开口的平面示意图；
图3为本公开至少一实施例提供的一种显示基板的部分截面示意图；
图4A为本公开至少一实施例提供的一种显示基板的像素界定层的子像素开口、黑矩阵层的第一透光开口以及发光器件的第一电极层的平面示意图；
图4B为本公开至少一实施例提供的一种显示基板的像素界定层的子像素开口、黑矩阵层的第一透光开口以及发光器件的第一电极层的另一平面示意图；
图5为本公开至少一实施例提供的一种显示基板的另一部分截面示意图；
图6为本公开至少一实施例提供的一种显示基板的多个子像素的平面排布图；
图7为图6中的显示基板的多个子像素对应的黑矩阵层的多个的第一透光开口的平面排布图；
图8A为本公开至少一实施例提供的一种显示基板的多个子像素的另一平面排布图；
图8B为图8A中的显示基板的多个子像素对应的黑矩阵层的多个的第一透光开口的平面排布图；
图9为本公开至少一实施例提供的一种显示基板的多个子像素的再一平面排布图；
图10为图9中的显示基板的多个子像素对应的黑矩阵层的多个的第一透光开口的平面排布图；
图11A为本公开至少一实施例提供的一种显示基板的多个子像素的再另一平面排布图；
图11B为图11A中的显示基板的多个子像素对应的黑矩阵层的多 个的第一透光开口的平面排布图；
图12为本公开至少一实施例提供的一种显示基板的平面示意图；
图13为本公开至少一实施例提供的一种显示基板的黑矩阵层和彩膜层的平面示意图；
图14A为本公开至少一实施例提供的显示基板的像素驱动电路的示意图；
图14B为本公开至少一实施例提供的显示基板的另一像素驱动电路的示意图；
图15～图21B为本公开至少一实施例提供的一种显示基板的各个功能层的部分平面示意图以及各个功能层依次叠层后的部分平面示意图；
以及
图22为本公开至少一实施例提供的一种显示装置的截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了防止屏幕反光，传统的OLED显示基板通常通过在显示基板上贴上一层偏光片，来提升显示基板在环境光下的使用舒适度。但是，本公开的发明人发现，偏光片的透过率通常只有40％左右，导致显示基板的光取出率较低，进而导致显示基板的功耗较高。
在一些实施例中，可以采用COE(Cover film On Encapsulation)技术，即利用彩膜(color film，CF)取代偏光片的技术，来提高显示基板的光取出率，并且该技术有利于显示基板向高集成度、轻薄化方向发展。
例如，图1示出了一种示例性的采用COE技术的显示基板的部分截面示意图，如图1所示，显示基板具有像素界定层E、发光器件、黑矩阵层C和封装层F等结构。像素界定层E具有子像素开口E1，子像素开口E1暴露发光器件的阳极D，子像素开口E1内以及阳极D上形成有发光器件的发光层B1和阴极B2，在子像素开口E1限定的范围内，发光层B1与阳极D接触，发光层B1可以被阳极D和阴极B2共同驱动而发光，由此，子像素开口E1限定的区域为子像素的有效发光区域。封装层F设置在发光器件上，黑矩阵层C设置在封装层F上，黑矩阵层C具有子像素出光开口C1，用于暴露子像素的有效发光区域，以便子像素的发光器件发出的光出射。例如，子像素出光开口C1中形成有彩膜A，彩膜A的颜色与发光器件的发光层发出的光的颜色相同，进而可以提高显示基板的出光纯度，并提高显示基板的光取出率；或者，发光器件的发光层发出白光，增加彩膜A后，可以形成单色光。
但是，本公开的发明人发现，如图1所示，外界光(如图1的箭头所示)经过子像素出光开口C1的边缘会产生衍射，并且外界光经过发光器件的阳极和阴极反射出来的光经过子像素出光开口C1的边缘也会产生衍射，由此产生显示基板的色分离现象，即外界光以及外界光经发光器件的阳极和阴极反射的光在子像素出光开口C1的边缘产生颜色的现象。通过研究，上述衍射现象产生的衍射光范围(衍射光形状)与子像素出光开口C1的形状和大小有相关性。
例如，图2示出了一种示例性的显示基板的一个子像素对应的像素界定层的子像素开口和黑矩阵层的子像素出光开口的平面示意图，如图2所示，像素界定层E的子像素开口E1限定的区域的平面形状呈六边形，相应地，黑矩阵层C的子像素出光开口C1限定的区域的平面形状也呈六边形。由于采用COE技术的显示基板中黑矩阵层C的子像素出光开口C1较小，例如在λ*10 2量级，在目前的子像素排列中，例如在具有红色子像素、绿色子像素和蓝色子像素的子像素排列中，在六边形的子像素出光开口C1处，显示基板在外界光下(例如点光源下)，不可避免地会产生单色光(红色、绿色 和蓝色等)的衍射效应，且因为不同颜色子像素的发光器件的发光效率不同，不同颜色子像素对应的像素界定层E的子像素开口E1的形状和尺寸也通常不同，其中，开口尺寸较窄的子像素与开口尺寸较短的子像素产生的衍射现象更加严重，这些衍射现象进一步加重了色分离现象的程度。
需要注意的是，本公开的实施例中，色分离现象指的是，显示基板在息屏状态时，在外界光下(例如点光源、线光源下)，反射光呈现颜色(例如红色、绿色和蓝色)分离的现象。
本公开至少一实施例提供一种显示基板以及显示装置，该显示基板具有阵列排布的多个子像素，且包括衬底基板、设置在衬底基板上的驱动电路层、设置在驱动电路层的远离衬底基板一侧的像素界定层、发光器件层以及设置在发光器件层远离衬底基板一侧的黑矩阵层，多个子像素的每个包括设置在驱动电路层中的像素驱动电路以及设置在发光器件层中的发光器件，像素驱动电路配置为驱动发光器件，像素界定层包括多个子像素开口，发光器件包括在远离衬底基板的方向上依次叠层设置的第一电极层、发光材料层和第二电极层，像素界定层设置在第一电极层的远离衬底基板的一侧，且多个子像素开口分别暴露多个子像素的发光器件的第一电极层，黑矩阵层具有在垂直于衬底基板的板面的方向上分别暴露多个子像素的发光器件的多个第一透光开口，多个第一透光开口中的至少一个具有弧形边缘，在垂直于衬底基板的板面的方向上，至少部分多个子像素开口与多个第一透光开口一一对应且至少部分重叠。
在本公开至少一实施例提供的上述显示基板中，多个第一透光开口中的至少一个具有弧形边缘，该弧形边缘可以减少甚至消除外界光在黑矩阵层的第一透光开口边缘出现衍射而使显示基板出现色分离的现象，进而提高显示基板的显示效果。
下面，通过几个具体的实施例来详细介绍本公开实施例提供的显示基板以及显示装置。
图3示出了本公开至少一实施例提供的显示基板的截面示意图，如图3所示，该显示基板具有阵列排布的多个子像素，图3中示出一个子像素作为示例，该显示基板包括衬底基板101、设置在衬底基板101上的驱动电路层102、设置在驱动电路层102的远离衬底基板101一侧的发光器件层以及设置在发光器件层远离衬底基板101一侧的黑矩阵层 113。
如图3所示，每个子像素包括设置在驱动电路层102中的像素驱动电路以及设置在发光器件层中的发光器件EM，像素驱动电路配置为驱动发光器件EM。黑矩阵层113具有在垂直于衬底基板101的板面的方向上(即图中的竖直方向上)分别暴露多个子像素的发光器件EM的多个第一透光开口1131，以分别透过多个子像素的发光器件EM发出的光。例如，图4A示出了该第一透光开口1131的平面示意图，即在平行于衬底基板101的板面的方向上的平面示意图，如图4A所示，至少一个第一透光开口1131具有弧形边缘，例如，每个第一透光开口1131均具有弧形边缘。
例如，在一些实施例中，如图4A所示，在平行于衬底基板101的板面的方向上，至少一个第一透光开口1131(例如每个第一透光开口1131)的平面形状基本呈椭圆形(或者称芒果形)、半椭圆形、圆形、半圆形、跑道形(图中示出的情况)或者半跑道形等形状或其变形形状。
需要注意的是，本公开的实施例中，跑道形是指由一个长方形和在该长方形的相对两侧的两个圆弧形成的类似于跑道的形状，该跑道形具有相对平行设置的两条直边以及相对设置的两个圆弧。芒果形可以看做是椭圆形的变形形状，具有相对设置的两个弧形边缘，具体可以参考稍后描述的图6和图7。
例如，如图3所示，每个子像素的像素驱动电路包括至少一个薄膜晶体管TFT和存储电容Cst等结构。薄膜晶体管TFT包括有源层1021、栅极1022、源极1023和漏极1024等。薄膜晶体管TFT的源极1023与发光器件EM的第一电极层104电连接。例如，存储电容Cst包括第一电容电极C1和第二电容电极C2。例如，存储电容Cst的第一电容电极C1与薄膜晶体管TFT的栅极1022同层设置。
例如，像素驱动电路可以形成为2T1C(两个薄膜晶体管一个存储电容)、6T1C(六个薄膜晶体管一个存储电容)等结构，从而包括多个薄膜晶体管，该多个薄膜晶体管具有如图3所示的叠层结构相似或相同的结构，图3中仅示出了与发光器件直接连接的薄膜晶体管，该薄膜晶体管可以是驱动薄膜晶体管，也可以是发光控制薄膜晶体管等。
另外需要注意的是，在本公开的实施例中，“同层设置”为两个功能 层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
此外，如图3所示，显示面板还可以包括设置在衬底基板101上的缓冲层103、设置在有源层1021上的第一栅绝缘层1024、设置在栅极1022和第一电容电极C1上的第二栅绝缘层1025、设置在第二电容电极CE2上的层间绝缘层1026、设置在源极1023和漏极1024上的钝化层1027以及设置在钝化层1027上的平坦化层109等结构。
例如，在一些实施例中，如图3所示，显示基板还可以包括设置在驱动电路层102的远离衬底基板101一侧的像素界定层108，例如，像素界定层108设置在平坦化层109上，像素界定层108包括多个子像素开口1081，发光器件EM包括在远离衬底基板101的方向上依次叠层设置的第一电极层104、发光材料层105和第二电极层106，像素界定层108设置在第一电极层104的远离衬底基板101的一侧，且多个子像素开口1081分别暴露多个子像素的发光器件EM的第一电极层104。在垂直于衬底基板101的板面的方向上，即图中的竖直方向上，多个子像素开口1081与多个第一透光开口1131一一对应且至少部分重叠。由此，发光器件EM发出的光可从第一透光开口1131出射，以实现显示效果。
例如，在一些实施例中，如图4A所示，在平行于衬底基板101的板面的方向上，至少一个子像素开口1081的平面形状基本呈椭圆形(或者称芒果形)、半椭圆形、圆形、半圆形、跑道形(图中示出的情况)或者半跑道形等形状或其变形形状。
例如，在一些实施例中，如图4A所示，在对应的一个子像素开口1081和一个第一透光开口1131中，在平行于衬底基板101的板面的方向上，子像素开口1081的平面形状与第一透光开口1131的平面形状相同，图中示出为均为跑道形。
例如，在一些实施例中，如图4A所示，子像素开口1081在衬底基板101上的正投影位于第一透光开口1131在衬底基板101上的正投影内；也即，子像素开口1081的平面尺寸小于第一透光开口1131的平面尺寸。
由于在子像素开口1081限定的范围内，发光材料层105与第一电极层104接触，发光材料层105可以被第一电极层104和第二电极层106共同驱动而发光，由此，子像素开口1081限定的区域为该子像素的有效发光区域。通过将子像素开口1081的平面形状设计为与第一透光开口1131的平面形状基本相同，且子像素开口1081的平面尺寸小于第一透光开口1131的平面尺寸，使得该子像素的有效发光区域充分被第一透光开口1131暴露，该子像素的发光器件发出的光可充分从第一透光开口1131出射，由此显示基板可以充分利用子像素的发光器件发出的光进行显示，提高显示基板的出光率，节约能耗。
例如，在一些实施例中，如图4A所示，子像素开口1081在衬底基板101上的正投影的边缘与第一透光开口1131在衬底基板101上的正投影的边缘的最小距离D1为1μm-3μm，例如为1.5μm、2μm或者2.5μm等，也即子像素开口1081相对于第一透光开口1131内缩1μm-3μm，以使得子像素开口1081限定的有效发光区域充分被第一透光开口1131暴露。
例如，在一些实施例中，如图3和图4A所示，第一电极层104包括主体部1041和连接部1042，连接部1042配置为与像素驱动电路电连接，主体部1041的至少部分被子像素开口1081暴露。例如，在平行于衬底基板101的板面的方向上，主体部1041的平面形状与子像素开口1081的平面形状相同。
例如，在一些实施例中，如图4A所示，子像素开口1081在衬底基板101上的正投影位于主体部1041在衬底基板101上的正投影内。由此，被子像素开口1081暴露的主体部1041的形状和尺寸等于子像素开口1081的形状和尺寸，因此在制备过程中，可以通过设计子像素开口1081的尺寸获得每个子像素的有效发光面积，另外，尺寸较大的主体部1041还为制备过程中子像素开口1081可能产生的位置偏差留出余量。
例如，在一些实施例中，如图4A所示，子像素开口1081在衬底基板101上的正投影的边缘与主体部1041在衬底基板101上的正投影的边缘的最小距离D2为1μm-5μm，例如2.5μm、3μm或者3.5μm等，也即子像素开口1081相对于主体部1041内缩1μm-5μm。
例如，在一些实施例中，如图4A所示，与子像素开口1081对应设置的第一透光开口1131在衬底基板101上的正投影位于主体部1041在衬底基板101上的正投影内，也即在平行于衬底基板101的板面的方向上，主体部1041、第一透光开口1131以及子像素开口1081的平面尺寸逐渐减小。该设计有利于提高显示基板的制备良率、提高显示基板的出光率以及减弱甚至消除显示基板出现色分离的现象。
例如，在另一些实施例中，如图4B所示，主体部1041在衬底基板101上的正投影位于与子像素开口1081对应设置的第一透光开口1131在衬底基板101上的正投影内。此时，第一透光开口1131与主体部1041的形状基本相同，第一透光开口1131相对于主体部1041外扩，该方案也可以提高显示基板的出光率以及减弱甚至消除显示基板出现色分离的现象。
例如，在一些实施例中，如图3所示，显示基板还可以包括设置在像素界定层108上的隔垫物107以及设置在子像素的发光器件EM上的封装层EN等结构，例如，封装层EN可以包括多个子封装层，以提高其封装效果。例如，封装层EN可以为复合封装层，包括第一无机封装层110、第二有机封装层111和第三无机封装层112。例如，第一无机封装层110和第二无机封装层112可以采用氮化硅、氧化硅、氮氧化硅等无机材料形成，第一有机封装层111可以采用聚酰亚胺(PI)、环氧树脂等有机材料形成。该复合封装层可以显示面板上的功能结构形成多重保护，具有更好的封装效果。
例如，在另一些实施例中，如图5所示，显示基板还可以包括连接电极1043，子像素的发光器件EM的第一电极层104通过该连接电极1043与薄膜晶体管TFT的源极1023电连接。例如，连接电极1043上还形成有另一平坦化层1091，此时，像素界定层108设置在该平坦化层1091上。对于图5所示的显示基板，其他结构可以参考图3和图4A所示的显示基板的描述，在此不再赘述。
例如，本公开的实施例中，衬底基板101可以包括聚酰亚胺(PI)等柔性绝缘材料或者玻璃基板等刚性绝缘材料。例如，在一些示例中，衬底基板101可以为多个柔性层和多个阻挡层交替设置的叠层结构。此时，柔性层可以包括聚酰亚胺，阻挡层可以包括氧化硅、氮化硅或者氮 氧化硅等无机绝缘材料。例如，缓冲层103可以包括氮化硅、氧化硅、氮氧化硅等无机材料。有源层1021可以采用多晶硅和金属氧化物等材料，第一栅绝缘层1024和第二栅绝缘层1025可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，栅极1022和第一电容电极C1可以采用铜、铝、钛、钴等金属材料，例如可以形成为单层结构或者多层结构，例如钛/铝/钛、钼/铝/钼等多层结构，第二电容电极C2可以采用铜、铝、钛、钴等金属或者合金材料，层间绝缘层1026可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，钝化层1027可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，例如，在一些实施例中，显示基板也可以没有如图3和图5所示的钝化层。源漏电极1023和1024可以采用铜、铝、钛、钴等金属材料，例如可以形成为单层结构或者多层结构，例如钛/铝/钛、钼/铝/钼等多层结构，第一电极层104例如为阳极层，包括ITO、IZO等金属氧化物或者Ag、Al、Mo等金属或其合金。发光材料层105的材料可以为有机发光材料，例如，发光材料层105的材料可根据需求选择可发出某一颜色光(例如红光、蓝光或者绿光等)的发光材料。第二电极层106例如为阴极层，包括Mg、Ca、Li或Al等金属或其合金，或者IZO、ZTO等金属氧化物，又或者PEDOT/PSS(聚3，4-乙烯二氧噻吩/聚苯乙烯磺酸盐)等具有导电性能有机材料。平坦化层109(以及平坦化层1091)、像素界定层108以及隔垫物107可以采用聚酰亚胺等有机绝缘材料。本公开的实施例对各个功能层的材料不做具体限定。
例如，在一些实施例中，如图3所示，显示基板还可以包括彩膜层114，彩膜层114包括多个彩膜图案1141，多个彩膜图案1141分别设置在多个第一透光开口1131中。由此，子像素的发光器件EM发出的光可透过彩膜图案1141出射，以提高出射光的纯度。
例如，如图3所示，显示基板还可以包括设置在黑矩阵层113和彩膜层114上的保护盖板115，以保护显示基板的结构。例如，保护盖板115可以为玻璃盖板，可通过光学透明胶(图中未示出)结合在显示基板上。
例如，在一些实施例中，如图3所示，黑矩阵层113还可以具有多个第二透光开口1132，多个第二透光开口1132分别设置在多个第一透 光开口1131之间，驱动电路层包括多个透光部分1020；至少部分第二透光开口1132与至少部分多个透光部分1020一一对应设置，配置为可透过与衬底基板101的板面呈预定角度范围的光，例如透过图中示出的光线L。由此，光线L可从显示基板的显示侧(图中的上侧)透过显示基板达到显示基板的非显示侧(图中的下侧)，以供显示基板非显示侧可能设置的感光装置(例如图像传感器等)进行感光操作。
例如，多个透光部分1020包括透光绝缘材料，该透光绝缘材料包括上述第一栅绝缘层1024、第二栅绝缘层1025、层间绝缘层1026、钝化层1027等绝缘层的透光绝缘材料。
例如，在一些实施例中，在对应设置的第二透光开口1132和透光部分1020中，在平行于衬底基板101的板面的方向上，第二透光开口1132的平面尺寸小于透光部分1020的平面尺寸，稍后详细介绍。
例如，在一些实施例中，在对应设置的第二透光开口1132和透光部分1020中，第二透光开口1132在衬底基板101上的正投影与透光部分1020在衬底基板101上的正投影至少部分重叠，稍后详细介绍。
例如，在一些实施例中，如图6所示，显示基板的多个子像素包括红色子像素R、绿色子像素G和蓝色子像素B，像素界定层包括红色子像素开口11、绿色子像素开口12和蓝色子像素开口13，红色子像素R、绿色子像素G和蓝色子像素B的发光器件EM分别形成在像素界定层的红色子像素开口11、绿色子像素开口12和蓝色子像素开口13中。
例如，图7示出了图6中的多个子像素对应的黑矩阵层113的多个第一透光开口1131，如图7所示，暴露红色子像素R的发光器件EM的第一透光开口1131基本呈第一椭圆形11-1(或者叫芒果形，由对称的两个圆弧形成)，暴露绿色子像素G的发光器件的第一透光开口1131基本呈第二椭圆形12-1(或者叫芒果形)，第二椭圆形12-1的长轴的长度L2小于第一椭圆形11-1的长轴的长度L1，第二椭圆形12-1的短轴的长度W2小于第一椭圆形11-1的短轴的长度L1；暴露蓝色子像素B的发光器件的第一透光开口1131基本呈第三椭圆形13-1，第三椭圆形13-1的长轴的长度L3小于第一椭圆形11-1的长轴的长度L1，第三椭圆形13-1的短轴的长度W3大于第一椭圆形的短轴的长度L1。
例如，如图6和图7所示，暴露红色子像素R的发光器件EM的 第一透光开口1131与红色子像素R对应的像素界定层的红色子像素开口11的形状相同，且红色子像素开口11的平面尺寸小于暴露红色子像素R的发光器件EM的第一透光开口1131的平面尺寸；暴露绿色子像素G的发光器件EM的第一透光开口1131与绿色子像素G对应的像素界定层的绿色子像素开口12的形状相同，且绿色子像素开口12的平面尺寸小于暴露绿色子像素G的发光器件EM的第一透光开口1131的平面尺寸；暴露蓝色子像素B的发光器件EM的第一透光开口1131与蓝色子像素B对应的像素界定层的蓝色子像素开口13的形状相同，且蓝色子像素开口13的平面尺寸小于暴露蓝色子像素B的发光器件EM的第一透光开口1131的平面尺寸。
通过对上述呈现椭圆形(或者芒果形)的子像素的显示基板进行Lab色彩空间检测，例如，采用色彩分析仪对处于暗态的显示基板进行检测，得出，Lab值为7.68，而呈现六边形(如图2所示)的子像素的显示基板，Lab值为28.3，Lab值越低，表示显示基板产生色分离的现象越少，可见，本公开实施例提供的显示基板明显减弱了显示基板出现色分离的程度。
例如，在另一些示例中，如图8A和图8B所示，绿色子像素G对应的像素界定层的绿色子像素开口12基本呈半椭圆形，暴露绿色子像素G的发光器件的第一透光开口1311也基本呈半椭圆形12-2，即椭圆形的一半。例如，半椭圆形12-2的长度L21小于第一椭圆形11-1的长轴的长度L1，半椭圆形12-2的宽度W21小于或等于第一椭圆形11-1的短轴的长度W1。例如，该示例的其他子像素的第一透光开口1311和子像素开口与图6和图7相同，这里不再赘述。
例如，在一些示例中，如图6-图8B所示，一个红色子像素R、两个绿色子像素G和一个蓝色子像素B组成一个像素单元，多个子像素组成的多个像素单元在衬底基板101上阵列排布。例如，在另一些实施例中，也可以一个红色子像素R、一个绿色子像素G和一个蓝色子像素B组成一个像素单元，多个子像素组成的多个像素单元在衬底基板101上阵列排布，本公开的实施例对像素单元的具体形式不做限定。
例如，在另一些实施例中，如图9和图10所示，多个子像素包括红色子像素R、绿色子像素G和蓝色子像素B，暴露红色子像素R的 发光器件的第一透光开口1131基本呈第一跑道形21-1，暴露绿色子像素G的发光器件的第一透光开口1131基本呈半跑道形22-1，例如，半跑道形22-1的长度L5小于第一跑道形的长轴的长度L4，半跑道形22-1的宽度W5大于或等于第一跑道形的短轴的长度W4；暴露蓝色子像素B的发光器件的第一透光开口1131基本呈第三跑道形23-1，第三跑道形23-1的长轴的长度L6小于第一跑道形21-1的长轴的长度L4，第三跑道形23-1的短轴的长度W6大于第一跑道形21-1的短轴的长度W4。
通过对上述呈现跑道形(或者半跑道形)的子像素的显示基板进行Lab色彩空间检测，得出，Lab值为5.18，远低于呈现六边形(如图2所示)的子像素的显示基板的Lab值28.3。
例如，在另一些实施例中，如图11A和图11B所示，暴露绿色子像素G的发光器件的第一透光开口1131基本呈第二跑道形22-2，第二跑道形22-2的长轴的长度L7小于第一跑道形21-1的长轴的长度L4，第二跑道形22-2的短轴的长度W7小于或等于第一跑道形21-1的短轴的长度W4。相应地，绿色子像素G对应的像素界定层的绿色子像素开口22也呈第二跑道形。该示例的其他子像素的第一透光开口1311和子像素开口与图9和图10相同，这里不再赘述。
例如，在一些示例中，如图9-图11B所示，一个红色子像素R、两个绿色子像素G和一个蓝色子像素B组成一个像素单元，多个子像素组成的多个像素单元在衬底基板101上阵列排布。例如，在另一些实施例中，也可以一个红色子像素R、一个绿色子像素G和一个蓝色子像素B组成一个像素单元，多个子像素组成的多个像素单元在衬底基板101上阵列排布，本公开的实施例对像素单元的具体形式不做限定。
例如，图12示出了本公开至少一实施例提供的一种显示基板的平面示意图，如图12所示，该示例中，一个红色子像素R、两个绿色子像素G和一个蓝色子像素B组成一个像素单元，且各个子像素对应的黑矩阵层的第一透光开口1131、像素界定层的子像素开口1081以及第一电极层104的主体部1041形状均呈椭圆形(或称芒果形)。
例如，如图7所示，暴露红色子像素的发光器件的第一透光开口1131包括相对的第一弧形边缘RL1和第二弧形边缘RL2以及在第一弧形边缘RL1和第二弧形边缘RL2相交位置的第一尖端RO1和第二尖端 RO2，第一尖端RO1和第二尖端RO2相对，由此构成芒果形。
例如，暴露蓝色子像素的发光器件的第一透光开口1131包括相对的第三弧形边缘BL1和第四弧形边缘BL2以及在第三弧形边缘BL1和第四弧形边缘BL2相交位置第三尖端BO1和第四尖端BO2，第三尖端BO1和第四尖端BO2相对。
例如，暴露绿色子像素的发光器件的第一透光开口1131包括第五弧形边缘GL1以及位于第五弧形边缘GL1一端的第五尖端GO1。
此时，暴露红色子像素的发光器件的第一透光开口和暴露蓝色子像素的发光器件的第一透光开口均具有相对设置的两个尖端，暴露绿色子像素的发光器件的第一透光开口只有一个尖端；该设置可以降低显示基板出现色分离的程度。
需要注意的是，本公开的实施例中，由于实际工艺精度以及工艺误差等原因，所形成的尖端可能并不具有尖角形状，但是尖端的曲率相对于弧形边缘的曲率有变化，例如曲率在尖端处产生突变。
例如，如图6所示，绿色子像素G对应的像素界定层的绿色子像素开口12包括第六弧形边缘GL3以及位于第六弧形边缘GL3一端的第六尖端GO3，如图12所示，绿色子像素的发光器件的第一电极层的主体部包括第七弧形边缘GL4，第七弧形边缘GL4不包括尖端。该设置可以降低显示基板在绿色子像素处出现色分离的程度。
例如，如图12所示，黑矩阵层包括多个第二透光开口1132，驱动电路层包括多个透光部分1020，一个第二透光开口1132对应一个透光部分1020，且在对应设置的第二透光开口1132和透光部分1020中，在平行于衬底基板101的板面的方向上，第二透光开口1132的平面尺寸小于透光部分1020的平面尺寸。例如，在一些示例中，在对应设置的第二透光开口1132和透光部分1020中，第二透光开口1132在衬底基板101上的正投影与透光部分1020在衬底基板101上的正投影至少部分重叠，例如，第二透光开口1132在衬底基板101上的正投影位于透光部分1020在衬底基板101上的正投影内部。由此，如图3和图5所示，光线L可从显示基板的显示侧(图中的上侧)依次通过第二透光开口1132和透光部分1020达到显示基板的非显示侧(图中的下侧)，以供显示基板非显示侧可能设置的感光装置(例如图像传感器等)进行 感光操作。
例如，在一些实施例中，如图12所示，驱动电路层102包括相互平行设置且周期排布的第一信号线S1和第二信号线S2，第一信号线S1和第二信号线S2配置为向多个子像素SP提供不同的电信号。例如，多个第二透光开口1132在衬底基板101上的正投影分别位于一条第一信号线S1在衬底基板101上的正投影和与该一条第一信号线S1距离最近的一条第二信号线S2在衬底基板101上的正投影之间。
例如，在一些实施例中，第一信号线S1为发光控制信号线EMT，第二信号线为复位电压线VNT，稍后详述。
需要说明的是，考虑到实际生产中存在的工艺误差以及结构误差等，形成的信号线可能并非直线，例如具有凹凸不平的部分等，在本公开的实施例中，第一信号线S1和第二信号线S2“相互平行”可以指第一信号线S1和第二信号线S2的延伸方向之间形成的角度在15度范围内，而不一定是严格意义上的平行。
例如，如图12所示，驱动电路层还可以包括相互平行设置且周期排布的第三信号线S3和第四信号线S4，第三信号线S3和第四信号线S4分别与第一信号线S1和第二信号线S2相交，例如垂直，第三信号线S3和第四信号线S4配置为向多个子像素提供不同的电信号，多个第二透光开口1032在衬底基板101上的正投影分别位于一条第三信号线S3在衬底基板101上的正投影和与该第三信号线相邻的一条第四信号线S4在衬底基板101上的正投影之间。
例如，在一些实施例中，第三信号线S3为第一电源线VDD1，第四信号线S4为数据线DT，稍后详述。
例如，如图12所示，第一信号线S1、第二信号线S2、第三信号线S3和第四信号线S4限定了多个第一区域RG，即图中虚线框圈出的区域，多个第二透光开口1032在衬底基板101上的正投影分别位于多个第一区域RG在衬底基板101上的正投影内。
例如，图13示出了显示基板的黑矩阵层和彩膜层的部分平面示意图，并示出了多个第一透光开口1131、多个第二透光开口1132以及多个彩膜图案1141的平面示意图。如图13所示，在垂直于衬底基板101的板面的方向上，多个彩膜图案1141包括与第一子像素(例如红色子 像素)的发光器件至少部分重叠的第一彩膜图案1141A以及与第二子像素(例如绿色子像素)的发光器件至少部分重叠的第二彩膜图案1141B。在平行于衬底基板101的板面的方向上，第一彩膜图案1141A的平面形状不同于第二彩膜图案1141B的平面形状，且第一彩膜图案1141A的面积大于第二彩膜图案1141B的面积。
例如，如图13所示，第一彩膜图案1141A的平面形状基本呈矩形，例如为具有缺口的矩形，第二彩膜图案1141B的平面形状基本呈半椭圆形。例如，第一彩膜图案1141A和第二彩膜图案1141B的面积分别大于其覆盖的第一透光开口1131的面积，以充分实现滤光作用。
例如，在一些示例中，第一彩膜图案1141A的面积与第二彩膜图案1141B的面积的比值范围为(1～1.5):1，例如1.2:1或者1.4:1等。
例如，如图13所示，在垂直于衬底基板101的板面的方向上，多个彩膜图案1141还包括与第三子像素(例如蓝色子像素)的发光器件至少部分重叠的第三彩膜图案1141C。在平行于衬底基板101的板面的方向上，第三彩膜图案1141C的平面形状与第一彩膜图案1141A和第二彩膜图案1141B的平面形状不同，第三彩膜图案1141C的面积大于第一彩膜图案1141A的面积以及第二彩膜图案1141B的面积。例如，第三彩膜图案1141C的平面形状为异形，以充分实现滤光作用。
例如，在一些实施例中，第一彩膜图案1141A的面积、第二彩膜图案1141B的面积以及第三彩膜图案1141C的面积的比值范围为(1～1.5):1:(1～1.6)，例如1.2:1：1.1或者1.4:1:1.3等。
例如，如图13所示，在垂直于衬底基板101的板面的方向上，多个彩膜图案1141还包括与第四子像素(例如绿色子像素)的发光器件至少部分重叠的第四彩膜图案1141D。在平行于衬底基板101的板面的方向上，第四彩膜图案1141D的平面形状与第二彩膜图案1141B的平面形状基本相同，第四彩膜图案1141D的面积基本等于第二彩膜图案1141D的面积。
例如，第四彩膜图案1141D的平面形状基本呈半椭圆形，且其面积基本等于第二彩膜图案1141D的面积，例如第四彩膜图案1141D的面积与第二彩膜图案1141D的面积的差异不大于第二彩膜图案1141D的面积的10％。
本公开的实施例中，黑矩阵层113可以对射入显示基板的光线进行吸收，降低显示基板对外界光的反射率，提升显示基板的显示效果；通过在黑矩阵层113上覆盖彩膜层114，彩膜层114可以对射入显示基板的光线进行二次吸收，以进一步降低显示基板对外界光的反射率，提升显示基板的显示效果。经过对图13所示的多个彩膜图案1141进行测试，得出该多个彩膜图案1141具有如图13所示的形状与大小分布时，多个彩膜图案1141可以充分实现滤光作用以及光反射作用，使得显示基板的显示效果更好。
例如，在一些实施例中，如图13所示，在垂直于衬底基板101的板面的方向上，第四彩膜图案1141D与第四透光子开口1132D部分重叠。
例如，在一些示例中，如图13所示，第一子像素P1对应的第一彩膜图案1141A的横向尺寸1141A～1为27μm～33μm，例如28μm、29μm或者30μm等，纵向尺寸1141A～2为30μm～35μm，例如32μm、33μm或者34μm等；第二子像素P2对应的第二彩膜图案1141B的横向尺寸1141B～1为20μm～25μm，例如21μm、22μm或者23μm等，纵向尺寸1141B～2为23μm～28μm，例如25μm、26μm或者27μm等；第三子像素P3对应的第三彩膜图案1141C的横向尺寸1141C～1为32μm～38μm，例如34μm、35μm或者36μm等，纵向尺寸1141C～2为35μm～45μm，例如38μm、40μm或者42μm等；第四子像素P4对应的第四彩膜图案1141D的横向尺寸1141D～1为20μm～25μm，例如21μm、22μm或者23μm等，纵向尺寸1141D～2为23μm～28μm，例如25μm、26μm或者27μm等。
例如，在一些实施例中，多个彩膜图案1141的边缘与多个第二透光开口1132的边缘的最小距离为1μm-5μm。例如，如图13所示，对于至少部分相邻的彩膜图案1141与第二透光开口1132，彩膜图案1141与第二透光开口1132之间具有间隔，且彩膜图案1141的边缘与第二透光开口1132的边缘的最小距离为1μm-5μm，以避免彩膜图案1141过滤通过第二透光开口1132的光。
例如，结合图13和图8A等，对于与同一子像素对应的一个彩膜图案1141和一个子像素开口1081，彩膜图案1141的平面形状与子像素开口1081的平面形状不相同。例如，多个第二透光开口1132的至少部分边缘与其相 邻的彩膜图案1141的边缘的至少部分平行。例如，在图13中虚线框示出的部分，第二透光开口1132的部分边缘与其相邻的彩膜图案1141的部分边缘平行。
下面，通过一个具体的示例来详细介绍本公开实施例提供的显示基板的各个功能层的结构以及电路排布。该示例中，子像素采用7T1C像素驱动电路驱动发光器件EM。
例如，图14A示出了一种7T1C像素电路的电路图。如图14A所示，该像素电路包括驱动电路122、数据写入电路126、补偿电路128、存储电路127、第一发光控制电路123、第二发光控制电路124及复位电路129。
例如，驱动电路122包括控制端131、第一端132和第二端133，其配置为控制流经发光器件EM的驱动电流，且驱动电路122的控制端131和第一节点N1连接，驱动电路122的第一端132和第二节点N2连接，驱动电路122的第二端133和第三节点N3连接。
例如，数据写入电路126包括控制端、第一端和第二端，其控制端配置为接收第一扫描信号，第一端配置为接收数据信号，第二端与驱动电路122的第一端132(第二节点N2)连接，且配置为响应于该第一扫描信号Ga1将该数据信号写入驱动电路122的第一端132。例如，数据写入电路126的第一端与数据线12连接以接收该数据信号，控制端与扫描线11连接以接收该第一扫描信号Ga1。
例如，在数据写入阶段，数据写入电路126可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动电路122的第一端132(第二节点N2)，并将数据信号存储在存储电路127中，以在例如发光阶段时可以根据该数据信号生成驱动发光器件EM发光的驱动电流。
例如，补偿电路128包括控制端、第一端和第二端，其控制端配置为接收第二扫描信号Ga2，其第一端和第二端分别与驱动电路122的控制端131和第二端133电连接，该补偿电路配置为响应于该第二扫描信号对该驱动电路120进行阈值补偿。
例如，存储电路127与驱动电路122的控制端131及第一电压端VDD电连接，配置为存储数据写入电路126写入的数据信号。例如，在数据写入和补偿阶段，补偿电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入电路126写入的数据信号存储在该存储电路127中。例如，同 时在数据写入和补偿阶段，补偿电路128可以将驱动电路122的控制端131和第二端133电连接，从而可以使驱动电路122的阈值电压的相关信息也相应地存储在该存储电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动电路122进行控制，使得驱动电路122的输出得到补偿。
例如，第一发光控制电路123与驱动电路122的第一端132(第二节点N2)以及第一电压端VDD连接，且配置为响应于第一发光控制信号将第一电压端VDD的第一电源电压施加至驱动电路122的第一端132。例如，如图14A所示，第一发光控制电路123和第一发光控制端EM1、第一电压端VDD以及第二节点N2连接。
例如，第二发光控制电路124和第二发光控制端EM2、发光器件EM的第一端510以及驱动电路122的第二端132连接，且配置为响应于第二发光控制信号使得驱动电流可被施加至发光器件EM。
例如，在发光阶段，第二发光控制电路123响应于第二发光控制端EM2提供的第二发光控制信号而开启，从而驱动电路122可以通过第二发光控制电路123将驱动电流施加至发光器件EM以使其发光；而在非发光阶段，第二发光控制电路123响应于第二发光控制信号而截止，从而避免有电流流过发光器件EM而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制电路124也可以响应于第二发光控制信号而开启，从而可以结合复位电路以对驱动电路122以及发光器件EM进行复位操作。
例如，第二发光控制信号EM2可以与第一发光控制信号EM1相同或不同，例如二者可以连接到相同或不同的信号输出端。
例如，复位电路129与复位电压端Vinit以及发光器件EM的第一端134(第四节点N4)连接，且配置为响应于复位信号将复位电压施加至发光器件EM的第一端134。在另一些示例中，如图14A所示，该复位信号还可以施加至驱动电路的控制端131，也即第一节点N1。例如，复位信号为该第二扫描信号，复位信号还可以是和第二扫描信号同步的其他信号，本公开的实施例对此不作限制。例如，如图14A所示，该复位电路129分别和发光器件EM的第一端134、复位电压端Vinit以及复位控制端Rst(复位控制线)连接。例如，在初始化阶段，复位电路129可以响应于复位信号而开启，从而可以将复位电压施加至发光器件EM的第一端134及第一节点N1，从而 可以对驱动电路122、补偿电路128以及发光器件EM进行复位操作，消除之前的发光阶段的影响。
例如，发光器件EM包括第一端134和第二端135，发光器件EM的第一端134配置为从驱动电路122的第二端133接收驱动电流，发光器件EM的第二端135配置为与第二电压端VSS连接。例如，在一个示例中，如图14A所示，发光器件EM的第一端134可以通过第二发光电路124连接至第三节点N3。本公开的实施例包括但不限于此情形。例如，发光器件EM可以为各种类型的OLED，例如顶发射、底发射、双侧发射等，可以发红光、绿光、蓝光或白光等，该OLED的第一电极层和第二电极层分别作为该发光器件的第一端134和第二端135。本公开的实施例对发光器件的具体结构不作限制。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符合Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，Rst既可以表示复位控制端又可以表示复位信号，符号Vinit既可以表示复位电压端又可以表示复位电压，符号VDD既可以表示第一电压端又可以表示第一电源电压，符号VSS既可以表示第二电压端又可以表示第二电源电压。以下各实施例与此相同，不再赘述。
图14B为图14A所示的像素电路的一种具体实现示例的电路图。如图14B所示，该像素电路包括：第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容Cst。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第七晶体管被用作开关晶体管。
例如，如图14B所示，驱动电路122可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动电路122的控制端131，和第一节点N1连接；第一晶体管T1的第一极作为驱动电路122的第一端132，和第二节点N2连接；第一晶体管T1的第二极作为驱动电路122的第二端133，和第三节点N3连接。
例如，如图14B所示，数据写入电路126可以实现为第二晶体管T2。 第二晶体管T2的栅极和第一扫描线(第一扫描信号端Ga1)连接以接收第一扫描信号，第二晶体管T2的第一极和数据线(数据信号端Vd)连接以接收数据信号，第二晶体管T2的第二极和驱动电路122的第一端132(第二节点N2)连接。例如，该第二晶体管T2为P型晶体管，例如有源层为低温掺杂多晶硅的薄膜晶体管。
例如，如图14B所示，补偿电路128可以实现为第三晶体管T3。第三晶体管T3的栅极配置为和第二扫描线(第二扫描信号端Ga2)连接以接收第二扫描信号，第三晶体管T3的第一极和驱动电路122的控制端131(第一节点N1)连接，第三晶体管T3的第二极和驱动电路122的第二端133(第三节点N3)连接。
例如，如图14B所示，存储电路127可以实现为存储电容Cst，该存储电容Cst包括第一电容电极C1和第二电容电极C2，该第一电容电极C1和第一电压端VDD连接，该第二电容电极C2和驱动电路122的控制端131连接。
例如，如图14B所示，第一发光控制电路123可以实现为第四晶体管T4。第四晶体管T4的栅极和第一发光控制线(第一发光控制端EM1)连接以接收第一发光控制信号，第四晶体管T4的第一极和第一电压端VDD连接以接收第一电源电压，第四晶体管T4的第二极和驱动电路122的第一端132(第二节点N2)连接。
例如，发光器件EM可以具体实现为发光二极管(OLED)，其的第一电极层(这里为阳极)和第四节点N4连接配置为通过第二发光控制电路124从驱动电路122的第二端133接收驱动电流，发光器件EM的第二电极层(这里为阴极)配置为和第二电压端VSS连接以接收第二电源电压。例如第二电压端可以接地，即VSS可以为0V。
例如，第二发光控制电路124可以实现为第五晶体管T5。第五晶体管T5的栅极和第二发光控制线(第二发光控制端EM2)连接以接收第二发光控制信号，第五晶体管T5的第一极和驱动电路122的第二端133(第三节点N3)连接，第五晶体管T5的第二极和发光器件EM的第一端134(第四节点N4)连接。
例如，复位电路129可以包括第一复位电路和第二复位电路，该第一复位电路配置为响应于第一复位信号Rst1将第一复位电压Vini1施加到第一节 点N1，该第二复位电路配置为响应于第二复位信号Rst2将第二复位电压Vini2施加到第四节点N4。例如，如图14B所示，该第一复位电路实现为第六晶体管T6，该第二复位电路实现为第七晶体管T7。第六晶体管T6的栅极配置为和第一复位控制端Rst1连接以接收第一复位信号Rst1，第六晶体管T6的第一极和第一复位电压端Vinit1连接以接收第一复位电压Vinit1，第六晶体管T6的第二极配置为和第一节点N1连接。第七晶体管T7的栅极配置为和第二复位控制端Rst2连接以接收第二复位信号Rst2，第七晶体管T7的第一极和第二复位电压端Vinit2连接以接收第二复位电压Vinit2，第七晶体管T7的第二极配置为和第四节点N4连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
例如，结合图12，第一信号线S1为发光控制线EMT，用于传输上述第一发光控制信号EM1和第二发光控制信号EM2；第二信号线S2为复位电压线VNT，用于传输上述第一复位电压Vinit1和第二复位电压Vini2。例如，复位电压线VNT的远离发光控制线EMT的一侧还具有复位控制线RST，用于传输上述第一复位信号Rst1和第二复位信号Rst2。
下面详细介绍上述像素驱动电路的版图设计。
例如，图15示出了该显示基板的半导体层的示意图，该半导体层用于形成多个子像素的像素驱动电路的薄膜晶体管T1～T7的有源层，图12中示出两行子像素的像素驱动电路，下面以直接相邻的四个子像素(即第一子像素100a、第二子像素100b、第三子像素100c和第四子像素100d)的像素驱动电路为例进行介绍，图中的虚线框示出了各个子像素的像素驱动电路所在的区域，本公开的实施例不限于此布局。
例如，半导体层上还设置有第一栅绝缘层，图中未示出，可参考图3或图5中的第一栅绝缘层1024。
例如，图16A示出了显示基板的第一栅金属层的示意图，第一栅金属层设置第一栅绝缘层上，图16B示出了显示基板的第一栅金属层与半导体层叠 层的示意图。
例如，如图16A和图16B所示，第一栅金属层包括多条发光控制线EMT、多条复位控制线RST、多条扫描线GATE以及多个存储电容Cst的第一电容电极C1，例如，发光控制线EMT、复位控制线RST、扫描线GATE以及存储电容Cst的第一电容电极C1与薄膜晶体管T1～T7的有源层交叠的部分构成薄膜晶体管T1～T7的栅极。多条发光控制线EMT、多条复位控制线RST、多条扫描线GATE分别与多行子像素一一对应电连接以提供相应的电信号。
例如，第一栅金属层上还设置有第二栅绝缘层，图中未示出，可参考图3和图5中的第二栅绝缘层1025。
图17A示出了显示基板的第二栅金属层的示意图，第二栅金属层设置在第二栅绝缘层上，图17B示出了显示基板的第二栅金属层与第一栅金属层和半导体层叠层的示意图。
例如，如图17A和图17B所示，该第二栅金属层包括存储电容Cst的第二电容电极C2以及多条复位电压线VNT。存储电容Cst的第二电容电极C2与第一电容电极C1至少部分交叠，以形成电容。多条复位电压线VNT与多行子像素一一对应电连接以提供相应的电信号。
例如，第二栅金属层上还设置有层间绝缘层，图中未示出，可参考图3和图5中的层间绝缘层1026。
图18A示出了显示基板的第一源漏金属层的示意图，第一源漏金属层设置在层间绝缘层上，图18B示出了显示基板的第一源漏金属层与第二栅金属层、第一栅金属层和半导体层叠层的示意图。
如图18A和图18B所示，第一源漏金属层包括多条第一电源线VDD1。例如，该多条第一电源线VDD1分别与多列子像素一一对应电连接以提供第一电源电压。例如，第一源漏金属层还包括该多条数据线DT。该多条数据线DT与多列子像素一一对应电连接以提供数据信号。例如，第一源漏金属层还包括多个连接电极CL，用于连接第二电容电极C2与第三晶体管T3的第一极，或者连接第六晶体管T6的第一极与复位电压线VNT，或者连接第五晶体管T5的第二极与发光器件的第一电极层等。
例如，第一源漏金属层上还设置有钝化层和平坦化层，图中未示出，可参考图3和图5中的钝化层1027和平坦化层1091。
图19A示出了显示基板的第二源漏金属层的示意图，第二源漏金属层设 置在平坦化层1091上，图19B示出了显示基板的第二源漏金属层与第一源漏金属层、第二栅金属层、第一栅金属层和半导体层叠层的示意图。
如图19A和图19B所示，第二源漏金属层包括第二电源线VDD2，第二电源线VDD2呈网格状，例如，第二电源线VDD2与第一电源线VDD1电连接，以有助于降低电源线上的电阻从而降低电源线的压降，并有助于将第一电源电压均匀地输送至显示基板的各个子像素中。例如，第二源漏金属层还可以包括连接电极1043，用于连接发光器件的第一电极层以及第一晶体管T1的第一极。例如，在垂直于衬底基板的板面的方向上，第二电源线VDD2与第一电极层104的主体部1042至少部分重叠。
例如，第二源漏金属层上还设置有另一平坦化层，即平坦化层109，图20示出了该平坦化层的平面示意图，且结合图3和图5，平坦化层109中具有多个过孔VA。此时，第一电极层104通过平坦化层109中的过孔VA与连接电极1043连接。
例如，位于同一行的多个子像素对应的平坦化层109的多个过孔VA不在一条直线上。例如，如图20所示，位于同一行的相邻的一个第一子像素(例如红色子像素)、一个第二子像素(例如绿色子像素)、一个第三子像素(例如蓝色子像素)和一个第四子像素(例如绿色子像素)分别对应过孔VA1～VA4，过孔VA1～VA4不在同一直线上。
通过将平坦化层109的多个过孔VA设计为不在一条直线上，可以将像素驱动电路的走线避让开一个较大的透光区，形成足够面积的透光部分。
图21A示出了显示基板的第一电极材料层的示意图，第一电极材料层设置在钝化层109上，图21B示出了显示基板的第一电极材料层与第二源漏金属层、第一源漏金属层、第二栅金属层、第一栅金属层和半导体层叠层的示意图。
如图21A和图21B所示，第一电极材料层包括多个子像素的发光器件EM的第一电极层，多个子像素的发光器件EM的第一电极层分别通过平坦化层109中的多个过孔VA与连接电极1043连接。例如，该第一电极层上设置有发光器件EM的发光材料层，发光材料层上设置有第二电极层。
例如，发光器件EM上方还形成有封装层、黑矩阵层、保护盖板115等其他功能层，在此不再赘述。
本公开至少一实施例还提供一种显示装置，图22示出了该显示装 置的截面示意图，如图22所示，该显示装置包括本公开实施例提供的显示基板，图22中示出图3所示的显示基板作为示例。
例如，如图22所示，该显示装置还包括纹路触摸表面S以及图像传感器阵列30，例如，保护盖板115的表面实现为纹路触摸表面S。图像传感器阵列设置在驱动电路层102的远离发光器件层的一侧，包括多个图像传感器31(图中示出一个作为示例)，多个图像传感器31配置为可接收从发光器件层中的多个发光器件EM发出的且经在纹路触摸表面S的纹路(例如指纹、掌纹等)反射至多个图像传感器31的光以用于纹路采集。
例如，参考图12，黑矩阵层包括多个第二透光开口1132，驱动电路层包括多个透光部分1020，一个第二透光开口1132对应一个透光部分1020，此时，多个图像传感器31配置为可接收从发光器件层中的多个发光器件EM发出的且经在纹路触摸表面S的纹路反射，并通过黑矩阵层113的多个第二透光开口1132以及驱动电路层的多个透光部分1020到达多个图像传感器31的光以用于纹路采集。由此，通过多个第二透光开口1132以及多个透光部分1020，多个图像传感器31可充分接收被纹路反射的光，从而可提高纹路识别速度以及纹路识别精度。
本公开实施例提供的显示装置还可以具有其他结构，具体可以参考相关技术，在此不再赘述。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (22)

  1. 一种显示基板，具有阵列排布的多个子像素，且包括衬底基板、设置在所述衬底基板上的驱动电路层、设置在所述驱动电路层的远离所述衬底基板一侧的像素界定层、发光器件层以及设置在所述发光器件层远离所述衬底基板一侧的黑矩阵层，
    其中，所述多个子像素的每个包括设置在所述驱动电路层中的像素驱动电路以及设置在所述发光器件层中的发光器件，所述像素驱动电路配置为驱动所述发光器件，
    所述像素界定层包括多个子像素开口，所述发光器件包括在远离所述衬底基板的方向上依次叠层设置的第一电极层、发光材料层和第二电极层，所述像素界定层设置在所述第一电极层的远离所述衬底基板的一侧，且所述多个子像素开口分别暴露所述多个子像素的发光器件的第一电极层，
    所述黑矩阵层具有在垂直于所述衬底基板的板面的方向上分别暴露所述多个子像素的发光器件的多个第一透光开口，所述多个第一透光开口中的至少一个具有弧形边缘，
    在垂直于所述衬底基板的板面的方向上，至少部分所述多个子像素开口与多个第一透光开口一一对应且至少部分重叠。
  2. 根据权利要求1所述的显示基板，其中，在平行于所述衬底基板的板面的方向上，所述多个第一透光开口中的至少一个的平面形状呈椭圆形、半椭圆形、圆形、半圆形、跑道形或者半跑道形。
  3. 根据权利要求1所述的显示基板，其中，在平行于所述衬底基板的板面的方向上，所述多个子像素开口中的至少一个的平面形状呈椭圆形、半椭圆形、圆形、半圆形、跑道形或者半跑道形。
  4. 根据权利要求1-3任一所述的显示基板，其中，在对应的一个子像素开口和一个第一透光开口中，在平行于所述衬底基板的板面的方向上，所述子像素开口的平面形状与所述第一透光开口的平面形状相同。
  5. 根据权利要求4所述的显示基板，其中，所述子像素开口在所述衬底基板上的正投影位于所述第一透光开口在所述衬底基板上的正投影内。
  6. 根据权利要求5所述的显示基板，其中，所述子像素开口在所述 衬底基板上的正投影的边缘与所述第一透光开口在所述衬底基板上的正投影的边缘的最小距离为1μm-3μm。
  7. 根据权利要求1-3任一所述的显示基板，其中，所述第一电极层包括主体部和连接部，所述连接部配置为与所述像素驱动电路电连接，所述主体部的至少部分被所述子像素开口暴露；
    在平行于所述衬底基板的板面的方向上，所述主体部的平面形状与所述子像素开口的平面形状至少部分相同。
  8. 根据权利要求7所述的显示基板，其中，所述子像素开口在所述衬底基板上的正投影位于所述主体部在所述衬底基板上的正投影内。
  9. 根据权利要求8所述的显示基板，其中，所述子像素开口在所述衬底基板上的正投影的边缘与所述主体部在所述衬底基板上的正投影的边缘的最小距离为1μm-5μm。
  10. 根据权利要求9所述的显示基板，其中，与所述子像素开口对应设置的第一透光开口在所述衬底基板上的正投影位于所述主体部在所述衬底基板上的正投影内。
  11. 根据权利要求9所述的显示基板，其中，所述主体部在所述衬底基板上的正投影位于与所述子像素开口对应设置的第一透光开口在所述衬底基板上的正投影内。
  12. 根据权利要求1-3任一所述的显示基板，还包括彩膜层，所述彩膜层包括多个彩膜图案，所述多个彩膜图案分别设置在所述多个第一透光开口中。
  13. 根据权利要求1-3任一所述的显示基板，其中，所述黑矩阵层还具有多个第二透光开口，所述多个第二透光开口分别设置在所述多个第一透光开口之间，所述驱动电路层包括多个透光部分；
    至少部分所述多个第二透光开口与至少部分所述多个透光部分一一对应设置，配置为可透过与所述衬底基板的板面呈预定角度范围的光。
  14. 根据权利要求13所述的显示基板，其中，在对应设置的第二透光开口和透光部分中，在平行于所述衬底基板的板面的方向上，所述第二透光开口的平面尺寸小于所述透光部分的平面尺寸。
  15. 根据权利要求14所述的显示基板，其中，在对应设置的第二透 光开口和透光部分中，所述第二透光开口在所述衬底基板上的正投影与所述透光部分在所述衬底基板上的正投影至少部分重叠。
  16. 根据权利要求1-3任一所述的显示基板，其中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，
    暴露所述红色子像素的发光器件的第一透光开口基本呈第一椭圆形，
    暴露所述绿色子像素的发光器件的第一透光开口基本呈第二椭圆形，所述第二椭圆形的长轴的长度小于所述第一椭圆形的长轴的长度，所述第二椭圆形的短轴的长度小于所述第一椭圆形的短轴的长度；或者，暴露所述绿色子像素的发光器件的第一透光开口基本呈半椭圆形，以及
    暴露所述蓝色子像素的发光器件的第一透光开口基本呈第三椭圆形，所述第三椭圆形的长轴的长度小于所述第一椭圆形的长轴的长度，所述第三椭圆形的短轴的长度大于所述第一椭圆形的短轴的长度。
  17. 根据权利要求16所述的显示基板，其中，暴露所述红色子像素的发光器件的第一透光开口包括相对的第一弧形边缘和第二弧形边缘以及在所述第一弧形边缘和所述第二弧形边缘相交位置的第一尖端和第二尖端，所述第一尖端和所述第二尖端相对；
    暴露所述蓝色子像素的发光器件的第一透光开口包括相对的第三弧形边缘和第四弧形边缘以及在所述第三弧形边缘和所述第四弧形边缘相交位置第三尖端和第四尖端，所述第三尖端和所述第四尖端相对；以及
    暴露所述绿色子像素的发光器件的第一透光开口包括第五弧形边缘以及位于所述第五弧形边缘一端的第五尖端。
  18. 根据权利要求17所述的显示基板，其中，所述绿色子像素对应的子像素开口包括第六弧形边缘以及位于所述第六弧形边缘一端的第六尖端，
    所述绿色子像素的发光器件的第一电极层的主体部包括第七弧形边缘，所述第七弧形边缘不包括尖端。
  19. 根据权利要求1-3任一所述的显示基板，其中，所述多个子像素包括红色子像素、绿色子像素和蓝色子像素，
    暴露所述红色子像素的发光器件的第一透光开口基本呈第一跑道形，
    暴露所述绿色子像素的发光器件的第一透光开口基本呈第二跑道形，所述第二跑道形的长轴的长度小于所述第一跑道形的长轴的长度，所述第二跑道形的短轴的长度小于所述第一跑道形的短轴的长度；或者，暴露所述绿色子像素的发光器件的第一透光开口基本呈半跑道形，以及
    暴露所述蓝色子像素的发光器件的第一透光开口基本呈第三跑道形，所述第三跑道形的长轴的长度小于所述第一跑道形的长轴的长度，所述第三跑道形的短轴的长度大于所述第一跑道形的短轴的长度。
  20. 根据权利要求16所述的显示基板，其中，一个红色子像素、两个绿色子像素和一个蓝色子像素组成一个像素单元，所述多个子像素组成的多个像素单元在所述衬底基板上阵列排布。
  21. 一种显示装置，包括权利要求1-20任一所述的显示基板。
  22. 根据权利要求21所述的显示装置，还包括纹路触摸表面以及图像传感器阵列，
    其中，所述图像传感器阵列设置在所述驱动电路层的远离所述发光器件层的一侧，包括多个图像传感器，所述多个图像传感器配置为可接收从所述发光器件层中的多个发光器件发出的且经在所述纹路触摸表面的纹路反射至所述多个图像传感器的光以用于纹路采集。
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