WO2022236707A1 - 一种相变存储器及其制作方法、电子设备 - Google Patents

一种相变存储器及其制作方法、电子设备 Download PDF

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Publication number
WO2022236707A1
WO2022236707A1 PCT/CN2021/093123 CN2021093123W WO2022236707A1 WO 2022236707 A1 WO2022236707 A1 WO 2022236707A1 CN 2021093123 W CN2021093123 W CN 2021093123W WO 2022236707 A1 WO2022236707 A1 WO 2022236707A1
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Prior art keywords
material layer
layer
insulating material
electrode
conductive
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PCT/CN2021/093123
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English (en)
French (fr)
Inventor
应成伟
秦青
周雪
焦慧芳
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华为技术有限公司
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Priority to PCT/CN2021/093123 priority Critical patent/WO2022236707A1/zh
Priority to CN202180093300.7A priority patent/CN116889117A/zh
Publication of WO2022236707A1 publication Critical patent/WO2022236707A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Definitions

  • the present application relates to the technical field of memory, in particular to a phase-change memory, a manufacturing method thereof, and electronic equipment.
  • Phase change memory phase change memory
  • PCM phase change memory
  • CMOS complementary metal oxide semiconductor, complementary metal oxide semiconductor
  • Phase-change memory uses electric current to drive the crystallization and amorphization of phase-change materials to store information.
  • the phase-change memory includes multiple memory cells. When the phase-change material in the memory cell is in a crystallized state, the resistance of the memory cell is low. At this time, the information stored in the memory cell can be recorded as the first logic information, such as "0". ; When the phase-change material in the memory cell is in an amorphized state, the resistance of the memory cell is relatively high. At this time, the information stored in the memory cell can be recorded as the second logic information, such as "1". By judging the resistance of the memory cell, it can be judged whether the memory cell stores "0" or "1".
  • the structure of a storage cell in a phase-change memory is shown in FIG. 1 .
  • the storage cell 100 includes a heater electrode 101 , a phase-change material layer 102 and a first electrode 103 that are sequentially stacked. Since the phase-change material layer 102 in the memory cell 100 is driven by a current to generate a large amount of heat to change the phase state, the phase-change memory is an energy-consuming device. At present, it is possible to increase the phase change speed of the phase change material layer 102 by increasing the current, so as to increase the read and write speed of the phase change memory, but increasing the current will lead to increased power consumption. Therefore, increasing the phase change speed of the phase change material layer 102 in the phase change memory while reducing power consumption is an urgent problem to be solved for the phase change memory.
  • Embodiments of the present application provide a phase-change memory, a manufacturing method thereof, and an electronic device, which can solve the problem of increased power consumption caused by increasing the phase-change speed of a phase-change material layer in the phase-change memory.
  • a phase-change memory which includes a plurality of memory cells distributed in an array, and the memory cells include: a heating electrode, a phase-change material layer and a first electrode stacked in sequence; the heating electrode includes an insulating material layer and a plurality of conductive channels formed by defects are arranged in the insulating material layer, and the conductive channels are in contact with the phase change material layer. Since the heating electrode includes an insulating material layer and a plurality of conductive channels formed by defects in the insulating material layer, the conductive channel plays a role in conducting electricity in the heating electrode, and the conductive channel is formed by defects, so the conductive channel is along the direction perpendicular to the storage element.
  • each direction of the stacking direction are small, for example, along each direction perpendicular to the stacking direction of the storage element, the size L of the conductive channel is in the range of 0 ⁇ L ⁇ 10nm, so that multiple conductive channels and phase transitions
  • the contact area of the material layer is small, that is, the contact area between the conductive part of the heating electrode and the phase change material layer is small, and the smaller the contact area between the conductive channel and the phase change material layer is, the phase change area in the phase change material layer is smaller.
  • the smaller the volume the greater the current density.
  • the smaller the volume of the phase change region in the phase change material layer the greater the current density.
  • the embodiment of the present application can increase the phase change speed of the phase change material layer to increase the read and write speed of the phase change memory while reducing power consumption.
  • the heating electrode in the storage unit provided in the embodiment of the present application conducts electricity, it is the conductive channel, and the conductive channel 1012 is formed by defects, so the conductive channel 1012 is along the vertical direction of the storage element.
  • the dimensions in all directions of the stacking direction are smaller, so the contact area between the conductive channel and the phase change material layer in the heating electrode provided by the embodiment of the present application is smaller, so compared with the blade electrode structure, the embodiment of the present application can further improve the phase change.
  • the phase change speed of the material layer can be changed, and the power consumption can be further reduced.
  • the conductive channel runs through the insulating material layer.
  • the conductive channel runs through the insulating material layer, and the defect in the insulating material layer is used as the conductive channel. Since the size of the defect in the insulating material layer is very small, about a few nanometers, it conducts electricity in all directions perpendicular to the stacking direction of the storage element.
  • the dimension L of the channel is very small, so that the contact area between the conductive channel in the heating electrode and the phase-change material layer is small, so the volume of the phase-change region in the phase-change material layer is small and the current density is high. Based on this, the power consumption can be reduced while increasing the phase change speed of the phase change material layer.
  • the material of the insulating material layer is a polycrystalline material, and the defects include grain boundaries of the polycrystalline material.
  • the grain boundary in the insulating material layer is used as the conduction channel, so that the size L of the conduction channel is relatively small in all directions perpendicular to the stacking direction of the storage element.
  • the heating electrode further includes a conductive discontinuous thin film layer; the discontinuous thin film layer includes a plurality of mutually independent islands; the discontinuous thin film layer is located on the side of the conductive channel away from the phase change material layer , the plurality of islands in the discontinuous film layer are spaced apart by a layer of insulating material, the thickness of the layer of insulating material being greater than the thickness of the discontinuous film layer; wherein the conductive pathway is in contact with the islands in the discontinuous film layer.
  • the insulating material layer can be formed by the tip discharge of the islands in the discontinuous film layer to form a conductive channel. In this way, the size L of the formed conductive channel can be compared in each direction perpendicular to the stacking direction of the storage element. Small.
  • the material of the discontinuous film layer includes one or more of magnesium, platinum or aluminum.
  • the discontinuous thin film layer can be formed by controlling process parameters such as the rate of chemical vapor deposition, sputtering or spraying, and the thickness of the discontinuous thin film layer according to the properties of the material of the discontinuous thin film layer.
  • the heating electrode further includes an insulating discontinuous thin film layer; the discontinuous thin film layer includes a plurality of mutually independent islands; the discontinuous thin film layer is located on a side of the insulating material layer away from the phase change material layer On the side, the insulating material layer separates a plurality of islands in the discontinuous film layer; wherein, the conductive channel is located between the islands, the conductive channel runs through the insulating material layer, and the resistivity of the discontinuous film layer is greater than that of the insulating material layer. Resistivity.
  • the conductive channel can be formed by breaking down the insulating material layer through the partial discharge of the second electrode between the islands. In this way, the dimension L of the formed conductive channel along each direction perpendicular to the stacking direction of the storage element can be formed. smaller.
  • the heating electrode further includes a conductive layer arranged on the side of the insulating material layer away from the phase-change material layer; the crystal structure of the material of the conductive layer is a columnar crystal; wherein, the conductive channel and the end of the columnar crystal ministry contacts.
  • the conductive channel can be formed by puncturing the insulating material layer through discharge at the tip of the columnar crystal. In this way, the dimension L of the formed conductive channel in each direction perpendicular to the stacking direction of the storage element can be relatively small.
  • the material of the conductive layer includes titanium nitride.
  • the crystal structure of titanium nitride is columnar crystal.
  • the material of the insulating material layer includes one or more of magnesium oxide, strontium oxide, aluminum oxide, tantalum oxide, titanium oxide or hafnium oxide.
  • the material of the insulating material layer can be selected from some metal oxides.
  • the storage unit further includes a second electrode disposed on a side of the heating electrode away from the phase-change material layer; wherein the conductive channel is electrically connected to the second electrode.
  • the first electrode of the storage unit is electrically connected to the bit line, and the second electrode of the storage unit is electrically connected to the gate device.
  • the phase-change memory further includes: a bit line, a word line, and a source line; the memory cell further includes: a gate device; the first pole of the gate device is electrically connected to the heating electrode, and the gate The second electrode of the device is electrically connected to the source line; the third electrode of the gate device is electrically connected to the word line, and the first electrode of the storage unit is electrically connected to the bit line.
  • the gating device may be, for example, a transistor or a gating tube, and the transistor may be, for example, a bipolar transistor, a triode, a field effect transistor, and the like.
  • the strobe device is a transistor, the first pole can be the source, the second pole can be the drain; or, the first pole can be the drain, the second pole can be the source, and the third pole can be the gate.
  • an electronic device in a second aspect, includes a printed circuit board and a phase-change memory electrically connected to the printed circuit board, and the phase-change memory is the phase-change memory provided in the above-mentioned first aspect. Since the electronic device has the same technical effect as that of the above-mentioned phase-change memory, reference can be made to the above, and details will not be repeated here.
  • a method for manufacturing a phase-change memory includes: first, forming a plurality of gate devices distributed in an array on a substrate; next, forming a plurality of gate devices distributed in an array on the substrate.
  • the manufacturing method of any storage element includes: first, forming an auxiliary layer on the substrate; next, forming a phase-change material layer on the auxiliary layer; then Next, the first electrode is formed on the phase-change material layer; next, the auxiliary layer is initialized by applying a current to form a heating electrode; wherein, the heating electrode includes an insulating material layer and a plurality of conductive electrodes formed by defects arranged in the insulating material layer.
  • the channel; the conductive channel is in contact with the phase change material layer.
  • the manufacturing method of the phase-change memory has the same technical effect as that of the phase-change memory provided by the above-mentioned first aspect, which can be referred to above, and will not be repeated here.
  • the manufacturing method of any storage element includes: firstly, forming a heating electrode on the substrate; next, forming a phase-change material layer on the heating electrode; next, forming a phase-change material layer on the A first electrode is formed on it; wherein, the heating electrode includes an insulating material layer and a plurality of conductive channels formed by defects arranged in the insulating material layer; the conductive channels are in contact with the phase change material layer.
  • the manufacturing method of the storage element has the same technical effect as that of the storage element in the phase-change memory provided by the first aspect above, which can be referred to above, and will not be repeated here.
  • forming the auxiliary layer on the substrate includes: forming an insulating material layer on the substrate; applying a current to the auxiliary layer to initialize, and forming a heating electrode, including: applying a current to the insulating material layer to initialize, Defects in the insulating material layer form conductive paths through the insulating material layer to form heating electrodes.
  • the conductive channel runs through the insulating material layer, and the defect in the insulating material layer is used as the conductive channel. Since the size of the defect in the insulating material layer is very small, about a few nanometers, it conducts electricity in all directions perpendicular to the stacking direction of the storage element.
  • the dimension L of the channel is very small, so that the contact area between the conductive channel in the heating electrode and the phase-change material layer is small, so the volume of the phase-change region in the phase-change material layer is small and the current density is high. Based on this, the power consumption can be reduced while increasing the phase change speed of the phase change material layer.
  • the manufacturing process of the conductive channel is simple, so that the manufacturing cost of the phase change memory can be reduced.
  • the grain boundary in the insulating material layer is used as the conduction channel, so that the size L of the conduction channel is relatively small in all directions perpendicular to the stacking direction of the storage element.
  • forming the insulating material layer on the substrate includes: forming a discontinuous thin film layer on the substrate; the discontinuous thin film layer includes a plurality of mutually independent islands; oxidizing the discontinuous thin film layer processing to form a layer of insulating material.
  • the material of the insulating material layer thus formed is oxide.
  • forming the auxiliary layer on the substrate includes: forming a conductive layer on the substrate; the crystal structure of the material of the conductive layer is a columnar crystal; forming an insulating material layer on the conductive layer; applying to the auxiliary layer The current is initialized to form a heating electrode, including: applying a current to the conductive layer and the insulating material layer to initialize, the tip discharge of the columnar crystal breaks down the insulating material layer, and forms a conductive channel in the insulating material layer to form a heating electrode; The channels are in contact with the ends of the columnar crystals.
  • the conductive channel is formed by the point discharge of the columnar crystal to break down the insulating material layer, the conductive channel formed by the defect is along each direction perpendicular to the stacking direction of the storage element, and the size of the conductive channel is very small, about several nanometers. , in this way, the contact area between the conductive channel in the heating electrode and the phase-change material layer is very small, so the volume of the phase-change region in the phase-change material layer is small, and the current density is large, so it can improve the phase-change material layer. Reduce power consumption while changing speed.
  • forming the auxiliary layer on the substrate includes: forming a conductive discontinuous thin film layer on the substrate; the discontinuous thin film layer includes a plurality of mutually independent islands; on the discontinuous thin film layer Forming an insulating material layer; wherein, the insulating material layer separates a plurality of islands in the discontinuous film layer, and the thickness of the insulating material layer is greater than the thickness of the discontinuous film layer; applying current to the auxiliary layer is initialized to form a heating electrode, Including: applying current to the discontinuous film layer and the insulating material layer to initialize, the tip discharge of the island breaks down the insulating material layer, and forms a conductive channel in the insulating material layer to form a heating electrode; wherein, the conductive channel and the discontinuous film island contact.
  • the size L of the conduction channel is very small in each direction perpendicular to the stacking direction of the storage element, about several In this way, the contact area between the conductive channel in the heating electrode and the phase-change material layer is very small, so the volume of the phase-change region in the phase-change material layer is small, and the current density is large, so the phase-change material layer can be improved. While increasing the speed of the phase change, the power consumption is reduced.
  • any method for manufacturing the storage element before forming the auxiliary layer on the substrate, further includes: forming a second electrode on the substrate; and electrically connecting the conductive channel in the heating electrode to the second electrode.
  • forming the auxiliary layer on the substrate includes: forming an insulating discontinuous thin film layer on the substrate; the discontinuous thin film layer includes a plurality of mutually independent islands; on the discontinuous thin film layer Forming an insulating material layer; wherein, the insulating material layer separates a plurality of islands in the discontinuous thin film layer; the resistivity of the discontinuous thin film layer is greater than the resistivity of the insulating material layer; applying current to the auxiliary layer is initialized to form a heating Electrodes, including: applying current to the discontinuous film layer and insulating material layer to initialize, the partial discharge of the second electrode between the islands breaks down the insulating material layer, and forms a conductive channel in the insulating material layer, and the conductive channel runs through the insulating material layer to form a heating electrode.
  • the conductive channel is formed by the partial discharge breakdown of the insulating material layer where the second electrode is located between the islands, the size L of the conductive channel is very small in each direction perpendicular to the stacking direction of the storage element, about several In this way, the contact area between the conductive channel in the heating electrode and the phase-change material layer is very small, so the volume of the phase-change region in the phase-change material layer is small, and the current density is large, so the phase-change material layer can be improved. While increasing the speed of the phase change, the power consumption is reduced.
  • Fig. 1 is a schematic structural diagram of a storage unit provided by the prior art
  • FIG. 2 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an electronic device provided by another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a phase change memory provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a storage element provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram during the manufacturing process of a storage element provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a storage element provided by another embodiment of the present application.
  • Fig. 8a is a schematic structural diagram of a phase-change material layer or a first electrode provided by an embodiment of the present application
  • Fig. 8b is a schematic structural diagram of a phase-change material layer or a first electrode provided by another embodiment of the present application.
  • Fig. 8c is a schematic structural diagram of a phase-change material layer or a first electrode provided by another embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a method for manufacturing a storage element provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram during the manufacturing process of a storage element provided by another embodiment of the present application.
  • Fig. 11 is a schematic structural diagram of a heating electrode provided in an embodiment of the present application.
  • FIG. 12 is a schematic flowchart of a method for manufacturing a storage element provided by another embodiment of the present application.
  • FIG. 13 is a schematic structural diagram during the manufacturing process of a storage element provided by another embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a storage element provided by another embodiment of the present application.
  • FIG. 15 is a schematic flowchart of a method for manufacturing a storage element provided by another embodiment of the present application.
  • FIG. 16 is a schematic structural diagram during the manufacturing process of a storage element provided by another embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a storage element provided by another embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a storage element provided by another embodiment of the present application.
  • FIG. 19 is a schematic flowchart of a method for manufacturing a storage element provided by another embodiment of the present application.
  • FIG. 20 is a schematic structural diagram during the manufacturing process of a storage element provided by another embodiment of the present application.
  • first”, second, etc. are used for convenience of description only, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediary.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • the direction indications such as up, down, left, right, front and back, etc. used to explain the structure and movement of different components in the present application are relative. These indications are pertinent when the parts are in the positions shown in the figures. However, should the description of component locations change, these directional indications will change accordingly.
  • An embodiment of the present application provides an electronic device, which can be, for example, a mobile phone, a tablet computer (pad), a personal digital assistant (personal digital assistant, PDA), a TV, a smart wearable product (for example, a smart watch, Smart bracelets), virtual reality (virtual reality, VR) terminal equipment, augmented reality (augmented reality, AR) terminal equipment, charging small household appliances (such as soybean milk machines, sweeping robots), drones, radars, aerospace equipment and Different types of user equipment or terminal equipment such as vehicle equipment; the electronic equipment may also be network equipment such as a base station.
  • the embodiment of the present application does not specifically limit the specific form of the electronic device.
  • FIG. 2 is a schematic structural diagram of an electronic device exemplarily provided by an embodiment of the present application.
  • the electronic device 1 includes components such as a storage device 11 , a processor 12 , an input device 13 , and an output device 14 .
  • the structure of the electronic device shown in FIG. 2 does not constitute a limitation to the electronic device 1, and the electronic device 1 may include more or less components than those shown in FIG. 2 , Or some of the components shown in FIG. 2 may be combined, or the arrangement of components may be different from that shown in FIG. 2 .
  • the storage device 11 is used to store software programs and modules.
  • the storage device 11 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program required by a function (such as a sound playback function, an image playback function, etc.); Data created by the use of electronic devices (such as audio data, image data, phonebook, etc.), etc.
  • the storage device 11 includes an external memory 111 and an internal memory 112 .
  • the data stored in the external memory 111 and the internal memory 112 can be transferred to each other.
  • the external storage 111 includes, for example, a hard disk, a U disk, a floppy disk, and the like.
  • the internal memory 112 includes, for example, random access memory, read-only memory, and the like. Wherein, the random access memory may be, for example, a phase-change memory, a magnetic memory, or a ferroelectric memory.
  • the processor 12 is the control center of the electronic device 1. It uses various interfaces and lines to connect various parts of the entire electronic device 1. By running or executing software programs and/or modules stored in the storage device 11, and calling The data in the device 11 executes various functions of the electronic device 1 and processes data, so as to monitor the electronic device 1 as a whole.
  • the processor 12 may include one or more processing units.
  • the processor 12 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a flight controller, Video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural network processor (neural-network processing unit, NPU), etc.
  • different processing units may be independent devices, or may be integrated in one or more processors.
  • the processor 12 may integrate an application processor and a modem processor, wherein the application processor mainly processes operating systems, user interfaces, and application programs, and the modem processor mainly processes wireless communications. It can be understood that the modem processor may not be integrated into the processor 12 .
  • the aforementioned application processor may be, for example, a central processing unit (central processing unit, CPU).
  • CPU central processing unit
  • the processor 12 is taken as a CPU as an example, and the CPU may include a computing unit 121 and a controller 122 .
  • the arithmetic unit 121 acquires the data stored in the internal memory 112 and processes the data stored in the internal memory 112 , and the processed result is usually sent back to the internal memory 112 .
  • the controller 122 can control the arithmetic unit 121 to process data, and the controller 122 can also control the external memory device 111 and the internal memory 112 to store data or read data.
  • the input device 13 is used to receive input numbers or character information, and generate key signal input related to user settings and function control of the electronic device.
  • the input device 13 may include a touch screen and other input devices.
  • the touch screen also known as the touch panel, can collect the user's touch operation on or near the touch screen (such as the user's operation on the touch screen or near the touch screen with any suitable object or accessory such as a finger, stylus), and according to the preset
  • the program drives the corresponding connected device.
  • the touch screen may include two parts: a touch detection device and a touch controller.
  • the touch detection device detects the user's touch orientation, and detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and sends it to the to the processor 12, and can receive and execute commands sent by the processor 12.
  • touch screens can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic waves.
  • Other input devices may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control buttons, power switch buttons, etc.), trackballs, mice, joysticks, and the like.
  • the controller 122 in the processor 12 may also control the input device 13 to receive an input signal or not to receive an input signal.
  • the number or character information received by the input device 13 and the key signal input related to the user setting and function control of the electronic device can be stored in the internal memory 112 .
  • the output device 14 is used to output the signal corresponding to the data input by the input device 13 and stored in the internal memory 112 .
  • the output device 14 outputs a sound signal or a video signal.
  • the controller 122 in the above-mentioned processor 12 can also control the output device 14 to output a signal or not to output a signal.
  • the thick arrows in FIG. 2 are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission.
  • a single arrow between the input device 13 and the internal memory 112 indicates that the data received by the input device 13 is transmitted to the internal memory 112 .
  • the double arrow between the computing unit 121 and the internal storage 112 indicates that the data stored in the internal storage 112 can be transmitted to the computing unit 121 , and the data processed by the computing unit 121 can be transmitted to the internal storage 112 .
  • Thin arrows in FIG. 2 indicate components that the controller 122 can control.
  • the controller 122 may control the external memory device 111, the internal memory 112, the computing unit 121, the input device 13, the output device 14, and the like.
  • the electronic device 1 shown in FIG. 2 may also include various sensors.
  • a gyro sensor for example, a hygrometer sensor, an infrared sensor, a magnetometer sensor, etc., which will not be repeated here.
  • the electronic device 1 may also include a wireless fidelity (wireless fidelity, WiFi) module, a Bluetooth module, etc., which will not be repeated here.
  • the electronic device may perform some or all of the steps in the embodiment of the present application. Perform other operations or variations of various operations.
  • each step may be performed in a different order presented in the embodiment of the present application, and it may not be necessary to perform all operations in the embodiment of the present application.
  • Each embodiment of the present application may be implemented independently or in any combination, which is not limited in the present application.
  • the electronic device 1 may further include a middle frame 15 , a rear case 16 and a display screen 17 .
  • the rear case 16 and the display screen 17 are respectively located on two sides of the middle frame 15 , and the middle frame 15 and the display screen 17 are arranged in the rear case 16 .
  • the middle frame 15 includes a supporting plate 150 for carrying the display screen 17 , and a frame 151 around the supporting plate 150 .
  • the electronic device 1 may also include a printed circuit board (printed circuit boards, PCB) disposed on the surface of the carrier plate 150 facing the rear case 16, and some electronic devices in the electronic device 1 such as the above-mentioned phase-change memory 10 may be disposed on the printed circuit boards. on the board; wherein, the phase change memory 10 is electrically connected to the printed circuit board PCB.
  • PCB printed circuit board
  • the embodiment of the present application also provides a phase-change memory, which can be applied to the above-mentioned electronic device 1 , for example, can be used as the internal memory 112 in the above-mentioned electronic device 1 .
  • the structure of the phase change memory 10 includes: a plurality of memory cells 100 distributed in an array, and the memory cells 100 include a gate device and a memory element 100A electrically connected to the gate device.
  • the gating device may be, for example, a transistor or a gating tube, and the transistor may be, for example, a bipolar transistor, a triode, or a field effect transistor.
  • the gate device includes a first pole, a second pole and a third pole. Both the following and FIG. 4 take the gate device as a transistor T as an example for illustration.
  • the phase change memory 10 also includes a plurality of parallel word lines (word line, WL) and a plurality of parallel arrangement of bit lines (bit line, BL), and the word line WL and the bit line BL cross each other but are isolated from each other, for example, The word line WL and the bit line BL are perpendicular to each other.
  • Bit line BL is electrically connected to memory element 100A.
  • the phase change memory 10 also includes a plurality of source lines (source lines, SL) arranged in parallel. In some examples, the source line SL is parallel to the bit line BL.
  • the transistor T includes a first pole, a second pole and a third pole; the first pole and the second pole serve as the interface for the current inflow or outflow when the transistor is turned on, and the third stage is the control pole (also called the gate gate) of the transistor. pole), for example, the first pole is the source, and the second pole is the drain; or, the first pole is the drain, and the second pole is the source.
  • the gate of the transistor T is electrically connected to the word line WL
  • the first electrode of the transistor T is electrically connected to the memory element 100A
  • the second electrode of the transistor T is electrically connected to the source line SL.
  • the word line WL is also electrically connected to the word line control circuit, and the word line WL is provided with a high level signal or a low level signal through the word line control circuit, so that the transistor T is turned on or off.
  • the transistor T is an N-type transistor
  • the high-level signal controls the transistor T to be turned on
  • the low-level signal controls the transistor T to be turned off.
  • the transistor T is a P-type transistor
  • the low-level signal controls the transistor T to be turned on
  • the high-level signal controls the transistor T to be turned off.
  • bit line BL is also electrically connected to a bit line control circuit, and a signal is provided to the bit line BL through the bit line control circuit.
  • the source line SL may be grounded.
  • the second electrodes of the transistors T in the plurality of memory cells 100 arranged in the Y direction are electrically connected to the same source line SL, and the storage in the plurality of memory cells 100 arranged in the Y direction
  • the element 100A is electrically connected to the same bit line BL, and the gates of the transistors T in the plurality of memory cells 100 arranged in the X direction are electrically connected to the same word line WL.
  • the structure of the storage element 100A in the above storage unit 100 will be described as an example below.
  • the above-mentioned storage element 100A includes a heating electrode 101, a phase-change material layer 102, and a first electrode (also referred to as an upper electrode) 103 that are sequentially stacked; 100A also includes a second electrode (also referred to as a lower electrode) 104 disposed on the side of the heating electrode 101 away from the phase-change material layer 102 .
  • the heating electrode 101 adopts a blade-type electrode structure (wall architecture).
  • the thickness d of the heating electrode 101 is much smaller than the width W and height H of the heating electrode 101 .
  • bit line BL is electrically connected to the storage element 100A, that is, the bit line BL is electrically connected to the first electrode 103 of the storage element 100A.
  • the first electrode of the transistor T is electrically connected to the storage element 100A, that is, the first electrode of the transistor T is electrically connected to the second electrode 104 of the storage element 100A.
  • the second electrode 104 is electrically connected to the first electrode of the transistor T through a via hole on the insulating layer.
  • the heating electrode 101 is directly electrically connected to the first electrode of the transistor T through the via hole on the insulating layer, since the area of the lower surface of the heating electrode 101 is small, there may be a problem that the heating electrode 101 is not electrically connected to the via hole on the insulating layer. In turn, there is a risk that the heating electrode 101 is not electrically connected to the first pole of the transistor T, so that the storage element 100A may not be electrically connected to the first pole of the transistor T.
  • the second electrode 104 can be provided in the storage element 100A, and the second electrode 104 is electrically connected to the first electrode of the transistor T through the via hole on the insulating layer, so that the first electrode of the storage element 100A and the transistor T can be ensured. connect. Referring to FIG. 4 , the first electrodes 103 in the memory elements 100A of the plurality of memory cells 100 arranged in the Y direction are electrically connected to the same bit line BL.
  • phase change memory 10 Based on the above storage unit 100 and the structure of the storage element 100A in the storage unit 100 , the working principle of the phase change memory 10 will be described below by taking one storage unit 100 as an example.
  • the transistor T When the memory cell 100 is written, the transistor T is in the conduction state.
  • the current flowing through the memory element 100A is a small current and a long pulse, the phase change material in the phase change material layer 102 will be in a crystallized state.
  • the resistance of the unit 100 is low, and it can be considered that the storage unit 100 stores the first logic information, which can be represented by “0” for example; when the current flowing through the storage element 100A is a large current and a short pulse, the phase change material The phase-change material in the layer 102 is in an amorphized state. At this time, the resistance of the memory cell is relatively high. It can be considered that the memory cell 100 stores the second logic information.
  • the second logic information can be represented by "1", for example.
  • a constant current flows from the bit line BL through the memory element 100A, and then flows out from the second electrode of the turned-on transistor T. In this way, a potential difference is generated at both ends of the memory element 100A. According to the magnitude of the potential difference, the resistance of the storage element 100A can be determined, and then it can be judged whether the information stored in the storage element 100A is the first logic information "0" or the second logic information "1".
  • the heating electrode 101 since the heating electrode 101 adopts a blade-type electrode structure, the contact area between the heating electrode 101 and the phase-change material layer 102 is small, so the volume of the phase-change region (also called a programming region) is small, and the current density In this way, on the one hand, the phase change speed of the phase change material layer 102 is higher; on the other hand, the current required for the phase change of the phase change material layer 102 in the phase change region can be reduced, Thereby, power consumption can be reduced. Based on this, when the heating electrode 101 adopts a blade-type electrode structure, since the contact area between the heating electrode 101 and the phase change material 102 is small, the phase change speed of the phase change material layer 102 can be increased to improve the phase change. While increasing the reading and writing speed of the memory 10, the power consumption can be reduced.
  • FIG. 6 the manufacturing process flow of the storage element 100A shown in FIG. 5 is shown in FIG. 6.
  • the left figure in FIG. 6 is a schematic cross-sectional view parallel to the stacking direction Z and parallel to the X direction. It is a schematic cross-sectional view parallel to the stacking direction Z and parallel to the Y direction.
  • making the storage element 100A as shown in FIG. 5 specifically includes the following steps:
  • a plurality of second electrodes 104 distributed in an array are formed, and the coating material 1051 is filled around and above the second electrodes 104; next, the coating material 1051 is etched to form a plurality of arrays arranged in sequence along the Y direction, and The strip-shaped bumps 1052 extending along the X direction, the upper surface of each second electrode 104 is exposed in the gap between the bumps 1052 .
  • a phase-change material layer 102 is formed on each heating electrode 104, and the phase-change material layers 102 above the plurality of second electrodes 104 arranged along the Y direction can be electrically connected together; next, the cladding material 1051 is filled, And ground until the upper surface of the phase-change material layer 102 is exposed; Next, a first electrode 103 is formed on each phase-change material layer 102, and the first electrodes 103 above a plurality of second electrodes 104 arranged in the Y direction can be are electrically connected together; next, the encapsulation material 1051 is filled. Wherein, all the covering materials 1051 constitute the covering layer 105 .
  • the heating electrode 101 in the fabricated memory element 100A has a blade-type electrode structure.
  • the thickness d of the heating electrode 101 can be determined by controlling the thickness of the grown conductive film.
  • the minimum thickness of the grown conductive film can reach about ten nanometers. In some examples, the minimum thickness of the heating electrode 101 can be 10nm ⁇ 15nm.
  • the width (wall width) W of the heater electrode 101 along the X direction can be controlled by a photolithography process.
  • the contact area between the heating electrode 101 and the phase change material layer 102 is determined by the thickness d of the heating electrode 101 and the width W of the heating electrode 101 along the X direction.
  • the thickness of the conductive thin film can be made smaller by controlling the growth process, the thickness of the heating electrode 101 formed can be controlled to be smaller, and then the contact area between the heating electrode 101 and the phase change material layer 102 can be made smaller .
  • the thickness of the conductive film can be controlled to be small by controlling the growth process, and then the thickness d of the heating electrode 101 can be controlled to be made small
  • the width W of the heating electrode 101 along the X direction is controlled by the photolithography process.
  • the width W of the heating electrode 101 along the X direction is difficult to further shrink, and the width W of the heating electrode 101 along the X direction controlled by the lithography process is usually more than 10 nm.
  • the current required to make the phase change material layer 102 undergo a phase change is about 100 ⁇ A;
  • the width W along the X direction is 45 nm, the current required to cause the phase change of the phase change material layer 102 is about 180 ⁇ A. Since the photolithography process limits the width W of the heating electrode 101 along the X direction, it is difficult to shrink further, so the contact area between the heating electrode 101 and the phase change material layer 102 is difficult to further shrink, so the current density cannot be further increased. The phase change speed of the change material layer 102 cannot be further increased, and the power consumption cannot be further reduced.
  • the embodiment of the present application also provides a storage element 100A.
  • the structure of the storage element 100A is shown in FIG.
  • the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects (defect) arranged in the insulating material layer 1011, conducting
  • the channel 1012 is in contact with the phase change material layer 102 , and the conductive channel 1012 is electrically connected to the second electrode 104 .
  • phase change memory 10 is the same as that described above, which can be referred to above, and will not be repeated here.
  • the material of the insulating material layer 1011 may be crystal or amorphous.
  • the material of the insulating material layer 1011 may be a single crystal material or a polycrystalline material.
  • the defects in the insulating material layer 1011 may include, for example, dislocations, grain boundaries, vacancies (such as oxygen vacancies) (holes), or metal wires. It should be understood that when the defect in the insulating material layer 1011 reaches a certain concentration at the position where the conductive channel 1012 is located, the conductive channel 1012 can be formed.
  • the conductive channel 1012 includes but is not limited to being formed by one type of defect, and the conductive channel 1012 may be formed by multiple types of defects.
  • conductive channels 1012 may be formed by grain boundaries.
  • the conductive channel 1012 may be composed of grain boundaries, vacancies, dislocations and the like.
  • the defect when the material in contact with at least one of the two ends of the conductive channel 1012 is an active metal, the defect may include a wire. In some other examples, when the material in contact with both ends of the conductive channel 1012 is an inactive metal, for example, the material in contact with one end of the conductive channel 1012 is platinum (Pt), and the material in contact with the other end of the conductive channel 1012 In the case of titanium nitride (TiN), the defects may include dislocations, grain boundaries, vacancies, and the like.
  • the size of the conductive channel 1012 in each direction perpendicular to the stacking direction Z of the storage element 100A is relatively small.
  • the dimension L of the conductive channel 1012 along each direction perpendicular to the stacking direction Z of the storage element 100A ranges from 0 ⁇ L ⁇ 10nm, that is, the range of the radial dimension L of the conductive channel 1012 is 0 ⁇ L ⁇ 10nm.
  • the size L of the conductive channel 1012 may be, for example, 1 nm, 3 nm, 5 nm, 8 nm, or 10 nm.
  • the number of conductive channels 1012 in the heating electrode 101 is not limited, and can be set as required.
  • the conductive channel 1012 in the heating electrode 101 can be straight or curved.
  • the conductive channel 1012 can be arranged perpendicular to the second electrode 104 , or can be arranged obliquely relative to the second electrode 104 . Different conductive channels 1012 may or may not intersect each other.
  • the material of the phase change material layer 102 should have phase change properties.
  • the material of the phase change material layer 102 may be one or more of GeTe (germanium tellurium) alloy, Sb2Te5 (antimony tellurium) alloy or Ge2Sb2Te5 (germanium antimony tellurium) alloy.
  • GeTe germanium tellurium
  • Sb2Te5 antimony tellurium
  • Ge2Sb2Te5 germanium antimony tellurium
  • GST is a phase change material most widely used in phase change memories 10 at present.
  • the material of the first electrode 103 and the material of the second electrode 104 may include one or more of copper (Cu), silver (Ag), aluminum (Al), and gold (Au).
  • the first electrode 103 and the second electrode 104 may have a single-layer structure or a multi-layer structure.
  • the second electrodes 104 in the multiple storage elements 100A are independent from each other, and the heating electrodes 101 in the multiple storage elements 100A are independent from each other.
  • the phase change material layers 102 in multiple storage elements 100A are independent of each other; in other examples, as shown in FIG. 8b, the phase change material layers 102 in multiple storage elements 100A
  • the phase-change material layers 102 are electrically connected together, that is, a plurality of phase-change material layers 102 form an entire layer structure; in some other examples, as shown in FIG.
  • the layers 102 are electrically connected together, that is, multiple phase change material layers 102 form multiple strip structures.
  • the first electrodes 103 in multiple storage elements 100A are independent of each other; in other examples, as shown in FIG. 8b, the first electrodes 103 in multiple storage elements 100A Electrically connected together, that is, a plurality of first electrodes 103 form an entire layer structure; in some other examples, as shown in FIG. 8c, the first electrodes 103 in a plurality of storage elements 100A arranged along the Y direction are electrically connected together, That is, a plurality of first electrodes 103 form a plurality of strip structures.
  • the embodiment of the present application provides a phase-change memory 10.
  • the storage unit 100 of the phase-change memory 10 includes a second electrode 104, a heating electrode 101, a phase-change material layer 102, and a first electrode 103 that are sequentially stacked. Since the heating electrode 101 includes The insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects are arranged in the insulating material layer 1011.
  • the conductive channels 1012 that play a conductive role in the heating electrode 101, and the conductive channels 1012 are formed by defects, so the conductive channels 1012 are along the vertical direction
  • the dimensions in each direction of the stacking direction Z of the storage element 100A are relatively small, for example, along each direction perpendicular to the stacking direction Z of the storage element 100A, the size L of the conductive channel 1012 can be in the range of 0 ⁇ L ⁇ 10 nm, such that Therefore, the contact area between the plurality of conductive channels 1012 and the phase-change material layer 102 is relatively small, that is, the contact area between the conductive part of the heating electrode 101 and the phase-change material layer 102 is relatively small, while the contact area between the conductive channels 1012 and the phase-change material layer The smaller the contact area of 102 is, the smaller the volume of the phase change region in the phase change material layer 102 is, and the higher the current density is.
  • phase change speed of the phase change material layer 102 can be increased to increase the read/write speed of the phase change memory 10 while reducing power consumption.
  • the heating electrode 101 in the storage unit 100 provided in the embodiment of the present application conducts electricity, the conductive channel 1012 is formed by defects, so the conductive channel 1012 is along the vertical direction.
  • the size in each direction of the stacking direction Z of the storage element 100A is small, so the contact area between the conductive channel 1012 and the phase-change material layer 102 in the heating electrode 101 provided by the embodiment of the present application is smaller, so compared with the blade electrode structure , the embodiment of the present application can further increase the phase change speed of the phase change material layer 102 and further reduce power consumption.
  • the embodiment of the present application also provides a method for manufacturing a phase change memory, including:
  • a plurality of gating devices distributed in an array are formed on the substrate; next, a plurality of storage elements 100A distributed in an array are formed on the substrate, the gating devices are electrically connected to the storage elements 100A in one-to-one correspondence, and one storage element 100A is electrically connected to the A gating device constitutes a memory cell 100 .
  • the types of the gate devices can be referred to above, and will not be repeated here.
  • the manufacturing method of the storage element 100A in any storage unit 100 may include the following steps:
  • the substrate 105 can be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate; it can also be a glass (glass) substrate or include an organic material base, etc.
  • a semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate
  • Si silicon
  • Ge germanium
  • GaN gallium nitride
  • GaAs gallium arsenide
  • forming the second electrode 104 on the substrate 105 includes: firstly, forming a conductive film on the substrate 105 ; and then, performing a patterning process on the conductive film to form the second electrode 104 .
  • the conductive thin film can be formed by chemical vapor deposition (chemical vapor deposition, CVD), sputtering or spraying.
  • the patterning process includes processes such as coating photoresist, mask exposure, development and etching.
  • the second electrode 104 may have a single-layer structure or a multi-layer structure.
  • the material of the second electrode 104 can refer to the above-mentioned embodiments, and will not be repeated here.
  • the material of the phase-change material layer 102 can refer to the above-mentioned embodiments, which will not be repeated here.
  • the phase change material layer 102 may be formed by chemical vapor deposition, sputtering or spraying.
  • forming the first electrode 103 on the phase-change material layer 102 includes: firstly, forming a conductive film on the phase-change material layer 102 ; then, performing a patterning process on the conductive film to form the first electrode 103 .
  • the conductive thin film may be formed by chemical vapor deposition, sputtering, or spraying.
  • the patterning process includes processes such as coating photoresist, mask exposure, development and etching.
  • the first electrode 103 may have a single-layer structure or a multi-layer structure.
  • the material of the first electrode 103 can refer to the above-mentioned embodiments, and will not be repeated here.
  • the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects disposed in the insulating material layer 1011;
  • the conductive channel 1012 is in contact with the phase change material layer 102 , and the conductive channel 1012 is electrically connected to the second electrode 104 .
  • the size of the conductive path 1012 in each direction perpendicular to the stacking direction Z of the memory element 100A is small.
  • the dimension L of the conductive channel 1012 in each direction perpendicular to the stacking direction Z of the storage element 100A is in a range of 0 ⁇ L ⁇ 10 nm.
  • the dimension L of the conductive channel 1012 may be, for example, 1 nm, 3 nm, 5 nm, 8 nm or 10 nm.
  • a voltage can be applied to the first electrode 103 through the bit line BL, and a voltage can be applied to the second electrode 105 through the source line SL, so as to apply a current to the auxiliary layer 106 for initialization. It can be understood that when the auxiliary layer 106 is initialized, the applied current should be relatively large.
  • the number of conductive channels 1012 in the heating electrode 101 is not limited, and can be set as required.
  • the conductive channel 1012 in the heater electrode 101 can be straight or curved.
  • the conductive channel 1012 can be arranged perpendicular to the second electrode 104 , or can be arranged obliquely relative to the second electrode 104 . Different conductive channels 1012 may or may not intersect each other.
  • the method for manufacturing the storage element 100A in any one of the above-mentioned storage units 100 may also include the following steps:
  • step S20 reference may be made to the above step S10, which will not be repeated here.
  • the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects disposed in the insulating material layer 1011; the conductive channels 1012 are electrically connected to the second electrode 104 connect.
  • the size L, quantity and shape of the conductive channels 1012 can refer to the above-mentioned step S14 , which will not be repeated here.
  • step S22 reference may be made to the above step S12, which will not be repeated here.
  • step S23 reference may be made to the above step S13, which will not be repeated here.
  • the storage element 100A in any one of the storage units 100 of the above-mentioned phase change memory 10 can be manufactured by using the manufacturing method of the storage element 100A provided in steps S10-S14 or steps S20-S23.
  • multiple memory cell elements 100A in the phase change memory 10 can be fabricated simultaneously.
  • step S10 to step S14 or step S20 to step S23 has the same technical effect as the above phase change memory 10, and reference can be made to the above description of the technical effect of the phase change memory 10 , which will not be repeated here.
  • the structure of the storage element 100A provided by Embodiment 1 is shown in FIG. 7 , including: a second electrode 104, a heating electrode 101, a phase-change material layer 102, and a first electrode 103 that are stacked in sequence;
  • the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects in the insulating material layer 1011 , the conductive channels 1012 penetrate the insulating material layer 1011 , the conductive channels 1012 are in contact with the phase change material layer 102 , and the conductive channels 1012 are electrically connected to the second electrode 104 .
  • the material of the insulating material layer 1011 is a polycrystalline material
  • the defects constituting the conductive channel 1012 include grain boundaries of the polycrystalline material.
  • FIG. 11 is a top view of the heating electrode 1011. It can be seen from FIG. 11 that the insulating material layer 1011 includes a plurality of grain boundaries.
  • the material of the insulating material layer 1011 includes magnesium oxide (MgO), strontium oxide (SrO), aluminum oxide (Al 2 O 3 ), tantalum oxide (TaO x ), titanium oxide (TiO 2 ) or hafnium oxide ( One or more of HfO 2 ).
  • the conductive channel 1012 runs through the insulating material layer 1011, and the defects in the insulating material layer 1011 are used as the conductive channel 1012. Because the defects in the insulating material layer 1011, such as grain boundaries, are very small in size, about several nanometers , so along each direction perpendicular to the stacking direction Z of the storage element 100A, the size L of the conductive channel 1012 is very small, so that the contact area between the conductive channel 1012 in the heating electrode 101 and the phase change material layer 102 is small, so the phase The phase change region in the change material layer 102 has a smaller volume and a higher current density. Based on this, the power consumption can be reduced while increasing the phase change speed of the phase change material layer 102 .
  • the first embodiment also provides a method for manufacturing the storage element 100A, which can be used to manufacture the storage element 100A provided in the first embodiment above.
  • the method for manufacturing the storage element 100A includes the following steps:
  • step S100 reference may be made to the above step S10, which will not be repeated here.
  • the discontinuous thin film layer 107 includes a plurality of mutually independent islands.
  • the discontinuous thin film layer 107 can be formed by chemical vapor deposition, sputtering or spraying.
  • the discontinuous thin film layer 107 can be formed by controlling the process parameters such as the rate of chemical vapor deposition, sputtering or spraying, the thickness of the discontinuous thin film layer 107 according to the properties of the material of the discontinuous thin film layer 107 .
  • the material of the discontinuous thin film layer 107 includes one or more of magnesium (Mg), strontium (Sr) or aluminum (Al).
  • the thickness of the discontinuous thin film layer 107 cannot be too large.
  • the thickness h of the discontinuous thin film layer 107 is in the range of 0 ⁇ h ⁇ 8nm.
  • the thickness h of the discontinuous thin film layer 107 can be 1 nm, 3 nm, 5 nm, or 8 nm, etc.
  • the material of the insulating material layer 1011 may be crystal or amorphous.
  • the material of the insulating material layer 1011 may be a single crystal material or a polycrystalline material.
  • the material of the insulating material layer 1011 may be one or more of magnesium oxide, strontium oxide or aluminum oxide.
  • the defects in the insulating material layer 1011 may or may not penetrate through the insulating material layer 1011 .
  • the material of the insulating material layer 1011 is a polycrystalline material, and defects in the insulating material layer 1011 include grain boundaries. At this time, the multiple grain boundaries of the insulating material layer 1011 may or may not penetrate the insulating material layer 1011 .
  • the formed insulating material layer 1011 is continuous.
  • step S103 reference may be made to the above step S12, which will not be repeated here.
  • step S104 reference may be made to the above step S13, which will not be repeated here.
  • the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects arranged in the insulating material layer 1011; the conductive channels 1012 are in contact with the phase change material layer 102, and the conductive channels 1012 are electrically connected to the second electrode 104 .
  • the material of the insulating material layer 1011 is polycrystalline material; the insulating material layer 1011 is initialized by applying a current, and the grain boundary of the polycrystalline material penetrates the insulating material layer 1011 to form a conductive channel 1012 to form the heating electrode 101 .
  • a voltage can be applied to the first electrode 103 through the bit line BL, and a voltage can be applied to the second electrode 105 through the source line SL, so as to apply a current to the insulating material layer 1011 for initialization. It can be understood that when initializing the insulating material layer 1011 , the applied current should be relatively large, so that the defects in the insulating material layer 1011 can penetrate the insulating material layer 1011 , thereby forming the conductive channel 1012 .
  • the insulating material layer 1011 formed in step S102 includes defects such as grain boundaries, these defects such as grain boundaries may not penetrate the insulating material layer 1011. The boundary can penetrate through the insulating material layer 1011, so that a conductive channel 1012 can be formed.
  • the size L, quantity and shape of the conductive channels 1012 can refer to the above step S14, and will not be repeated here.
  • the insulating material layer 1011 can be formed through step S101 and step S102. In some examples, the insulating material layer 1011 may also be directly formed on the second electrode 104 .
  • the conductive channel 1012 formed by defects is obtained, and the manufacturing process of the conductive channel 1012 is simple, thereby reducing the manufacturing cost of the phase change memory 10 .
  • the difference between the second embodiment and the first embodiment is that the structures of the heating electrodes 101 are different.
  • the structure of the memory element 100A provided by the second embodiment is shown in FIG. 14 , including: the second electrode 104 , the heating electrode 101 , the phase-change material layer 102 and the first electrode 103 arranged sequentially;
  • the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects in the insulating material layer 1011, the conductive channels 1012 are in contact with the phase change material layer 102, and the conductive channels 1012 are electrically connected to the second electrode 104;
  • the heating electrode 101 also includes conductive discontinuous The thin film layer 107;
  • the discontinuous thin film layer 107 includes a plurality of mutually independent islands;
  • the discontinuous thin film layer 107 is located on the side of the conductive channel 1012 away from the phase change material layer 102, and the insulating material layer 1011 connects the discontinuous thin film layer 107
  • the plurality of islands are spaced apart, and the thickness of the insulating material layer 1011 is greater than the thickness of the discontinuous
  • the islands in the discontinuous thin film layer 107 may protrude toward the side close to the phase-change material layer 102 , or may protrude toward the side away from the phase-change material layer 102 .
  • the material of the insulating material layer 1011 can refer to the above-mentioned first embodiment, which will not be repeated here.
  • the material of the discontinuous thin film layer 107 may include one or more of magnesium (Mg), platinum (pt) or aluminum (Al).
  • the material of the insulating material layer 1011 is oxide of the material of the discontinuous thin film layer 107 , for example, the material of the insulating material layer 1011 is magnesium oxide, and the material of the discontinuous thin film layer 107 is magnesium. In some other examples, the material of the insulating material layer 1011 is an oxide of other metals except the material of the continuous film layer 107 .
  • the material of the insulating material layer 1011 is tantalum oxide, and the material of the discontinuous film layer 107 is magnesium.
  • the material of the insulating material layer 1011 is the oxide of the material of the discontinuous thin film layer 107
  • the boundaries of the islands in the discontinuous thin film layer 107 may not be clearly distinguished in the heater electrode 101 .
  • the material of the insulating material layer 1011 is an oxide of a metal other than the material of the continuous thin film layer 107
  • the boundaries of the islands in the discontinuous thin film layer 107 can be distinguished in the heater electrode 101 .
  • Embodiment 2 also provides a method for manufacturing a storage element 100A, which can be used, for example, to manufacture a storage element 100A as shown in FIG. 14 .
  • the method for manufacturing the storage element 100A, as shown in FIG. 15 includes the following steps:
  • step S200 reference may be made to the above step S10, which will not be repeated here.
  • the discontinuous thin film layer 107 includes a plurality of mutually independent islands.
  • the material of the conductive discontinuous thin film layer 107 can be referred to above, and will not be repeated here.
  • the discontinuous thin film layer 107 can be formed by chemical vapor deposition, sputtering or spraying.
  • the discontinuous thin film layer 107 can be formed by controlling the chemical vapor deposition, sputtering or spraying rate, the thickness of the discontinuous thin film layer 107 and other process parameters according to the properties of the material of the discontinuous thin film layer 107 .
  • the thickness of the discontinuous thin film layer 107 cannot be too large.
  • the thickness h of the discontinuous thin film layer 107 is in the range of 0 ⁇ h ⁇ 8nm.
  • the thickness h of the discontinuous thin film layer 107 can be 1 nm, 3 nm, 5 nm, or 8 nm, etc.
  • the discontinuous thin film layer 107 is conductive, the islands in the discontinuous thin film layer 107 are also conductive.
  • an insulating material layer 1011 is formed on the discontinuous thin film layer 107; wherein, the insulating material layer 1011 separates a plurality of islands in the discontinuous thin film layer 107, and the thickness of the insulating material layer 1011 is greater than The thickness of the discontinuous film layer 107 .
  • the material of the insulating material layer 1011 can be referred to above, and will not be repeated here.
  • the insulating material layer 1011 can be formed by chemical vapor deposition, sputtering or spraying.
  • step S203 reference may be made to the above step S12, which will not be repeated here.
  • step S204 reference may be made to the above step S13, which will not be repeated here.
  • the size L, quantity and shape of the conductive channels 1012 can refer to the above-mentioned step S14 , which will not be repeated here.
  • a voltage can be applied to the first electrode 103 through the bit line BL, and a voltage can be applied to the second electrode 105 through the source line SL, thereby applying a current to the discontinuous thin film layer 107 and the insulating material layer 1011 for initialization, so that the island The discharge from the object tip breaks down the insulating material layer 1011 to form a conductive channel 1012 .
  • the applied current should be relatively large.
  • the top of the island is far away from the surface of the insulating material layer 1011 away from the second electrode 104 , the top of the island is easy to break through the insulating material layer 1011 to form the conductive channel 1012 .
  • the islands may protrude toward a side close to the phase change material layer 102 , or may protrude toward a side away from the phase change material layer 102 .
  • the tip of the island is more likely to discharge and break through the insulating material layer 1011 to form a conductive channel 1012 .
  • the conductive channel 1012 is formed through the discharge breakdown of the insulating material layer 1011 at the tips of the islands in the discontinuous thin film layer 107, the conductive channel 1012 formed by the defect is along the stacking direction perpendicular to the storage element 100A.
  • the size L of the conductive channel is very small, about several nanometers. In this way, the contact area between the conductive channel 1012 in the heating electrode 101 and the phase-change material layer 102 is very small, so the phase-change material layer 102 The volume of the middle phase change region is small, and the current density is relatively high, so the power consumption can be reduced while increasing the phase change speed of the phase change material layer 102 .
  • the manufacturing process of the conductive channel 1012 is simple, thereby reducing the manufacturing cost of the phase change memory 10 .
  • the difference between the third embodiment and the first and second embodiments is that the structure of the heating electrode 101 is different.
  • the structure of the memory element 100A provided by Embodiment 2 is shown in FIG. 17 , including: a second electrode 104, a heating electrode 101, a phase-change material layer 102, and a first electrode 103 that are sequentially stacked;
  • the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects arranged in the insulating material layer 1011, the conductive channels 1012 are in contact with the phase change material layer 102, and the conductive channels 1012 are electrically connected to the second electrode 104;
  • the heating electrode 101 also includes insulating discontinuous Thin film layer 107;
  • the discontinuous thin film layer 107 includes a plurality of mutually independent islands;
  • the discontinuous thin film layer 107 is located on the side of the insulating material layer 1011 away from the phase change material layer 102, and the insulating material layer 1011 separates the discontinuous thin film layer 107 A plurality of islands are spaced apart; wherein, the conductive channel 1012 is located
  • the insulating performance of the discontinuous thin film layer 107 is better than that of the insulating material layer 1011 .
  • the islands in the discontinuous thin film layer 107 may protrude toward the side close to the phase-change material layer 102 , or may protrude toward the side away from the phase-change material layer 102 .
  • the thickness of the insulating material layer 1011 may be greater than or equal to the thickness of the discontinuous film layer 107 .
  • the materials of the discontinuous film layer 107 and the insulating material layer 1011 may include one or more of tantalum oxide, titanium oxide, magnesium oxide, aluminum oxide, strontium oxide or hafnium oxide.
  • Embodiment 3 also provides a manufacturing method of the storage element 100A, the manufacturing method of the storage element 100A provided in the third embodiment is similar to the manufacturing method of the storage unit 100A provided in the second embodiment, the difference lies in step S201, step S202 and step S205.
  • step S201 in the second embodiment may be replaced with step S300
  • step S202 in the second embodiment may be replaced with step S301
  • step S205 in the second embodiment may be replaced with step S302
  • other steps are the same.
  • the discontinuous thin film layer 107 includes a plurality of mutually independent islands.
  • the material of the insulating discontinuous thin film layer 107 can be referred to above, and will not be repeated here.
  • the formation method and thickness of the discontinuous thin film layer 107 can refer to the above step S201.
  • the discontinuous thin film layer 107 formed in step S201 is conductive, and the discontinuous thin film layer 107 formed in step S300 is insulating.
  • the thickness of the insulating material layer 1011 may be greater than or equal to the thickness of the discontinuous film layer 107 .
  • the material of the insulating material layer 1011 can refer to the above, and will not be repeated here.
  • the method for forming the insulating material layer 1011 can refer to step S202 , which will not be repeated here.
  • step S202 since the discontinuous thin film layer 107 is conductive, the resistivity of the insulating material layer 1011 is greater than that of the discontinuous thin film layer 107, and in step S301, the resistivity of the discontinuous thin film layer 107 is greater than that of the insulating material layer 1011 resistivity.
  • the size L, quantity and shape of the conductive channels 1012 can refer to the above-mentioned step S14 , which will not be repeated here.
  • a voltage can be applied to the first electrode 103 through the bit line BL, and a voltage can be applied to the second electrode 105 through the source line SL, so as to apply a current to the discontinuous film layer 107 and the insulating material layer 1011 for initialization, so that the first The partial discharge of the two electrodes 104 between the islands breaks down the insulating material layer 1011 to form a conductive channel 1012 in the insulating material layer 1011 .
  • the applied current should be relatively large.
  • the resistivity of the discontinuous film layer 107 is greater than the resistivity of the insulating material layer 1011, when a current is applied, the part of the second electrode 104 located between the islands is easy to discharge and break through the insulating material layer 1011, thereby Conductive vias 1012 are formed.
  • the conductive channel 1012 is formed by the partial discharge breakdown of the insulating material layer 1011 when the second electrode 104 is located between the islands, the conductive channel 1012 composed of defects is formed along the stacking direction perpendicular to the storage element 100A.
  • the size L of the conductive channel is very small, about several nanometers.
  • the contact area between the conductive channel 1012 in the heating electrode 101 and the phase-change material layer 102 is very small, so the phase-change material layer 102
  • the volume of the middle phase change region is small, and the current density is relatively high, so the power consumption can be reduced while increasing the phase change speed of the phase change material layer 102 .
  • the manufacturing cost of the phase change memory 10 can be reduced because the manufacturing process of the conductive channel 1012 is simple.
  • Embodiment 4 The difference between Embodiment 4 and Embodiment 1, Embodiment 2, and Embodiment 3 is that the structure of the heating electrode 101 is different.
  • the structure of the storage element 100A provided in Embodiment 4 is shown in FIG. 18 , including: the second electrode 104 , the heating electrode 101 , the phase-change material layer 102 and the first electrode 103 arranged sequentially;
  • the heating electrode 101 includes an insulating material layer 1011 and a plurality of conductive channels 1012 formed by defects in the insulating material layer 1011, the conductive channels 1012 are in contact with the phase change material layer 102, and the conductive channels 1012 are electrically connected to the second electrode 104;
  • the heating electrode 101 also includes a Layer 1011 is away from the conductive layer 108 on the side of the phase change material layer 102; the crystal structure of the material of the conductive layer 108 is columnar crystal; wherein, the conductive channel 1012 is in contact with the end of the columnar crystal.
  • the crystal structure of the material of the conductive layer 108 is a columnar crystal, and the insulating material layer 1011 is disposed on the conductive layer 108, when the insulating material layer 1011 is formed on the conductive layer 108, referring to FIG. 18, the insulating material layer 1011 The insulating material in will be filled between the columnar crystals of the conductive layer 108 .
  • the growth direction of the columnar crystals is the same as the stacking direction Z of the layers in the memory element 100A.
  • the type and size of the defect, the material of the insulating material layer 1011 and the like can be referred to above, and will not be repeated here.
  • the material of the conductive layer 108 includes titanium nitride (TiN).
  • TiN titanium nitride
  • the crystal structure of titanium nitride is columnar crystals.
  • Embodiment 4 also provides a method for manufacturing a storage element 100A, which can be used, for example, to manufacture the storage element 100A shown in FIG. 18 .
  • the method for manufacturing the storage element 100A, as shown in FIG. 19 includes the following steps:
  • step S400 reference may be made to the above step S10, which will not be repeated here.
  • the material of the conductive layer 108 includes titanium nitride.
  • the conductive layer 108 may be grown by physical vapor deposition.
  • the material of the insulating material layer 1011 can be referred to above, and will not be repeated here.
  • the insulating material layer 1011 can be formed by chemical vapor deposition, sputtering or spraying.
  • the crystal structure of the material of the conductive layer 108 is columnar crystals, when the insulating material layer 1011 is formed, the insulating material in the insulating material layer 1011 will be filled between the columnar crystals of the conductive layer 108 .
  • step S403 reference may be made to the above step S12, which will not be repeated here.
  • step S404 reference may be made to the above step S13, which will not be repeated here.
  • the size L, quantity and shape of the conductive channels 1012 can refer to the above-mentioned step S14 , which will not be repeated here.
  • the crystal structure of the conductive layer 108 is a columnar crystal, when a current is applied to the conductive layer 108 , the tip of the columnar crystal will discharge.
  • a voltage can be applied to the first electrode 103 through the bit line BL, and a voltage can be applied to the second electrode 105 through the source line SL, so as to apply a current to the conductive layer 108 and the insulating material layer 1011 for initialization, so that the columnar crystal
  • the tip discharge breaks down the insulating material layer 1011 to form a conductive channel 1012 .
  • the applied current should be relatively large.
  • the conductive channel 1012 is formed by breaking down the insulating material layer 1011 through the point discharge of the columnar crystal, the conductive channel 1012 formed by defects is along each direction perpendicular to the stacking direction Z of the storage element 100A,
  • the size L of the conduction channel is very small, about several nanometers. In this way, the contact area between the conduction channel 1012 in the heating electrode 101 and the phase-change material layer 102 is very small, so the volume of the phase-change region in the phase-change material layer 102 is relatively small.
  • the current density is small, and the current density is relatively large, so the power consumption can be reduced while increasing the phase change speed of the phase change material layer 102 .
  • the manufacturing cost of the phase change memory 10 can be reduced due to the simple manufacturing process of the conductive channel 1012 while obtaining the conductive channel formed by defects.

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Abstract

本申请实施例提供一种相变存储器及其制作方法、电子设备，涉及存储器技术领域，可以解决提高相变存储器中相变材料层的相变速度，导致的功耗增加的问题。该相变存储器包括阵列分布的多个存储单元，所述存储单元包括：依次层叠设置的加热电极、相变材料层和第一电极；所述加热电极包括绝缘材料层和设置在所述绝缘材料层内由缺陷构成的多个导电通道，所述导电通道与所述相变材料层接触。

Description

一种相变存储器及其制作方法、电子设备 技术领域
本申请涉及存储器技术领域，尤其涉及一种相变存储器及其制作方法、电子设备。
背景技术
相变存储器(phase change memory，PCM)是一种新型非易失性存储器，因其具有读写速度快、密度高、CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)兼容性好而得到广泛关注。
相变存储器是利用电流来驱动相变材料的晶化和非晶化来存储信息的。相变存储器包括多个存储单元，当存储单元中的相变材料处于晶化状态时，存储单元的电阻较低，此时可以将存储单元存储的信息记为第一逻辑信息，例如“0”；当存储单元中的相变材料处于非晶化状态时，存储单元的电阻较高，此时可以将存储单元存储的信息记为第二逻辑信息，例如“1”。通过判断存储单元的电阻，从而可以判断存储单元存储的是“0”或“1”。
相变存储器中的存储单元的结构如图1所示，存储单元100包括依次层叠设置的加热电极101、相变材料层102和第一电极103。由于存储单元100中的相变材料层102是通过电流驱动加热电极101产生大量的热来改变相态的，因此相变存储器是一种能耗型器件。目前，可以采用增大电流的方式，提高相变材料层102的相变速度，以提高相变存储器的读写速度，但是增大电流又会导致功耗增加。因此，提高相变存储器中相变材料层102的相变速度，同时降低功耗是相变存储器急需解决的问题。
发明内容
本申请的实施例提供一种相变存储器及其制作方法、电子设备，可以解决提高相变存储器中相变材料层的相变速度，导致的功耗增加的问题。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种相变存储器，该相变存储器包括阵列分布的多个存储单元，存储单元包括：依次层叠设置的加热电极、相变材料层和第一电极；加热电极包括绝缘材料层和设置在绝缘材料层内由缺陷构成的多个导电通道，导电通道与相变材料层接触。由于加热电极包括绝缘材料层和设置在绝缘材料层内由缺陷构成的多个导电通道，加热电极中起导电作用的是导电通道，而导电通道由缺陷构成，因而导电通道沿垂直于存储元件的层叠方向的各个方向上的尺寸较小，例如沿垂直于存储元件的层叠方向的各个方向上，导电通道的尺寸L的范围为0＜L≤10nm，这样一来，多个导电通道与相变材料层的接触面积较小，即加热电极中起导电作用的部分与相变材料层的接触面积较小，而导电通道与相变材料层的接触面积越小，相变材料层中相变区域的体积越小，且电流密度越大。相变材料层中相变区域的体积越小，电流密度越大，一方面，可以提高相变材料层发生相变的速度，进而提高相变存储器的读写速度；另一方面，可以使得相变材料层发生相变的所需的电流可以减小，这样一来，可以降低功耗。基于此，本申请实施例，可以在提高相变材料层的相变速度，以提高相变存储器的读 写速度的同时，降低功耗。
相对于加热电极为刀片式电极结构，由于本申请实施例提供的存储单元中的加热电极中起导电作用的是导电通道，而导电通道1012由缺陷构成，因而导电通道1012沿垂直于存储元件的层叠方向的各个方向上的尺寸较小，因此本申请实施例提供的加热电极中导电通道与相变材料层的接触面积更小，因而相对于刀片式电极结构，本申请实施例可以进一步提高相变材料层的相变速度，且进一步降低功耗。
在一种可选的实施方式中，导电通道贯穿绝缘材料层。导电通道贯穿绝缘材料层，利用绝缘材料层内的缺陷作为导电通道，由于绝缘材料层内的缺陷的尺寸非常小，约为几个纳米，因而沿垂直于存储元件的层叠方向的各个方向，导电通道的尺寸L非常小，这样一来，加热电极中导电通道与相变材料层的接触面积较小，因此相变材料层中相变区域的体积较小，电流密度较大。基于此，可以在提高相变材料层的相变速度的同时，降低功耗。
在一种可选的实施方式中，绝缘材料层的材料为多晶材料，缺陷包括多晶材料的晶界。利用绝缘材料层内的晶界作为导电通道，这样沿垂直于存储元件的层叠方向的各个方向，导电通道的尺寸L比较小。
在一种可选的实施方式中，加热电极还包括导电的非连续薄膜层；非连续薄膜层包括多个相互独立的岛状物；非连续薄膜层位于导电通道远离相变材料层的一侧，绝缘材料层将非连续薄膜层中的多个岛状物间隔开，绝缘材料层的厚度大于非连续薄膜层的厚度；其中，导电通道与非连续薄膜层中的岛状物接触。此处，可以通过非连续薄膜层中的岛状物尖端放电击穿绝缘材料层形成导电通道，这样一来，可以使得形成的导电通道沿垂直于存储元件的层叠方向的各个方向的尺寸L比较小。
在一种可选的实施方式中，非连续薄膜层的材料包括镁、铂或铝中的一种或多种。此处，可以根据非连续薄膜层的材料的性质，通过控制化学气相沉积、溅射或喷涂的速率、非连续薄膜层的厚度等工艺参数，以形成非连续薄膜层。
在一种可选的实施方式中，加热电极还包括绝缘的非连续薄膜层；非连续薄膜层包括多个相互独立的岛状物；非连续薄膜层位于绝缘材料层远离相变材料层的一侧，绝缘材料层将非连续薄膜层中的多个岛状物间隔开；其中，导电通道位于岛状物之间，导电通道贯穿绝缘材料层，非连续薄膜层的电阻率大于绝缘材料层的电阻率。此处，可以通过第二电极位于岛状物之间的部分放电击穿绝缘材料层形成导电通道，这样一来，可以使得形成的导电通道沿垂直于存储元件的层叠方向的各个方向的尺寸L比较小。
在一种可选的实施方式中，加热电极还包括设置在绝缘材料层远离相变材料层一侧的导电层；导电层的材料的晶体结构为柱状晶体；其中，导电通道与柱状晶体的端部接触。此处，可以通过柱状晶体的尖端放电击穿绝缘材料层形成导电通道，这样一来，可以使得形成的导电通道沿垂直于存储元件的层叠方向的各个方向的尺寸L比较小。
在一种可选的实施方式中，导电层的材料包括氮化钛。其中，氮化钛的晶体结构为柱状晶体。
在一种可选的实施方式中，绝缘材料层的材料包括氧化镁、氧化锶、氧化铝、氧化钽、氧化钛或氧化铪中的一种或多种。绝缘材料层的材料可以选择一些金属氧化物。
在一种可选的实施方式中，存储单元还包括设置在加热电极远离相变材料层一侧 的第二电极；其中，导电通道与第二电极电连接。存储单元的第一电极与位线电连接，存储单元的第二电极与选通器件电连接。当第二电极上流有电流时，电流会流向加热电极中的导电通道，从而使导电通道产生大量的热，以驱动相变材料层发生相变。
在一种可选的实施方式中，相变存储器还包括：位线、字线以及源极线；存储单元还包括：选通器件；选通器件的第一极与加热电极电连接，选通器件的第二极与源极线电连接；选通器件的第三极与字线电连接，存储单元的第一电极与位线电连接。其中，选通器件例如可以为晶体管或选通管，晶体管例如可以为双极性晶体管、三极管和场效应晶体管等。当选通器件为晶体管时，可以是第一极为源极，第二极为漏极；或者，第一极为漏极，第二极为源极，第三极为栅极。
第二方面，提供一种电子设备，该电子设备包括印刷电路板以及与印刷电路板电连接的相变存储器，相变存储器为上述第一方面提供的相变存储器。由于该电子设备具有与上述相变存储器相同的技术效果，可以参考上述，此处不再赘述。
第三方面，提供一种相变存储器的制作方法，该相变存储器的制作方法包括：首先，在基底上形成阵列分布的多个选通器件；接下来，在基底上形成阵列分布的多个存储元件；存储元件和选通器件一一对应电连接；其中，任意一个存储元件的制作方法，包括：首先，在基底上形成辅助层；接下来，在辅助层上形成相变材料层；接下来，在相变材料层上形成第一电极；接下来，对辅助层施加电流进行初始化，形成加热电极；其中，加热电极包括绝缘材料层和设置在绝缘材料层内由缺陷构成的多个导电通道；导电通道与相变材料层接触。该相变存储器的制作方法具有与上述第一方面提供的相变存储器相同的技术效果，可以参考上述，此处不再赘述。
在一种可选的实施方式中，任意一个存储元件的制作方法，包括：首先，在基底上形成加热电极；接下来，在加热电极上形成相变材料层；接下来，在相变材料层上形成第一电极；其中，加热电极包括绝缘材料层和设置在绝缘材料层内由缺陷构成的多个导电通道；导电通道与相变材料层接触。该存储元件的制作方法具有与上述第一方面提供的相变存储器中的存储元件相同的技术效果，可以参考上述，此处不再赘述。
在一种可选的实施方式中，在基底上形成辅助层，包括：在基底上形成绝缘材料层；对辅助层施加电流进行初始化，形成加热电极，包括：对绝缘材料层施加电流进行初始化，绝缘材料层内的缺陷贯穿绝缘材料层形成导电通道，以形成加热电极。导电通道贯穿绝缘材料层，利用绝缘材料层内的缺陷作为导电通道，由于绝缘材料层内的缺陷的尺寸非常小，约为几个纳米，因而沿垂直于存储元件的层叠方向的各个方向，导电通道的尺寸L非常小，这样一来，加热电极中导电通道与相变材料层的接触面积较小，因此相变材料层中相变区域的体积较小，电流密度较大。基于此，可以在提高相变材料层的相变速度的同时，降低功耗。此外，本实施方式在获得由缺陷构成的导电通道的同时，由于导电通道的制作工艺简单，从而可以降低相变存储器的制作成本。
在一种可选的实施方式中，绝缘材料层的材料为多晶材料；对辅助层施加电流进行初始化，形成加热电极，包括：对绝缘材料层施加电流进行初始化，多晶材料的晶界贯穿绝缘材料层形成导电通道，以形成加热电极。利用绝缘材料层内的晶界作为导电通道，这样沿垂直于存储元件的层叠方向的各个方向上，导电通道的尺寸L比较小。
在一种可选的实施方式中，在基底上形成绝缘材料层，包括：在基底上形成非连 续薄膜层；非连续薄膜层包括多个相互独立的岛状物；对非连续薄膜层进行氧化处理，形成绝缘材料层。这样形成的绝缘材料层的材料为氧化物。
在一种可选的实施方式中，在基底上形成辅助层，包括：在基底上形成导电层；导电层的材料的晶体结构为柱状晶体；在导电层上形成绝缘材料层；对辅助层施加电流进行初始化，形成加热电极，包括：对导电层和绝缘材料层施加电流进行初始化，柱状晶体的尖端放电击穿绝缘材料层，在绝缘材料层内形成导电通道，以形成加热电极；其中，导电通道与柱状晶体的端部接触。由于导电通道是通过柱状晶体的尖端放电击穿绝缘材料层形成的，因而由缺陷构成的导电通道沿垂直于存储元件的层叠方向的各个方向上，导电通道的尺寸非常小，约为几个纳米，这样一来，加热电极中导电通道与相变材料层的接触面积非常小，因此相变材料层中相变区域的体积较小，电流密度较大，因而可以在提高相变材料层的相变速度的同时，降低功耗。
在此基础上，本实施方式在获得由缺陷构成的导电通道的同时，由于导电通道的制作工艺简单，从而可以降低相变存储器的制作成本。
在一种可选的实施方式中，在基底上形成辅助层，包括：在基底上形成导电的非连续薄膜层；非连续薄膜层包括多个相互独立的岛状物；在非连续薄膜层上形成绝缘材料层；其中，绝缘材料层将非连续薄膜层中的多个岛状物间隔开，绝缘材料层的厚度大于非连续薄膜层的厚度；对辅助层施加电流进行初始化，形成加热电极，包括：对非连续薄膜层和绝缘材料层施加电流进行初始化，岛状物尖端放电击穿绝缘材料层，在绝缘材料层内形成导电通道，以形成加热电极；其中，导电通道与非连续薄膜中的岛状物接触。由于导电通道是通过非连续薄膜层中的岛状物尖端放电击穿绝缘材料层形成的，因而沿垂直于存储元件的层叠方向的各个方向上，导电通道的尺寸L非常小，约为几个纳米，这样一来，加热电极中导电通道与相变材料层的接触面积非常小，因此相变材料层中相变区域的体积较小，电流密度较大，因而可以在提高相变材料层的相变速度的同时，降低功耗。
在此基础上，本实施方式在获得由缺陷构成的导电通道的同时，由于导电通道的制作工艺简单，从而可以降低相变存储器的制作成本。
在一种可选的实施方式中，在基底上形成辅助层之前，任意一个存储元件的制作方法还包括：在基底上形成第二电极；加热电极中的导电通道与第二电极电连接。可以参考上述有关第二电极的技术效果的描述，此处不再赘述。
在一种可选的实施方式中，在基底上形成辅助层，包括：在基底上形成绝缘的非连续薄膜层；非连续薄膜层包括多个相互独立的岛状物；在非连续薄膜层上形成绝缘材料层；其中，绝缘材料层将非连续薄膜层中的多个岛状物间隔开；非连续薄膜层的电阻率大于绝缘材料层的电阻率；对辅助层施加电流进行初始化，形成加热电极，包括：对非连续薄膜层和绝缘材料层施加电流进行初始化，第二电极位于岛状物之间的部分放电击穿绝缘材料层，在绝缘材料层内形成导电通道，导电通道贯穿绝缘材料层，以形成加热电极。由于导电通道是第二电极位于岛状物之间的部分放电击穿绝缘材料层形成的，因而沿垂直于存储元件的层叠方向的各个方向上，导电通道的尺寸L非常小，约为几个纳米，这样一来，加热电极中导电通道与相变材料层的接触面积非常小，因此相变材料层中相变区域的体积较小，电流密度较大，因而可以在提高相变材料层的相变 速度的同时，降低功耗。
在此基础上，本实施方式在获得由缺陷构成的导电通道的同时，由于导电通道的制作工艺简单，从而可以降低相变存储器的制作成本。
附图说明
图1为现有技术提供的一种存储单元的结构示意图；
图2为本申请的实施例提供的一种电子设备的结构示意图；
图3为本申请的另一实施例提供的一种电子设备的结构示意图；
图4为本申请的实施例提供的一种相变存储器的结构示意图；
图5为本申请的实施例提供的一种存储元件的结构示意图；
图6为本申请的实施例提供的一种存储元件的制作过程中的结构示意图；
图7为本申请的另一实施例提供的一种存储元件的结构示意图；
图8a为本申请的实施例提供的一种相变材料层或第一电极的结构示意图；
图8b为本申请的另一实施例提供的一种相变材料层或第一电极的结构示意图；
图8c为本申请的又一实施例提供的一种相变材料层或第一电极的结构示意图；
图9为本申请的实施例提供的一种存储元件的制作方法的流程示意图；
图10为本申请的另一实施例提供的一种存储元件的制作过程中的结构示意图；
图11为本申请的实施例提供的一种加热电极的结构示意图；
图12为本申请的另一实施例提供的一种存储元件的制作方法的流程示意图；
图13为本申请的又一实施例提供的一种存储元件的制作过程中的结构示意图；
图14为本申请的又一实施例提供的一种存储元件的结构示意图；
图15为本申请的又一实施例提供的一种存储元件的制作方法的流程示意图；
图16为本申请的又一实施例提供的一种存储元件的制作过程中的结构示意图；
图17为本申请的又一实施例提供的一种存储元件的结构示意图；
图18为本申请的又一实施例提供的一种存储元件的结构示意图；
图19为本申请的又一实施例提供的一种存储元件的制作方法的流程示意图；
图20为本申请的又一实施例提供的一种存储元件的制作过程中的结构示意图。
附图标记：1-电子设备；10-相变存储器；11-存储装置；12-处理器；13-输入设备；14-输出设备；15-中框；16-后壳；17-显示屏；100-存储单元；100A-存储元件；101-加热电极；102-相变材料层；103-第一电极；104-第二电极；105-包覆层；106-辅助层；107-非连续薄膜层；108-导电层；111-外存储器；112-内存储器；121-运算器；122-控制器；150-承载板；151-边框；1011-绝缘材料层；1012-导电通道；1051-包覆材料；1052-凸块。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请实施例中，除非另有明确的规定和限定，术语“电连接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在本申请实施例中，例如上、下、左、右、前和后等用于解释本申请中不同部件的结构和运动的方向指示是相对的。当部件处于图中所示的位置时，这些指示是恰当的。但是，如果元件位置的说明发生变化，那么这些方向指示也将会相应地发生变化。
本申请实施例提供一种电子设备，该电子设备例如可以为手机(mobile phone)、平板电脑(pad)、个人数字助理(personal digital assistant，PDA)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备、充电家用小型电器(例如豆浆机、扫地机器人)、无人机、雷达、航空航天设备和车载设备等不同类型的用户设备或者终端设备；该电子设备还可以为基站等网络设备。本申请实施例对电子设备的具体形式不作特殊限制。
图2为本申请实施例示例性的提供的一种电子设备的架构示意图。如图2所示，该电子设备1包括：存储装置11、处理器12、输入设备13、输出设备14等部件。本领域技术人员可以理解到，图2中示出的电子设备的结构并不构成对该电子设备1的限定，该电子设备1可以包括比如图2所示的部件更多或更少的部件，或者可以组合如图2所示的部件中的某些部件，或者可以与如图2所示的部件布置不同。
存储装置11用于存储软件程序以及模块。存储装置11主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备的使用所创建的数据(比如音频数据、图像数据、电话本等)等。此外，存储装置11包括外存储器111和内存储器112。外存储器111和内存储器112存储的数据可以相互传输。外存储器111例如包括硬盘、U盘、软盘等。内存储器112例如包括随机存储器、只读存储器等。其中，随机存储器例如可以为相变存储器、磁性存储器或铁电存储器等。
处理器12是该电子设备1的控制中心，利用各种接口和线路连接整个电子设备1的各个部分，通过运行或执行存储在存储装置11内的软件程序和/或模块，以及调用存储在存储装置11内的数据，执行电子设备1的各种功能和处理数据，从而对电子设备1进行整体监控。可选的，处理器12可以包括一个或多个处理单元。例如，处理器12可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，飞行 控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。例如，处理器12可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器12中。上述的应用处理器例如可以为中央处理器(central processing unit，CPU)。图2中以处理器12为CPU为例，CPU可以包括运算器121和控制器122。运算器121获取内存储器112存储的数据，并对内存储器112存储的数据进行处理，处理后的结果通常送回内存储器112。控制器122可以控制运算器121对数据进行处理，控制器122还可以控制外存储器置111和内存储器112存储数据或读取数据。
输入设备13用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。示例的，输入设备13可以包括触摸屏以及其他输入设备。触摸屏，也称为触摸面板，可收集用户在触摸屏上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触摸屏上或在触摸屏附近的操作)，并根据预先设定的程式驱动相应的连接装置。可选的，触摸屏可包括触摸检测装置和触摸控制器两个部分。其中，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给处理器12，并能接收处理器12发来的命令并加以执行。此外，可以采用电阻式、电容式、红外线以及表面声波等多种类型实现触摸屏。其他输入设备可以包括但不限于物理键盘、功能键(比如音量控制按键、电源开关按键等)、轨迹球、鼠标、操作杆等中的一种或多种。上述处理器12中的控制器122还可以控制输入设备13接收输入的信号或不接收输入的信号。此外，输入设备13接收到的输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入可以存储在内存储器112中。
输出设备14用于输出输入设备13输入，并存储在内存储器112中的数据对应的信号。例如，输出设备14输出声音信号或视频信号。上述处理器12中的控制器122还可以控制输出设备14输出信号或不输出信号。
需要说明的是，图2中的粗箭头用于表示数据的传输，粗箭头的方向表示数据传输的方向。例如，输入设备13和内存储器112之间的单箭头表示输入设备13接收到的数据向内存储器112传输。又例如，运算器121和内存储器112之间的双箭头表示内存储器112存储的数据可以向运算器121传输，且运算器121处理后的数据可以向内存储器112传输。图2中的细箭头表示控制器122可以控制的部件。示例的，控制器122可以对外存储器置111、内存储器112、运算器121、输入设备13和输出设备14等进行控制。
可选的，如图2所示的电子设备1还可以包括各种传感器。例如陀螺仪传感器、湿度计传感器、红外线传感器、磁力计传感器等，在此不再赘述。可选的，该电子设备1还可以包括无线保真(wireless fidelity，WiFi)模块、蓝牙模块等，在此不再赘述。
可以理解的，本申请实施例中，电子设备(例如上述图2示出的电子设备)可以 执行本申请实施例中的部分或全部步骤，这些步骤或操作仅是示例，本申请实施例还可以执行其它操作或者各种操作的变形。此外，各个步骤可以按照本申请实施例呈现的不同的顺序来执行，并且有可能并非要执行本申请实施例中的全部操作。本申请各实施例可以单独实施，也可以任意组合实施，本申请对此不作限定。
为了方便进一步对电子设备1的结构进行说明，以下以电子设备1为手机为例进行示例性介绍。如图3所示，电子设备1还可以包括中框15、后壳16以及显示屏17。后壳16和显示屏17分别位于中框15的两侧，且中框15和显示屏17设置于后壳16内。中框15包括用于承载显示屏17的承载板150，以及绕承载板150一周的边框151。电子设备1还可以包括设置于承载板150朝向后壳16的表面上的印刷电路板(printed circuit boards，PCB)，电子设备1中的一些电子器件例如上述的相变存储器10可以设置于印刷电路板上；其中，相变存储器10与印刷电路板PCB电连接。
本申请实施例还提供一种相变存储器，该相变存储器可以应用于上述的电子设备1中，例如可以用于作为上述电子设备1中的内部存储器112。
如图4所示，本申请实施例提供的相变存储器10的结构包括：阵列分布的多个存储单元100，存储单元100包括选通器件和与选通器件电连接的存储元件100A。选通器件例如可以为晶体管或选通管，晶体管例如可以为双极性晶体管、三极管和场效应晶体管等。其中，选通器件包括第一极、第二极和第三极。下文以及图4均以选通器件为晶体管T为例进行示意。相变存储器10还包括多条平行排列的字线(word line，WL)和多条平行排列的位线(bit line，BL)，且字线WL与位线BL相互交叉但相互隔离，例如，字线WL与位线BL相互垂直。位线BL与存储元件100A电连接。相变存储器10还包括多条平行排列的源极线(source line，SL)。在一些示例中，源极线SL与位线BL平行。其中，晶体管T包括第一极、第二极和第三极；第一极和第二极作为晶体管导通时的电流流入或流出的接口，第三级是晶体管的控制极(也称为栅极)，比如，第一极为源极，第二极为漏极；或者，第一极为漏极，第二极为源极。晶体管T的栅极与字线WL电连接，晶体管T的第一极与存储元件100A电连接，晶体管T的第二极与源极线SL电连接。
在一些示例中，字线WL还与字线控制电路电连接，通过字线控制电路为字线WL提供高电平信号或低电平信号，以使晶体管T处于导通状态或截止状态。在晶体管T为N型晶体管的情况下，高电平信号控制晶体管T导通，低电平信号控制晶体管T截止。在晶体管T为P型晶体管的情况下，低电平信号控制晶体管T导通，高电平信号控制晶体管T截止。
在一些示例中，位线BL还与位线控制电路电连接，通过位线控制电路为位线BL提供信号。
在一些示例中，源极线SL可以接地。
在一些示例中，参考图4，沿Y方向排列的多个存储单元100中的晶体管T的第二极与同一条源极线SL电连接，沿Y方向排列的多个存储单元100中的存储元件100A与同一条位线BL电连接，沿X方向排列的多个存储单元100中的晶体管T的栅极与同一条字线WL电连接。
以下对上述存储单元100中的存储元件100A的结构进行示例性介绍。
在一种可选的实施例中，如图5所示，上述存储元件100A包括依次层叠设置的加热电极101、相变材料层102和第一电极(也可以称为上电极)103；存储元件100A还包括设置在加热电极101远离相变材料层102一侧的第二电极(也可以称为下电极)104。其中，加热电极101采用刀片式电极结构(wall architecture)。对于刀片式电极结构，参考图5，加热电极101的厚度d远小于加热电极101的宽度W和高度H。
需要说明的是，上述位线BL与存储元件100A电连接，即位线BL与存储元件100A的第一电极103电连接。上述晶体管T的第一极与存储元件100A电连接，即上述晶体管T的第一极与存储元件100A的第二电极104电连接。可以理解的是，第二电极104通过绝缘层上的过孔与晶体管T的第一极电连接。若加热电极101直接通过绝缘层上的过孔与晶体管T的第一极电连接，由于加热电极101下表面的面积较小，因而可能存在加热电极101与绝缘层上的过孔未电连接的风险，进而存在加热电极101与晶体管T的第一极未电连接的风险，这样一来，存储元件100A与晶体管T的第一极可能未电连接。基于此，可以在存储元件100A中设置第二电极104，第二电极104通过绝缘层上的过孔与晶体管T的第一极电连接，从而可以确保存储元件100A与晶体管T的第一极电连接。参考图4，沿Y方向排列的多个存储单元100的存储元件100A中的第一电极103与同一条位线BL电连接。
基于上述存储单元100以及存储单元100中存储元件100A的结构，以下以一个存储单元100为例，对相变存储器10的工作原理进行说明。
存储单元100在写入时，晶体管T处于导通状态，当流经存储元件100A的电流为小电流，长脉冲时，相变材料层102中的相变材料会处于晶化状态，此时存储单元100的电阻较低，可以认为存储单元100存储了第一逻辑信息，第一逻辑信息例如可以用“0”表示；当流经存储元件100A的电流为大电流，短脉冲时，相变材料层102中的相变材料会处于非晶化状态，此时存储单元的电阻较高，可以认为存储单元100存储了第二逻辑信息，第二逻辑信息例如可以用“1”表示。
存储单元100在读取时，恒定的电流从位线BL流经存储元件100A，再到导通的晶体管T的第二极流出，这样一来，在存储元件100A的两端会产生电位差。根据电位差的大小，可以确定存储元件100A的电阻，进而可以判断存储元件100A存储的信息是第一逻辑信息“0”，还是第二逻辑信息“1”。
参考图5，由于加热电极101采用刀片式电极结构，因此加热电极101与相变材料层102的接触面积较小，因而相变区域(也可以称为编程区域)的体积较小，且电流密度较大，这样一来，一方面，相变材料层102发生相变的速度较高；另一方面，可以使得位于相变区域的相变材料层102发生相变所需的电流可以减小，从而可以降低功耗。基于此，在加热电极101采用刀片式电极结构的情况下，由于加热电极101和相变材料的102的接触面积较小，因而可以在提高相变材料层102的相变速度，以提高相变存储器10的读写速度的同时，可以降低功耗。
在一些示例中，图5所示的存储元件100A的制作工艺流程如图6所示,图6中左图为沿平行于层叠方向Z，且平行于X方向的剖面示意图，图6中右图为沿平行于层叠方向Z，且平行于Y方向的剖面示意图。
参考图6，制作如图5所示的存储元件100A，具体包括如下步骤：
首先，形成多个阵列分布的第二电极104，并在第二电极104的周围和上方填充包覆材料1051；接下来，对包覆材料1051进行刻蚀形成多个沿Y方向依次排列，且沿X方向延伸的条状的凸块1052，每个第二电极104的上表面露出于凸块1052之间的间隙。
接下来，生长导电薄膜，并利用光刻工艺对导电薄膜进行刻蚀，以在每个条状的凸块1052的侧面形成导电条，需要说明的是，刻蚀后形成的导电条可能为L型，即导电条可能会由凸块1052的侧面向第二电极104的表面延伸部分；接下来，利用光刻工艺对形成在凸块1052的侧面的导电条进行刻蚀，形成多个加热电极101，一个加热电极101与一个第二电极104对应；接下来，填充包覆材料1051，并磨平直至露出加热电极101。
接下来，在每个加热电极104上形成相变材料层102，沿Y方向排列的多个第二电极104上方的相变材料层102可以电连接在一起；接下来，填充包覆材料1051，并磨平直至露出相变材料层102的上表面；接下来，在每个相变材料层102上形成第一电极103，沿Y方向排列的多个第二电极104上方的第一电极103可以电连接在一起；接下来，填充包覆材料1051。其中，所有的包覆材料1051构成包覆层105。
基于上述存储元件100A的制作流程可知，制作的存储元件100A中的加热电极101为刀片式电极结构。其中，加热电极101的厚度d可以通过控制生长的导电薄膜的厚度决定，生长的导电薄膜的厚度最小可以达到十几个纳米左右，在一些示例中，加热电极101的厚度最小可以做到10nm～15nm。加热电极101沿X方向的宽度(wall width)W可以通过光刻工艺控制。加热电极101与相变材料层102的接触面积由加热电极101的厚度d和加热电极101沿X方向的宽度W决定。在形成导电薄膜时，由于通过控制生长工艺可以使得导电薄膜的厚度较小，从而可以控制形成的加热电极101的厚度较小，进而可以使得加热电极101与相变材料层102的接触面积较小。
然而，虽然可以通过控制生长工艺，控制导电薄膜的厚度较小，进而控制加热电极101的厚度d制作的较小，但是加热电极101沿X方向的宽度W是由光刻工艺控制的，基于光刻工艺，加热电极101沿X方向的宽度W很难进一步微缩，光刻工艺控制的加热电极101沿X方向的宽度W通常在10nm以上。在加热电极101的厚度d为10nm～15nm的情况下，在加热电极101沿X方向的宽度W为30nm时，使相变材料层102发生相变所需的电流为100μA左右；在加热电极101沿X方向的宽度W为45nm时，使相变材料层102发生相变所需的电流为180μA左右。由于光刻工艺限制了加热电极101沿X方向的宽度W很难进一步微缩，因此加热电极101与相变材料层102接触的面积很难进一步微缩，因而电流密度无法进一步增加，这样一来，相变材料层102的相变速度无法进一步提高，且功耗无法进一步降低。
基于上述，为了进一步提高相变材料层102的相变速度，且进一步降低功耗，本申请实施例还提供一种存储元件100A，存储元件100A的结构如图7所示，包括依次层叠设置的第二电极104、加热电极101、相变材料层102和第一电极103；加热电极101包括绝缘材料层1011和设置在绝缘材料层1011内由缺陷(defect)构成的多个导电通道1012，导电通道1012与相变材料层102接触，且导电通道1012与第二电极104电连接。
需要说明的是，相变存储器10的工作原理与上述相同，可以参考上述，此处不再赘述。
此处，绝缘材料层1011的材料可以是晶体，也可以是非晶体。在绝缘材料层1011的材料为晶体的情况下，绝缘材料层1011的材料可以是单晶材料，也可以是多晶材料。
在此基础上，绝缘材料层1011内的缺陷例如可以包括位错、晶界、空位(例如氧空位)(hole)、或金属丝等。应当理解到，当绝缘材料层1011内的缺陷在导电通道1012所在位置处达到一定浓度时，便可以形成导电通道1012。
另外，可以理解的是，导电通道1012包括但不限于由一种类型的缺陷构成，导电通道1012可以由多种类型的缺陷构成。例如，导电通道1012可以由晶界构成。又例如，导电通道1012可以由晶界、空位、位错等构成。
在一些示例中，当与导电通道1012的两端中至少一端接触的材料为活泼金属时，上述缺陷可以包括金属丝。在另一些示例中，当与导电通道1012的两端接触的材料为非活泼金属时，例如，与导电通道1012的一端接触的材料为铂(pt)，与导电通道1012的另一端接触的材料为氮化钛(TiN)时，上述缺陷可以包括位错、晶界或空位等。
可以理解的是，由于导电通道1012由缺陷构成，因而导电通道1012沿垂直于存储元件100A的层叠方向Z的各个方向上的尺寸较小。在一些示例中，如图7所示，导电通道1012沿垂直于存储元件100A的层叠方向Z的各个方向(即沿平行于相变材料层102的各个方向)上的尺寸L的范围为0＜L≤10nm，即导电通道1012的径向尺寸L的范围为0＜L≤10nm。
此处，沿垂直于存储元件100A的层叠方向Z的各个方向上，导电通道1012的尺寸L例如可以为1nm、3nm、5nm、8nm或10nm等。
此外，对于加热电极101中的导电通道1012的数量不进行限定，可以根据需要进行设置。
在此基础上，加热电极101中的导电通道1012可以直的，也可以是弯曲的。导电通道1012可以垂直于第二电极104设置，也可以相对于第二电极104倾斜设置。不同的导电通道1012之间可以相交，也可以不相交。
上述相变材料层102的材料应具有相变特性。在一些示例中，相变材料层102的材料可以为GeTe(锗碲)合金、Sb2Te5(锑碲)合金或Ge2Sb2Te5(锗锑碲)合金中的一种或多种。其中，Ge2Sb2Te5合金可以简称为GST，GST是目前相变存储器10中应用最广泛的一种相变材料。
在一些示例中，第一电极103的材料和第二电极104的材料例如可以包括铜(Cu)、银(Ag)、铝(Al)、金(Au)中的一种或多种。此外，第一电极103和第二电极104可以为单层结构，也可以为多层结构。
应当理解到，在相变存储器10中，多个存储元件100A中的第二电极104相互独立，多个存储元件100A中的加热电极101相互独立。在此基础上，在一些示例中，如图8a所示，多个存储元件100A中的相变材料层102相互独立；在另一些示例中，如图8b所示，多个存储元件100A中的相变材料层102电连接在一起，即多个相变材料层102构成整层结构；在又一些示例中，如图8c所示，沿Y方向排列的多个存储元件100A中的相变材料层102电连接在一起，即多个相变材料层102构成多个条状结构。
此外，在一些示例中，如图8a所示，多个存储元件100A中的第一电极103相互独立；在另一些示例中，如图8b所示，多个存储元件100A中的第一电极103电连接在一起，即多个第一电极103构成整层结构；在又一些示例中，如图8c所示，沿Y方向排列的多个存储元件100A中的第一电极103电连接在一起，即多个第一电极103构成多个条状结构。
本申请实施例提供一种相变存储器10，相变存储器10的存储单元100包括依次层叠设置的第二电极104、加热电极101、相变材料层102和第一电极103，由于加热电极101包括绝缘材料层1011和设置在绝缘材料层1011内由缺陷构成的多个导电通道1012，加热电极101中起导电作用的是导电通道1012，而导电通道1012由缺陷构成，因而导电通道1012沿垂直于存储元件100A的层叠方向Z的各个方向上的尺寸较小，例如沿垂直于存储元件100A的层叠方向Z的各个方向上，导电通道1012的尺寸L的范围可以为0＜L≤10nm，这样一来，多个导电通道1012与相变材料层102的接触面积较小，即加热电极101中起导电作用的部分与相变材料层102的接触面积较小，而导电通道1012与相变材料层102的接触面积越小，相变材料层102中相变区域的体积越小，且电流密度越大。相变材料层102中相变区域的体积越小，电流密度越大，一方面，可以提高相变材料层102发生相变的速度，进而提高相变存储器10的读写速度；另一方面，可以使得相变材料层102发生相变的所需的电流可以减小，这样一来，可以降低功耗。基于此，本申请实施例，可以在提高相变材料层102的相变速度，以提高相变存储器10的读写速度的同时，降低功耗。
相对于加热电极101为刀片式电极结构，由于本申请实施例提供的存储单元100中的加热电极101中起导电作用的是导电通道1012，而导电通道1012由缺陷构成，因而导电通道1012沿垂直于存储元件100A的层叠方向Z的各个方向上的尺寸较小，因此本申请实施例提供的加热电极101中导电通道1012与相变材料层102的接触面积更小，因而相对于刀片式电极结构，本申请实施例可以进一步提高相变材料层102的相变速度，且进一步降低功耗。
本申请实施例还提供一种相变存储器的制作方法，包括：
在基底上形成阵列分布的多个选通器件；接下来，在基底上形成阵列分布的多个存储元件100A，选通器件与存储元件100A一一对应电连接，一个存储元件100A和与其电连接的一个选通器件构成一个存储单元100。此处，选通器件的类型可以参考上述，此处不再赘述。
其中，任意一个存储单元100中存储元件100A的制作方法，例如任意一个如图7所示的存储单元100中存储元件100A的制作方法，如图9所示，可以包括如下步骤：
S10、如图10所示，在基底105上形成第二电极104。
此处，基底105可以是半导体基底，例如硅(Si)基底、锗(Ge)基底、氮化镓(GaN)基底、砷化鎵(GaAs)基底；也可以是玻璃(glass)基底或包括有机材料的基底等。
在一些示例中，在基底105上形成第二电极104，包括：首先，在基底105上形成导电薄膜；接下来，对导电薄膜进行构图工艺形成第二电极104。此处，可以采用化学气相沉积法(chemical vapor deposition，CVD)、溅射法或喷涂法等方法形成导电薄膜。构图工艺包括涂覆光刻胶、掩膜曝光、显影以及刻蚀等工艺。
另外，第二电极104可以是单层结构，也可以是多层结构。第二电极104的材料可以参考上述实施例，此处不再赘述。
S11、如图10所示，在第二电极104上形成辅助层106。
S12、如图10所示，在辅助层106上形成相变材料层102。
此处，相变材料层102的材料可以参考上述实施例，此处不再赘述。
在一些示例中，可以采用化学气相沉积法、溅射法或喷涂法等方法形成相变材料层102。
S13、如图10所示，在相变材料层102上形成第一电极103。
在一些示例中，在相变材料层102上形成第一电极103，包括：首先，在相变材料层102上形成导电薄膜；接下来，对导电薄膜进行构图工艺形成第一电极103。此处，可以采用化学气相沉积法、溅射法或喷涂法等方法形成导电薄膜。构图工艺包括涂覆光刻胶、掩膜曝光、显影以及刻蚀等工艺。
此处，第一电极103可以单层结构，也可以是多层结构。第一电极103的材料可以参考上述实施例，此处不再赘述。
S14、如图10所示，对辅助层106施加电流进行初始化，形成加热电极101；其中，加热电极101包括绝缘材料层1011和设置在绝缘材料层1011内由缺陷构成的多个导电通道1012；导电通道1012与相变材料层102接触，且导电通道1012与第二电极104电连接。
此处，缺陷的类型可以参考上述，此处不再赘述。
由于导电通道1012由缺陷构成，因而导电通道1012沿垂直于存储元件100A的层叠方向Z的各个方向上的尺寸较小。在一些示例中，导电通道1012沿垂直于存储元件100A的层叠方向Z的各个方向上的尺寸L的范围为0＜L≤10nm。
在一些示例中，沿垂直于存储元件100A的层叠方向Z的各个方向上，导电通道1012的尺寸L例如可以为1nm、3nm、5nm、8nm或10nm等。
应当理解到，可以通过位线BL给第一电极103施加电压，通过源极线SL给第二电极105施加电压，从而给辅助层106施加电流进行初始化。可以理解的是，对辅助层106进行初始化时，施加的电流应较大。
此处，对于加热电极101中的导电通道1012的数量不进行限定，可以根据需要进行设置。
此外，加热电极101中的导电通道1012可以直的，也可以是弯曲的。导电通道1012可以垂直于第二电极104设置，也可以相对于第二电极104倾斜设置。不同导电通道1012之间可以相交，也可以不相交。
在一种可选的实施例中，上述任意一个存储单元100中存储元件100A的制作方法，例如任意一个如图7所示的存储单元100中存储元件100A的制作方法，还可以包括如下步骤：
S20、在基底105上形成第二电极104。
需要说明的是，步骤S20可以参考上述步骤S10，此处不再赘述。
S21、在第二电极104上形成加热电极101；其中，加热电极101包括绝缘材料层1011和设置在绝缘材料层1011内由缺陷构成的多个导电通道1012；导电通道1012与 第二电极104电连接。
需要说明的是，导电通道1012的尺寸L、数量以及导电通道1012的形态可以参考上述步骤S14，此处不再赘述。
S22、在加热电极101上形成相变材料层102；导电通道1012与相变材料层102接触。
需要说明的是，步骤S22可以参考上述步骤S12，此处不再赘述。
S23、在相变材料层102上形成第一电极103。
需要说明的是，步骤S23可以参考上述步骤S13，此处不再赘述。
可以理解的是，上述相变存储器10中的任意一个存储单元100中的存储元件100A均可以采用步骤S10～步骤S14或步骤S20～步骤S23提供的存储元件100A的制作方法制作得到。此外，相变存储器10中的多个存储单元元件100A可以同时制作得到。
可以理解的是，上述步骤S10～步骤S14或步骤S20～步骤S23提供的相变存储器的制作方法具有与上述相变存储器10相同的技术效果，可以参考上述有关相变存储器10的技术效果的描述，此处不再赘述。
以下提供几个具体的实施例，对存储单元100中存储元件100A的结构以及存储元件100A的制作方法进行示例性介绍。
实施例一
实施例一提供的存储元件100A的结构如图7所示，包括：依次层叠设置的第二电极104、加热电极101、相变材料层102和第一电极103；加热电极101包括绝缘材料层1011和设置在绝缘材料层1011内由缺陷构成的多个导电通道1012，导电通道1012贯穿绝缘材料层1011，导电通道1012与相变材料层102接触，且导电通道1012与第二电极104电连接。
此处，缺陷的类型、尺寸等可以参考上述，此处不再赘述。
在一些示例中，绝缘材料层1011的材料为多晶材料，上述构成导电通道1012的缺陷包括多晶材料的晶界。
应当理解到，在绝缘材料层1011的材料为多晶材料的情况下，绝缘材料层1011的材料包括晶界。图11为加热电极1011的俯视图，从图11可以看出，绝缘材料层1011包括多个晶界。
在一些示例中，绝缘材料层1011的材料包括氧化镁(MgO)、氧化锶(SrO)、氧化铝(Al 2O 3)、氧化钽(TaO x)、氧化钛(TiO 2)或氧化铪(HfO 2)中的一种或多种。
在本实施例一中，导电通道1012贯穿绝缘材料层1011，利用绝缘材料层1011内的缺陷作为导电通道1012，由于绝缘材料层1011内的缺陷例如晶界的尺寸非常小，约为几个纳米，因而沿垂直于存储元件100A的层叠方向Z的各个方向，导电通道1012的尺寸L非常小，这样一来，加热电极101中导电通道1012与相变材料层102的接触面积较小，因此相变材料层102中相变区域的体积较小，电流密度较大。基于此，可以在提高相变材料层102的相变速度的同时，降低功耗。
本实施例一还提供一种存储元件100A的制作方法，可以用于制作上述实施例一提供的存储元件100A，存储元件100A的制作方法，如图12所示，包括如下步骤：
S100、如图13所示，在基底105上形成第二电极104。
需要说明的是，步骤S100可以参考上述步骤S10，此处不再赘述。
S101、如图13所示，在第二电极104上形成非连续薄膜层107；非连续薄膜层107包括多个相互独立的岛状物。
此处，可以采用化学气相沉积法、溅射法或喷涂法等方法形成非连续薄膜层107。
需要说明的是，可以根据非连续薄膜层107的材料的性质，通过控制化学气相沉积、溅射或喷涂的速率、非连续薄膜层107的厚度等工艺参数，以形成非连续薄膜层107。
在一些示例中，非连续薄膜层107的材料包括镁(Mg)、锶(Sr)或铝(Al)中的一种或多种。
应当理解到，为了确保能够形成非连续薄膜层107，因此非连续薄膜层107的厚度不能太大，在一些示例中，非连续薄膜层107的厚度h的范围为0＜h≤8nm。
例如，非连续薄膜层107的厚度h可以为1nm、3nm、5nm或8nm等。
S102、如图13所示，对非连续薄膜层107进行氧化处理，形成绝缘材料层1011。
此处，绝缘材料层1011的材料可以是晶体，也可以是非晶体。在绝缘材料层1011的材料为晶体的情况下，绝缘材料层1011的材料可以是单晶材料，也可以是多晶材料。
示例的，绝缘材料层1011的材料可以为氧化镁、氧化锶或氧化铝中的一种或多种。
可以理解的是，在步骤S102中形成的绝缘材料层1011，此时，绝缘材料层1011内的缺陷可以贯穿绝缘材料层1011，也可以未贯穿绝缘材料层1011。示例的，绝缘材料层1011的材料为多晶材料，绝缘材料层1011内的缺陷包括晶界。此时，绝缘材料层1011的多个晶界可以贯穿绝缘材料层1011，也可以未贯穿绝缘材料层1011。
此外，在一些示例中，对非连续薄膜层107进行氧化处理后，形成的绝缘材料层1011是连续的。
S103、如图13所示，在绝缘材料层1011上形成相变材料层102
需要说明的是，步骤S103可以参考上述步骤S12，此处不再赘述。
S104、如图13所示，在相变材料层102上形成第一电极103。
需要说明的是，步骤S104可以参考上述步骤S13，此处不再赘述。
S105、如图13所示，对绝缘材料层1011施加电流进行初始化，绝缘材料层1011内的缺陷贯穿绝缘材料层1011形成导电通道1012，以形成加热电极101。其中，加热电极101包括绝缘材料层1011和设置在绝缘材料层1011内由缺陷构成的多个导电通道1012；导电通道1012与相变材料层102接触，且导电通道1012与第二电极104电连接。
在一些示例中，绝缘材料层1011的材料为多晶材料；对绝缘材料层1011施加电流进行初始化，多晶材料的晶界贯穿绝缘材料层1011形成导电通道1012，以形成加热电极101。
应当理解到，可以通过位线BL给第一电极103施加电压，通过源极线SL给第二电极105施加电压，从而给绝缘材料层1011施加电流进行初始化。可以理解的是，对绝缘材料层1011进行初始化时，施加的电流应较大，这样绝缘材料层1011内的缺陷才可以贯穿绝缘材料层1011，从而可以形成导电通道1012。
需要说明的是，虽然步骤S102中形成的绝缘材料层1011内包括缺陷例如晶界，但是这些缺陷例如晶界可能未贯穿绝缘材料层1011，对绝缘材料层1011施加电流进行初始化后，缺陷例如晶界可以贯穿绝缘材料层1011，从而可以形成导电通道1012。
此处，导电通道1012的尺寸L、数量以及导电通道1012的形态可以参考上述步骤 S14，此处不再赘述。
基于上述可知，通过步骤S101和步骤S102可以形成绝缘材料层1011。在一些示例中，还可以直接在第二电极104上直接形成绝缘材料层1011。
基于上述步骤S100～步骤S105可知，本实施例一在获得由缺陷构成的导电通道1012的同时，由于导电通道1012的制作工艺简单，从而可以降低相变存储器10的制作成本。
实施例二
实施例二和实施例一的区别在于，加热电极101的结构不相同。
实施例二提供的存储元件100A的结构如图14所示，包括：依次层叠设置的第二电极104、加热电极101、相变材料层102和第一电极103；加热电极101包括绝缘材料层1011和设置在绝缘材料层1011内由缺陷构成的多个导电通道1012，导电通道1012与相变材料层102接触，且导电通道1012与第二电极104电连接；加热电极101还包括导电的非连续薄膜层107；非连续薄膜层107包括多个相互独立的岛状物；非连续薄膜层107位于导电通道1012远离相变材料层102的一侧，绝缘材料层1011将非连续薄膜层107中的多个岛状物间隔开，绝缘材料层1011的厚度大于非连续薄膜层107的厚度；导电通道1012与非连续薄膜层107中的岛状物接触。
需要说明的是，非连续薄膜层107中的岛状物可以向靠近相变材料层102的一侧凸起，也可以向远离相变材料层102的一侧凸起。
此处，缺陷的类型、尺寸等可以参考上述，此处不再赘述。
此外，绝缘材料层1011的材料可以参考上述实施例一，此处不再赘述。
在一些示例中，非连续薄膜层107的材料可以包括镁(Mg)、铂(pt)或铝(Al)中的一种或多种。
在一些示例中，绝缘材料层1011的材料为非连续薄膜层107的材料的氧化物，例如，绝缘材料层1011的材料为氧化镁，非连续薄膜层107的材料为镁。在另一些示例中，绝缘材料层1011的材料为除非连续薄膜层107的材料以外的其它金属的氧化物。例如，绝缘材料层1011的材料为氧化钽，非连续薄膜层107的材料为镁。
需要说明的是，当绝缘材料层1011的材料为非连续薄膜层107的材料的氧化物时，则加热电极101中有可能不能清楚地分辨出非连续薄膜层107中岛状物的边界。当绝缘材料层1011的材料为除非连续薄膜层107的材料以外的其它金属的氧化物，则加热电极101中可以分辨出非连续薄膜层107中岛状物的边界。
实施例二还提供一种存储元件100A的制作方法，例如可以用于制作如图14所示的存储元件100A，该存储元件100A的制作方法，如图15所示，包括如下步骤：
S200、如图16所示，在基底105上形成第二电极104。
需要说明的是，步骤S200可以参考上述步骤S10，此处不再赘述。
S201、如图16所示，在第二电极104上形成导电的非连续薄膜层107；非连续薄膜层107包括多个相互独立的岛状物。
此处，导电的非连续薄膜层107的材料可以参考上述，此处不再赘述。
此外，可以采用化学气相沉积法、溅射法或喷涂法等方法形成非连续薄膜层107。
需要说明的是，可以根据非连续薄膜层107的材料的性质，通过控制化学气相沉积、 溅射或喷涂的速率、非连续薄膜层107的厚度等工艺参数，以形成非连续薄膜层107。
应当理解到，为了确保能够形成非连续薄膜层107，因此非连续薄膜层107的厚度不能太大，在一些示例中，非连续薄膜层107的厚度h的范围为0＜h≤8nm。
例如，非连续薄膜层107的厚度h可以为1nm、3nm、5nm或8nm等。
可以理解的是，由于非连续薄膜层107是导电的，因此非连续薄膜层107中的岛状物也是导电的。
S202、如图16所示，在非连续薄膜层107上形成绝缘材料层1011；其中，绝缘材料层1011将非连续薄膜层107中的多个岛状物间隔开，绝缘材料层1011的厚度大于非连续薄膜层107的厚度。
此处，绝缘材料层1011的材料可以参考上述，此处不再赘述。
需要说明的是，可以采用化学气相沉积法、溅射法或喷涂法等方法形成绝缘材料层1011。
S203、如图16所示，在绝缘材料层1011上形成相变材料层102。
需要说明的是，步骤S203可以参考上述步骤S12，此处不再赘述。
S204、如图16所示，在相变材料层102上形成第一电极103。
需要说明的是，步骤S204可以参考上述步骤S13，此处不再赘述。
S205、如图16所示，对非连续薄膜层107和绝缘材料层1011施加电流进行初始化，岛状物尖端放电击穿绝缘材料层1011，在绝缘材料层1011内形成由缺陷构成的导电通道1012，形成加热电极101；导电通道1012与非连续薄膜层107中的岛状物接触，且与相变材料层102接触。
可以理解的是，岛状物尖端放电击穿绝缘材料层1011时，会在绝缘材料层1011内形成缺陷，缺陷可以构成导电通道1012。
此处，导电通道1012的尺寸L、数量以及导电通道1012的形态可以参考上述步骤S14，此处不再赘述。
应当理解到，可以通过位线BL给第一电极103施加电压，通过源极线SL给第二电极105施加电压，从而给非连续薄膜层107和绝缘材料层1011施加电流进行初始化，以使岛状物尖端放电击穿绝缘材料层1011，以形成导电通道1012。为了确保岛状物尖端放电能够击穿绝缘材料层1011，因而施加的电流应较大。
可以理解的是，由于岛状物的顶端距离绝缘材料层1011远离第二电极104的表面的距离较小，因而岛状物的顶端处易于击穿绝缘材料层1011，形成导电通道1012。
此处，岛状物可以向靠近相变材料层102的一侧凸起，也可以向远离相变材料层102的一侧凸起。在岛状物向靠近相变材料层102的一侧凸起的情况下，岛状物的顶端更易于放电击穿绝缘材料层1011，形成导电通道1012。
在本实施例二中，由于导电通道1012是通过非连续薄膜层107中的岛状物尖端放电击穿绝缘材料层1011形成的，因而由缺陷构成的导电通道1012沿垂直于存储元件100A的层叠方向Z的各个方向上，导电通道的尺寸L非常小，约为几个纳米，这样一来，加热电极101中导电通道1012与相变材料层102的接触面积非常小，因此相变材料层102中相变区域的体积较小，电流密度较大，因而可以在提高相变材料层102的相变速度的同时，降低功耗。
在此基础上，本实施例二在获得由缺陷构成的导电通道1012的同时，由于导电通道1012的制作工艺简单，从而可以降低相变存储器10的制作成本。
实施例三
实施例三和实施一、实施例二的区别之处，加热电极101的结构不相同。
实施例二提供的存储元件100A的结构如图17所示，包括：依次层叠设置的第二电极104、加热电极101、相变材料层102和第一电极103；加热电极101包括绝缘材料层1011和设置在绝缘材料层1011内由缺陷构成的多个导电通道1012，导电通道1012与相变材料层102接触，且导电通道1012与第二电极104电连接；加热电极101还包括绝缘的非连续薄膜层107；非连续薄膜层107包括多个相互独立的岛状物；非连续薄膜层107位于绝缘材料层1011远离相变材料层102的一侧，绝缘材料层1011将非连续薄膜层107中的多个岛状物间隔开；其中，导电通道1012位于岛状物之间，导电通道1012贯穿绝缘材料层1011，非连续薄膜层107的电阻率大于绝缘材料层1011的电阻率。
由于非连续薄膜层107的电阻率大于绝缘材料层1011的电阻率，因而非连续薄膜层107的绝缘性能比绝缘材料层1011的绝缘性能更好。
需要说明的是，非连续薄膜层107中的岛状物可以向靠近相变材料层102的一侧凸起，也可以向远离相变材料层102的一侧凸起。
此处，绝缘材料层1011的厚度可以大于或等于非连续薄膜层107的厚度。
在一些示例中，非连续薄膜层107和绝缘材料层1011的材料可以包括氧化钽、氧化钛、氧化镁、氧化铝、氧化锶或氧化铪中的一种或多种。
实施例三还提供一种存储元件100A的制作方法，实施例三提供的存储元件100A的制作方法与实施例二提供的存储单元100A的制作方法相似，不同之处在于步骤S201、步骤S202和步骤S205。
在实施例三中，可以将实施例二中的步骤S201替换为步骤S300，将实施例二中的步骤S202替换为步骤S301，将实施例二中的步骤S205替换为步骤S302，其它步骤相同。
S300、在第二电极104上形成绝缘的非连续薄膜层107；非连续薄膜层107包括多个相互独立的岛状物。
此处，绝缘的非连续薄膜层107的材料可以参考上述，此处不再赘述。
此外，非连续薄膜层107的形成方法、厚度等可以参考上述步骤S201。
步骤S201中形成的非连续薄膜层107是导电的，步骤S300中形成的非连续薄膜层107是绝缘的。
S301、在非连续薄膜层107上形成绝缘材料层1011；其中，绝缘材料层1011将非连续薄膜层107中的多个岛状物间隔开；非连续薄膜层107的电阻率大于绝缘材料层1011的电阻率。
此处，绝缘材料层1011的厚度可以大于或等于非连续薄膜层107的厚度。
此外，绝缘材料层1011的材料可以参考上述，此处不再赘述。绝缘材料层1011的形成方法可以参考步骤S202，此处不再赘述。
步骤S202中，由于非连续薄膜层107是导电的，因此绝缘材料层1011的电阻率大于非连续薄膜层107的电阻率，而步骤S301中，非连续薄膜层107的电阻率大于绝缘材 料层1011的电阻率。
S302、如图17所示，对非连续薄膜层107和绝缘材料层1011施加电流进行初始化，第二电极104位于岛状物之间的部分放电击穿绝缘材料层1011，在绝缘材料层1011内形成由缺陷构成的导电通道1012，导电通道1012贯穿绝缘材料层1011，形成加热电极101。
可以理解的是，第二电极104位于岛状物之间的部分放电击穿绝缘材料层1011时，会在绝缘材料层1011内形成缺陷，缺陷可以构成导电通道1012。
此处，导电通道1012的尺寸L、数量以及导电通道1012的形态可以参考上述步骤S14，此处不再赘述。
应当理解到，可以通过位线BL给第一电极103施加电压，通过源极线SL给第二电极105施加电压，从而给非连续薄膜层107和绝缘材料层1011施加电流进行初始化，以使第二电极104位于岛状物之间的部分放电击穿绝缘材料层1011，在绝缘材料层1011内形成导电通道1012。为了确保第二电极104位于岛状物之间的部分放电能够击穿绝缘材料层1011，因而施加的电流应较大。
需要说明的是，由于非连续薄膜层107的电阻率大于绝缘材料层1011的电阻率，因而施加电流时，第二电极104位于岛状物之间的部分易于放电击穿绝缘材料层1011，以形成导电通道1012。
在本实施例三中，由于导电通道1012是第二电极104位于岛状物之间的部分放电击穿绝缘材料层1011形成的，因而由缺陷构成的导电通道1012沿垂直于存储元件100A的层叠方向Z的各个方向上，导电通道的尺寸L非常小，约为几个纳米，这样一来，加热电极101中导电通道1012与相变材料层102的接触面积非常小，因此相变材料层102中相变区域的体积较小，电流密度较大，因而可以在提高相变材料层102的相变速度的同时，降低功耗。
在此基础上，本实施例三在获得由缺陷构成的导电通道1012的同时，由于导电通道1012的制作工艺简单，从而可以降低相变存储器10的制作成本。
实施例四
实施例四和实施例一、实施例二、实施例三的区别之处，加热电极101的结构不相同。
实施例四提供的存储元件100A的结构如图18所示，包括：依次层叠设置的第二电极104、加热电极101、相变材料层102和第一电极103；加热电极101包括绝缘材料层1011和设置在绝缘材料层1011内由缺陷构成的多个导电通道1012，导电通道1012与相变材料层102接触，且导电通道1012与第二电极104电连接；加热电极101还包括设置在绝缘材料层1011远离相变材料层102一侧的导电层108；导电层108的材料的晶体结构为柱状晶体；其中，导电通道1012与柱状晶体的端部接触。
应当理解到，由于导电层108的材料的晶体结构为柱状晶体，而导电层108上设置有绝缘材料层1011，因而在导电层108上形成绝缘材料层1011时，参考图18，绝缘材料层1011中的绝缘材料会填充在导电层108的柱状晶体之间。
需要说明的是，柱状晶体的生长方向与存储元件100A中多个层的层叠方向Z相同。
此处，缺陷的类型、尺寸、绝缘材料层1011的材料等可以参考上述，此处不再赘述。
在一些示例中，导电层108的材料包括氮化钛(TiN)。氮化钛的晶体结构为柱状晶体。
实施例四还提供一种存储元件100A的制作方法，例如可以用于制作如图18所示的存储元件100A，该存储元件100A的制作方法，如图19所示，包括如下步骤：
S400、如图20所示，基底105上形成第二电极104。
需要说明的是，步骤S400可以参考上述步骤S10，此处不再赘述。
S401、如图20所示，在第二电极104上形成导电层108；导电层108的材料的晶体结构为柱状晶体。
在一些示例中，导电层108的材料包括氮化钛。
此处，示例的，可以利用物理气相沉积的方法生长形成导电层108。
S402、如图20所示，在导电层108上形成绝缘材料层1011。
此处，绝缘材料层1011的材料可以参考上述，此处不再赘述。
需要说明的是，可以采用化学气相沉积法、溅射法或喷涂法等方法形成绝缘材料层1011。
可以理解的是，由于导电层108的材料的晶体结构为柱状晶体，因而形成绝缘材料层1011时，绝缘材料层1011中的绝缘材料会填充在导电层108的柱状晶体之间。
S403、如图20所示，在绝缘材料层1011上形成相变材料层102。
需要说明的是，步骤S403可以参考上述步骤S12，此处不再赘述。
S404、如图20所示，在相变材料层102上形成第一电极103。
需要说明的是，步骤S404可以参考上述步骤S13，此处不再赘述。
S405、如图20所示，对导电层108和绝缘材料层1011施加电流进行初始化，柱状晶体的尖端放电击穿绝缘材料层1011，在绝缘材料层1011内形成由缺陷构成的导电通道1012，以形成加热电极101；其中，导电通道1012与柱状晶体的端部接触。
可以理解的是，柱状晶体的尖端放电击穿绝缘材料层1011时，会在绝缘材料层1011内形成缺陷，缺陷可以构成导电通道1012。
此处，导电通道1012的尺寸L、数量以及导电通道1012的形态可以参考上述步骤S14，此处不再赘述。
需要说明的是，由于导电层108的晶体结构为柱状晶体，因而给导电层108施加电流时，柱状晶体的尖端会放电。
应当理解到，可以通过位线BL给第一电极103施加电压，通过源极线SL给第二电极105施加电压，从而给导电层108和绝缘材料层1011施加电流进行初始化，以使柱状晶体的尖端放电击穿绝缘材料层1011，以形成导电通道1012。为了确保柱状晶体的尖端放电能够击穿绝缘材料层1011，因而施加的电流应较大。
在本实施例四中，由于导电通道1012是通过柱状晶体的尖端放电击穿绝缘材料层1011形成的，因而由缺陷构成的导电通道1012沿垂直于存储元件100A的层叠方向Z的各个方向上，导电通道的尺寸L非常小，约为几个纳米，这样一来，加热电极101中导电通道1012与相变材料层102的接触面积非常小，因此相变材料层102中相变区域的 体积较小，电流密度较大，因而可以在提高相变材料层102的相变速度的同时，降低功耗。
在此基础上，本实施例四在获得由缺陷构成的导电通道的同时，由于导电通道1012的制作工艺简单，从而可以降低相变存储器10的制作成本。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种相变存储器，其特征在于，包括阵列分布的多个存储单元，所述存储单元包括：依次层叠设置的加热电极、相变材料层和第一电极；
    所述加热电极包括绝缘材料层和设置在所述绝缘材料层内由缺陷构成的多个导电通道，所述导电通道与所述相变材料层接触。
  2. 根据权利要求1所述的相变存储器，其特征在于，所述导电通道贯穿所述绝缘材料层。
  3. 根据权利要求2所述的相变存储器，其特征在于，所述绝缘材料层的材料为多晶材料，所述缺陷包括所述多晶材料的晶界。
  4. 根据权利要求1所述的相变存储器，其特征在于，所述加热电极还包括导电的非连续薄膜层；所述非连续薄膜层包括多个相互独立的岛状物；
    所述非连续薄膜层位于所述导电通道远离所述相变材料层的一侧，所述绝缘材料层将所述非连续薄膜层中的多个所述岛状物间隔开，所述绝缘材料层的厚度大于所述非连续薄膜层的厚度；
    其中，所述导电通道与所述非连续薄膜层中的所述岛状物接触。
  5. 根据权利要求4所述的相变存储器，其特征在于，所述非连续薄膜层的材料包括镁、铂或铝中的一种或多种。
  6. 根据权利要求1所述的相变存储器，其特征在于，所述加热电极还包括绝缘的非连续薄膜层；所述非连续薄膜层包括多个相互独立的岛状物；
    所述非连续薄膜层位于所述绝缘材料层远离所述相变材料层的一侧，所述绝缘材料层将所述非连续薄膜层中的多个所述岛状物间隔开；
    其中，所述导电通道位于所述岛状物之间，所述导电通道贯穿所述绝缘材料层，所述非连续薄膜层的电阻率大于所述绝缘材料层的电阻率。
  7. 根据权利要求1所述的相变存储器，其特征在于，所述加热电极还包括设置在所述绝缘材料层远离所述相变材料层一侧的导电层；所述导电层的材料的晶体结构为柱状晶体；
    其中，所述导电通道与所述柱状晶体的端部接触。
  8. 根据权利要求7所述的相变存储器，其特征在于，所述导电层的材料包括氮化钛。
  9. 根据权利要求1-8任一项所述的相变存储器，其特征在于，所述绝缘材料层的材料包括氧化镁、氧化锶、氧化铝、氧化铪、氧化钛或氧化钽中的一种或多种。
  10. 根据权利要求1-9任一项所述的相变存储器，其特征在于，所述存储单元还包括设置在所述加热电极远离所述相变材料层一侧的第二电极；
    其中，所述导电通道与所述第二电极电连接。
  11. 根据权利要求1-10任一项所述的相变存储器，其特征在于，所述相变存储器还包括：位线、字线以及源极线；
    所述存储单元还包括：选通器件；所述选通器件的第一极与所述加热电极电连接，所述选通器件的第二极与所述源极线电连接；所述选通器件的第三极与所述字线电连接，
    所述存储单元的所述第一电极与所述位线电连接。
  12. 一种电子设备，包括印刷电路板以及与所述印刷电路板电连接的相变存储器，其 特征在于，所述相变存储器为如权利要求1-11任一项所述的相变存储器。
  13. 一种相变存储器的制作方法，其特征在于，包括：在基底上形成阵列分布的多个选通器件；
    在所述基底上形成阵列分布的多个存储元件；所述存储元件和所述选通器件一一对应电连接；
    其中，任意一个所述存储元件的制作方法，包括：
    在所述基底上形成辅助层；
    在所述辅助层上形成相变材料层；
    在所述相变材料层上形成第一电极；
    对所述辅助层施加电流进行初始化，形成加热电极；其中，所述加热电极包括绝缘材料层和设置在所述绝缘材料层内由缺陷构成的多个导电通道；所述导电通道与所述相变材料层接触。
  14. 根据权利要求13所述的制作方法，其特征在于，所述在所述基底上形成辅助层，包括：在所述基底上形成绝缘材料层；
    所述对所述辅助层施加电流进行初始化，形成加热电极，包括：对所述绝缘材料层施加电流进行初始化，所述绝缘材料层内的缺陷贯穿所述绝缘材料层形成所述导电通道，以形成所述加热电极。
  15. 根据权利要求14所述的制作方法，其特征在于，所述绝缘材料层的材料为多晶材料；
    所述对所述辅助层施加电流进行初始化，形成加热电极，包括：对所述绝缘材料层施加电流进行初始化，所述多晶材料的晶界贯穿所述绝缘材料层形成所述导电通道，以形成所述加热电极。
  16. 根据权利要求14或15所述的制作方法，其特征在于，所述在所述基底上形成绝缘材料层，包括：
    在所述基底上形成非连续薄膜层；所述非连续薄膜层包括多个相互独立的岛状物；
    对所述非连续薄膜层进行氧化处理，形成绝缘材料层。
  17. 根据权利要求13所述的制作方法，其特征在于，所述在所述基底上形成辅助层，包括：
    在所述基底上形成导电层；所述导电层的材料的晶体结构为柱状晶体；
    在所述导电层上形成绝缘材料层；
    所述对所述辅助层施加电流进行初始化，形成加热电极，包括：对所述导电层和所述绝缘材料层施加电流进行初始化，所述柱状晶体的尖端放电击穿所述绝缘材料层，在所述绝缘材料层内形成所述导电通道，以形成所述加热电极；其中，所述导电通道与所述柱状晶体的端部接触。
  18. 根据权利要求13所述的制作方法，其特征在于，所述在所述基底上形成辅助层，包括：在所述基底上形成导电的非连续薄膜层；所述非连续薄膜层包括多个相互独立的岛状物；
    在所述非连续薄膜层上形成绝缘材料层；其中，所述绝缘材料层将所述非连续薄膜层中的多个所述岛状物间隔开，所述绝缘材料层的厚度大于所述非连续薄膜层的厚度；
    所述对所述辅助层施加电流进行初始化，形成加热电极，包括：对所述非连续薄膜层和所述绝缘材料层施加电流进行初始化，所述岛状物尖端放电击穿所述绝缘材料层，在所述绝缘材料层内形成导电通道，以形成所述加热电极；其中，所述导电通道与所述非连续薄膜中的所述岛状物接触。
  19. 根据权利要求13-18任一项所述的制作方法，其特征在于，所述在所述基底上形成辅助层之前，所述任意一个所述存储元件的制作方法还包括：
    在所述基底上形成第二电极；所述加热电极中的所述导电通道与所述第二电极电连接。
  20. 根据权利要求19所述的制作方法，其特征在于，所述在所述基底上形成辅助层，包括：在所述基底上形成绝缘的非连续薄膜层；所述非连续薄膜层包括多个相互独立的岛状物；
    在所述非连续薄膜层上形成绝缘材料层；其中，所述绝缘材料层将所述非连续薄膜层中的多个所述岛状物间隔开；所述非连续薄膜层的电阻率大于所述绝缘材料层的电阻率；
    所述对所述辅助层施加电流进行初始化，形成加热电极，包括：对所述非连续薄膜层和所述绝缘材料层施加电流进行初始化，所述第二电极位于所述岛状物之间的部分放电击穿所述绝缘材料层，在所述绝缘材料层内形成导电通道，所述导电通道贯穿所述绝缘材料层，以形成所述加热电极。
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CN1602550A (zh) * 2001-12-12 2005-03-30 松下电器产业株式会社 非易失性存储器
TW200802840A (en) * 2006-06-15 2008-01-01 Ind Tech Res Inst Phase-change memory cell structures and methods for fabricating the same
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WO2020159214A1 (ko) * 2019-01-29 2020-08-06 한양대학교 산학협력단 다결정 금속 산화물층을 포함하는 선택소자 및 이를 포함하는 크로스포인트 메모리

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