WO2022104742A1 - 一种铁电存储器及电子设备 - Google Patents

一种铁电存储器及电子设备 Download PDF

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WO2022104742A1
WO2022104742A1 PCT/CN2020/130620 CN2020130620W WO2022104742A1 WO 2022104742 A1 WO2022104742 A1 WO 2022104742A1 CN 2020130620 W CN2020130620 W CN 2020130620W WO 2022104742 A1 WO2022104742 A1 WO 2022104742A1
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electrode
ferroelectric memory
ferroelectric
voltage
memory cell
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PCT/CN2020/130620
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English (en)
French (fr)
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江安全
杨喜超
张岩
江钧
汪超
魏侠
秦健鹰
Original Assignee
华为技术有限公司
复旦大学
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Application filed by 华为技术有限公司, 复旦大学 filed Critical 华为技术有限公司
Priority to CN202080104665.0A priority Critical patent/CN116472581A/zh
Priority to PCT/CN2020/130620 priority patent/WO2022104742A1/zh
Publication of WO2022104742A1 publication Critical patent/WO2022104742A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

Definitions

  • the present application relates to the technical field of ferroelectric memory, and in particular, to a ferroelectric memory and an electronic device.
  • Ferroelectric random access memory also known as "ferroelectric memory”.
  • ferroelectric memory also known as "ferroelectric memory”.
  • the disadvantage of traditional ferroelectric memory is the destructive readout of information, and the size scaling is limited.
  • the size of the planar structure can only be reduced to 130 nm.
  • conductive-domain-wall ferroelectric random access memory DW-FRAM for short
  • the principle of DW-FRAM storing data is that under the action of an electric field, the ferroelectric in DW-FRAM When there are two regions with different polarization directions (also known as electric domains) in the material, the interface between the electric domain and the electric domain forms a ferroelectric domain wall, and the ferroelectric domain wall has conductivity; under the action of an electric field, When the ferroelectric materials in DW-FRAM have the same polarization direction, the ferroelectric domain wall disappears, and the ferroelectric memory can be stored as logical information (“0” or “1”) based on the generation and disappearance of the ferroelectric domain wall data.
  • the cross-bar array structure includes a plurality of first voltage lines and a plurality of second voltage lines that cross each other.
  • a ferroelectric memory element is disposed at the intersection of a first voltage line and a second voltage line, and the ferroelectric memory element includes a ferroelectric thin film layer and a read-write electrode pair in contact with the ferroelectric memory thin film layer. It is found that there is a natural interface layer on the surface of the ferroelectric thin film layer in DW-FRAM near the read-write electrode pair, which can serve as a natural selection tube.
  • the turn-on voltage Von also called threshold voltage Vth, that is, the threshold voltage value for insulating and conducting the ferroelectric memory element
  • Vth threshold voltage
  • the coercive voltage of ferroelectric memory elements gradually decreases.
  • the read voltage Vread should be greater than the turn-on voltage Von and less than the coercive voltage Vc. Since the turn-on voltage Von is fixed, it is limited In order to reduce the coercive voltage and the read voltage, the write voltage should be greater than the coercive voltage. In this way, the reduction of the read and write voltage of the ferroelectric memory element is limited, which is not conducive to the reduction of power consumption.
  • Embodiments of the present application provide a ferroelectric memory and an electronic device for adjusting the turn-on voltage of a ferroelectric memory element.
  • a ferroelectric memory in a first aspect, includes a first voltage line, a second voltage line and a ferroelectric memory element; the ferroelectric memory element includes a ferroelectric thin film layer disposed on a substrate; the ferroelectric thin film layer includes a ferroelectric thin film layer that protrudes to a side away from the substrate storage unit; the ferroelectric storage element also includes a first electrode and a second electrode oppositely arranged on both sides of the ferroelectric storage unit; the first electrode is in contact with the first surface and the side surface of the ferroelectric storage unit, and the second electrode is in contact with the ferroelectric storage unit The first surface and/or the side surface of the memory cell is in contact; the first surface is the surface of the ferroelectric memory cell away from the substrate; wherein the first electrode is electrically connected to the first voltage line; the second electrode is electrically connected to the second voltage line .
  • the first electrode Since the first electrode is in contact with the first surface and the side surface of the ferroelectric memory cell, when the first logic information "1" is written and the first write voltage is applied, the part of the ferroelectric memory cell close to the first electrode is formed with the ferroelectric memory cell.
  • the oppositely polarized domains of the portion of the thin film layer close to the substrate, after removing the first write voltage, the domain wall between the oppositely polarized domains in the ferroelectric thin film layer intersects with the first surface of the ferroelectric memory cell , and does not intersect the second electrode.
  • the turn-on voltage Von of the ferroelectric memory element is related to the distance ⁇ L between the intersection point T where the domain wall intersects with the first surface of the ferroelectric memory cell and the second electrode along the opposite direction of the first electrode and the second electrode.
  • the size of the distance L between the first electrode and the second electrode can be adjusted by ⁇ L, and then the turn-on voltage Von can be adjusted, thereby realizing the adjustment of the turn-on voltage of the ferroelectric memory element.
  • adjusting the turn-on voltage Von is equivalent to adjusting the resistance value of the ferroelectric thin film layer away from the substrate surface, so the readout current can be increased by adjusting the turn-on voltage Von, thereby making the ferroelectric memory element read faster.
  • the coercive voltage Vc of the ferroelectric memory element gradually decreases.
  • the turn-on voltage Von of the ferroelectric memory element can be reduced, so that the read voltage can be greater than the turn-on voltage Von and smaller than the coercive voltage Vc of the ferroelectric memory element, so the existing The problem of limiting the reduction of the coercive voltage Vc in the technology.
  • the read and write voltages are also reduced accordingly, thereby reducing power consumption.
  • the length L1 of the first electrode in contact with the first surface of the ferroelectric memory cell is greater than the length L1 of the second electrode and the first surface of the ferroelectric memory cell Contact length L2. Since L1 is greater than L2, by adjusting L1 and L2, the ferroelectric memory element can be changed from writing the first logic information "1" to the coercive voltage Vc that needs to be overcome to write the second logic information "0" and make the ferroelectric memory element
  • the storage element 20 needs to overcome the same coercive voltage Vc from writing the second logic information "0" to writing the first logic information "1", so as to realize the symmetrical adjustment of the positive and negative coercive voltages. In this way, Ferroelectric memory elements store logical information for longer periods of time.
  • the length L1 of the first electrode in contact with the first surface of the ferroelectric memory cell is 0 ⁇ L1 ⁇ 500nm.
  • the length L2 of the second electrode in contact with the first surface of the ferroelectric memory cell is 0 ⁇ L2 ⁇ 100 nm.
  • the distance L between the first electrode and the second electrode is 0 ⁇ L ⁇ 500 nm.
  • the distance between the intersection of the domain wall and the first surface of the ferroelectric memory cell and the second electrode can be adjusted along the opposite direction of the first electrode and the second electrode when the first logic information is written. ⁇ L, thereby realizing the adjustable turn-on voltage Von of the ferroelectric memory element.
  • the ferroelectric thin film layer includes a conductive thin film layer; wherein, the conductive thin film layer is located on the surface of the ferroelectric thin film layer away from the substrate. Since the ferroelectric thin film layer includes a conductive thin film layer located on the surface of the ferroelectric thin film layer away from the substrate, the coercive voltage of the ferroelectric memory element can be reduced and the read current can be increased.
  • the thickness h of the ferroelectric thin film layer is in the range of 5nm ⁇ h ⁇ 10um.
  • the ferroelectric memory cell located between the first electrode and the second electrode.
  • the width d of at least one of the portion, the first electrode and the second electrode is in the range of 5 nm ⁇ d ⁇ 10 ⁇ m. If the width d is too large, it is not conducive to the miniaturization of the ferroelectric memory element, and the number of ferroelectric memory elements included in the ferroelectric memory decreases, that is, the density of the ferroelectric memory element included in the ferroelectric memory decreases. If the width d is too small, the current flowing through the first electrode and the second electrode will be small. Based on this, the range of the width d is set to 5nm ⁇ d ⁇ 10 ⁇ m, so that the influence caused by the width being too large or too small can be avoided.
  • an electronic device in a second aspect, includes a circuit board and a ferroelectric memory electrically connected to the circuit board; wherein, the ferroelectric memory is the above-mentioned ferroelectric memory.
  • the electronic device has the same technical effects as the foregoing embodiments, which will not be repeated here.
  • a data writing method is provided, and the data writing method is used in the above-mentioned ferroelectric memory.
  • the data writing method comprises: applying a first writing voltage between the first voltage line and the second voltage line, so that the part of the ferroelectric memory cell close to the first electrode forms polarization with the part of the ferroelectric thin film layer close to the substrate.
  • the domains with opposite directions, the domain walls between domains with opposite polarization directions in the ferroelectric thin film layer intersect with the second electrode; after the first write voltage is removed, the domain walls move towards the direction close to the first electrode, and the domain walls move toward the first electrode.
  • the wall intersects the first surface of the ferroelectric memory cell and does not intersect the second electrode to write the first logic information; a second write voltage is applied between the first voltage line and the second voltage line to make the ferroelectric
  • the polarization directions of the thin film layers are the same to write the second logic information; wherein, the direction of the first write voltage is opposite to the direction of the second write voltage.
  • the distance ⁇ L between the intersection point T where the domain wall intersects with the first surface of the ferroelectric memory cell and the second electrode will affect the ferroelectric memory
  • the turn-on voltage Von of the element can be adjusted by adjusting the size of the distance L between the first electrode and the second electrode, and ⁇ L can be adjusted, thereby adjusting the turn-on voltage Von, thereby realizing the regulation of the turn-on voltage of the ferroelectric memory element.
  • the intersection point between the domain wall and the first surface of the ferroelectric memory cell and the second electrode is 0 ⁇ L ⁇ 500nm.
  • the distance ⁇ L of the ferroelectric memory element can be adjusted by adjusting the distance ⁇ L between the intersection point T where the domain wall intersects the first surface of the ferroelectric memory cell and the second electrode along the opposite direction of the first electrode and the second electrode. Turn-on voltage Von.
  • the distance between the domain wall and the first surface of the ferroelectric memory cell intersects The distance ⁇ L between the intersection point and the second electrode.
  • a data reading method is provided, and the data reading method is used in the above-mentioned ferroelectric memory.
  • the data reading method includes: applying a reading voltage between a first voltage line and a second voltage line, and judging the part of the ferroelectric memory cell close to the first electrode according to the magnitude of the current on the first voltage line or the second voltage line Whether the polarization direction of the ferroelectric memory cell is reversed to form a domain wall, so as to read the logic information stored in the ferroelectric memory cell; the direction of the read voltage is the same as the direction of the write voltage when the ferroelectric memory cell generates the domain wall.
  • the first electrode, the second electrode and the domain wall form a conductive path.
  • the current value on the first voltage line or the second voltage line is read to be larger, it can be determined that the ferroelectric memory cell is close to the first voltage line.
  • the polarization direction of the part of the electrode is reversed, and domain walls are formed in the ferroelectric thin film layer, that is, it can be determined that the ferroelectric memory element stores the first logic information.
  • FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • 3a is a schematic structural diagram of a ferroelectric memory provided by an embodiment of the application.
  • 3b is a schematic structural diagram of a ferroelectric memory according to another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a ferroelectric memory according to another embodiment of the present application.
  • FIG. 5a is a schematic structural diagram of a ferroelectric memory element provided by an embodiment of the present application.
  • 5b is a schematic structural diagram of a ferroelectric memory element provided by another embodiment of the present application.
  • 5c is a schematic structural diagram of a ferroelectric memory element provided by another embodiment of the present application.
  • FIG. 6 is a schematic top-view structure diagram of a first electrode, a second electrode, and a ferroelectric memory cell according to an embodiment of the present application;
  • FIG. 7a is a schematic top-view structural diagram of a first electrode, a second electrode, and a ferroelectric memory cell according to another embodiment of the present application;
  • Fig. 7b is the topography of Fig. 7a observed under the scanning electron microscope
  • FIG. 8 is a schematic structural diagram of a ferroelectric memory element according to still another embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a ferroelectric memory element according to another embodiment of the present application.
  • FIG. 10 is a graph showing the relationship between the turn-on voltage Von and L according to an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a ferroelectric memory element according to another embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a ferroelectric memory according to still another embodiment of the present application.
  • 16 is a schematic structural diagram of a ferroelectric memory according to another embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a ferroelectric memory according to another embodiment of the present application.
  • 01-electronic equipment 10-ferroelectric memory; 11-memory; 12-processor; 13-input device; 14-output device; 15-middle frame; 16-back shell; 17-display screen; 20-ferroelectric storage Element; 100-ferroelectric memory element array; 101-insulation layer; 111-external memory; 112-internal memory; 121-calculator; 122-controller; 150-carrying board; 151-frame; 200-substrate; 201- 202-first electrode; 203-second electrode; 2011-ferroelectric memory cell; 2011a-domain wall.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated; It can also be indirectly connected through an intermediary.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • module generally refers to a functional structure divided according to logic, and the “module” may be implemented by pure hardware, or by a combination of software and hardware.
  • and/or describes the association relationship of the associated objects, indicating that there can be three kinds of relationships. For example, A and/or B can indicate that A exists alone, B exists alone, and there are three kinds of A and B at the same time. a situation.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • Embodiments of the present application provide an electronic device.
  • the electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a TV, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (virtual reality, VR) terminal device, an augmented reality (augmented reality), AR) terminal equipment and other electronic products.
  • a smart wearable product for example, a smart watch, a smart bracelet
  • VR virtual reality
  • AR augmented reality
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • FIG. 1 is a schematic structural diagram of an electronic device according to an exemplary embodiment of the present application.
  • the electronic device 01 includes: a memory 11 , a processor 12 , an input device 13 , an output device 14 and other components.
  • the structure of the electronic device shown in FIG. 1 does not constitute a limitation to the electronic device 01, and the electronic device 01 may include more or less components than those shown in FIG. 1 , Either some of the components shown in FIG. 1 may be combined, or the components may be arranged differently than those shown in FIG. 1 .
  • the memory 11 is used to store software programs and modules.
  • the memory 11 mainly includes a stored program area and a stored data area, wherein the stored program area can store an operating system, an application program (such as a sound playback function, an image playback function, etc.) required for at least one function; Data created by the use of the device (such as audio data, image data, phone book, etc.), etc.
  • the memory 11 includes an external memory 111 and an internal memory 112 . Data stored in the external memory 111 and the internal memory 112 can be transferred to each other.
  • the external storage 111 includes, for example, a hard disk, a U disk, a floppy disk, and the like.
  • the internal memory 112 includes, for example, random access memory, read-only memory, and the like.
  • the random access memory may be, for example, a ferroelectric random access memory, hereinafter referred to as a ferroelectric memory.
  • the processor 12 is the control center of the electronic device 01, using various interfaces and lines to connect various parts of the entire electronic device 01, by running or executing the software programs and/or modules stored in the memory 11, and calling the stored in the memory 11. Execute various functions of the electronic device 01 and process data, so as to monitor the electronic device 01 as a whole.
  • the processor 12 may include one or more processing units.
  • the processor 12 may include an application processor (AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (ISP), a flight controller, Video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (neural-network processing unit, NPU), etc.
  • different processing units may be independent devices, or may be integrated in one or more processors.
  • the processor 12 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface and application programs, and the like, and the modem processor mainly handles wireless communication.
  • the above-mentioned modulation and demodulation processor may not be integrated into the processor 12 .
  • the above-mentioned application processor may be, for example, a central processing unit (central processing unit, CPU).
  • CPU central processing unit
  • the processor 12 is taken as an example of a CPU, and the CPU may include an arithmetic unit 121 and a controller 122 .
  • the arithmetic unit 121 acquires the data stored in the internal memory 112 and processes the data stored in the internal memory 112 , and the processed result is usually sent back to the internal memory 112 .
  • the controller 122 can control the arithmetic unit 121 to process data, and the controller 122 can also control the external memory 111 and the internal memory 112 to store or read data.
  • the input device 13 is used for receiving input numerical or character information, and generating key signal input related to user setting and function control of the electronic device.
  • the input device 13 may include a touch screen and other input devices.
  • a touch screen also known as a touch panel, collects the user's touch operations on or near the touch screen (such as the user's operations on or near the touch screen with a finger, a stylus, or any suitable object or accessory), and performs pre-set operations on or near the touch screen. program to drive the corresponding connection device.
  • the touch screen may include two parts, a touch detection device and a touch controller.
  • the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and then sends it to the touch controller.
  • the processor 12 can receive commands from the processor 12 and execute them.
  • touch screens can be implemented such as resistive, capacitive, infrared, and surface acoustic waves.
  • Other input devices may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control keys, power switch keys, etc.), trackballs, mice, joysticks, and the like.
  • the controller 122 in the above-mentioned processor 12 can also control the input device 13 to receive the input signal or not to receive the input signal.
  • inputted numerical or character information received by the input device 13 and input of key signals generated related to user settings and function control of the electronic device may be stored in the internal memory 112 .
  • the output device 14 is used to output the signal corresponding to the data input by the input device 13 and stored in the internal memory 112 .
  • the output device 14 outputs a sound signal or a video signal.
  • the controller 122 in the above-mentioned processor 12 may also control the output device 14 to output a signal or not to output a signal.
  • the thick arrows in FIG. 1 are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission.
  • a single arrow between input device 13 and internal memory 112 indicates that data received by input device 13 is transferred to internal memory 112 .
  • the double arrow between the calculator 121 and the internal memory 112 indicates that the data stored in the internal memory 112 can be transferred to the calculator 121 , and the data processed by the calculator 121 can be transferred to the internal memory 112 .
  • the thin arrows in FIG. 1 indicate components that the controller 122 can control.
  • the controller 122 can control the external memory 111, the internal memory 112, the arithmetic unit 121, the input device 13, the output device 14, and the like.
  • the electronic device 01 shown in FIG. 1 may further include various sensors.
  • a gyroscope sensor for example, a hygrometer sensor, an infrared sensor, a magnetometer sensor, etc.
  • the electronic device may further include a wireless fidelity (wireless fidelity, WiFi) module, a Bluetooth module, and the like, which are not described herein again.
  • an electronic device may perform some or all of the steps in the embodiment of the present application. These steps or operations are only examples, and the embodiment of the present application may also Perform other operations or variants of various operations. In addition, various steps may be performed in different orders presented in the embodiments of the present application, and may not be required to perform all the operations in the embodiments of the present application. Each embodiment of the present application may be implemented independently or in any combination, which is not limited in this application.
  • the electronic device 01 may further include a middle frame 15 , a rear case 16 and a display screen 17 .
  • the rear case 16 and the display screen 17 are respectively located on two sides of the middle frame 15 , and the middle frame 15 and the display screen 17 are arranged in the rear case 16 .
  • the middle frame 15 includes a carrier board 150 for carrying the display screen 17 , and a frame 151 surrounding the carrier board 150 .
  • the electronic device 01 may also include a circuit board disposed on the surface of the carrier board 150 facing the rear case 16, such as a printed circuit board (printed circuit boards, PCB) and some electronic devices disposed on the circuit board, such as the above-mentioned ferroelectric Memory 10; wherein, the ferroelectric memory 10 is electrically connected to the circuit board.
  • a circuit board disposed on the surface of the carrier board 150 facing the rear case 16, such as a printed circuit board (printed circuit boards, PCB) and some electronic devices disposed on the circuit board, such as the above-mentioned ferroelectric Memory 10; wherein, the ferroelectric memory 10 is electrically connected to the circuit board.
  • the embodiment of the present application further provides a ferroelectric memory 10, the ferroelectric memory 10 includes a substrate and at least one layer of a ferroelectric memory element array 100 disposed on the substrate.
  • ferroelectric memory 10 includes a layer of ferroelectric memory element array 100 disposed on a substrate.
  • the ferroelectric memory 10 includes a multi-layer ferroelectric memory element array 100 arranged on a substrate and arranged in sequence (FIG. 3b shows that the ferroelectric memory 10 includes a three-layer ferroelectric memory element array.
  • the ferroelectric memory 10 further includes an insulating layer 101 disposed between two adjacent layers of ferroelectric storage element arrays 100, and the insulating layer 101 can separate the two adjacent layers of ferroelectric storage element arrays 100 open.
  • the direction in which the multilayer ferroelectric memory element array 100 is sequentially arranged may be perpendicular to the substrate, or may be parallel to the substrate.
  • the structure of the ferroelectric memory 10 is exemplarily introduced below by taking the ferroelectric memory 10 including the one-layer ferroelectric memory element array 100 as an example.
  • the ferroelectric memory 10 includes the multilayer ferroelectric memory element arrays 100 arranged in sequence, each layer of the ferroelectric memory element array 100 in the multilayer ferroelectric memory element array 100 has the same structure as the ferroelectric memory 10 including a layer of iron
  • the structure of the ferroelectric storage element array 100 is the same.
  • the ferroelectric memory 10 (or each layer of the ferroelectric memory element array 100) includes a substrate, a plurality of first voltage lines m and a plurality of second voltage lines n, and a plurality of intersecting first voltage lines m and a plurality of second voltage lines n disposed on the substrate.
  • ferroelectric memory element 20 FIG. 3 a takes a plurality of first voltage lines m extending in the row direction and a plurality of second voltage lines n extending in the column direction as an example.
  • each row of ferroelectric storage elements 20 is electrically connected to a first voltage line m
  • each column of ferroelectric storage elements 20 is electrically connected to a second voltage line n.
  • the ferroelectric memory 10 provided by the embodiment of the present application has a crossbar structure.
  • the ferroelectric memory 10 (or each layer of the ferroelectric memory element array 100 ) further includes a plurality of row address lines (A0, A1 . . . Ai-2, Ai-1) and a plurality of column address lines (Ai, Ai) that cross each other +1...An-1, An).
  • each row of ferroelectric storage elements 20 is electrically connected to one row address line
  • each column of ferroelectric storage elements 20 is electrically connected to one column address line.
  • the connection relationship between the row address lines and the column address lines and the plurality of ferroelectric memory elements 20 is not shown in FIG. 4 .
  • the ferroelectric memory 10 further includes a read/write controller, a row address decoder and a column address decoder.
  • the above-mentioned first voltage line m and second voltage line n are both electrically connected to the read-write controller.
  • the above-mentioned plurality of row address lines are all electrically connected to the row address decoder, and the above-mentioned plurality of column address lines are all electrically connected to the column address decoder.
  • the read/write controller further includes a charge pump, which is used to enable the selected ferroelectric memory element 20 to obtain a relatively high write rate during data writing. input voltage.
  • the working principle of the ferroelectric memory 10 will be introduced below with reference to FIG. 4 .
  • the processor for managing the ferroelectric memory 10 controls the row address decoder and the column address decoder to address based on the location where the data is to be stored, and selects the ferroelectric memory to be written.
  • the ferroelectric storage element 20a in FIG. 4 is selected.
  • the read/write controller applies a write voltage Vw to the first voltage line m and the second voltage line n connected to the ferroelectric memory element 20a, the applied write voltage Vw is greater than the coercive voltage Vc of the ferroelectric memory element, and the write voltage
  • the direction is bipolar, that is, positive or negative, so that the polarization direction of the ferroelectric storage element 20 is reversed or the polarization direction is restored, so as to control the generation or disappearance of the ferroelectric domain wall in the ferroelectric storage element 20a, so as to increase the ferroelectric storage element 20a.
  • the element 20a writes logic information "1" or logic information "0".
  • the processor for managing the ferroelectric memory 10 controls the row address decoder and the column address decoder to perform addressing based on the location where the data to be read is stored, and selects the data to be read.
  • the ferroelectric memory element 20a in FIG. 4 is selected.
  • the read-write controller applies the read voltage Vr to the first voltage line m and the second voltage line n connected to the ferroelectric memory element 20a.
  • the applied read voltage Vr is smaller than the coercive voltage Vc of the ferroelectric storage element 20, but greater than the turn-on voltage Von of the ferroelectric storage element 20.
  • the direction of the read voltage Vr corresponds to the write voltage corresponding to the generation of ferroelectric domain walls when writing data.
  • the direction of the read voltage Vr is the same as the direction of the initial polarization, that is to say, the direction of the read voltage Vr is opposite to the initial polarization direction.
  • the output amplifier can read the current value flowing on the first voltage line m or the second voltage line n in real time. If the current value is greater than the preset reference value, the first logic information is read. For example, the first logic information is logic information "1". At this time, it can be determined that the ferroelectric storage element 20a stores the first logic information. If the current value is less than the preset reference value, the second logic information is read, and the second logic information is, for example, logic information "0". At this time, it can be determined that the ferroelectric storage element 20a stores the second logic information.
  • the ferroelectric memory element 20 includes a ferroelectric thin film layer 201 disposed on a substrate 200 ;
  • the ferroelectric storage element 20 also includes a first electrode 202 and a second electrode 203 disposed on both sides of the ferroelectric storage unit 2011; the first electrode 202 is in contact with the first surface and the side surface of the ferroelectric storage unit 2011, and the second The electrode 203 is in contact with the first surface and/or the side surface of the ferroelectric memory cell 2011; the first surface is the surface of the ferroelectric memory cell 2011 parallel to the substrate 200 and away from the substrate 200; wherein the first electrode 202 is connected to the first voltage line m is electrically connected; the second electrode 203 is electrically connected to the second voltage line n.
  • FIG. 5a, 5b and 5c are cross-sectional views of the ferroelectric memory element 20 in FIG. 4 along the aa direction.
  • the ferroelectric memory cell 2011 is illustrated with a dashed box in Figures 5a, 5b and 5c.
  • the "first surface is the surface of the ferroelectric memory cell 2011 parallel to the substrate 200 and away from the substrate 200" in the above-mentioned "parallel to the substrate 200" means parallel to the surface in contact with the substrate 200 and the ferroelectric thin film layer 201 .
  • the second electrode 203 is in contact with the first surface of the ferroelectric memory cell 2011; it may also be as shown in FIG. 5b, the second electrode 203 is in contact with the side surface of the ferroelectric memory cell 2011 contact; of course, as shown in FIG. 5 c , the second electrode 203 is in contact with both the first surface and the side surface of the ferroelectric memory cell 2011 .
  • the second surface of the ferroelectric thin film layer 201 that is, the surface of the ferroelectric thin film layer 201 away from the substrate 200 includes the first surface and the side surface of the ferroelectric memory cell 2011 , and the first surface and the ferroelectric memory cell 2011 . other surfaces than the sides.
  • the first electrode 202 and the second electrode 203 may or may not be in contact with other surfaces of the second surface of the ferroelectric thin film layer 201 except the first surface and the side surface of the ferroelectric memory cell 2011.
  • the first electrode 202 and the second electrode 203 are oppositely disposed on both sides of the ferroelectric memory cell 2011, that is, the ferroelectric memory cell 2011 separates the first electrode 202 and the second electrode 203, and the first electrode 202 and the second electrode 203 are independent of each other and do not touch.
  • the materials of the first electrode 202 and the second electrode 203 include platinum (Pt), aluminum (Al), chromium (Cr), titanium (Ti), gold (Au), Cu (copper), W ( tungsten), titanium nitride (TiN), polysilicon, compounds of silicon and metals, strontium ruthenate (SrRuO 3 ), niobium-doped strontium titanate (Nb: SrTiO 3 ), niobium oxide (Nb 2 O 5 ), nickel One or more of (Ni), cobalt (Co), ruthenium (Ru), ruthenium dioxide (RuO 2 ), iridium (Ir), and iridium dioxide (IrO 2 ).
  • the first electrode 202 and the second electrode 203 may be a single-layer structure or a multi-layer structure, and each layer structure may be selected from one or more of the above-mentioned materials.
  • the first electrode 202 and the second electrode 203 are fabricated simultaneously.
  • the specific manufacturing process may be, for example, firstly forming a layer of conductive film; then patterning the conductive film, and simultaneously forming the first electrode 202 and the second electrode 203 .
  • the first electrode 202 and the second electrode 203 are separately fabricated. In this case, the first electrode 202 may be fabricated first, and then the second electrode 203 may be fabricated; or the second electrode 203 may be fabricated first, and then the first electrode 202 may be fabricated.
  • first electrode 202 and second electrode 203 may also be referred to as a read-write electrode pair.
  • the length L1 of the first electrode 202 in contact with the first surface of the ferroelectric memory cell 2011 is 0 ⁇ L1 ⁇ 500nm .
  • L1 may be 5 nm, 60 nm, 100 nm, 300 nm, or 500 nm, or the like.
  • the length L2 of the second electrode 203 in contact with the first surface of the ferroelectric memory cell 2011 is 0 ⁇ L2 ⁇ 100nm .
  • L2 may be 0, 10 nm, 50 nm, 80 nm, 100 nm, and the like.
  • the second electrode 203 is only in contact with the side surface of the ferroelectric memory cell 2011 , and does not contact with the first surface of the ferroelectric memory cell 2011 .
  • the distance L between the first electrode 202 and the second electrode 203 is 0 ⁇ L ⁇ 500nm.
  • L may be 5 nm, 10 nm, 50 nm, 100 nm, or 500 nm, or the like.
  • the distance L between the first electrode 202 and the second electrode 203 may pass the length of the first electrode 202 in contact with the first surface of the ferroelectric memory cell 2011
  • the length L2 of L1 and the second electrode 203 in contact with the first surface of the ferroelectric memory cell 2011 is adjusted.
  • the length L1 of the contact between the first electrode 202 and the first surface of the ferroelectric memory cell 2011 can be selected first, and then by adjusting the second electrode 203
  • the length L2 in contact with the first surface of the ferroelectric memory cell 2011 adjusts the distance L between the first electrode 202 and the second electrode 203 .
  • the ferroelectric memory cell 2011 is located in the The portion between the first electrode 202 and the second electrode 203 and the width d of at least one of the first electrode 202 and the second electrode 203 are in the range of 5 nm ⁇ d ⁇ 10 ⁇ m.
  • the above-mentioned width d is in the range of 5 nm ⁇ d ⁇ 500 nm.
  • the shape of the first surface of the ferroelectric memory cell 2011 is not limited.
  • the shape of the first surface is a rectangle, and the first surface is located on the first electrode 202 and the second electrode 203
  • the shape of the part in between is also rectangular.
  • the shape of the first surface is an irregular shape, and the shape of the first surface consists of a rectangle and a trapezoid arranged on both sides of the rectangle along the opposite direction perpendicular to the first electrode 202 and the second electrode 203. constitute.
  • a portion of the first surface between the first electrode 202 and the second electrode 203 has a rectangular shape.
  • the shape of the ferroelectric memory cell 2011 is designed as shown in FIG.
  • FIG. 6 and 7a are top views of the ferroelectric memory element 20.
  • FIG. FIG. 7b is a topographic view of the ferroelectric memory element 20 shown in FIG. 7a observed under a scanning electron microscope.
  • the portion of the ferroelectric memory cell 2011 located between the first electrode 202 and the second electrode 203 and the width d of the first electrode 202 and the second electrode 203 may be the same or different.
  • the portion of the ferroelectric memory cell 2011 located between the first electrode 202 and the second electrode 203, the width d of the first electrode 202 and the second electrode 203 may be 5 nm, 10 nm, 100 nm, 500 nm, 1 ⁇ m, 5 ⁇ m and 10 ⁇ m, etc.
  • the ferroelectric memory cell 2011 is located between the first electrode 202 and the second electrode in the ferroelectric memory cell 2011
  • the part between 203 and the width d of the first electrode 202 and the second electrode 203 is too large, which is not conducive to the miniaturization of the ferroelectric storage element 20, and the number of ferroelectric storage elements 20 included in the ferroelectric memory 10 is reduced, that is, The density of the ferroelectric memory element 20 included in the ferroelectric memory 10 is reduced.
  • the portion of the ferroelectric memory cell 2011 located between the first electrode 202 and the second electrode 203 If along the direction perpendicular to the opposite direction of the first electrode 202 and the second electrode 203 and the direction perpendicular to the thickness of the ferroelectric memory cell 2011, the portion of the ferroelectric memory cell 2011 located between the first electrode 202 and the second electrode 203, If the width d of the first electrode 202 and the second electrode 203 is too small, the current flowing through the first electrode 202 and the second electrode 203 will be small.
  • the The part between the electrode 202 and the second electrode 203, and the width d of at least one of the first electrode 202 and the second electrode 203 is set in the range of 5 nm ⁇ d ⁇ 10 ⁇ m, which can avoid the influence caused by too large or too small width.
  • the material of the ferroelectric thin film layer 201 may include, but is not limited to, lithium niobate (LiNbO 3 ), blackened lithium niobate, doped lithium niobate, lithium tantalate (LiTaO 3 ), Blackened lithium tantalate, doped lithium tantalate, bismuth ferrite (BiFeO 3 ), doped bismuth ferrite (eg lanthanum doped bismuth ferrite), lead zirconium titanate (piezoelectric ceramic transducer, PZT), doped lead zirconium titanate, barium titanate (BaTiO 3 ), doped barium titanate, strontium tantalate, doped strontium tantalate, strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), doped strontium bismuth tantalate salt.
  • lithium niobate LiNbO 3
  • Blackened lithium tantalate doped lithium tanta
  • the dopant in the doped lithium niobate or the doped lithium tantalate may include magnesium oxide (MgO), iron (Fe), manganese (Mn), erbium (Er) or titanium (Ti), etc. one or more of.
  • MgO magnesium oxide
  • Fe iron
  • Mn manganese
  • Er erbium
  • Ti titanium
  • the concentration range of lithium niobate or lithium tantalate doped with MgO may be 0-10 mol %.
  • ferroelectric thin film layer 201 magnetron sputtering method, chemical vapor deposition method (chemical vapor deposition, CVD), pulsed laser deposition (pulsed laser deposition, PLD), bonding process, etc.
  • a thin film with uniform thickness is formed on the substrate 200; then, the pattern on the mask can be transferred to the thin film through a process such as photolithography, electron beam direct writing or nano-imprinting, and the pattern on the mask is connected to the ferroelectric memory.
  • the patterns of the cells 2011 are the same, thus realizing the pattern transfer of the ferroelectric memory cells 2011; after that, the ferroelectric memory cells 2011 are formed by dry etching or wet etching technology.
  • the side surface and the first surface of the ferroelectric memory cell 2011 may be vertical or non-vertical due to process reasons.
  • the side surface of the ferroelectric memory cell 2011 is taken as an example to be perpendicular to the first surface for illustration.
  • the thickness h of the ferroelectric thin film layer 201 is in the range of 5 nm ⁇ h ⁇ 10 ⁇ m.
  • the thickness h of the ferroelectric thin film layer 201 may be 5 nm, 10 nm, 50 nm, 100 nm, 500 nm, 1 ⁇ m or 10 ⁇ m, or the like.
  • the thickness of the ferroelectric thin film layer 201 is not uniform.
  • the thickness h refers to the distance from the surface of the ferroelectric thin film layer 201 close to the substrate 200 to the first surface of the ferroelectric memory cell 2011 .
  • the length of the ferroelectric thin film layer 201 close to the substrate 200 is greater than the length of the first surface of the ferroelectric memory cell 2011 .
  • the embodiment of the present application does not limit the initial polarization direction of the ferroelectric thin film layer 201 , as long as the initial polarization direction of the ferroelectric thin film layer 201 is not related to the electric field formed between the first electrode 202 and the second electrode 203
  • the direction may be vertical, that is, as long as the initial polarization direction of the ferroelectric thin film layer 201 has an in-plane component parallel to the substrate 200 .
  • the direction of the electric field formed between the first electrode 202 and the second electrode 203 is parallel to the substrate 200 , as long as the initial polarization direction of the ferroelectric thin film layer 201 is not perpendicular to the substrate 200 .
  • the initial polarization direction P1 of the ferroelectric thin film layer 201 is parallel to the substrate 200 to the right.
  • the material of the above-mentioned substrate 200 may be various substrate materials commonly used in the ferroelectric memory 10 .
  • the material of the substrate 200 is one or more of silicon (Si), strontium titanate (SrTiO 3 ), and lithium niobate. Since a silicon substrate is easily compatible with a CMOS (complementary metal oxide semiconductor, complementary metal oxide semiconductor) process, which facilitates mass production, in some examples, the material of the substrate 200 is silicon. On this basis, if the ferroelectric thin film layer 201 is formed by an epitaxial growth process or the like, the selection of the material of the substrate 200 is mainly determined by the material of the ferroelectric thin film layer 201 .
  • an electrical insulating buffer needs to be inserted between the silicon substrate and the ferroelectric thin film layer 201 Floor.
  • the material of the electrically insulating buffer layer is, for example, SiO 2 (silicon dioxide) or the like.
  • the lattice structure of the surface of the ferroelectric thin film layer 201 away from the substrate 200 and the lattice structure inside the ferroelectric thin film layer 201 will be different, and the ferroelectric thin film layer 201 The surface away from the substrate 200 is equivalent to having a passivation layer; on the other hand, when the ferroelectric memory cell 2011 is formed by etching, the surface of the ferroelectric thin film layer 201 away from the substrate 200 will suffer from etching loss.
  • the surface of the ferroelectric thin film layer 201 away from the substrate 200 is equivalent to the existence of a natural selection tube, so the ferroelectric memory element 20 has the turn-on voltage Von, that is, the ferroelectric memory element 20 in the embodiment of the present application has the characteristics of the non-volatile storage and selection tubes.
  • the ferroelectric memory element 20 provided by the embodiment of the present application does not need to be additionally provided with a selection transistor.
  • the following describes the data writing method of the ferroelectric memory element 20 with reference to FIGS. 8 , 9 and 11 , and the data reading method of the ferroelectric memory element 20 with reference to FIG. 8 . Be explained.
  • FIGS. 8 , 9 and 11 it is taken as an example that the initial polarization direction P1 of the ferroelectric thin film layer 201 is parallel to the rightward of the substrate 200 .
  • Data writing of the ferroelectric memory element 20 includes:
  • the first voltage line m electrically connected to the ferroelectric storage element 20 A first write voltage is applied between the ferroelectric memory cell 2011 and the second voltage line n, so that the part of the ferroelectric memory cell 2011 close to the first electrode 202 forms the polarization direction (ie the initial polarization) of the part of the ferroelectric thin film layer 201 close to the substrate 200
  • the domain walls 2011a between the domains with opposite polarization directions in the ferroelectric thin film layer 201 intersect with the second electrode 203; as shown in FIG.
  • the domain walls 2011a moves toward the direction close to the first electrode 202, the domain wall 2011a intersects the first surface of the ferroelectric memory cell 2011 and does not intersect the second electrode 203, thereby writing the first logic information "1".
  • the direction of the first write voltage is opposite to the initial polarization direction of the ferroelectric thin film layer 201 . Since the first electrode 202 is electrically connected to the first voltage line m, and the second electrode 203 is electrically connected to the second voltage line n, the first write voltage is applied between the first voltage line m and the second voltage line n, that is, at A first write voltage is applied between the first electrode 202 and the second electrode 203 .
  • the ferroelectric storage element 20 stores the second logic information "0".
  • the polarization direction of the portion of the memory cell 2011 close to the first electrode 202 is reversed, forming an electric domain opposite to the polarization direction of the portion of the ferroelectric thin film layer 201 close to the substrate 200; if the ferroelectric memory element 20 stores the first If the logic information is “1”, after the first write voltage is applied, the polarization direction of the electric domain of the part of the ferroelectric memory cell 2011 close to the first electrode 202 remains opposite to the polarization direction of the part of the ferroelectric thin film layer 201 close to the substrate 200 .
  • the embodiments of the present application are described by taking as an example that the ferroelectric memory element 20 stores the second logic information "0" before the first logic information "1" is written to the ferroelectric memory element 20 .
  • the portion of the ferroelectric memory cell 2011 close to the first electrode 202 forms an electric domain whose polarization direction is opposite to that of the portion of the ferroelectric thin film layer 201 close to the substrate 200 .
  • 2011a extends until it intersects with the second electrode 203 .
  • the polarization direction of the part of the electric domain near the second electrode 203 in the electric domain is reversed back to the ferroelectric
  • the polarization direction of the portion of the thin film layer 201 close to the substrate 200 is the same direction, while the electric domain close to the first electrode 201 maintains the polarization direction when the first write voltage is applied. That is, after the first write voltage is removed, the electric domain reversed by the first write voltage shrinks toward the direction close to the first electrode 202 .
  • the direction of the first writing voltage is, for example, is the direction from the first electrode 202 to the second electrode 203 .
  • a positive voltage may be applied to the first voltage line m
  • a negative voltage or grounding process may be applied to the second voltage line n.
  • the direction of the electric field formed between the first electrode 202 and the second electrode 203 is directed from the first electrode 202 to the second electrode 203 , and the electric field formed between the first electrode 202 and the second electrode 203 is in a direction parallel to the substrate 200
  • the electric field component of the ferroelectric memory cell 2011 close to the first electrode 202 is reversed, forming an electric domain opposite to the polarization direction of the part of the ferroelectric thin film layer 201 close to the substrate 200.
  • the polarization direction is P2 shown in FIG. 8 (ie, the polarization direction P2 is parallel to the substrate 200 to the left).
  • the portion of the ferroelectric memory cell 2011 close to the first electrode 202 is The polarization direction is reversed, and the cross-sectional shape of the domain formed after the reversal is triangular or triangular-like. In this way, domain walls 2011 a are formed between domains with opposite polarization directions in the ferroelectric thin film layer 201 to intersect with the first surface of the ferroelectric memory cell 2011 .
  • the cross-sectional view of the domain wall 2011a between the domains with opposite polarization directions in the ferroelectric thin film layer 201 may be a straight line, such as the domain wall 2011a in FIG. 9, or it may be a curve, such as FIG. Domain walls 2011b and 2011c in 9. That is, the cross-sectional shape of the electric domain formed in the portion of the ferroelectric memory cell 2011 close to the first electrode 202 may be triangular, or may be approximately triangular (ie, triangular-like).
  • the intersection point T and the second electrode where the domain wall 2011a intersects with the first surface of the ferroelectric memory cell 2011 The distance ⁇ L between 203, that is, the size of the electric domain formed by the inversion of the polarization direction of the part of the ferroelectric memory cell 2011 close to the first electrode 202 when the first logic information "1" is written, is the same as the size of the electric domain formed along the first.
  • the opposite direction of the first electrode 202 and the second electrode 203 is related to the size of the distance L between the first electrode 202 and the second electrode 203 .
  • ⁇ L can be adjusted by adjusting the size of the distance L between the first electrode 202 and the second electrode 203 .
  • the distance L between the first electrode 202 and the second electrode 203 can be adjusted in the process of fabricating the ferroelectric memory 10.
  • the length L1 of the contact between the first electrode 202 and the first surface of the ferroelectric memory cell 2011 is set first. , and then adjust the distance L between the first electrode 202 and the second electrode 203 by adjusting the length L2 of the contact between the second electrode 203 and the first surface of the ferroelectric memory cell 2011 .
  • the distance ⁇ L between the intersection point T where the domain wall 2011a intersects with the first surface of the ferroelectric memory cell 2011 and the second electrode 203 is less than or equal to along the opposite direction of the first electrode 202 and the second electrode 203 .
  • the distance L between 202 and the second electrode 203 is ⁇ L ⁇ L. This is because under the action of the depolarization field, part of the electric domains between the first electrode 202 and the second electrode 203 will return to the initial polarization state, but the reversed electric domains near the first electrode 202 are different from those that have not been reversed. The reversed electrical domains reach equilibrium, and the reversed electrical domains near the first electrode 202 maintain the state at the time of writing.
  • the intersection point where the domain wall 2011 a intersects with the first surface of the ferroelectric memory cell 2011 The spacing ⁇ L between T and the second electrode 203 is 0 ⁇ L ⁇ 500 nm.
  • ⁇ L may be 10 nm, 50 nm, 100 nm, 200 nm, or 500 nm, or the like.
  • the turn-on voltage Von of the ferroelectric memory element 20 and the intersection of the domain wall 2011a and the first surface of the ferroelectric memory cell 2011 in the opposite direction of the first electrode 202 and the second electrode 203 T is related to the distance ⁇ L between the second electrodes 203 .
  • each ferroelectric memory element 20 is in a direction opposite to a first electrode 202 and a second electrode 203, the first electrode 202 being in contact with the first surface of the ferroelectric memory cell 2011
  • the length L1 is 170 nm, and along the opposite direction of the first electrode 202 and the second electrode 203, the length L2 of the second electrode 203 in contact with the first surface of the ferroelectric memory cell 2011 is 80 nm.
  • the distance L between the electrode 202 and the second electrode 203 is different.
  • FIG. 10 is a graph showing the change trend of the turn-on voltage Von of the ferroelectric memory element 20 with the distance L between the first electrode 202 and the second electrode 203 .
  • each test result point represents the turn-on voltage Von corresponding to the L value of a certain ferroelectric memory element 20
  • the second logic information needs to be written into the ferroelectric memory element 20, for example, logic information “0”, the first voltage line m and the second voltage line n (that is, the first voltage line m and the second voltage line n)
  • a second write voltage is applied between the first electrode 202 and the second electrode 203), so that the polarization direction of the ferroelectric thin film layer 201 is the same, so that the second logic information "0" is written; wherein, the direction of the first write voltage is the same as The direction of the second write voltage is opposite.
  • the direction of the second write voltage is opposite to the direction of the first write voltage
  • the direction of the second write voltage is the direction from the first electrode 202 to the second electrode 203
  • the second electrode 203 points in the direction of the first electrode 202 .
  • a positive voltage may be applied to the second voltage line n
  • a negative voltage or grounding process may be applied to the first voltage line m.
  • the direction of the electric field formed between the first electrode 202 and the second electrode 203 is directed from the second electrode 203 to the first electrode 202 , and the electric field formed between the first electrode 202 and the second electrode 203 is in a direction parallel to the substrate 200
  • the electric field component of the ferroelectric memory cell 2011 reverses the polarization direction of the domain whose polarization direction is parallel to the substrate 200 to the left, and the reversed polarization direction is parallel to the substrate 200 to the right.
  • the ferroelectric The polarization direction of the thin film layer 201 is the same, and the domain wall 2011a in the ferroelectric thin film layer 201 disappears, thereby realizing the writing of the second logic information "0".
  • the first write voltage and the second write voltage applied between the first voltage line m and the second voltage line n are both greater than or equal to the ferroelectric thin film layer
  • the coercive voltage Vc of 201, the coercive voltage Vc is the voltage that can reverse the electric domain of the part of the applied electric field under the action of the applied electric field.
  • the data reading method of the ferroelectric storage element 20 includes:
  • a read voltage is applied between the first voltage line m and the second voltage line n, and the polarization of the part of the ferroelectric memory cell 2011 close to the first electrode 202 is determined according to the magnitude of the current on the first voltage line m or the second voltage line n Whether the direction is reversed to form the domain wall 2011a to read the logic information stored in the ferroelectric memory cell 2011.
  • the direction of the read voltage is the same as the direction of the write voltage when the ferroelectric memory cell 2011 generates domain walls.
  • the read voltage is applied between the first voltage line m and the second voltage line n, that is, the first A read voltage is applied between the electrode 202 and the second electrode 203 .
  • the direction of the write voltage is from the first electrode 202 to the second electrode 203
  • the direction of the read voltage is from the first electrode 202 to the second electrode 203
  • a positive voltage may be applied to the first voltage line m
  • a negative voltage or grounding treatment may be applied to the second voltage line n. It should be understood that the magnitude of the current on the first voltage line m or the second voltage line n can be read through the sense amplifier.
  • the ferroelectric memory element 20 when the read voltage applied between the first voltage line m and the second voltage line n When the voltage is greater than the turn-on voltage Von, an obvious current value can be read on the first voltage line m or the second voltage line n. Based on this, the read voltage applied between the first voltage line m and the second voltage line n is greater than the turn-on voltage Von of the ferroelectric memory element 20 .
  • the first voltage line The read voltage applied between m and the second voltage line n is smaller than the coercive voltage Vc of the ferroelectric thin film layer 201 .
  • the ferroelectric memory cell 2011 When a read voltage is applied between the first voltage line m and the second voltage line n, if the ferroelectric memory cell 2011 stores the second logic information "0", since there is no domain wall 2011a in the ferroelectric thin film layer 201, then The current flowing on the first voltage line m and the second voltage line n will be relatively small. Based on this, if it is read that the current on the first voltage line m or the second voltage line n is relatively small, it can be determined that there is no domain wall 2011a in the ferroelectric thin film layer 201, that is, there is no pole in the ferroelectric thin film layer 201. In this way, the second logic information "0" stored in the ferroelectric storage unit 2011 can be read, thereby realizing non-destructive reading of the ferroelectric storage element.
  • the intersection point T where the domain wall 2011a intersects with the first surface of the ferroelectric memory cell 2011 and the second electrode 203 The distance ⁇ L>0, so as shown in FIG. 11 , when a read voltage is applied between the first voltage line m and the second voltage line n, since the read voltage is greater than the turn-on voltage Von, the read voltage makes the domain wall 2011a intersects with the second electrode 203 . In this way, after the domain wall 2011a intersects with the first electrode 202 and the second electrode 203, a conductive path can be formed.
  • the ferroelectric memory element 20 returns to the state before the read operation.
  • the ferroelectric memory element 20 returns to the state shown in FIG. 9 , that is, the ferroelectric memory cell 2011 The electric domain formed in the portion close to the first electrode 202 is reduced.
  • FIG. 12 is a test chart of the I (current)-V (voltage) curve of the ferroelectric memory element 20 during the data writing process and the data reading process. It can be seen from the I-V curve test chart of the data writing process in Figure 12 that the write voltage gradually increases from 0V. When the write voltage increases to nearly 2.9V, the current value rapidly increases to about 5 ⁇ A. At this time, the domain wall 2011a and the The second electrode 203 contacts, and then, with the increase of the write voltage, the current value jumps around 5 ⁇ A. When the write voltage increases to 4V, the current value also gradually decreases with the gradual decrease of the write voltage.
  • the read voltage gradually increases from 0V.
  • the current value gradually increases with the increase of the read voltage.
  • the current value also decreases gradually.
  • the domain wall 2011a gradually expands to the direction close to the second electrode 203, and the length of the domain wall 2011a increases, so the current value gradually increases.
  • a specific embodiment is provided below to describe the operation process of writing the first logic information "1" and the operation process of reading the first logic information "1" of the ferroelectric memory element 20 .
  • the width d of the first electrode 202 and the second electrode 203 is 110 nm
  • the width d of the first electrode 202 and the second electrode 203 is 110 nm.
  • the length L1 of the first electrode 202 in contact with the first surface of the ferroelectric memory cell 2011 is 60 nm
  • the length L2 of the second electrode 203 in contact with the first surface of the ferroelectric memory cell 2011 is 10 nm
  • the gap between the first electrode 202 and the second electrode 203 is 60 nm
  • the initial polarization direction of the ferroelectric thin film layer 201 is parallel to the substrate 200 to the right as an example.
  • the operation process of writing the first logic information “1” is: Referring to FIG. 8 , when a first write voltage of 4V is applied between the first electrode 202 and the second electrode 203 , the voltage between the first electrode 202 and the second electrode 203 is The direction of the generated electric field is directed from the first electrode 202 to the second electrode 203. Under the action of the electric field, the polarization direction of the part of the ferroelectric memory cell 2011 close to the first electrode 202 is reversed, and the polarization direction is parallel to the substrate 200. The electric domain to the left, the cross-sectional shape of the electric domain is triangular or triangular-like. As shown in FIG.
  • the portion of the ferroelectric memory cell 2011 close to the first electrode 202 still has a triangular or triangular-like electric domain in cross-section.
  • the distance ⁇ L between the intersection point T where the domain wall 2011a intersects the first surface of the ferroelectric memory cell 2011 and the second electrode 203 is about 30 nm.
  • the operation process of reading the first logic information "1" is as follows: referring to FIG. 8 , a read voltage is applied between the first voltage line m and the second voltage line n. At this time, the read voltage is greater than the corresponding turn-on voltage when ⁇ L is 30 nm.
  • the polarization direction of the portion of the ferroelectric memory cell 2011 corresponding to the gap between the first electrode 202 and the second electrode 203 is reversed, and the reversed polarization direction is parallel to the substrate 200 to the left, That is to say, the left-polarized electric domain formed by the part of the ferroelectric memory cell 2011 close to the first electrode 202 expands in the direction close to the second electrode 203, so that the domain wall 2011a is connected to the second electrode 203, and the first The electrode 202, the domain wall 2011a and the second electrode 203 form a conductive channel so that a read current can be generated.
  • Figure 13 is an image of the ferroelectric memory element 20 after applying a reverse erase voltage of -4V.
  • the left figure in FIG. 13 is a topography of the ferroelectric memory element 20 under a scanning electron microscope.
  • the middle diagram in FIG. 13 is a piezoelectric amplitude imaging diagram of the ferroelectric memory element 20 .
  • the right figure in FIG. 13 is a piezoelectric phase imaging diagram of the ferroelectric memory element 20 .
  • FIG. 14 is an image of the ferroelectric memory element 20 after the first write voltage of 4V is applied and the first write voltage is removed. At this time, after applying the first write voltage of 4V, ⁇ L is about 30 nm.
  • the left figure in FIG. 14 is a topography of the ferroelectric memory element 20 under a scanning electron microscope.
  • the middle diagram in FIG. 14 is a piezoelectric amplitude imaging diagram of the ferroelectric memory element 20 .
  • the right figure in FIG. 14 is a piezoelectric phase imaging diagram of the ferroelectric memory element 20 . Comparing Fig. 13 and Fig.
  • the ferroelectric memory 10 includes a first voltage line m, a second voltage line n, and a ferroelectric storage element 20 .
  • the ferroelectric memory element 20 includes a ferroelectric thin film layer 201 disposed on a substrate 200; the ferroelectric thin film layer 201 includes a ferroelectric memory cell 2011 protruding to a side away from the substrate 200; the ferroelectric memory element 20 also includes a The first electrode 202 and the second electrode 203 on both sides of the electric storage cell 2011; the first electrode 202 is in contact with the first surface and the side surface of the ferroelectric storage cell 2011, and the second electrode 203 is in contact with the first surface of the ferroelectric storage cell 2011 and/or side contact; the first surface is the surface of the ferroelectric memory cell 2011 away from the substrate; wherein the first electrode 202 is electrically connected to the first voltage line m; the second electrode 203 is electrically connected to the second voltage line n.
  • the first electrode 202 Since the first electrode 202 is in contact with the first surface and the side surface of the ferroelectric memory cell 2011, when the first logic information "1" is written and the first write voltage is applied, the part of the ferroelectric memory cell 2011 close to the first electrode 202 An electric domain opposite to the polarization direction of the portion of the ferroelectric thin film layer 201 close to the substrate 200 is formed. After the first write voltage is removed, the domain wall 2011a between the electric domains with the opposite polarization direction in the ferroelectric thin film layer 201 and the iron The first surface of the electrical storage cell 2011 intersects and does not intersect the second electrode 203 .
  • While the turn-on voltage Von of the ferroelectric memory element 20 is opposite to the direction along the opposite direction of the first electrode 202 and the second electrode 203, between the intersection point T where the domain wall 2011a intersects with the first surface of the ferroelectric memory cell 2011 and the second electrode 203
  • the distance ⁇ L is related. By adjusting the distance L between the first electrode 202 and the second electrode 203 , ⁇ L can be adjusted, and then the turn-on voltage Von can be adjusted, thereby realizing the regulation of the turn-on voltage Von of the ferroelectric storage element 20 .
  • adjusting the turn-on voltage Von is equivalent to adjusting the resistance value of the ferroelectric thin film layer 201 away from the surface of the substrate 200 , so the readout current can be increased by adjusting the turn-on voltage Von, thereby increasing the read speed of the ferroelectric memory element 20 faster.
  • the coercive voltage Vc of the ferroelectric memory element 20 is gradually reduced.
  • the turn-on voltage Von of the ferroelectric memory element 20 can be reduced, so that the read voltage can be greater than the turn-on voltage Von and smaller than the coercive voltage Vc of the ferroelectric memory element 20 , so the problem of limiting the reduction of the coercive voltage Vc in the prior art can be solved.
  • the read and write voltages are also reduced accordingly, thereby reducing power consumption.
  • the ferroelectric storage element 20b is a ferroelectric storage element to be selected for read and write operations, and the configuration voltage of the equivalent array is 1/3Vdd mode, even if Von>1/3Vdd, in this case, the voltage disposed across the unselected ferroelectric memory element 20 is 1/3Vdd. Because the ferroelectric memory element 20 has natural selectivity, the voltage ⁇ Von is configured between the first electrode 202 and the second voltage 203 of the unselected ferroelectric memory element 20, and the ferroelectric memory element 20 is in an inactive state, while the selected ferroelectric memory element 20 is in an inactive state.
  • a first write voltage is applied across the storage element 20 to reverse the polarization direction of the selected ferroelectric storage element 20b, and the first logic information "1" is written; on the contrary, the selected ferroelectric storage element 20b is applied with a first write voltage
  • the second writing voltage is opposite to the first writing voltage, reverses the polarization direction of the selected ferroelectric memory element 20b to the initial state again, and writes the first logic information "0", that is Erase operation.
  • a read voltage is applied between the first electrode 202 and the second electrode 203 of the selected ferroelectric memory element 20b.
  • the direction of the read voltage is the same as that of the first write voltage.
  • the read voltage is less than the first write voltage and greater than the turn-on voltage Von.
  • the configuration voltage 1/2Vdd mode can also be used, that is, Von>1/2Vdd, where Vdd is the power supply voltage, which is greater than the write voltage value.
  • a voltage of 1/2Vdd is applied to both the first voltage line m and the second voltage line n electrically connected to the unselected ferroelectric memory element 20 .
  • the configuration voltage mode can also adopt the crossbar mode floating mode, that is, the two ends of the unselected ferroelectric storage elements 20 are not configured with voltage and are in a floating state.
  • the length L1 of the first electrode 202 in contact with the first surface of the ferroelectric memory cell 2011 and the length L1 of the second electrode 203 and the ferroelectric memory cell 2011 The length L2 of the first surface contact is the same. In other embodiments, along the opposite direction of the first electrode 202 and the second electrode 203 , the length L1 of the first electrode 202 in contact with the first surface of the ferroelectric memory cell 2011 is greater than the length L1 of the second electrode 203 and the ferroelectric memory cell 2011 The length L2 of the first surface contact.
  • the ferroelectric memory element 20 needs to be overcome to change from writing the first logic information "1" to writing the second logic information "0" under the action of the depolarization field.
  • the coercive voltage Vc is different from the coercive voltage Vc that needs to be overcome to change the ferroelectric memory element 20 from writing the second logic information "0" to writing the first logic information "1".
  • the ferroelectric storage element 20 when L1 is greater than L2, by adjusting L1 and L2, the ferroelectric storage element 20 can be changed from writing the first logic information "1" to writing the second logic information "0".
  • the coercive voltage Vc is the same as the coercive voltage Vc that needs to be overcome to make the ferroelectric memory element 20 change from writing the second logic information "0" to writing the first logic information "1", so as to realize the positive and negative coercivity. Symmetrical regulation of the voltage, so that the logic information stored in the ferroelectric memory element 20 is retained for a longer time.
  • the ferroelectric thin film layer 201 includes a conductive thin film layer; wherein, the conductive thin film layer is located on the surface of the ferroelectric thin film layer away from the substrate 200 .
  • the surface of the ferroelectric thin film layer 201 away from the substrate 200 may be modified to form a conductive thin film layer.
  • the above-mentioned modification treatments include, but are not limited to, metal thermal diffusion, ion implantation, and surface blackening treatments.
  • the metal that can be used for the above-mentioned metal thermal diffusion is one or more of Cr, Ti, Ir, Cu, Ag (silver), Co, Pt, Al, and Ni.
  • the metal ions that can be implanted by ion implantation are one or more of Cr, Ti, Ir, Cu, Ag, Co, Pt, Al, and Ni.
  • the surface of the ferroelectric thin film layer away from the substrate 200 is modified to form a conductive thin film layer, thereby reducing the coercive voltage of the ferroelectric memory element 20 and increasing the read current.

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Abstract

一种铁电存储器及电子设备，涉及铁电存储技术领域，用于对铁电存储元件(20)的开启电压进行调节。该铁电存储器包括基底(200)以及设置在基底(200)上的第一电压线、第二电压线以及铁电存储元件(20)；铁电存储元件(20)包括设置在基底(200)上的铁电薄膜层(201)；铁电薄膜层(201)包括向远离基底(200)一侧凸起的铁电存储单元(2011)；铁电存储元件(20)还包括相对设置于铁电存储单元(2011)两侧的第一电极(202)和第二电极(203)；第一电极(202)与铁电存储单元(2011)的第一表面和侧面均接触，第二电极(203)与铁电存储单元(2011)的第一表面和/或侧面接触；第一表面为铁电存储单元(2011)的与基底(200)平行且远离基底(200)的表面；其中，第一电极(202)与第一电压线电连接；第二电极(203)与第二电压线电连接。

Description

一种铁电存储器及电子设备 技术领域
本申请涉及铁电存储技术领域，尤其涉及一种铁电存储器及电子设备。
背景技术
铁电随机存储器(ferroelectric random access memory，简称FRAM)，也可以称为“铁电存储器”。传统的铁电存储器的缺点是破坏性读出信息，并且尺寸微缩受限，目前平面结构尺寸仅能缩小到130nm。近年来，导电畴壁铁电存储器(conductive-domain-wall ferroelectric random access memory，简称DW-FRAM)被发明，DW-FRAM存储数据的原理为当在电场的作用下，DW-FRAM中的铁电材料存在两个极化方向不同的区域(也可以称为电畴)时，电畴与电畴之间的界面形成铁电畴壁，铁电畴壁具有导电性；当在电场的作用下，DW-FRAM中的铁电材料具有相同的极化方向时，该铁电畴壁消失，铁电存储器可以基于铁电畴壁的产生和消失作为逻辑信息(“0”或“1”)来存储数据。
由于DW-FRAM具有非破坏性读取电流，尺寸可微缩，结构简单等优点，因而可以制作高密度交叉棒(crossbar)阵列结构。交叉棒阵列结构包括相互交叉的多条第一电压线和多条第二电压线。一条第一电压线和一条第二电压线交叉位置处设置有一个铁电存储元件，铁电存储元件包括铁电薄膜层以及与铁电存储薄膜层接触的读写电极对。研究发现DW-FRAM中铁电薄膜层靠近读写电极对的表面存在天然界面层，该天然界面层可以作为天然的选择管。现有的铁电存储元件，由于天然界面层的厚度一定，因而开启电压Von(也可以称为阈值电压Vth，即，使铁电存储元件绝缘和导通的临界电压值)的大小固定。随着铁电存储元件逐渐微型化，铁电存储元件的矫顽电压逐渐降低，然而在读操作过程中，读电压Vread应大于开启电压Von，小于矫顽电压Vc，由于开启电压Von固定，因而限制了矫顽电压和读电压的降低，而写电压应大于矫顽电压，这样一来，限制了铁电存储元件的读写电压的降低，进而不利于功耗的降低。
发明内容
本申请实施例提供一种铁电存储器及电子设备，用于对铁电存储元件的开启电压进行调节。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种铁电存储器。该铁电存储器包括第一电压线、第二电压线以及铁电存储元件；铁电存储元件包括设置在基底上的铁电薄膜层；铁电薄膜层包括向远离基底一侧凸起的铁电存储单元；铁电存储元件还包括相对设置于铁电存储单元两侧的第一电极和第二电极；第一电极与铁电存储单元的第一表面和侧面均接触，第二电极与铁电存储单元的第一表面和/或侧面接触；第一表面为铁电存储单元远离基底的表面；其中，第一电极与第一电压线电连接；第二电极与所述第二电压线电连接。由于第一电极与铁电存储单元的第一表面和侧面接触，因而在写入第一逻辑信息“1”，施加第一写电压时，铁电 存储单元靠近第一电极的部分形成与铁电薄膜层靠近基底的部分的极化方向相反的电畴，撤掉第一写电压后，铁电薄膜层中极化方向相反的电畴之间的畴壁与铁电存储单元的第一表面相交，且不与第二电极相交。而铁电存储元件的开启电压Von与沿第一电极和第二电极相对的方向，畴壁与铁电存储单元的第一表面相交的交点T和第二电极之间的间距ΔL有关，通过调节第一电极和第二电极之间的间距L的大小可以调节ΔL，进而可以调节开启电压Von，从而实现了对铁电存储元件的开启电压的调节。此外，调节开启电压Von，相当于对铁电薄膜层远离基底表面的电阻值进行调节，因而可以通过调节开启电压Von使得读出电流增大，进而使得铁电存储元件的读取速度更快。
在此基础上，随着铁电存储元件的微型化，铁电存储元件的矫顽电压Vc逐渐降低，由于本申请实施例提供的铁电存储元件的开启电压Von可以调节，因而在铁电存储元件的矫顽电压Vc降低时，可以降低铁电存储元件的开启电压Von，这样一来，便可以满足读电压大于开启电压Von，小于铁电存储元件的矫顽电压Vc，因此可以解决现有技术中限制矫顽电压Vc降低的问题。此外，矫顽电压Vc和开启电压Von都降低时，读写电压也会相应地降低，从而可以降低功耗。
在一种可能的实施方式中，沿第一电极和第二电极相对的方向，第一电极与铁电存储单元的第一表面接触的长度L1大于第二电极与铁电存储单元的第一表面接触的长度L2。由于L1大于L2，因而通过调节L1和L2，可以使铁电存储元件由写入第一逻辑信息“1”变为写入第二逻辑信息“0”需要克服的矫顽电压Vc和使铁电存储元件20由写入第二逻辑信息“0”变为写入第一逻辑信息“1”需要克服的矫顽电压Vc相同，从而实现了对正负矫顽电压的对称调节，这样一来，铁电存储元件存储的逻辑信息保持时间更长。
在一种可能的实施方式中，沿第一电极和第二电极相对的方向，第一电极与铁电存储单元的第一表面接触的长度L1为0＜L1≤500nm。
在一种可能的实施方式中，沿第一电极和第二电极相对的方向，第二电极与铁电存储单元的第一表面接触的长度L2为0≤L2≤100nm。
在一种可能的实施方式中，沿第一电极和第二电极相对的方向，第一电极和第二电极之间的间距L为0＜L≤500nm。通过调节L的大小可以调节在写入第一逻辑信息时，沿第一电极和第二电极相对的方向，畴壁与铁电存储单元的第一表面相交的交点和第二电极之间的间距ΔL，进而实现铁电存储元件的开启电压Von可调。
在一种可能的实施方式中，铁电薄膜层包括导电薄膜层；其中，导电薄膜层位于铁电薄膜层远离基底的表面。由于铁电薄膜层包括位于铁电薄膜层远离基底的表面的导电薄膜层，从而可以降低铁电存储元件的矫顽电压，增大读取电流。
在一种可能的实施方式中，铁电薄膜层的厚度h的范围为5nm≤h≤10um。
在一种可能的实施方式中，沿垂直于第一电极和第二电极相对的方向以及垂直于铁电存储单元的厚度的方向，铁电存储单元中位于第一电极和第二电极之间的部分、第一电极和第二电极中至少一个的宽度d的范围为5nm≤d≤10μm。若宽度d太大，则不利于铁电存储元件的微型化，铁电存储器中包括的铁电存储元件数量减小，即铁电存储器中包括的铁电存储元件的密度降低。若宽度d太小，则流过第一电极和第二电极的电流会较小。基于此，将宽度d的范围设置为5nm≤d≤10μm，这样可以避免 宽度太大或太小造成的影响。
第二方面，提供一种电子设备。该电子设备包括电路板以及与所述电路板电连接的铁电存储器；其中，该铁电存储器为上述的铁电存储器。该电子设备具有与前述实施例相同的技术效果，此处不再赘述。
第三方面，提供一种数据写入方法，该数据写入方法用于上述的铁电存储器中。该数据写入方法包括：在第一电压线和第二电压线之间施加第一写电压，以使铁电存储单元靠近第一电极的部分形成与铁电薄膜层靠近基底的部分的极化方向相反的电畴，铁电薄膜层中极化方向相反的电畴之间的畴壁与第二电极相交；在撤掉第一写电压后，畴壁向靠近第一电极的方向移动，畴壁与铁电存储单元的第一表面相交，且不与第二电极相交，以写入第一逻辑信息；在第一电压线和第二电压线之间施加第二写电压，以使铁电薄膜层的极化方向相同，以写入第二逻辑信息；其中，第一写电压的方向与第二写电压的方向相反。在写入第一逻辑信息时，沿第一电极和第二电极相对的方向，畴壁与铁电存储单元的第一表面相交的交点T和第二电极之间的间距ΔL会影响铁电存储元件的开启电压Von，通过调节第一电极和第二电极之间的间距L的大小可以调节ΔL，进而可以调节开启电压Von，从而实现了对铁电存储元件的开启电压的调节。
在一种可能的实施方式中，撤掉第一写电压后，沿第一电极和第二电极相对的方向，畴壁与铁电存储单元的第一表面相交的交点和第二电极之间的间距ΔL为0<ΔL≤500nm。此处，可以通过调节沿第一电极和第二电极相对的方向，畴壁与铁电存储单元的第一表面相交的交点T和第二电极之间的间距ΔL，来调节铁电存储元件的开启电压Von。
在一种可能的实施方式中，通过调节第一电极和第二电极之间的间距L来调节沿第一电极和第二电极相对的方向，畴壁与铁电存储单元的第一表面相交的交点和第二电极之间的间距ΔL。
第四方面，提供一种数据读取方法，该数据读取方法用于上述的铁电存储器中。该数据读取方法包括：在第一电压线和第二电压线之间施加读电压，根据第一电压线或第二电压线上的电流大小判断铁电存储单元靠近所述第一电极的部分的极化方向是否被反转形成畴壁，以读取所述铁电存储单元存储的逻辑信息；读电压的方向与铁电存储单元产生畴壁时写电压的方向相同。若读取到第一电压线或第二电压线上的电流比较小，则可以判断出铁电薄膜层中不存在畴壁，进而读取到铁电存储单元存储的是第二逻辑信息；若读取到第一电压线或第二电压线上的电流比较大，则可以判断出铁电薄膜层中存在畴壁，进而读取到铁电存储单元存储的是第一逻辑信息。
在一种可能的实施方式中，在沿第一电极和第二电极相对的方向，畴壁与铁电存储单元的第一表面相交的交点和第二电极之间的间距ΔL＞0时；在第一电压线和第二电压线之间施加的读电压，使得畴壁与第二电极相交。这样一来，第一电极、第二电极以及畴壁形成导电通路，当读取到第一电压线或第二电压线上的电流值较大时，则可以判断出铁电存储单元靠近第一电极的部分的极化方向被反转，铁电薄膜层中形成有畴壁，也即可以判断出铁电存储元件存储的是第一逻辑信息。
附图说明
图1为本申请的实施例提供的一种电子设备的架构示意图；
图2为本申请的实施例提供的一种电子设备的结构示意图；
图3a为本申请的实施例提供的一种铁电存储器的结构示意图；
图3b为本申请的另一实施例提供的一种铁电存储器的结构示意图；
图4为本申请的又一实施例提供的一种铁电存储器的结构示意图；
图5a为本申请的实施例提供的一种铁电存储元件的结构示意图；
图5b为本申请的另一实施例提供的一种铁电存储元件的结构示意图；
图5c为本申请的又一实施例提供的一种铁电存储元件的结构示意图；
图6为本申请的实施例提供的一种第一电极、第二电极和铁电存储单元的俯视结构示意图；
图7a为本申请的另一实施例提供的一种第一电极、第二电极和铁电存储单元的俯视结构示意图；
图7b为图7a在扫描电镜下观测到的形貌图；
图8为本申请的再一实施例提供的一种铁电存储元件的结构示意图；
图9为本申请的另一实施例提供的一种铁电存储元件的结构示意图；
图10为本申请的实施例提供的一种开启电压Von与L的关系曲线图；
图11为本申请的又一实施例提供的一种铁电存储元件的结构示意图；
图12为本申请的实施例提供的一种数据写入过程和数据读取过程的I-V曲线测试图；
图13为本申请的实施例提供的一种铁电存储元件的图像；
图14为本申请的另一实施例提供的一种铁电存储元件的图像；
图15为本申请的再一实施例提供的一种铁电存储器的结构示意图；
图16为本申请的另一实施例提供的一种铁电存储器的结构示意图；
图17为本申请的又一实施例提供的一种铁电存储器的结构示意图。
附图标记：
01-电子设备；10-铁电存储器；11-存储器；12-处理器；13-输入设备；14-输出设备；15-中框；16-后壳；17-显示屏；20-铁电存储元件；100-铁电存储元件阵列；101-绝缘层；111-外存储器；112-内存储器；121-运算器；122-控制器；150-承载板；151-边框；200-基底；201-铁电薄膜层；202-第一电极；203-第二电极；2011-铁电存储单元；2011a-畴壁。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元。
此外，本申请实施例中，“上”、“下”、“左”以及“右”不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相 应地发生变化。在附图中，为了清楚起见，夸大了层和区域的厚度，图示中的各部分之间的尺寸比例关系并不反映实际的尺寸比例关系。
本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。
本申请实施例中，术语“模块”通常是按照逻辑划分的功能性结构，该“模块”可以由纯硬件实现，或者，软硬件结合实现。本申请实施例中，“和/或”描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B可以表示：单独存在A，单独存在B，同时存在A和B这三种情况。
本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等词旨在以具体方式呈现相关概念。
本申请实施例提供一种电子设备。该电子设备可以包括手机(mobile phone)、平板电脑(pad)、电视、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备等电子产品。本申请实施例对上述电子设备的具体形式不做特殊限制。
图1为本申请实施例示例性的提供的一种电子设备的架构示意图。如图1所示，该电子设备01包括：存储器11、处理器12、输入设备13、输出设备14等部件。本领域技术人员可以理解到，图1中示出的电子设备的结构并不构成对该电子设备01的限定，该电子设备01可以包括比如图1所示的部件更多或更少的部件，或者可以组合如图1所示的部件中的某些部件，或者可以与如图1所示的部件布置不同。
存储器11用于存储软件程序以及模块。存储器11主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备的使用所创建的数据(比如音频数据、图像数据、电话本等)等。此外，存储器11包括外存储器111和内存储器112。外存储器111和内存储器112存储的数据可以相互传输。外存储器111例如包括硬盘、U盘、软盘等。内存储器112例如包括随机存储器、只读存储器等。其中，随机存储器例如可以为铁电随机存储器，以下简称为铁电存储器。
处理器12是该电子设备01的控制中心，利用各种接口和线路连接整个电子设备01的各个部分，通过运行或执行存储在存储器11内的软件程序和/或模块，以及调用存储在存储器11内的数据，执行电子设备01的各种功能和处理数据，从而对电子设备01进行整体监控。可选的，处理器12可以包括一个或多个处理单元。例如，处理器12可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，飞行控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。例如， 处理器12可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器12中。上述的应用处理器例如可以为中央处理器(central processing unit，CPU)。图1中以处理器12为CPU为例，CPU可以包括运算器121和控制器122。运算器121获取内存储器112存储的数据，并对内存储器112存储的数据进行处理，处理后的结果通常送回内存储器112。控制器122可以控制运算器121对数据进行处理，控制器122还可以控制外存储器111和内存储器112存储数据或读取数据。
输入设备13用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。示例的，输入设备13可以包括触摸屏以及其他输入设备。触摸屏，也称为触摸面板，可收集用户在触摸屏上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触摸屏上或在触摸屏附近的操作)，并根据预先设定的程式驱动相应的连接装置。可选的，触摸屏可包括触摸检测装置和触摸控制器两个部分。其中，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给处理器12，并能接收处理器12发来的命令并加以执行。此外，可以采用电阻式、电容式、红外线以及表面声波等多种类型实现触摸屏。其他输入设备可以包括但不限于物理键盘、功能键(比如音量控制按键、电源开关按键等)、轨迹球、鼠标、操作杆等中的一种或多种。上述处理器12中的控制器122还可以控制输入设备13接收输入的信号或不接收输入的信号。此外，输入设备13接收到的输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入可以存储在内存储器112中。
输出设备14用于输出输入设备13输入，并存储在内存储器112中的数据对应的信号。例如，输出设备14输出声音信号或视频信号。上述处理器12中的控制器122还可以控制输出设备14输出信号或不输出信号。
需要说明的是，图1中的粗箭头用于表示数据的传输，粗箭头的方向表示数据传输的方向。例如，输入设备13和内存储器112之间的单箭头表示输入设备13接收到的数据向内存储器112传输。又例如，运算器121和内存储器112之间的双箭头表示内存储器112存储的数据可以向运算器121传输，且运算器121处理后的数据可以向内存储器112传输。图1中的细箭头表示控制器122可以控制的部件。示例的，控制器122可以对外存储器111、内存储器112、运算器121、输入设备13和输出设备14等进行控制。
可选的，如图1所示的电子设备01还可以包括各种传感器。例如陀螺仪传感器、湿度计传感器、红外线传感器、磁力计传感器等，在此不再赘述。可选的，该电子设备还可以包括无线保真(wireless fidelity，WiFi)模块、蓝牙模块等，在此不再赘述。
可以理解的，本申请实施例中，电子设备(例如上述图1示出的电子设备)可以执行本申请实施例中的部分或全部步骤，这些步骤或操作仅是示例，本申请实施例还可以执行其它操作或者各种操作的变形。此外，各个步骤可以按照本申请实施例呈现的不同的顺序来执行，并且有可能并非要执行本申请实施例中的全部操作。本申请各 实施例可以单独实施，也可以任意组合实施，本申请对此不作限定。
为了方便进一步对电子设备01的结构进行说明，以下以电子设备01为手机为例进行示例性介绍。如图2所示，电子设备01还可以包括中框15、后壳16以及显示屏17。后壳16和显示屏17分别位于中框15的两侧，且中框15和显示屏17设置于后壳16内。中框15包括用于承载显示屏17的承载板150，以及绕承载板150一周的边框151。电子设备01还可以包括设置于承载板150朝向后壳16的表面上的电路板，例如印刷电路板(printed circuit boards，PCB)以及设置于该电路板上的一些电子器件，例如上述的铁电存储器10；其中，铁电存储器10与电路板电连接。
本申请实施例还提供一种铁电存储器10，该铁电存储器10包括基底以及设置在基底上的至少一层铁电存储元件阵列100。在一些示例中，如图3a所示，铁电存储器10包括设置在基底上的一层铁电存储元件阵列100。在另一些示例中，如图3b所示，铁电存储器10包括设置在基底上，且依次排列的多层铁电存储元件阵列100(图3b以铁电存储器10包括三层铁电存储元件阵列100为例进行示意)，铁电存储器10还包括设置在相邻两层铁电存储元件阵列100之间的绝缘层101，该绝缘层101可以将相邻的两层铁电存储元件阵列100间隔开。此外，多层铁电存储元件阵列100依次排列的方向可以垂直于基底，也可以平行于基底。当铁电存储器10包括依次排列的多层铁电存储元件阵列100时，可以非常明显地提升存储密度。
需要说明的是，附图3a和图3b均未示意出基底。
以下以铁电存储器10包括一层铁电存储元件阵列100为例，对铁电存储器10的结构进行示例性介绍。当铁电存储器10包括依次排列的多层铁电存储元件阵列100时，多层铁电存储元件阵列100中的每一层铁电存储元件阵列100的结构都与铁电存储器10包括一层铁电存储元件阵列100时，铁电存储元件阵列100的结构相同。
如图3a所示，铁电存储器10(或者每层铁电存储元件阵列100)包括基底以及设置在基底上的相互交叉的多条第一电压线m和多条第二电压线n、以及多个铁电存储元件20。图3a以多条第一电压线m沿行方向延伸，多条第二电压线n沿列方向延伸为例。其中，每一行铁电存储元件20与一条第一电压线m电连接，每一列铁电存储元件20与一条第二电压线n电连接。
基于上述铁电存储器10的结构可知，本申请实施例提供的铁电存储器10具有crossbar结构。
此外，铁电存储器10(或者每层铁电存储元件阵列100)还包括相互交叉的多条行地址线(A0、A1…Ai-2、Ai-1)和多条列地址线(Ai、Ai+1…An-1、An)。其中，每一行铁电存储元件20与一条行地址线电连接，每一列铁电存储元件20与一条列地址线电连接。附图4中未示意出行地址线和列地址线与多个铁电存储元件20的连接关系。
如图4所示，铁电存储器10还包括读写控制器、行地址译码器和列地址译码器。上述的第一电压线m和第二电压线n均与读写控制器电连接。上述的多条行地址线均与行地址译码器电连接，上述的多条列地址线均与列地址译码器电连接。在一些实施例中，如图4所示，读写控制器还包括增压电路(charge pump)，增压电路用于使选中的铁电存储元件20在数据写入时能获得比较高的写入电压。
以下结合图4，对铁电存储器10的工作原理进行介绍。
当需要向铁电存储器10写入数据时，用于管理铁电存储器10的处理器基于数据所要存储的位置控制行地址译码器和列地址译码器进行寻址，选中所要写操作的铁电存储元件20，例如，选中图4中的铁电存储元件20a。然后，读写控制器向与铁电存储元件20a连接的第一电压线m和第二电压线n施加写电压Vw，所施加的写电压Vw大于铁电存储元件的矫顽电压Vc，写电压方向具有双极性，即可正可负，使铁电存储元件20发生极化方向反转或者极化方向恢复，以控制铁电存储元件20a中铁电畴壁产生或消失，从而向铁电存储元件20a写入逻辑信息“1”或逻辑信息“0”。
当需要从铁电存储器10读取数据时，用于管理铁电存储器10的处理器基于所要读取的数据存储的位置控制行地址译码器和列地址译码器进行寻址，选中所要读操作的铁电存储元件20，例如，选中图4中的铁电存储元件20a。然后，读写控制器向与铁电存储元件20a连接的第一电压线m和第二电压线n施加读电压Vr。所施加的读电压Vr小于铁电存储元件20的矫顽电压Vc，但是大于铁电存储元件20的开启电压Von，读电压Vr的方向与写入数据时铁电畴壁产生时对应的写电压的方向相同，也就是说读电压Vr的方向与初始极化方向相反，读写控制器向与铁电存储元件20a连接的第一电压线m和第二电压线n施加读电压后，通过读出放大器可以实时读取第一电压线m或第二电压线n上流过的电流值。若电流值大于预设参考值时，则读取到第一逻辑信息，第一逻辑信息例如为逻辑信息“1”，此时可以确定铁电存储元件20a存储的是第一逻辑信息。若电流值小于预设参考值时，则读取到第二逻辑信息，第二逻辑信息例如为逻辑信息“0”，此时可以确定铁电存储元件20a存储的是第二逻辑信息。
接下来，对上述铁电存储元件20的结构进行介绍。
如图5a、图5b和图5c所示，铁电存储元件20包括设置在基底200上的铁电薄膜层201；铁电薄膜层201包括向远离基底200一侧凸起的铁电存储单元2011；铁电存储元件20还包括相对设置于铁电存储单元2011两侧的第一电极202和第二电极203；第一电极202与铁电存储单元2011的第一表面和侧面均接触，第二电极203与铁电存储单元2011的第一表面和/或侧面接触；第一表面为铁电存储单元2011的与基底200平行且远离基底200的表面；其中，第一电极202与第一电压线m电连接；第二电极203与第二电压线n电连接。
附图5a、图5b和图5c为图4中铁电存储元件20沿aa向的剖面图。附图5a、图5b和图5c中用虚线框示意出了铁电存储单元2011。
上述“第一表面为铁电存储单元2011的与基底200平行且远离基底200的表面”中“与基底200平行”指的是与基底200和铁电薄膜层201接触的表面平行。
需要说明的是，可以是如图5a所示，第二电极203与铁电存储单元2011的第一表面接触；也可以是如图5b所示，第二电极203与铁电存储单元2011的侧面接触；当然还可以是如图5c所示，第二电极203与铁电存储单元2011的第一表面和侧面均接触。
参考图5c，铁电薄膜层201的第二表面，即铁电薄膜层201远离基底200的表面包括铁电存储单元2011的第一表面和侧面、以及除铁电存储单元2011的第一表面和侧面以外的其它表面。第一电极202和第二电极203可以与铁电薄膜层201的第二表 面中除铁电存储单元2011的第一表面和侧面以外的其它表面接触，也可以不接触。
此处，第一电极202和第二电极203相对设置于铁电存储单元2011两侧，即铁电存储单元2011将第一电极202和第二电极203间隔开，第一电极202和第二电极203相互独立，不接触。
在一些实施例中，第一电极202和第二电极203的材料包括铂(Pt)、铝(Al)、铬(Cr)、钛(Ti)、金(Au)、Cu(铜)、W(钨)、氮化钛(TiN)、多晶硅、硅和金属的化合物、钌酸锶(SrRuO 3)、掺杂铌的钛酸锶(Nb：SrTiO 3)、氧化铌(Nb 2O 5)、镍(Ni)、钴(Co)、钌(Ru)、二氧化钌(RuO 2)、铱(Ir)、二氧化铱(IrO 2)中的一种或多种。此外，第一电极202和第二电极203可以为单层结构，也可以为多层结构，每层结构都可以选用上述材料中的一种或多种。
在一些实施例中，第一电极202和第二电极203同时制作。具体制作过程例如可以为：先形成一层导电薄膜；再对导电薄膜进行构图，同时形成第一电极202和第二电极203。在另一些实施例中，第一电极202和第二电极203分别单独制作。在此情况下，可以先制作第一电极202，再制作第二电极203；也可以先制作第二电极203，再制作第一电极202。
上述的第一电极202和第二电极203也可以被称为读写电极对。
在一些实施例中，如图5c所示，沿第一电极202和第二电极203相对的方向，第一电极202与铁电存储单元2011的第一表面接触的长度L1为0＜L1≤500nm。
示例的，L1可以为5nm、60nm、100nm、300nm或500nm等。
在一些实施例中，如图5c所示，沿第一电极202和第二电极203相对的方向，第二电极203与铁电存储单元2011的第一表面接触的长度L2为0≤L2≤100nm。
示例的，L2可以为0、10nm、50nm、80nm、100nm等。当L2为0时，此时第二电极203仅与铁电存储单元2011的侧面接触，与铁电存储单元2011的第一表面不接触。
在一些实施例中，如图5c所示，沿第一电极202和第二电极203相对的方向，第一电极202和第二电极203之间的间距L为0＜L≤500nm。
示例的，L可以为5nm、10nm、50nm、100nm或500nm等。
此处，沿第一电极202和第二电极203相对的方向，第一电极202和第二电极203之间的间距L可以通过第一电极202与铁电存储单元2011的第一表面接触的长度L1和第二电极203与铁电存储单元2011的第一表面接触的长度L2进行调节。通常在设计第一电极202和第二电极203之间的间距L时，可以先选定好第一电极202与铁电存储单元2011的第一表面接触的长度L1，再通过调节第二电极203与铁电存储单元2011的第一表面接触的长度L2来调节第一电极202和第二电极203之间的间距L。
在一些实施例中，如图6和图7a所示，沿垂直于第一电极202和第二电极203相对的方向以及垂直于铁电存储单元2011的厚度的方向，铁电存储单元2011中位于第一电极202和第二电极203之间的部分、第一电极202和第二电极203中至少一个的宽度d的范围为5nm≤d≤10μm。
在一些示例中，上述宽度d的范围为5nm≤d≤500nm。
需要说明的是，对于铁电存储单元2011的第一表面的形状不做限定，例如，如图6所示，第一表面的形状为矩形，第一表面位于第一电极202和第二电极203之间的 部分的形状也为矩形。又例如，如图7a所示，第一表面的形状为不规则形状，第一表面的形状由矩形以及沿垂直于第一电极202和第二电极203相对的方向，设置在矩形两侧的梯形构成。第一表面位于第一电极202和第二电极203之间的部分的形状为矩形。将铁电存储单元2011的形状设计为如图7a和图7b所示的形状，这样是为了保证在第一电极202和第二电极203产生的电场的作用下，极化方向发生反转的电畴局限在第一电极202和第二电极203之间，不会发生电畴扩散现象。
图6和图7a为铁电存储元件20的俯视图。图7b为在扫描电镜下观测到的图7a所示的铁电存储元件20的形貌图。
此处，铁电存储单元2011中位于第一电极202和第二电极203之间的部分、第一电极202和第二电极203的宽度d可以相同，也可以不相同。
示例的，铁电存储单元2011中位于第一电极202和第二电极203之间的部分、第一电极202和第二电极203的宽度d可以为5nm、10nm、100nm、500nm、1μm、5μm和10μm等。
本申请实施例中，若沿垂直于第一电极202和第二电极203相对的方向以及垂直于铁电存储单元2011的厚度的方向，铁电存储单元2011中位于第一电极202和第二电极203之间的部分、第一电极202和第二电极203的宽度d太大，则不利于铁电存储元件20的微型化，铁电存储器10中包括的铁电存储元件20数量减小，即铁电存储器10中包括的铁电存储元件20的密度降低。若沿垂直于第一电极202和第二电极203相对的方向以及垂直于铁电存储单元2011的厚度的方向，铁电存储单元2011中位于第一电极202和第二电极203之间的部分、第一电极202和第二电极203的宽度d太小，则流过第一电极202和第二电极203的电流会较小。基于此，在本申请的一些实施例中，将沿垂直于第一电极202和第二电极203相对的方向以及垂直于铁电存储单元2011的厚度的方向，铁电存储单元2011中位于第一电极202和第二电极203之间的部分、第一电极202和第二电极203中至少一个的宽度d的范围设置为5nm≤d≤10μm，这样可以避免宽度太大或太小造成的影响。
在一些实施例中，铁电薄膜层201的材料可以包括但不限于：铌酸锂(LiNbO 3)、黑化的铌酸锂、掺杂的铌酸锂盐、钽酸锂(LiTaO 3)、黑化的钽酸锂、掺杂的钽酸锂盐、铁酸铋(BiFeO 3)、掺杂的铁酸铋盐(例如掺镧的铁酸铋盐)、钛酸铅锆(piezoelectric ceramic transducer，PZT)、掺杂的钛酸铅锆盐、钛酸钡(BaTiO 3)、掺杂的钛酸钡盐、钽酸锶、掺杂的钽酸锶盐、钽酸锶铋(SrBi 2Ta 2O 9，SBT)、掺杂的钽酸锶铋盐。其中，掺杂的铌酸锂盐或者掺杂的钽酸锂中的掺杂物可以包括氧化镁(MgO)、铁(Fe)、锰(Mn)、铒(Er)或钛(Ti)等中的一种或者多种。示例的，铌酸锂或者钽酸锂掺杂MgO的浓度范围可以为0-10mol％。
此处，在形成铁电薄膜层201时，可以先通过磁控溅射法、化学气相沉积法(chemical vapor deposition，CVD)、脉冲激光沉积法(pulsed laser deposition，PLD)、键合工艺等在基底200上形成一层厚度均匀的薄膜；然后，可以通过光刻、电子束直写或纳米压印等工艺将掩膜板上的图形转移到薄膜上，掩膜板上的图形与铁电存储单元2011的图形相同，因而实现了铁电存储单元2011的图形转移；之后，通过干法刻蚀或湿法刻蚀技术形成铁电存储单元2011。
应当理解到，在通过刻蚀形成铁电存储单元2011的过程中，由于工艺原因，铁电存储单元2011的侧面和第一表面可以是垂直的，也可以是非垂直的。本申请附图中，均以铁电存储单元2011的侧面和第一表面垂直为例进行示意。
在一些实施例中，如图5c所示，铁电薄膜层201的厚度h的范围为5nm≤h≤10μm。
示例的，铁电薄膜层201的厚度h可以为5nm、10nm、50nm、100nm、500nm、1μm或10μm等。
需要说明的是，由于铁电薄膜层201包括铁电存储单元2011，铁电存储单元2011相当于一个凸块，因而铁电薄膜层201的厚度是不均匀的，此处铁电薄膜层201的厚度h指的是铁电薄膜层201靠近基底200的表面到铁电存储单元2011的第一表面之间的距离。
在此基础上，应当理解到，沿第一电极202和第二电极203相对的方向，铁电薄膜层201靠近基底200的长度大于铁电存储单元2011的第一表面的长度。
需要说明的是，本申请实施例不对铁电薄膜层201的初始极化方向进行限定，只要铁电薄膜层201的初始极化方向不与第一电极202和第二电极203之间形成的电场方向垂直即可，即只要铁电薄膜层201的初始极化方向具有平行于基底200的面内分量即可。例如，第一电极202和第二电极203之间形成的电场方向平行于基底200，则只要铁电薄膜层201的初始极化方向不垂直于基底200即可。示例的，如图5a、图5b和图5c所示，铁电薄膜层201的初始极化方向P1平行于基底200向右。
此外，上述基底200的材料可以是铁电存储器10中常用的各种基底材料。在一些实施例中，基底200的材料为硅(Si)、钛酸锶(SrTiO 3)、铌酸锂中的一种或多种。由于硅衬底易于与CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)工艺兼容，有助于大规模生产，因而在一些示例中，基底200的材料为硅。在此基础上，若采用外延生长工艺等形成铁电薄膜层201，则基底200的材料的选择主要由铁电薄膜层201的材料决定。若采用键合工艺的方式将铁电薄膜层键合在基底200例如硅衬底上，则在一些实施例中，在硅衬底与铁电薄膜层201之间还需要插入一层电绝缘缓冲层。电绝缘缓冲层的材料例如为SiO 2(二氧化硅)等。
对于本申请实施例提供的铁电存储器10，由于一方面，铁电薄膜层201远离基底200的表面的晶格结构与铁电薄膜层201内部的晶格结构会有差异，铁电薄膜层201远离基底200的表面相当于有一层钝化层；另一方面，刻蚀形成铁电存储单元2011时，铁电薄膜层201远离基底200的表面会存在刻蚀损失，因而基于这两方面原因，铁电薄膜层201远离基底200的表面相当于存在一个天然选择管，因此铁电存储元件20具有开启电压Von，即本申请实施例中的铁电存储元件20具有非挥发性存储和选择管的双重功能，这样一来，本申请实施例提供的铁电存储元件20无需额外设置选择管。
基于上述铁电存储元件20的结构，以下结合图8、图9和图11，对铁电存储元件20的数据写入方法进行说明，结合图8，对铁电存储元件20的数据读取方法进行说明。图8、图9以及图11中均以铁电薄膜层201的初始极化方向P1平行于基底200向右为例。
铁电存储元件20的数据写入包括：
如图8所示，当需要向铁电存储元件20写入第一逻辑信息，第一逻辑信息例如为逻辑信息“1”时，在与该铁电存储元件20电连接的第一电压线m和第二电压线n之间施加第一写电压，以使铁电存储单元2011靠近第一电极202的部分形成与铁电薄膜层201靠近基底200的部分的极化方向(也即初始极化方向)相反的电畴，铁电薄膜层201中极化方向相反的电畴之间的畴壁2011a与第二电极203相交；如图9所示，在撤掉第一写电压后，畴壁2011a向靠近第一电极202的方向移动，畴壁2011a与铁电存储单元2011的第一表面相交，且不与第二电极203相交，从而写入第一逻辑信息“1”。此处，第一写电压的方向与铁电薄膜层201的初始极化方向相反。由于第一电极202与第一电压线m电连接，第二电极203与第二电压线n电连接，因而在第一电压线m和第二电压线n之间施加第一写电压，即在第一电极202和第二电极203之间施加第一写电压。
需要说明的是，在向铁电存储元件20写入第一逻辑信息“1”之前，若铁电存储元件20存储的是第二逻辑信息“0”，则施加第一写电压后，铁电存储单元2011靠近第一电极202的部分的极化方向被反转，形成与铁电薄膜层201靠近基底200的部分的极化方向相反的电畴；若铁电存储元件20存储的是第一逻辑信息“1”，则施加第一写电压后，铁电存储单元2011靠近第一电极202的部分的电畴的极化方向保持与铁电薄膜层201靠近基底200的部分的极化方向相反。本申请实施例，是以在向铁电存储元件20写入第一逻辑信息“1”之前，铁电存储元件20存储的是第二逻辑信息“0”为例进行的说明。
应当理解到，施加第一写电压后，铁电存储单元2011靠近第一电极202的部分形成极化方向与铁电薄膜层201靠近基底200的部分的极化方向相反的电畴，该电畴2011a一直延伸到与第二电极203相交。当第一写电压撤掉后，由于受到铁电薄膜层201自身的退极化场的作用，该电畴中靠近第二电极203的部分电畴的极化方向又再次反转回与铁电薄膜层201靠近基底200的部分的极化方向相同的方向，而靠近第一电极201的电畴保持施加第一写电压时的极化方向。也即，撤掉第一写电压后，被第一写电压反转的电畴向靠近第一电极202的方向收缩。
此处，以铁电薄膜层201的初始极化方向P1平行于基底200向右为例，在第一电极202和第二电极203之间施加第一写电压时,第一写电压的方向例如为由第一电极202指向第二电极203的方向。在此情况下，参考图8，可以向第一电压线m施加正电压，向第二电压线n施加负电压或接地处理。此时，第一电极202和第二电极203之间形成的电场方向由第一电极202指向第二电极203，第一电极202和第二电极203之间形成电场在平行于基底200的方向上的电场分量，使得铁电存储单元2011靠近第一电极202的部分的极化方向被反转，形成与铁电薄膜层201靠近基底200的部分的极化方向相反的电畴，反转后的极化方向为图8中所示的P2(即极化方向P2平行于基底200向左)。另外，参考图9，受退极化场的作用，撤销第一写电压后，铁电存储单元2011靠近第二电极203的部分的电畴反转回到初始极化方向(即极化方向平行于基底200向右)，而第一电极202附近的反转电畴保持反转后的方向(即极化方向平行于基底200向左)。
需要说明的是，由于第一电极202与铁电存储单元2011的第一表面和侧面接触， 因而参考图8和图9，写入操作后，铁电存储单元2011靠近第一电极202的部分的极化方向被反转，且反转后形成的电畴的剖视图的形状为三角形或类三角形。这样一来，铁电薄膜层201中极化方向相反的电畴之间形成畴壁2011a与铁电存储单元2011的第一表面相交。
应当理解到，由于第一电极202和第二电极203形成的电场在铁电存储单元2011各个位置处的电场强度是不同的，因而当铁电存储单元2011靠近第一电极202的部分在第一写电压的作用下反转后，铁电薄膜层201中极化方向相反的电畴之间的畴壁2011a的剖视图可能为直线，例如图9中的畴壁2011a，也可能为曲线，例如图9中的畴壁2011b和2011c。也即，铁电存储单元2011靠近第一电极202的部分形成的电畴的剖面形状可以为三角形，也可以为近似三角形(即类三角形)。
基于上述，在写入第一逻辑信息“1”时，沿第一电极202和第二电极203相对的方向，畴壁2011a与铁电存储单元2011的第一表面相交的交点T和第二电极203之间的间距ΔL，也即在写入第一逻辑信息“1”时，铁电存储单元2011靠近第一电极202的部分的极化方向被反转形成的电畴的大小，与沿第一电极202和第二电极203相对的方向，第一电极202和第二电极203之间的间距L的大小有关。可以通过调节第一电极202和第二电极203之间的间距L的大小来调节ΔL。第一电极202和第二电极203之间的间距L可以在制作铁电存储器10的过程中来调节，通常先设定好第一电极202与铁电存储单元2011的第一表面接触的长度L1，再通过调节第二电极203与铁电存储单元2011的第一表面接触的长度L2来调节第一电极202和第二电极203之间的间距L。应当理解到，畴壁2011a与铁电存储单元2011的第一表面相交的交点T和第二电极203之间的间距ΔL小于等于沿第一电极202和第二电极203相对的方向，第一电极202和第二电极203之间的间距L，即ΔL≤L。这是由于在退极化场的作用下，第一电极202和第二电极203之间的部分电畴会回到初始极化状态，但是在第一电极202附近反转的电畴与未反转的电畴达到平衡，第一电极202附近反转的电畴保持写入时的状态。
在一些实施例中，如图9所示，撤掉第一写电压后，沿第一电极202和第二电极203相对的方向，畴壁2011a与铁电存储单元2011的第一表面相交的交点T和第二电极203之间的间距ΔL为0＜ΔL≤500nm。
示例的，ΔL可以为10nm、50nm、100nm、200nm或500nm等。
在此基础上，可以理解的是，铁电存储元件20的开启电压Von与沿第一电极202和第二电极203相对的方向，畴壁2011a与铁电存储单元2011的第一表面相交的交点T和第二电极203之间的间距ΔL有关。
参考图10，提供多个铁电存储元件20，每个铁电存储元件20沿第一电极202和第二电极203相对的方向，第一电极202与铁电存储单元2011的第一表面接触的长度L1为170nm，沿第一电极202和第二电极203相对的方向，第二电极203与铁电存储单元2011的第一表面接触的长度L2为80nm，多个铁电存储元件20的第一电极202和第二电极203之间的间距L不相同，图10示意出了铁电存储元件20的开启电压Von随着第一电极202和第二电极203之间的间距L的变化趋势图。图10包括多个测试结果点，每个测试结果点表示某一铁电存储元件20的L值对应的开启电压Von，图10 中的直线是通过将多个测试结果点拟合得到。从图10可以看出，随着第一电极202和第二电极203之间的间距L逐渐减小，铁电存储元件20的开启电压Von逐渐减小。具体的，第一电极202和第二电极203之间的间距L从350nm逐渐降低到132nm，铁电存储元件20的开启电压Von从8.5V逐渐降低到0V。此处受工艺因素影响，在L＝132nm时，Von＝0V。在一些实施例中，在L值更小时，Von接近0V，如L＝5nm，Von＝0.3V等。应当理解到，受包括工艺和设计等因素影响，拟合线与L值的横轴交点不固定。从图10可以看出，通过调节L的大小可以实现开启电压Von可调。
如图11所示，当需要向铁电存储元件20写入第二逻辑信息，第二逻辑信息例如为逻辑信息“0”时，在第一电压线m和第二电压线n(即在第一电极202和第二电极203)之间施加第二写电压，以使铁电薄膜层201的极化方向相同，从而写入第二逻辑信息“0”；其中，第一写电压的方向与第二写电压的方向相反。
此处，由于第二写电压的方向与第一写电压的方向相反，若第一写电压的方向为由第一电极202指向第二电极203的方向，则第二写电压的方向为由第二电极203指向第一电极202的方向。在此情况下，参考图11，可以向第二电压线n施加正电压，向第一电压线m施加负电压或接地处理。此时，第一电极202和第二电极203之间形成的电场方向由第二电极203指向第一电极202，第一电极202和第二电极203之间形成电场在平行于基底200的方向上的电场分量，使得铁电存储单元2011中极化方向平行于基底200向左的电畴的极化方向反转，反转后的极化方向平行于基底200向右，这样一来，铁电薄膜层201的极化方向相同，铁电薄膜层201中的畴壁2011a消失，从而实现写入第二逻辑信息“0”。
在此基础上，在数据写入完成后，撤掉第二写电压后，铁电薄膜层201的极化方向不会发生变化。
基于上述铁电存储元件20的数据写入方法，应该理解到，在第一电压线m和第二电压线n之间施加的第一写电压和第二写电压均大于或等于铁电薄膜层201的矫顽电压Vc，矫顽电压Vc即为在外加电场的作用下，能使所加电场的部分的电畴发生反转的电压。
铁电存储元件20的数据读取方法包括：
在第一电压线m和第二电压线n之间施加读电压，根据第一电压线m或第二电压线n上的电流大小判断铁电存储单元2011靠近第一电极202的部分的极化方向是否被反转形成畴壁2011a，以读取铁电存储单元2011存储的逻辑信息。其中，读电压的方向与铁电存储单元2011产生畴壁时写电压的方向相同。由于第一电极202与第一电压线m电连接，第二电极203与第二电压线n电连接，因而在第一电压线m和第二电压线n之间施加读电压，即在第一电极202和第二电极203之间施加读电压。
如图8所示，在铁电存储单元2011产生畴壁2011a时写电压的方向为由第一电极202指向第二电极203时，读电压的方向为由第一电极202指向第二电极203。此时，可以向第一电压线m施加正电压，向第二电压线n施加负电压或接地处理。应该理解到，可以通过读出放大器读取第一电压线m或第二电压线n上的电流大小。
应当理解到，在铁电存储元件20为低阻态(例如铁电存储元件20存储第一逻辑信息时)的情况下，当在第一电压线m和第二电压线n之间施加的读电压大于开启电 压Von时，第一电压线m或第二电压线n上才能读到明显的电流值。基于此，在第一电压线m和第二电压线n之间施加的读电压大于铁电存储元件20的开启电压Von。此外，为了避免施加的读电压对铁电薄膜层201中电畴的极化方向进行反转，改变铁电存储元件20存储的逻辑信息，进而影响读取的准确性，因而在第一电压线m和第二电压线n之间施加的读电压小于铁电薄膜层201的矫顽电压Vc。
在第一电压线m和第二电压线n之间施加读电压时，若铁电存储单元2011存储的是第二逻辑信息“0”，由于铁电薄膜层201中不存在畴壁2011a，则第一电压线m和第二电压线n上流过的电流会比较小。基于此，若读取到第一电压线m或第二电压线n上的电流比较小，则可以判断出铁电薄膜层201中不存在畴壁2011a，即铁电薄膜层201中不存在极化方向相反的电畴，这样一来，便可以读取到铁电存储单元2011存储的第二逻辑信息“0”，实现铁电存储元件的非破坏性读取。
由于上述写入第一逻辑信息“1”时，在沿第一电极202和第二电极203相对的方向，畴壁2011a与铁电存储单元2011的第一表面相交的交点T和第二电极203之间的间距ΔL＞0，因而如图11所示，在第一电压线m和第二电压线n之间施加读电压时，由于读电压大于开启电压Von，因而该读电压使得畴壁2011a和第二电极203相交。这样一来，畴壁2011a与第一电极202、第二电极203均相交后，可以形成导电通路。基于此，当读取到第一电压线m或第二电压线n上的电流值较大时，则可以判断出铁电存储单元2011靠近第一电极202的部分的极化方向被反转，铁电薄膜层201中形成有畴壁2011a，也即可以判断出铁电存储元件20存储的是第一逻辑信息“1”。此时的读电压使畴壁2011a发生移动，即，使T点与第二电极203相交，让第二电极203与畴壁2011a连接。
在此基础上，当撤掉第一电极202和第二电极203之间的读电压后，铁电存储元件20又恢复到读操作之前的状态。示例的，当撤掉图8中施加在第一电压线m和第二电压线n之间的读电压时，铁电存储元件20又恢复到如图9所示的状态，即铁电存储单元2011靠近第一电极202的部分形成的电畴减小。
参考图12，图12为铁电存储元件20数据写入过程和数据读取过程的I(电流)-V(电压)曲线测试图。从图12中数据写入过程的I-V曲线测试图可以看出，写电压从0V开始逐渐增加，当写电压增加到接近2.9V时，电流值迅速增加到接近5μA左右，此时畴壁2011a与第二电极203接触，之后，随着写电压的增加，电流值在5μA左右跳变，当写电压增加到4V后，随着写电压的逐渐降低，电流值也逐渐降低。基于数据写入过程的I-V曲线测试图可知，当写电压为2.9V时，铁电薄膜层201中形成畴壁2011a，且畴壁2011a将第一电极202和第二电极203导通，因此电流值迅速增加。
从图12中数据读取过程的I-V曲线测试图可以看出，读电压从0V开始逐渐增加，当读电压增加到接近1.2V时，随着读电压的增加，电流值逐渐增加，当读电压增加到4V后，随着读电压的逐渐降低，电流值也逐渐降低。基于数据读取过程的I-V曲线测试图可知，当读电压增加到接近1.2V时，畴壁2011a与第二电极203相交，此时的开启电压Von＝1.2V，畴壁2011a将第一电极202和第二电极203导通，因此电流值大于0，随着读电压的增大，畴壁2011a逐渐向靠近第二电极203的方向扩展，畴壁2011a的长度增加，因此电流值逐渐增加。
以下提供一个具体的实施例，对铁电存储元件20的写第一逻辑信息“1”的操作过程和读第一逻辑信息“1”的操作过程进行说明。以沿垂直于第一电极202和第二电极203相对的方向以及垂直于铁电存储单元2011的厚度的方向，第一电极202和第二电极203的宽度d为110nm，沿第一电极202和第二电极203相对的方向，第一电极202与铁电存储单元2011的第一表面接触的长度L1为60nm，第二电极203与铁电存储单元2011的第一表面接触的长度L2为10nm，第一电极202和第二电极203之间的间隙为60nm，铁电薄膜层201的初始极化方向平行于基底200向右为例。
写第一逻辑信息“1”的操作过程为：参考图8，当向第一电极202和第二电极203之间施加4V的第一写电压时，第一电极202和第二电极203之间产生的电场方向由第一电极202指向第二电极203，在该电场的作用下，铁电存储单元2011靠近第一电极202的部分的极化方向被反转，形成极化方向平行于基底200向左的电畴，该电畴的剖面形状为三角形或类三角形。如图9所示，撤掉4V的第一写电压后，铁电存储单元2011靠近第一电极202的部分仍存在剖面形状为三角形或类三角形电畴。畴壁2011a与铁电存储单元2011的第一表面相交的交点T和第二电极203之间的间距ΔL约为30nm。
读第一逻辑信息“1”的操作过程为：参考图8，向第一电压线m和第二电压线n之间施加读电压，此时，读电压大于上述ΔL为30nm时对应的开启电压Von，施加读电压后，铁电存储单元2011中对应第一电极202和第二电极203之间间隙的部分的极化方向发生反转，反转后的极化方向平行于基底200向左，也即铁电存储单元2011靠近第一电极202的部分形成的极化方向向左的电畴向靠近第二电极203的方向扩展，这样一来，畴壁2011a与第二电极203相连，第一电极202、畴壁2011a以及第二电极203形成导电通道，从而可以产生读取电流。
在此基础上，当向第一电压线m和第二电压线n之间施加-4V的反向擦除电压，反向擦除电压的电压方向由第二电极203指向第一电极202后，如图11所示，铁电存储单元2011中极化方向在数据写入过程中被反转的电畴的极化方向又反转回与铁电薄膜层201的初始极化方向相同的方向，即铁电薄膜层201的极化方向相同，都是初始极化方向。
附图13为施加-4V的反向擦除电压后铁电存储元件20的图像。图13中左图为铁电存储元件20在扫描电镜下的形貌图。图13中中间图为铁电存储元件20的压电振幅成像图。图13中右图为铁电存储元件20的压电相位成像图。
附图14为施加4V的第一写电压后，再撤掉第一写电压后，铁电存储元件20的图像。此时，施加4V的第一写电压后，ΔL约为30nm。图14中左图为铁电存储元件20在扫描电镜下的形貌图。图14中中间图为铁电存储元件20的压电振幅成像图。图14中右图为铁电存储元件20的压电相位成像图。对比图13和图14可以看出，铁电存储单元2011靠近第一电极202的部分形成了电畴，图14中的压电振幅成像图和压电相位成像图中的虚线圈标示出了部分电畴。
本申请实施例提供一种铁电存储器10，铁电存储器10包括第一电压线m、第二电压线n以及铁电存储元件20。铁电存储元件20包括设置在基底200上的铁电薄膜层201；铁电薄膜层201包括向远离基底200一侧凸起的铁电存储单元2011；铁电存储 元件20还包括相对设置于铁电存储单元2011两侧的第一电极202和第二电极203；第一电极202与铁电存储单元2011的第一表面和侧面均接触，第二电极203与铁电存储单元2011的第一表面和/或侧面接触；第一表面为铁电存储单元2011远离基底的表面；其中，第一电极202与第一电压线m电连接；第二电极203与第二电压线n电连接。由于第一电极202与铁电存储单元2011的第一表面和侧面接触，因而在写入第一逻辑信息“1”，施加第一写电压时，铁电存储单元2011靠近第一电极202的部分形成与铁电薄膜层201靠近基底200的部分的极化方向相反的电畴，撤掉第一写电压后，铁电薄膜层201中极化方向相反的电畴之间的畴壁2011a与铁电存储单元2011的第一表面相交，且不与第二电极203相交。而铁电存储元件20的开启电压Von与沿第一电极202和第二电极203相对的方向，畴壁2011a与铁电存储单元2011的第一表面相交的交点T和第二电极203之间的间距ΔL有关，通过调节第一电极202和第二电极203之间的间距L的大小可以调节ΔL，进而可以调节开启电压Von，从而实现了对铁电存储元件20的开启电压Von的调节。此外，调节开启电压Von，相当于对铁电薄膜层201远离基底200表面的电阻值进行调节，因而可以通过调节开启电压Von使得读出电流增大，进而使得铁电存储元件20的读取速度更快。
在此基础上，随着铁电存储元件20的微型化，铁电存储元件20的矫顽电压Vc逐渐降低，由于本申请实施例提供的铁电存储元件20的开启电压Von可以调节，因而在铁电存储元件20的矫顽电压Vc降低时，可以降低铁电存储元件20的开启电压Von，这样一来，便可以满足读电压大于开启电压Von，小于铁电存储元件20的矫顽电压Vc，因此可以解决现有技术中限制矫顽电压Vc降低的问题。此外，矫顽电压Vc和开启电压Von都降低时，读写电压也会相应地降低，从而可以降低功耗。
图15为本申请实施例提供的一种crossbar结构局部阵列3×4等效示意图，图中铁电存储元件20b为选中待读写操作的铁电存储元件，该等效阵列配置电压为1/3Vdd模式，即使Von>1/3Vdd，在此情况下，未选中的铁电存储元件20两端配置的电压为1/3Vdd。由于铁电存储元件20具有天然的选通性，未被选中的铁电存储元件20的第一电极202和第二电压203之间配置电压<Von,处于未工作状态，而在选中的铁电存储元件20两端施加第一写入电压，使选中铁电存储元件20b的极化方向发生反转，写入第一逻辑信息“1”；相反地，在选中的铁电存储元件20b上施加第二写入电压，第二写入电压与第一写入电压方向相反，将选中的铁电存储元件20b的极化方向再次反转到初始状态，写入第一逻辑信息“0”，就是擦除操作。在选中的铁电存储元件20b的第一电极202和第二电极203之间施加读电压，读电压的方向与第一写电压方向相同，读电压小于第一写电压，大于开启电压Von，通过测量施加读电压后产生的电流大小，判断铁电存储元件20b存储的逻辑信息是“1”或者“0”。根据Von值与写入电压值的关系，如图16所示，也可以采用配置电压1/2Vdd模式，即Von>1/2Vdd，其中Vdd为电源电压，大于写入电压值，在此情况下，例如给与未选中的铁电存储元件20电连接的第一电压线m和第二电压线n上均施加电压为1/2Vdd。如图17所示，配置电压方式还可以采用crossbar方式floating(悬空)模式，即未选中的铁电存储元件20两端不配置电压，处于悬空状态。
在一些实施例中，沿第一电极202和第二电极203相对的方向，第一电极202与 铁电存储单元2011的第一表面接触的长度L1和第二电极203与铁电存储单元2011的第一表面接触的长度L2相同。在另一些实施例中，沿第一电极202和第二电极203相对的方向，第一电极202与铁电存储单元2011的第一表面接触的长度L1大于第二电极203与铁电存储单元2011的第一表面接触的长度L2。
应当理解到，在L1和L2相同的情况下，受退极化场作用，使铁电存储元件20由写入第一逻辑信息“1”变为写入第二逻辑信息“0”需要克服的矫顽电压Vc和使铁电存储元件20由写入第二逻辑信息“0”变为写入第一逻辑信息“1”需要克服的矫顽电压Vc不相同。
本申请实施例中，在L1大于L2的情况下，通过调节L1和L2，可以使铁电存储元件20由写入第一逻辑信息“1”变为写入第二逻辑信息“0”需要克服的矫顽电压Vc和使铁电存储元件20由写入第二逻辑信息“0”变为写入第一逻辑信息“1”需要克服的矫顽电压Vc相同，从而实现了对正负矫顽电压的对称调节，这样一来，铁电存储元件20存储的逻辑信息保持时间更长。
在一些实施例中，铁电薄膜层201包括导电薄膜层；其中，导电薄膜层位于铁电薄膜层远离基底200的表面。
此处，可以在形成第一电极202和第二电极203之前，对铁电薄膜层201远离基底200的表面进行改性处理，以形成导电薄膜层。
上述改性处理包括但不限于金属热扩散、离子注入以及表面黑化处理等。
此外，上述金属热扩散可以采用的金属为Cr、Ti、Ir、Cu、Ag(银)、Co、Pt、Al、Ni中的一种或多种。
另外，离子注入可以注入的金属离子为Cr、Ti、Ir、Cu、Ag、Co、Pt、Al、Ni中的一种或多种。
本申请实施例中，对铁电薄膜层远离基底200的表面进行改性处理，以形成导电薄膜层，从而可以降低铁电存储元件20的矫顽电压，增大读取电流。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (9)

  1. 一种铁电存储器，其特征在于，包括基底以及设置在所述基底上的第一电压线、第二电压线以及铁电存储元件；
    所述铁电存储元件包括设置在基底上的铁电薄膜层；所述铁电薄膜层包括向远离所述基底一侧凸起的铁电存储单元；
    所述铁电存储元件还包括相对设置于所述铁电存储单元两侧的第一电极和第二电极；所述第一电极与所述铁电存储单元的第一表面和侧面均接触，所述第二电极与所述铁电存储单元的第一表面和/或侧面接触；所述第一表面为所述铁电存储单元的与所述基底平行且远离所述基底的表面；
    其中，所述第一电极与所述第一电压线电连接；所述第二电极与所述第二电压线电连接。
  2. 根据权利要求1所述的铁电存储器，其特征在于，沿所述第一电极和所述第二电极相对的方向，所述第一电极与所述铁电存储单元的第一表面接触的长度L1大于所述第二电极与所述铁电存储单元的第一表面接触的长度L2。
  3. 根据权利要求1或2所述的铁电存储器，其特征在于，沿所述第一电极和所述第二电极相对的方向，所述第一电极与所述铁电存储单元的第一表面接触的长度L1为0＜L1≤500nm。
  4. 根据权利要求1-3任一项所述的铁电存储器，其特征在于，沿所述第一电极和所述第二电极相对的方向，所述第二电极与所述铁电存储单元的第一表面接触的长度L2为0≤L2≤100nm。
  5. 根据权利要求1-4任一项所述的铁电存储器，其特征在于，沿所述第一电极和所述第二电极相对的方向，所述第一电极和所述第二电极之间的间距L为0＜L≤500nm。
  6. 根据权利要求1所述的铁电存储器，其特征在于，所述铁电薄膜层包括导电薄膜层；
    其中，所述导电薄膜层位于所述铁电薄膜层远离所述基底的表面。
  7. 根据权利要求1所述的铁电存储器，其特征在于，所述铁电薄膜层的厚度h的范围为5nm≤h≤10um。
  8. 根据权利要求1所述的铁电存储器，其特征在于，沿垂直于所述第一电极和所述第二电极相对的方向以及垂直于所述铁电存储单元的厚度的方向，所述铁电存储单元中位于所述第一电极和所述第二电极之间的部分、所述第一电极和所述第二电极中至少一个的宽度d的范围为5nm≤d≤10μm。
  9. 一种电子设备，其特征在于，包括电路板以及与所述电路板电连接的铁电存储器；
    其中，所述铁电存储器为如权利要求1-8任一项所述的铁电存储器。
PCT/CN2020/130620 2020-11-20 2020-11-20 一种铁电存储器及电子设备 WO2022104742A1 (zh)

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