WO2022227019A1 - 一种形成栅极的方法及半导体器件 - Google Patents

一种形成栅极的方法及半导体器件 Download PDF

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WO2022227019A1
WO2022227019A1 PCT/CN2021/091551 CN2021091551W WO2022227019A1 WO 2022227019 A1 WO2022227019 A1 WO 2022227019A1 CN 2021091551 W CN2021091551 W CN 2021091551W WO 2022227019 A1 WO2022227019 A1 WO 2022227019A1
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opening
photoresist layer
photoresist
gate
layer
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PCT/CN2021/091551
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English (en)
French (fr)
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宁开明
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华为技术有限公司
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Priority to PCT/CN2021/091551 priority Critical patent/WO2022227019A1/zh
Priority to CN202180087364.6A priority patent/CN116670835A/zh
Publication of WO2022227019A1 publication Critical patent/WO2022227019A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

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  • the present application relates to the field of semiconductors, and in particular, to a method for forming a gate and a semiconductor device.
  • a high electron mobility transistor includes an epitaxial structure having a heterojunction and a source electrode, a drain electrode and a gate electrode formed on the epitaxial structure.
  • the size of the gate is generally made small, such as making the gate width 1um, 0.5um, 0.25um, 0.15um, 0.10um or 0.07um. But as the size of the gate gets smaller, the resistance of the gate increases and degrades the performance of the high electron mobility transistor. Therefore, the current gate structure is usually made into a T-shaped structure.
  • the part of the gate in contact with the epitaxial structure is made relatively small to improve the performance of the high electron mobility transistor, and the part of the gate far from the epitaxial structure is made relatively large to reduce the overall resistance of the gate, thereby avoiding The performance of high electron mobility transistors is affected by the large gate resistance.
  • the gate of the T-shaped structure it is necessary to form two layers of photoresist on the epitaxial structure (for example, the lower layer near the epitaxial structure), so as to use the photolithography technology to form the gate of the T-shaped structure twice.
  • the pattern structure of the large-sized part and the small-sized part of the pole is convenient to fill the metal to form the gate.
  • photolithography is performed on two layers of photoresist, it often occurs that when the upper layer of photoresist is exposed and developed to form a pattern structure, the upper layer of photoresist will pull the next layer due to the stress generated during the exposure and development process. of the photoresist causes the next layer of photoresist to deform.
  • there is a large error between the formed pattern structure and the expected size which reduces the quality of the gate of the T-shaped structure finally formed.
  • the embodiments of the present application provide a method for forming a gate and a semiconductor device, which solve the problem that there is a large error between the pattern structure formed by the photoresist and the expected size, which reduces the quality of the gate of the T-shaped structure finally formed.
  • embodiments of the present application provide a method for forming a gate.
  • the method includes sequentially forming a first photoresist layer and a second photoresist layer on the side of the epitaxial structure away from the substrate; exposing and developing the second photoresist layer and the first photoresist layer, A first opening is formed on the resist layer and a second opening is formed on the first photoresist layer; the first opening is larger than the second opening, and the second opening is located in the orthographic projection area of the first opening on the first photoresist layer ; Expose and develop the first photoresist layer to form a third opening on the first photoresist layer; the third opening covers the second opening, and the third opening is smaller than the first opening; in the first opening and the third opening Fill metal to form the gate.
  • the upper layer of the two layers of photoresist is exposed and developed, and the photoresist of the lower layer can be opened at the same time, so that the photoresist of the lower layer can be opened.
  • the resist can release the stress during exposure and development of the previous layer of photoresist through the opening. Therefore, the pulling of the upper layer of photoresist to the lower layer of photoresist can prevent the next layer of photoresist from being affected by the upper layer of photoresist, and the size error of the pattern structure formed after exposure and development is large.
  • the quality of the finally formed gate electrode can be improved.
  • filling the first opening and the third opening with metal to form the gate includes: forming a metal layer on the surface of the second photoresist layer by metal evaporation; wherein, the metal layer is filled in the first A gate is formed in the opening and the second opening.
  • filling the metal layer by means of metal evaporation is convenient for implementation and can form a relatively uniform gate structure.
  • the method further includes: stripping the second photoresist layer. In this way, by peeling off the second photoresist layer, the metal other than the gate electrode attached to the second photoresist layer can be removed, which facilitates subsequent formation of other structures.
  • the method further includes: baking the second photoresist layer.
  • the shape of the formed first opening can be made more stable and less deformed.
  • the method further includes: baking the first photoresist layer.
  • baking the first photoresist layer By baking the first photoresist layer, the shape of the formed third opening can be made more stable and less deformed.
  • the method further includes: exposing the first photoresist layer and the second photoresist layer to the second photoresist layer.
  • the resist layer is baked.
  • the thickness of the first photoresist layer is smaller than the thickness of the second photoresist layer.
  • both the first photoresist layer and the second photoresist layer use electron beam photoresist.
  • the second opening is a square opening.
  • inventions of the present application provide a semiconductor device.
  • the semiconductor device may include an epitaxial structure and a gate, source and drain disposed on the epitaxial structure.
  • the gate is formed by the method in the above-mentioned first aspect.
  • FIG. 1 is a schematic flowchart of a method for forming a gate according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a semiconductor device when a method for forming a gate provided by an embodiment of the present application is applied;
  • FIG. 3 is a schematic composition diagram of an epitaxial structure provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a semiconductor device when another method for forming a gate provided by an embodiment of the present application is applied;
  • FIG. 5 is a schematic structural diagram of a semiconductor device when another method for forming a gate provided by an embodiment of the present application is applied;
  • FIG. 6 is a schematic structural diagram of a semiconductor device when another method for forming a gate provided by an embodiment of the present application is applied;
  • FIG. 7 is a schematic structural diagram of a semiconductor device when another method for forming a gate provided by an embodiment of the present application is applied;
  • FIG. 8 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
  • High electron mobility transistors (HEMT) devices are semiconductor devices with larger breakdown voltage and power density, which are made by making full use of the two-dimensional electron gas formed by the heterojunction structure of semiconductors.
  • a high electron mobility transistor includes an epitaxial structure having a heterojunction and a source electrode, a drain electrode and a gate electrode formed on the epitaxial structure.
  • the size of the gate is generally made small, such as making the gate width 1um, 0.5um, 0.25um, 0.15um, 0.10um or 0.07um. But as the size of the gate gets smaller, the resistance of the gate increases and degrades the performance of the high electron mobility transistor. Therefore, the current gate structure is usually made into a T-shaped structure.
  • the part of the gate in contact with the epitaxial structure is made relatively small to improve the performance of the high electron mobility transistor, and the part of the gate far from the epitaxial structure is made relatively large to reduce the overall resistance of the gate, thereby avoiding The performance of high electron mobility transistors is affected by the large gate resistance.
  • the gate of the T-shaped structure it is necessary to form two layers of photoresist on the epitaxial structure (for example, the lower layer near the epitaxial structure), so as to use the photolithography technology to form the gate of the T-shaped structure twice.
  • the pattern structure of the large-sized part and the small-sized part of the pole is convenient to fill the metal to form the gate.
  • a layer of polymethyl methacrylate (PMMA) photoresist can be formed on the epitaxial structure, and then a layer of I line ( I-line) photoresist.
  • PMMA polymethyl methacrylate
  • the I-line photoresist is exposed and developed to form a pattern structure of a portion of the gate electrode of the T-shaped structure away from the epitaxial structure.
  • the PMMA photoresist is exposed and developed to form a pattern structure of the portion where the gate of the T-shaped structure is in contact with the epitaxial structure.
  • a layer of PMMA photoresist may be formed on the epitaxial structure, and then a layer of E-beam photoresist may be formed on the PMMA photoresist.
  • the E-beam photoresist is first exposed and developed to form a patterned structure of a portion of the gate electrode of the T-shaped structure away from the epitaxial structure.
  • the PMMA photoresist is exposed and developed to form a pattern structure of the portion where the gate of the T-shaped structure is in contact with the epitaxial structure.
  • embodiments of the present application provide a method for forming a gate.
  • a gate having a T-shaped structure with small dimensional error can be formed on the epitaxial structure of the semiconductor device.
  • FIG. 1 shows a schematic flowchart of a method for forming a gate according to an embodiment of the present application.
  • the method of forming a gate may include the following S101 to S104.
  • a first photoresist layer 202 and a second photoresist layer 203 are formed on the epitaxial structure 201 .
  • the epitaxial structure is used to form a semiconductor device with a gate electrode, a source electrode and a drain electrode, and the epitaxial structure may be a hierarchical structure including a heterojunction.
  • the epitaxial structure may include various types, which are not limited here.
  • the semiconductor device is a high electron mobility transistor device
  • the epitaxial structure as shown in FIG. 3 may include a substrate 301 and a buffer layer 302, a channel layer 303 and a barrier layer 304 formed on the substrate in sequence.
  • the first layer of photoresist in this step is formed on the barrier layer 304 of the epitaxial structure.
  • the materials used for the channel layer 303 and the barrier layer 304 respectively may be a gallium nitride channel layer and an aluminum gallium nitride barrier layer.
  • the channel layer 303 and the potential layer may also be
  • the barrier layer 304 is respectively set as a gallium nitride channel layer and an indium gallium nitride barrier layer, an indium gallium arsenide channel layer and an aluminum gallium arsenic barrier layer, etc., and the specific channel layer materials and barrier layer materials are not different here. It is limited as long as the channel layer 303 and the barrier layer 304 can form a heterojunction structure to generate a two-dimensional electron gas channel.
  • the substrate 301 can generally be a heterogeneous substrate such as sapphire, silicon carbide, and silicon. Therefore, by first forming the buffer layer 302 between the substrate 301 and the channel layer 303, the lattice mismatch and thermal mismatch between the channel layer 303 and the substrate 301 can be alleviated, so that the channel layer 303 can be more Good epitaxy is grown on substrate 301 .
  • a contact layer (not shown in the figure) may also be formed on the barrier layer 304 in the epitaxial structure shown in FIG. 3 .
  • the first photoresist layer and the second photoresist layer may be formed by coating, respectively.
  • the first photoresist layer is firstly coated on the side of the epitaxial structure away from the substrate, and then the second photoresist layer is coated on the first photoresist layer.
  • the first photoresist layer and the second photoresist layer are respectively formed by coating, which can make the first photoresist layer and the second photoresist layer more uniform, and the operation is convenient.
  • the large-sized portion and the small-sized portion of the first photoresist layer and the second photoresist layer are respectively used to form the gate of the T-shaped structure after exposure and development, so the first photoresist layer and the second photoresist layer are respectively used.
  • the thickness of the adhesive layer may be set according to the height of the large-sized portion and the height of the small-sized portion of the gate electrode of the T-shaped structure to be formed, respectively.
  • the first photoresist layer is used to form a small-sized portion corresponding to the gate of the T-shaped structure after exposure and development (ie, the portion where the gate is in contact with the epitaxial structure), and the second photoresist layer is used to form a corresponding portion after exposure and development.
  • the thickness of the first photoresist layer is generally equal to the height of the small-sized portion of the gate of the T-shaped structure.
  • the thickness is generally equal to the height of the large size portion of the T-shaped gate. Therefore, if the height of the small-sized portion of the gate of the T-shaped structure to be formed is smaller than that of the large-sized portion, the corresponding thickness of the first photoresist layer is smaller than that of the second photoresist layer.
  • the corresponding thickness of the first photoresist layer is greater than that of the second photoresist layer. If the height of the small-sized portion of the gate of the T-shaped structure to be formed is equal to the height of the large-sized portion, the corresponding thickness of the first photoresist layer is equal to the thickness of the second photoresist layer.
  • the first photoresist layer and the second photoresist layer may use the same photoresist, or may use different photoresists.
  • the first photoresist layer and the second photoresist layer both use electron beam (E-beam) photoresist.
  • E-beam electron beam
  • the photoresist that can be used for the first photoresist layer and the second photoresist layer can also be PMMA photoresist, I-line photoresist, etc., which is not limited here, as long as it is photoresist Can.
  • a first opening 402 is formed on the second photoresist layer 401
  • a second opening 404 is formed in the first photoresist layer 403 .
  • the stress generated by the second photoresist layer during the exposure and development process can be released, so that the pulling of the second photoresist layer to the first photoresist layer can prevent the first photoresist layer from being affected by the second photoresist layer. Due to the influence of the photoresist layer, the size error of the pattern structure formed after exposure and development is large.
  • first opening is larger than the second opening may mean that the opening width of the first opening is larger than the opening width of the second opening.
  • the shape and size (such as width and height) of the above-mentioned first opening are generally the same as the shape and size of the large-sized portion of the gate of the T-shaped structure to be formed (that is, the portion of the gate away from the epitaxial structure), so that The first opening is subsequently filled with metal to form a large portion of the T-shaped gate.
  • the size of the second opening can be set according to actual needs. Usually, the size of the second opening is smaller than the size of the small-sized portion of the T-shaped gate (that is, the portion where the gate is in contact with the epitaxial structure). An opening corresponding to the size of the small-sized portion of the T-shaped gate is formed on the basis of the two openings (ie, covering the second opening). Generally, for ease of formation, the second opening is typically a square mouth.
  • the shape of the second opening is not limited in the embodiment of the present application. In practical applications, only the second opening needs to be formed.
  • the second photoresist and the first photoresist can be firstly exposed to the second opening corresponding to the second opening.
  • the resist is exposed and developed.
  • the second photoresist layer is exposed and developed corresponding to the first opening to form the above-mentioned first opening and second opening.
  • other methods may also be used to form the first opening and the second opening by exposing and developing the first photoresist layer and the second photoresist layer, which are not limited here.
  • that the third opening is smaller than the first opening may be that the opening width of the third opening is smaller than the opening width of the first opening.
  • a third opening 502 is formed on the first photoresist layer 501 .
  • the third opening 502 is formed based on the second opening 404 shown in FIG. 4 (please refer to FIG. 4 ), that is, the size of the third opening 502 is larger than that of the second opening 404 , and the third opening 502 covers the second opening 404 .
  • the shape and size (such as width and height) of the above-mentioned third opening are generally the same as the shape and size of the small-sized portion of the gate of the T-shaped structure to be formed (that is, the portion where the gate is in contact with the epitaxial structure). In order to subsequently fill the third opening with metal to form a small-sized portion of the T-shaped gate.
  • the first opening and the third opening may be filled with metal by ion sputtering, or the first opening and the third opening may be filled with metal by metal vapor deposition.
  • a metal layer 602 can be formed on the surface of the second photoresist layer 601 by metal evaporation. and the third opening, so the metal layer 602 can be filled in the first opening and the third opening to form a gate.
  • the second photoresist in order to remove the metal attached to the second photoresist layer other than the gate structure, after the gate is formed, the second photoresist can also be removed by a lift-off process. Layer 601 peels off.
  • the second photoresist layer may be baked by a hot plate process.
  • the first photoresist layer may also be baked by a hot plate process.
  • the first opening and the second opening may be formed by exposing and developing the second photoresist layer and the first photoresist layer, and the first opening and the second opening may be formed by exposing and developing the first photoresist layer. After three openings, the first photoresist layer and the second photoresist layer are baked uniformly through a hot plate process.
  • the upper layer of the two layers of photoresist is exposed and developed, and the photoresist of the lower layer can be opened at the same time, so that the lower layer of photoresist can be opened.
  • a layer of photoresist can release the stress during exposure and development of the previous layer of photoresist through the opening. Therefore, the pulling of the upper layer of photoresist to the lower layer of photoresist can prevent the next layer of photoresist from being affected by the upper layer of photoresist, and the size error of the pattern structure formed after exposure and development is large. The quality of the finally formed gate electrode can be improved.
  • the embodiments of the present application further provide a semiconductor device.
  • the semiconductor device may include an epitaxial structure 801 and a gate electrode 802 and a source electrode 803 disposed on the epitaxial structure 801 . and drain 804.
  • the drain electrode of the semiconductor device can be formed by the method for forming the gate electrode described in the foregoing embodiments. Therefore, the gate in the semiconductor device has higher dimensional accuracy and higher quality.

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Abstract

本申请实施例公开了一种形成栅极的方法及半导体器件，涉及半导体领域。解决了光刻胶形成的图形结构与预期尺寸存在较大误差，降低最终形成的T形结构的栅极的质量的问题。具体方案为：在外延结构远离衬底的一侧依序形成第一光刻胶层以及第二光刻胶层；在第二光刻胶层上形成第一开口以及在第一光刻胶层上形成第二开口；第一开口大于第二开口，第二开口位于第一开口在第一光刻胶层上的正投影区域内；对第一光刻胶层曝光显影，在第一光刻胶层上形成第三开口；第三开口覆盖第二开口，且第三开口小于第一开口；在第一开口和第三开口内填充金属形成栅极。

Description

一种形成栅极的方法及半导体器件 技术领域
本申请涉及半导体领域，尤其涉及一种形成栅极的方法及半导体器件。
背景技术
通常高电子迁移率晶体管(high electron mobility transistor，HEMT)包括具有异质结的外延结构以及形成在外延结构上的源极、漏极和栅极。为了能够提高高电子迁移率晶体管的性能，一般会将栅极的尺寸做的很小，如将栅极的宽做到1um、0.5um、0.25um、0.15um、0.10um或者0.07um等。但是随着栅极的尺寸越来越小，栅极的电阻会越来越大又会降低高电子迁移率晶体管的性能。因此，目前的栅极结构通常做成T形结构。即将栅极与外延结构接触的部分做的相对较小，以提高高电子迁移率晶体管的性能，而将栅极远离外延结构的部分做的相对较大，以降低栅极整体的电阻，从而避免因栅极电阻较大而影响到高电子迁移率晶体管的性能。
一般，在形成T形结构的栅极时，需要在外延结构上分别形成两层光刻胶(如靠近外延结构的下面一层)，以利用光刻技术分别分两次形成T形结构的栅极的大尺寸部分和小尺寸部分的图形结构，以便于填充金属形成栅极。但是，在对两层光刻胶进行光刻时，经常会出现上一层光刻胶曝光显影形成图形结构时，因曝光显影过程中产生的应力作用上一层光刻胶会拉扯下一层的光刻胶导致下一层光刻胶变形。从而导致对下一层的光刻胶进行曝光显影后，形成的图形结构与预期尺寸存在较大误差的情况，降低最终形成的T形结构的栅极的质量。
发明内容
本申请实施例提供一种形成栅极的方法及半导体器件，解决了光刻胶形成的图形结构与预期尺寸存在较大误差，降低最终形成的T形结构的栅极的质量的问题。
为了达到上述目的，本申请实施例采用如下技术方案：
第一方面，本申请实施例提供一种形成栅极的方法。该方法包括在外延结构远离衬底的一侧依序形成第一光刻胶层以及第二光刻胶层；对第二光刻胶层和第一光刻胶层曝光显影，在第二光刻胶层上形成第一开口以及在第一光刻胶层上形成第二开口；第一开口大于第二开口，第二开口位于第一开口在第一光刻胶层上的正投影区域内；对第一光刻胶层曝光显影，在第一光刻胶层上形成第三开口；第三开口覆盖第二开口，且第三开口小于第一开口；在第一开口和第三开口内填充金属形成栅极。
采用上述技术方案，在形成T形结构的栅极时，先对两层光刻胶中的上一层进行曝光显影的同时能够对下一层的光刻胶进行开口，以使下一层光刻胶可以通过开口释放上一层光刻胶曝光显影时的应力。从而能够避免上一层光刻胶对下一层光刻胶的拉扯导致下一层光刻胶受到上一层光刻胶的影响而曝光显影后形成的图形结构尺寸误差较大的情况。能够提高最终形成的栅极的质量。
在一种可能的实现方式中，在第一开口和第三开口内填充金属形成栅极包括：在 第二光刻胶层的表面通过金属蒸镀形成金属层；其中，金属层填充于第一开口和第二开口内形成栅极。如此，通过金属蒸镀的方式填充金属层，便于实施且能够形成相对均匀的栅极结构。
在另一种可能的实现方式中，在第一开口和第三开口内填充金属形成栅极之后，方法还包括：剥离第二光刻胶层。如此，通过剥离第二光刻胶层，能够将栅极以外的附着在第二光刻胶层上的金属去除掉，便于后续形成其他结构。
在另一种可能的实现方式中，在对第二光刻胶层和第一光刻胶层曝光显影，在第二光刻胶层上形成第一开口以及在第一光刻胶层上形成第二开口之后，方法还包括：对第二光刻胶层进行烘烤。通过对第二光刻胶层的烘烤能够使形成的第一开口的形状更加稳固不易变形。
在另一种可能的实现方式中，在对第一光刻胶层曝光显影，在第一光刻胶层上形成第三开口之后，方法还包括：对第一光刻胶层进行烘烤。通过对第一光刻胶层进行烘烤，能够使形成的第三开口的形状更加稳固不易变形。
在另一种可能的实现方式中，在对第一光刻胶层曝光显影，在第一光刻胶层上形成第三开口之后，方法还包括：对第一光刻胶层和第二光刻胶层进行烘烤。通过在形成了第一开口和第三开口后再对第一光刻胶层和第二光刻胶层进行烘烤，能够简化工艺，并且可避免烘烤时对第一光刻胶层产生影响导致后续在第一光刻胶层上形成的第三开口尺寸误差较大。
在另一种可能的实现方式中，第一光刻胶层的厚度小于第二光刻胶层的厚度。
在另一种可能的实现方式中，第一光刻胶层和第二光刻胶层均采用电子束光刻胶。
在另一种可能的实现方式中，第二开口为方形口。
第二方面，本申请实施例提供了一种半导体器件。该半导体器件可以包括外延结构以及设置于外延结构上的栅极、源极和漏极。其中，栅极采用上述第一方面中的方法形成。
应当理解的是，上述第二方面的有益效果可以参见上述第一方面中的相关描述，在此不再赘述。
附图说明
图1为本申请实施例提供的一种形成栅极的方法的流程示意图；
图2为本申请实施例提供的一种形成栅极的方法应用时的半导体器件的结构示意图；
图3为本申请实施例提供的一种外延结构的组成示意图；
图4为本申请实施例提供的另一种形成栅极的方法应用时的半导体器件的结构示意图；
图5为本申请实施例提供的另一种形成栅极的方法应用时的半导体器件的结构示意图；
图6为本申请实施例提供的另一种形成栅极的方法应用时的半导体器件的结构示意图；
图7为本申请实施例提供的另一种形成栅极的方法应用时的半导体器件的结构示意图；
图8为本申请实施例提供的一种半导体器件的结构示意图。
具体实施方式
高电子迁移率晶体管(high electron mobility transistors，HEMT)器件，是一种充分利用半导体的异质结结构形成的二维电子气而制成的，具有更大击穿电压和功率密度的半导体器件。
通常高电子迁移率晶体管(high electron mobility transistor，HEMT)包括具有异质结的外延结构以及形成在外延结构上的源极、漏极和栅极。为了能够提高高电子迁移率晶体管的性能，一般会将栅极的尺寸做的很小，如将栅极的宽做到1um、0.5um、0.25um、0.15um、0.10um或者0.07um等。但是随着栅极的尺寸越来越小，栅极的电阻会越来越大又会降低高电子迁移率晶体管的性能。因此，目前的栅极结构通常做成T形结构。即将栅极与外延结构接触的部分做的相对较小，以提高高电子迁移率晶体管的性能，而将栅极远离外延结构的部分做的相对较大，以降低栅极整体的电阻，从而避免因栅极电阻较大而影响到高电子迁移率晶体管的性能。
一般，在形成T形结构的栅极时，需要在外延结构上分别形成两层光刻胶(如靠近外延结构的下面一层)，以利用光刻技术分别分两次形成T形结构的栅极的大尺寸部分和小尺寸部分的图形结构，以便于填充金属形成栅极。例如，在形成T形结构的栅极时，可以在外延结构上形成一层聚甲基丙烯酸甲酯(polymethyl methacrylate，PMMA)光刻胶，然后再在PMMA光刻胶上形成一层I线(I-line)光刻胶。然后，先曝光显影I-line光刻胶以形成T形结构的栅极的远离外延结构的部分的图形结构。然后再曝光显影PMMA光刻胶以形成T形结构的栅极与外延结构接触的部分的图形结构。又例如，在形成T形结构的栅极时，可以在外延结构上形成一层PMMA光刻胶，然后再在PMMA光刻胶上形成一层E-beam光刻胶。然后，先曝光显影E-beam光刻胶以形成T形结构的栅极的远离外延结构的部分的图形结构。然后再曝光显影PMMA光刻胶以形成T形结构的栅极与外延结构接触的部分的图形结构。
但是，在对两层光刻胶进行光刻时，经常会出现上一层光刻胶曝光显影形成图形结构时，因曝光显影过程中产生的应力作用上一层光刻胶会拉扯下一层的光刻胶导致下一层光刻胶变形。从而导致对下一层的光刻胶进行曝光显影后，形成的图形结构与预期尺寸存在较大误差的情况，降低最终形成的T形结构的栅极的质量。
为解决上述的问题，本申请实施例提供了一种形成栅极的方法。能够通过该形成栅极的方法在半导体器件的外延结构上形成尺寸误差较小的具有T形结构的栅极。
图1示出了本申请实施例提供的一种形成栅极的方法的流程示意图。如图1所示，该形成栅极的方法可以包括以下S101至S104。
S101、在外延结构远离衬底的一侧依序形成第一光刻胶层以及第二光刻胶层。
示例地，如图2所示，在外延结构201上形成第一光刻胶层202和第二光刻胶层203。
其中，外延结构用于与栅极、源极和漏极组成半导体器件，外延结构可以是包括异质结的层级结构。根据半导体器件的不同以及异质结的不同，外延结构可以包括多种，此处不做限制。例如，半导体器件为高电子迁移率晶体管器件，则外延结构如图3所示，可以包括衬底301以及依序形成于衬底上的缓冲层302、沟道层303和势垒层 304。相应地，该步骤中的第一层光刻胶则形成在该外延结构的势垒层304上。其中，沟道层303和势垒层304分别采用的材料，可以是氮化镓沟道层和铝镓氮势垒层，当然，在本申请实施例中，还可以将沟道层303和势垒层304分别设置为氮化镓沟道层和铟镓氮势垒层、铟镓砷沟道层和铝镓砷势垒层等，此处对于具体的沟道层材料和势垒层材料不做限制，只要能够使沟道层303和势垒层304形成异质结结构产生二维电子气沟道即可。其中，衬底301通常可以采用蓝宝石、碳化硅、硅等异质衬底。因此，通过在衬底301和沟道层303之间先形成缓冲层302，可以减轻沟道层303和衬底301之间的晶格失配和热失配，从而使沟道层303能够更好的外延生长于衬底301上。又例如，为了减小栅极与势垒层之间的接触电阻，还可以在图3所示的外延结构中的势垒层304上形成一层接触层(图中未示出)。
示例地，第一光刻胶层和第二光刻胶层可以分别通过涂布的方式形成。如，先将第一光刻胶层涂布在外延结构远离衬底的一侧，然后再将第二光刻胶层涂布在第一光刻胶层上。通过涂布的方式分别形成第一光刻胶层和第二光刻胶层，能够使第一光刻胶层和第二光刻胶层更加均匀，且操作便捷。
其中，第一光刻胶层和第二光刻胶层的分别用于曝光显影后形成T形结构的栅极的大尺寸部分和小尺寸部分，因此第一光刻胶层和第二光刻胶层的厚度可以分别根据要形成的T形结构的栅极的大尺寸部分的高和小尺寸部分的高进行设置。例如，第一光刻胶层用于曝光显影后形成对应于T形结构栅极的小尺寸部分(即栅极与外延结构接触的部分)，第二光刻胶层用于曝光显影后形成对应于T形结构栅极的大尺寸部分(即栅极远离外延结构的部分)，则第一光刻胶层的厚度一般等于T形结构栅极的小尺寸部分的高，第二光刻胶层的厚度一般等于T形结构栅极的大尺寸部分的高。因此，若将要形成的T形结构栅极的小尺寸部分的高小于大尺寸部分的高，则对应的第一光刻胶层的厚度小于第二光刻胶层的厚度。若将要形成的T形结构栅极的小尺寸部分的高大于大尺寸部分的高，则对应的第一光刻胶层的厚度大于第二光刻胶层的厚度。若将要形成的T形结构栅极的小尺寸部分的高等于大尺寸部分的高，则对应的第一光刻胶层的厚度等于第二光刻胶层的厚度。
可选地，第一光刻胶层和第二光刻胶层可以采用相同的光刻胶，也可以采用不同的光刻胶。例如，第一光刻胶层和第二光刻胶层均采用电子束(E-beam)光刻胶。当然，第一光刻胶层和第二光刻胶层分别可采用的光刻胶还可以是PMMA光刻胶，I-line光刻胶等，此处不做限制，只要是光刻胶即可。
S102、对第二光刻胶层和第一光刻胶层曝光显影，在第二光刻胶层上形成第一开口以及在第一光刻胶层上形成第二开口。其中，第一开口的大于第二开口，第二开口位于第一开口在第一光刻胶层上的正投影区域内(可结合图4所示)。
示例地，如图4所示，在第二光刻胶层401上形成第一开口402，同时在第一光刻胶层403中形成第二开口404。
通过该第二开口能够释放第二光刻胶层在曝光显影过程中产生的应力，从而能够避免第二光刻胶层对第一光刻胶层的拉扯导致第一光刻胶层受到第二光刻胶层的影响而曝光显影后形成的图形结构尺寸误差较大的情况。
其中，第一开口大于第二开口可以是指第一开口的开口宽度大于第二开口的开口 宽度。
需要说明的是，上述第一开口的形状及尺寸(如宽和高)一般与需要形成的T形结构栅极的大尺寸部分(即栅极远离外延结构的部分)的形状及尺寸相同，以便后续向第一开口中填充金属以形成T形结构栅极的大尺寸部分。而第二开口的尺寸可以根据实际需要进行设置，通常设置的第二开口的尺寸小于T形结构栅极的小尺寸部分(即栅极与外延结构接触的部分)的尺寸，以便后续能够在第二开口的基础上(即覆盖第二开口)形成与T形结构栅极的小尺寸部分的尺寸对应的开口。一般，为了便于形成，第二开口通常为方形口。当然，在本申请实施例中对第二开口的形状不做限制。在实际应用中，只需要形成有第二开口即可。
可选地，在对第二光刻胶层和第一光刻胶层曝光显影时，为了形成上述第一开口和第二开口，可以先对应第二开口对第二光刻胶和第一光刻胶进行曝光显影。然后再对应第一开口对第二光刻胶层进行曝光显影从而形成上述的第一开口和第二开口。当然，在本申请实施例中还可以采用其他方式通过对第一光刻胶层和第二光刻胶层进行曝光显影形成上述第一开口和第二开口，此处不做限制。
S103、对第一光刻胶层曝光显影，在第一光刻胶层上形成第三开口；第三开口覆盖第二开口，且第三开口小于第一开口。
其中，第三开口小于第一开口可以是第三开口的开口宽度小于第一开口的开口宽度。
示例地，在对第二光刻胶层曝光显影形成了第一开口后，如图5所示，在第一光刻胶层501上形成第三开口502。该第三开口502基于如图4所示的第二开口404(请参见图4)形成，即第三开口502的尺寸大于第二开口404的尺寸，第三开口502覆盖第二开口404。
需要说明的是，上述第三开口的形状及尺寸(如宽和高)一般与需要形成的T形结构栅极的小尺寸部分(即栅极与外延结构接触的部分)的形状及尺寸相同，以便后续向第三开口中填充金属以形成T形结构栅极的小尺寸部分。
S104、在第一开口和第三开口内填充金属形成栅极。
其中，可以通过离子溅射的方式向第一开口和第三开口内填充金属，也可以通过金属蒸镀的方式向第一开口和第三开口内填充金属。
示例地，在通过上述步骤形成了第一开口和第三开口后，如图6所示，可以通过金属蒸镀的形式在第二光刻胶层601表面形成金属层602，由于具有第一开口和第三开口，因此该金属层602能够填充于第一开口和第三开口中从而形成栅极。
可选地，结合图6和图7所示，为了去除栅极结构以外的附着在第二光刻胶层上的金属，在形成栅极后，还可以通过剥离工艺，将第二光刻胶层601剥离。
可选地，在本申请实施例中，为了能够使第二光刻胶层和第一光刻胶层上形成的开口(如第一开口和第三开口)形状更加稳固。还可以在对第二光刻胶层和第一光刻胶层进行曝光显影形成第一开口和第二开口后，通过热板工艺对第二光刻胶层进行烘烤。当然，在对第一光刻胶层进行曝光显影形成第三开口后，也可以通过热板工艺对第一光刻胶层进行烘烤。又或者，为了简化工艺，还可以在对第二光刻胶层和第一光刻胶层进行曝光显影形成第一开口和第二开口，以及在对第一光刻胶层进行曝光显影 形成第三开口后，统一通过热板工艺对第一光刻胶层和第二光刻胶层进行烘烤。
采用以上实施例中的方法，在形成T形结构的栅极时，先对两层光刻胶中的上一层进行曝光显影的同时能够对下一层的光刻胶进行开口，以使下一层光刻胶可以通过开口释放上一层光刻胶曝光显影时的应力。从而能够避免上一层光刻胶对下一层光刻胶的拉扯导致下一层光刻胶受到上一层光刻胶的影响而曝光显影后形成的图形结构尺寸误差较大的情况。能够提高最终形成的栅极的质量。
对应于前述实施例中的方法，本申请实施例还提供一种半导体器件，如图8所示，该半导体器件可以包括外延结构801以及设置于该外延结构801上的栅极802、源极803和漏极804。其中，该半导体器件的漏极可以采用前述实施例中所述的形成栅极的方法形成。从而使该半导体器件中的栅极具有更高的尺寸精度，和更高的质量。
以上，仅为本申请的部分实施例和实施方式，本申请的保护范围不局限于此，任何熟知本领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种形成栅极的方法，其特征在于，包括：
    在外延结构远离衬底的一侧依序形成第一光刻胶层以及第二光刻胶层；
    对所述第二光刻胶层和所述第一光刻胶层曝光显影，在所述第二光刻胶层上形成第一开口以及在所述第一光刻胶层上形成第二开口；所述第一开口大于所述第二开口，所述第二开口位于所述第一开口在所述第一光刻胶层上的正投影区域内；
    对所述第一光刻胶层曝光显影，在所述第一光刻胶层上形成第三开口；所述第三开口覆盖所述第二开口，且所述第三开口小于所述第一开口；
    在所述第一开口和所述第三开口内填充金属形成栅极。
  2. 根据权利要求1所述的方法，其特征在于，所述在所述第一开口和所述第三开口内填充金属形成栅极包括：
    在所述第二光刻胶层的表面通过金属蒸镀形成金属层；其中，所述金属层填充于所述第一开口和所述第二开口内形成栅极。
  3. 根据权利要求1或2所述的方法，其特征在于，在所述第一开口和所述第三开口内填充金属形成栅极之后，所述方法还包括：
    剥离所述第二光刻胶层。
  4. 根据权利要求1至3任一项所述的方法，其特征在于，在所述对所述第二光刻胶层和所述第一光刻胶层曝光显影，在所述第二光刻胶层上形成第一开口以及在所述第一光刻胶层上形成第二开口之后，所述方法还包括：
    对所述第二光刻胶层进行烘烤。
  5. 根据权利要求4所述的方法，其特征在于，在所述对所述第一光刻胶层曝光显影，在所述第一光刻胶层上形成第三开口之后，所述方法还包括：
    对所述第一光刻胶层进行烘烤。
  6. 根据权利要求1至3任一项所述的方法，其特征在于，在所述对所述第一光刻胶层曝光显影，在所述第一光刻胶层上形成第三开口之后，所述方法还包括：
    对所述第一光刻胶层和所述第二光刻胶层进行烘烤。
  7. 根据权利要求1至6任一项所述的方法，其特征在于，所述第一光刻胶层的厚度小于所述第二光刻胶层的厚度。
  8. 根据权利要求1至7任一项所述的方法，其特征在于，所述第一光刻胶层和所述第二光刻胶层均采用电子束光刻胶。
  9. 根据权利要求1至8任一项所述的方法，其特征在于，所述第二开口为方形口。
  10. 一种半导体器件，其特征在于，包括外延结构以及设置于所述外延结构上的栅极、源极和漏极，所述栅极采用如权利要求1至9任一项所述的方法形成。
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