WO2022224841A1 - 配線基板 - Google Patents

配線基板 Download PDF

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Publication number
WO2022224841A1
WO2022224841A1 PCT/JP2022/017319 JP2022017319W WO2022224841A1 WO 2022224841 A1 WO2022224841 A1 WO 2022224841A1 JP 2022017319 W JP2022017319 W JP 2022017319W WO 2022224841 A1 WO2022224841 A1 WO 2022224841A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
layer
metal layer
wiring board
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/017319
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
憲助 松橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to US18/264,704 priority Critical patent/US12408276B2/en
Priority to EP22791615.2A priority patent/EP4329436A4/en
Priority to CN202280013239.5A priority patent/CN116868696A/zh
Publication of WO2022224841A1 publication Critical patent/WO2022224841A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Definitions

  • the present disclosure relates to a wiring board in which an insulating coat layer that can serve as a groove or a mark for cutting is formed on a metal layer on the surface.
  • a wiring board on which electronic components such as semiconductor elements are mounted has a metal layer formed using a conductive material such as metal on the surface of an insulating substrate made of ceramic or the like. This metal layer is used as a connection terminal with an external electronic component.
  • a plated layer is formed on the surface of this metal layer to protect the metal layer.
  • the plated layer is formed using an electrolytic plating method. Electroplating is performed by energizing a wiring for plating electrically connected to a metal layer. After the plating layer is formed on the surface of the metal layer in this way, it is necessary to disconnect the metal layer and the plating wiring in order to electrically separate the metal layer from the plating wiring.
  • Patent Literature 1 describes grinding away a portion of the metallized layer using a grinder such as a leutor to electrically separate the metallized wiring layer and the metallized metal layer.
  • Japanese Patent Laid-Open No. 2002-200003 describes cutting a lead wiring that functions as a wiring for plating by irradiating light beams such as an ion beam, a laser beam, and an electron beam.
  • the intensity of the light beam irradiated to the surface of the substrate is increased too much. Then, there is a possibility that the light beam reaches the inside of the substrate and a deep groove is formed in the substrate. If a wiring layer or the like formed inside the substrate overlaps with such a groove forming region, the groove is also formed in the internal wiring layer. If the wiring layer is cut in this way, a conduction failure occurs in the wiring layer. Further, if the groove is formed in the metal layer formed inside the substrate, part of the metal layer will be exposed on the surface, increasing the possibility of short-circuiting the metal layer.
  • an object is to provide a wiring substrate that can reduce the possibility of cutting a metal layer such as a wiring layer formed inside the substrate.
  • a wiring board includes an insulating substrate, a surface metal layer provided on the surface of the insulating substrate and divided by grooves formed on the insulating substrate, and arranged inside the insulating substrate. and a wiring layer.
  • the wiring layer is arranged so as to bypass the groove formation region so as not to overlap the groove formation region when viewed from above.
  • an insulating coat layer may be provided around the groove.
  • the insulating coat layer can be used as a mark when forming the groove.
  • the wiring layer may be arranged so as to bypass the formation region of the insulation coat layer so as not to overlap the formation region of the insulation coat layer in a top view. good.
  • the wiring layer is provided so as not to overlap the forming region of the insulating coat layer, which serves as a mark when forming the groove, when viewed from above, so that the wiring layer is formed inside the insulating substrate during the groove forming process. It is possible to further reduce the possibility of disconnecting the wiring layer.
  • an internal metal layer is further provided inside the insulating substrate, and the internal metal layer has a , an opening may be formed so as to include the entire groove forming region.
  • the wiring layer may be provided at a position within 0.5 mm from the surface of the insulating substrate.
  • the insulating coat layer is formed at a position within 0.5 mm from the surface of the insulating substrate where the energy of the laser beam may reach.
  • a wiring layer can be arranged by detouring the formation region. Therefore, it is possible to avoid the possibility that the wiring layer is cut by the laser beam.
  • the internal metal layer may be provided at a position within 0.5 mm from the surface of the insulating substrate.
  • the insulating coat layer is formed at a position within 0.5 mm from the surface of the insulating substrate where the energy of the laser beam may reach. It is possible to prevent the internal metal layer from being provided at a position that overlaps the formation region when viewed from above. Therefore, the possibility of trench formation in the inner metal layer can be avoided.
  • the wiring board it is possible to reduce the possibility of cutting a metal layer such as a wiring layer formed inside the board.
  • FIG. 1 is a schematic plan view showing the configuration of a wiring board according to one embodiment
  • FIG. 2 is a schematic plan view showing the configuration of a semiconductor package in which a semiconductor element is mounted on the wiring substrate shown in FIG. 1
  • FIG. 2 is a plan view showing the configuration of the top surface of a portion of the wiring substrate shown in FIG. 1
  • FIG. FIG. 4 is a cross-sectional view showing the configuration of the AA line portion of the wiring substrate shown in FIG. 3
  • 4 is a plan view showing a solid pattern provided on a ceramic layer inside the wiring board shown in FIG. 3
  • FIG. 4 is a plan view showing internal wiring provided on a ceramic layer inside the wiring board shown in FIG. 3
  • FIG. 4 is a plan view showing a state in which grooves are formed in an alumina coat forming region of the wiring substrate shown in FIG. 3 ;
  • FIG. 8 is a cross-sectional view showing the configuration of the wiring board along line BB shown in FIG. 7;
  • FIG. 10 is a cross-sectional view showing the configuration of a wiring board according to a modification;
  • FIG. 10 is a plan view showing the configuration of the upper surface of a portion of the wiring board according to the second embodiment;
  • FIG. 11 is a cross-sectional view showing the configuration of the wiring board along line EE shown in FIG. 10;
  • 11 is a plan view showing a solid pattern and internal wiring provided on a ceramic layer inside the wiring board shown in FIG. 10;
  • a wiring board 1 will be described as an example of the wiring board according to the present invention.
  • a semiconductor chip 71 is mounted on the wiring board 1 to form a semiconductor package 70 .
  • FIG. 1 schematically shows the planar configuration of the wiring board 1.
  • the wiring board 1 has a substantially rectangular shape when viewed from above.
  • the outer shape of the wiring board 1 is formed by a ceramic substrate (insulating substrate) 11 including a plurality of ceramic layers.
  • a recess 10 having a substantially square shape is formed when viewed from above.
  • the bottom surface of the concave portion 10 serves as an element mounting portion 10a on which a semiconductor element such as a semiconductor chip 71 is mounted.
  • FIG. 2 shows a schematic configuration of the semiconductor package 70. As shown in FIG.
  • the wiring board 1 is electrically connected to the semiconductor chip 71 via bonding wires 72 .
  • each wiring portion 31 of the wiring substrate 1 and each connection terminal (not shown) of the semiconductor chip 71 are electrically connected by bonding wires 72 .
  • electrical signals can be transmitted between each wiring portion 31 and the semiconductor chip 71 .
  • Each wiring part 31 is formed on the upper surface of the base ceramic layer 20 .
  • an upper surface metal layer 51 is formed on the upper surface of the side wall of the ceramic substrate 11 formed so as to surround the recess 10 .
  • the upper metal layer 51 is formed on the surface of the second ceramic layer 22 located on the uppermost layer.
  • the upper metal layer 51 is used as plating wiring during electroplating.
  • the upper metal layer 51 has a frame-shaped conductive pattern surrounding the recess 10 . During electroplating, power applied to the terminal portion 53 is transmitted to each metal layer through the upper metal layer 51 .
  • the upper metal layer 51 has lead wiring portions 52 .
  • the lead wiring portion 52 is provided so as to branch off from a predetermined position of the upper surface metal layer 51 .
  • the layout position of the lead-out wiring portion 52 can be arbitrarily determined according to the shape of each conductive pattern such as wiring, terminals, and vias formed on the wiring board 1 .
  • a terminal portion 53 is provided at the tip of the lead wiring portion 52 .
  • This terminal portion 53 is used as a connection terminal for applying power during electroplating. Further, the terminal portion 53 is used as a terminal for inspection when the wiring board 1 is electrically inspected.
  • the surfaces of the upper surface metal layer 51 (including the lead wiring portion 52) and the terminal portion 53 are covered with a plated layer.
  • the plated layer is formed using an electrolytic plating method. Electroplating is performed by applying electric power to metal layers such as the upper metal layer 51 through the terminal portions 53 and the lead wiring portions 52 . After the plated layer is formed on the surface of the metal layer in this manner, the lead wiring portion 52 is cut, and the terminal portion 53 and the top metal layer 51 are electrically independent.
  • an alumina coat (insulating coat layer) 55 is provided on the lead-out wiring portion 52 so as to traverse part of the lead-out wiring portion 52 .
  • the alumina coat 55 serves as a mark of a cutting portion when performing the above-described wiring cutting processing (laser cutting) which is performed after the plating processing is finished.
  • the alumina coat 55 is formed by applying an insulating paste containing alumina to a predetermined position on the lead wiring portion 52 .
  • an alumina coat is given as an example of the insulating coat layer, but the material of the insulating coat layer is not limited to alumina as long as it has non-conductivity.
  • a liquid resin material is poured into the concave portion 10 of the ceramic substrate 11 while the semiconductor chip 71 is mounted on the wiring substrate 1 .
  • the concave portion 10 is filled with the resin.
  • the semiconductor package 70 is obtained.
  • a configuration in which the resin material is not poured into the concave portion 10 of the ceramic substrate 11 is also possible. That is, in another embodiment, the semiconductor package 70 is formed by mounting the semiconductor chip 71 on the wiring board 1 and electrically connecting them to each other.
  • the ceramic substrate 11 has a laminated structure in which a plurality of ceramic layers are laminated.
  • the ceramic substrate 11 has a configuration in which a base ceramic layer 20, a first ceramic layer 21, and a second ceramic layer 22 are laminated in order from the bottom (see FIG. 4, etc.).
  • Each ceramic layer can be formed of, for example, a high-temperature sintered ceramic containing alumina (Al 2 O 3 ) as a main component.
  • the ceramic layers may be formed of medium temperature fired ceramics (MTCC), such as glass-ceramics, or low temperature fired ceramics (LTCC).
  • MTCC medium temperature fired ceramics
  • LTCC low temperature fired ceramics
  • the base ceramic layer 20 has a substantially rectangular flat plate shape.
  • a recess 10 is formed in the central portion of the upper surface of the base ceramic layer 20 .
  • the bottom surface of the concave portion 10 serves as an element mounting portion 10a.
  • the first ceramic layer 21 has a substantially rectangular flat plate shape with substantially the same size as the base ceramic layer 20, and has a frame-like shape with an opening in the center.
  • the first ceramic layer 21 is laminated on the base ceramic layer 20 and provided so as to surround the outer peripheral portion of the upper surface of the base ceramic layer 20 when viewed from above.
  • the second ceramic layer 22 has the shape of a substantially rectangular plate having substantially the same size as the base ceramic layer 20 and the first ceramic layer 21, and has a frame-like shape with an opening in the center. there is The opening of the second ceramic layer 22 has substantially the same opening area as the opening of the first ceramic layer 21 .
  • the second ceramic layer 22 is laminated on the first ceramic layer 21 and provided so as to surround the outer peripheral portion of the upper surface of the first ceramic layer 21 when viewed from above.
  • the wiring board 1 is formed with the first ceramic layer 21 and the second ceramic layer 22 so as to surround the periphery of the recess 10 positioned at the center of the upper surface of the base ceramic layer 20 . Side walls of the ceramic substrate 11 are formed.
  • the first ceramic layer 21 and the second ceramic layer 22 have a frame-like shape with an opening in the center.
  • a configuration in which the two ceramic layers 22 are not provided with openings is also possible.
  • the wiring part 31 and the upper metal layer 51 formed on each ceramic layer are formed of a conductive pattern obtained by molding a conductive material into a predetermined shape.
  • the conductive pattern is, for example, copper (Cu), titanium (Ti), tungsten (W), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), molybdenum (Mo), nickel (Ni). , or a metal material such as manganese (Mn), or an alloy material containing these metal materials as a main component.
  • the conductive pattern For the formation of the conductive pattern, conventionally known methods such as a metallization method using printing paste and a method of transferring a patterned metal layer are used. Among these methods, it is preferable to use, for example, the metallizing method.
  • FIG. 3 shows the configuration around the lead-out wiring portion 52 in the wiring board 1.
  • FIG. 3 is a plan view showing an enlarged area of the wiring board 1 shown in FIG. 1 within the dashed frame.
  • FIG. 4 is a cross-sectional view showing the configuration of the wiring board 1 along line AA shown in FIG.
  • FIG. 5 is a plan view showing the pattern shape of a solid pattern (inner metal layer) 41 provided on the first ceramic layer 21 of the wiring board 1 shown in FIG.
  • FIG. 6 is a plan view showing the pattern shape of the internal wiring (wiring layer) 32 provided on the base ceramic layer 20 of the wiring board 1 shown in FIG.
  • the ceramic substrate 11 has a configuration in which a base ceramic layer 20, a first ceramic layer 21, and a second ceramic layer 22 are laminated in this order from the bottom. .
  • metal layers such as terminal portions 53 and lead wiring portions 52 are formed. These metal layers are also called surface metal layers.
  • an alumina coat 55 is arranged on the lead-out wiring portion 52 so as to partially cover the lead-out wiring portion 52 .
  • the alumina coat 55 is arranged so as to cross the extension direction of the lead wiring portion 52 , that is, to cross the lead wiring portion 52 .
  • a lower surface metal layer 35 is formed on the surface of the base ceramic layer 20 forming the lower surface of the ceramic substrate 11 .
  • the lower metal layer 35 is formed of a conductive pattern obtained by molding a conductive material into a predetermined shape, like the wiring part 31 and the upper metal layer 51 . As shown in FIG. 4 and the like, the lower surface metal layer 35 is electrically connected to a terminal portion 53 provided on the upper surface of the ceramic substrate 11 through vias 36 provided so as to penetrate the interior of the ceramic substrate 11 . It is
  • conductive patterns such as the internal wiring 32 and the solid pattern 41 are provided inside the ceramic substrate 11.
  • the internal wiring 32 and the solid pattern 41 are formed of a conductive pattern obtained by forming a conductive material into a predetermined shape, like the wiring portion 31 and the upper surface metal layer 51 .
  • a solid pattern 41 is provided on the first ceramic layer 21 .
  • the solid pattern 41 is provided so as to cover most of the surface of the first ceramic layer 21 .
  • the solid pattern 41 is connected to the ground (GND), for example.
  • GND ground
  • the solid pattern 41 is formed on the entire surface of the first ceramic layer 21 excluding the area where the vias 36 are arranged, the peripheral area thereof, and the pattern cutouts (openings) 42 .
  • the pattern cut-out portion 42 is formed by providing an opening in a part of the conductive pattern forming the solid pattern 41 .
  • the pattern cut-out portion 42 is provided in a region that overlaps the formation region of the alumina coat 55 in top view so as to include the entire formation region of the alumina coat 55 (see FIG. 5).
  • the shape of the opening of the pattern cut-out portion 42 is a substantially square shape, but the shape of the opening is not limited to a substantially square shape.
  • the pattern cut-out portion 42 may be formed by notching a portion of the end portion of the solid pattern 41 .
  • the solid pattern 41 is provided with the pattern cut-out portion 42 as described above, when the lead wiring portion 52 is cut using a laser beam or the like, the laser beam reaches the position where the solid pattern 41 is formed. It is possible to avoid the possibility of grooves being formed in the solid pattern 41 . As a result, even when the groove 61 is formed in the first ceramic layer 21, it is possible to prevent a part of the solid pattern 41 from being exposed to the surface, thereby reducing the possibility that the solid pattern 41 is short-circuited. be able to.
  • the internal wiring 32 is provided on the base ceramic layer 20 .
  • the internal wiring 32 is stretched in an arbitrary pattern shape between the base ceramic layer 20 and the first ceramic layer 21 .
  • a part of the internal wiring 32 is connected to the wiring portion 31 exposed on the upper surface of the wiring board 1 .
  • the internal wiring 32 is arranged so as to bypass the formation area of the alumina coat 55 so as not to overlap the formation area of the alumina coat 55 when viewed from above (see FIG. 6). As a result, when the lead-out wiring portion 52 is cut using a laser beam or the like, the laser beam reaches the formation position of the internal wiring 32, and the possibility that the internal wiring 32 is cut by the laser beam can be avoided. can.
  • FIG. 7 shows a state in which a groove 61 is formed in the formation region of the alumina coat 55 on the upper surface of the wiring substrate 1.
  • FIG. 7 corresponds to an enlarged view of the region within the dashed frame of the semiconductor package 70 shown in FIG.
  • FIG. 8 is a cross-sectional view showing the configuration of the wiring board 1 taken along line BB of FIG.
  • the groove 61 is provided so as to traverse the lead wiring portion 52 .
  • Such grooves 61 are formed by forming the wiring board 1 as shown in FIG. It can be formed by performing steps. The groove forming step is performed after the wiring board 1 is baked and then the metal layer formed on the substrate surface or the like is electroplated to form a plated layer. By forming the grooves 61 that divide the lead wiring portion 52 in this way, the electrical connection between the terminal portion 53 and the upper surface metal layer 51 can be cut off.
  • the grooving step is preferably performed using a laser beam.
  • a laser beam As a result, it is possible to form grooves by more accurately designating the target position, and to form finer grooves.
  • the laser beam to be used include general laser beams used for laser processing, such as CO 2 laser, fiber laser, and YAG laser.
  • the conditions for laser processing normal conditions for cutting wiring formed on a substrate can be applied.
  • the region C irradiated with the laser beam in the groove forming process is indicated by a dashed frame.
  • the area to be cut on the lead-out wiring portion 52 is provided with the alumina coat 55 that can serve as a mark of the cutting location.
  • the irradiation area C of the laser beam is within the formation area of the alumina coat 55 .
  • a laser beam is applied to the formation region of the alumina coat 55 .
  • a groove 61 is formed. As shown in FIG. 8 and the like, the groove 61 is formed even inside the ceramic substrate 11 .
  • the depth of the grooves 61 to be formed varies depending on various conditions such as the intensity of the laser beam, but may be, for example, about 0.5 mm at maximum from the substrate surface.
  • each ceramic layer such as the first ceramic layer 21 and the second ceramic layer 22 is, for example, within the range of 0.1 mm or more and 0.3 mm or less. Therefore, when the wiring board 1 is irradiated with a laser beam from above, the laser beam can reach the inside of the first ceramic layer 21 . Thereby, as shown in FIG. 8 , the groove 61 can be formed to penetrate the second ceramic layer 22 and extend to a part of the first ceramic layer 21 .
  • the solid pattern 41 provided between the first ceramic layer 21 and the second ceramic layer 22 is provided with the pattern cut-out portion 42 .
  • the pattern cut-out portion 42 is provided so as to include the entire formation area of the alumina coat 55 in the area overlapping the formation area of the alumina coat 55 in top view (see FIG. 5).
  • the irradiation area C of the laser beam is within the formation area of the alumina coat 55 .
  • the grooves 61 formed by irradiating the laser beam are located within the formation area of the pattern cutouts 42 when viewed from above. That is, the solid pattern 41 has a pattern cut-out portion 42 that includes the entire formation region of the grooves 61 in a region that overlaps with the formation region of the grooves 61 in top view.
  • an internal wiring 32 is provided between the base ceramic layer 20 and the first ceramic layer 21 .
  • the internal wiring 32 is arranged so as to bypass the formation region of the alumina coat 55 so as not to overlap the formation region of the alumina coat 55 in top view (see FIG. 6).
  • the irradiation area C of the laser beam is within the formation area of the alumina coat 55 .
  • the groove 61 formed by irradiating the laser beam is formed in a region that does not overlap the formation position of the internal wiring 32 when viewed from above. That is, the internal wiring 32 is arranged so as to bypass the formation region of the groove 61 so as not to overlap the formation region of the groove 61 in top view.
  • the depth of the grooves 61 formed in the groove forming process is, for example, about 0.5 mm at maximum from the substrate surface. Therefore, the present embodiment is preferably applied to a configuration in which the internal wiring 32 is provided at a position within 0.5 mm from the surface of the ceramic substrate 11 . Similarly, this embodiment is preferably applied to a configuration in which the solid pattern 41 is provided at a position within 0.5 mm from the surface of the ceramic substrate 11 .
  • the configuration of this embodiment is more preferably applied to a configuration in which the internal wiring 32 and solid pattern 41 are provided at positions within 0.3 mm from the surface of the ceramic substrate 11 .
  • Each ceramic layer has a thickness in the range of 0.1 mm to 0.3 mm. Therefore, the wiring layer formed on the ceramic layer that is three or more layers away from the substrate surface does not need to detour around the region where the alumina coat 55 and the groove 61 are formed.
  • the internal metal layer formed on the ceramic layer at a position three or more layers away from the substrate surface even if there is no opening in the region overlapping with the formation region of the alumina coat 55 and the groove 61 in top view, good.
  • FIG. 9 shows a cross-sectional configuration of a portion of the wiring board 101 according to one modification of the present embodiment.
  • the wiring board 101 has a ceramic substrate 111 .
  • the ceramic substrate 111 has a configuration in which a base ceramic layer 20, a third ceramic layer 23, a first ceramic layer 21, and a second ceramic layer 22 are laminated in this order from the bottom.
  • the wiring board 101 differs from the wiring board 1 in that a third ceramic layer 23 is further provided between the base ceramic layer 20 and the first ceramic layer 21 .
  • conductive patterns such as the internal wiring 32 and the solid pattern 41 are provided inside the ceramic substrate 111.
  • a configuration similar to that of the wiring board 1 can be applied to the configuration of the internal wiring 32 and the solid pattern 41 .
  • a metal layer 135 is further provided between the base ceramic layer 20 and the third ceramic layer 23 .
  • the metal layer 135 may function as a solid pattern or may function as an internal wiring.
  • a distance D from the surface of the ceramic substrate 111 to the arrangement position of the metal layer 135 is greater than 0.5 mm.
  • the metal layer 135 is provided at a position overlapping with the formation region of the groove 61 or the formation region of the alumina coat 55 in top view.
  • a wiring layer such as the metal layer 135 or an internal A metal layer may be provided.
  • the internal wiring 32 is detoured so as not to overlap with the formation region of the alumina coat 55 or the groove 61 when viewed from above. Arrangement is more preferable.
  • the solid pattern 41 has a pattern cut-out portion 42 in a region overlapping with the forming region of the alumina coat 55 or the groove 61 in top view. This makes it possible to omit the electrical inspection of each wiring performed after the wiring board 1 is manufactured.
  • the alumina coat 55 may not be provided. That is, in the wiring board according to the modified example, the groove 61 is provided so as to cross the lead wiring portion 52 provided on the surface of the ceramic substrate 11, but the alumina coat 55 is not provided around the groove 61. not The internal wiring 32 arranged inside the ceramic substrate 11 is arranged so as to detour so as not to overlap with the forming region of the groove 61 when viewed from above.
  • the terminal portion 53 provided at the tip of the lead-out wiring portion 52 is not limited to a connection terminal for applying electric power during electrolytic plating.
  • the terminal portion 53 may be a specific mounting pad such as, for example, a capacitor mounting pad. That is, the cutting process of the lead-out wiring portion 52 may be performed to separate a specific mounting pad from other mounting pads.
  • the wiring board 1 includes the ceramic substrate (insulating substrate) 11, the surface metal layer provided on the surface of the ceramic substrate 11, and the wiring arranged inside the ceramic substrate 11. and grooves 61 extending across the surface metal layer.
  • the surface metal layer (for example, the lead wiring portion 52) is divided by grooves 61.
  • the wiring layer (for example, the internal wiring 32) is arranged so as to bypass the formation region of the groove 61 so as not to overlap the formation region of the groove 61 when viewed from above.
  • the wiring board 1 When the wiring board 1 is shipped alone, the wiring board 1 may not have the groove 61 .
  • the wiring board 1 includes a ceramic substrate (insulating substrate) 11, a surface metal layer provided on the surface of the ceramic substrate 11, and a wiring layer disposed inside the ceramic substrate 11. and an insulating coat layer (for example, alumina coat 55) arranged so as to partially cover the surface metal layer (for example, lead wiring section 52).
  • the wiring layer (for example, the internal wiring 32) is arranged so as to bypass the formation region of the insulation coat layer so as not to overlap the formation region of the insulation coat layer when viewed from above.
  • the wiring layer formed inside the ceramic substrate 11 is cut. can reduce the probability.
  • the wiring board according to another modification includes an insulating substrate, a surface metal layer provided on the surface of the insulating substrate, a wiring layer disposed inside the insulating substrate, and the and an insulating coat layer arranged to cover part of the surface metal layer.
  • the wiring layer is arranged so as to bypass the forming region of the insulating coat layer so as not to overlap the forming region of the insulating coat layer when viewed from above.
  • the laser beam reaches the formation position of the internal wiring layer, thereby avoiding the possibility that the wiring layer is cut by the laser beam. can do.
  • an internal metal layer is further provided inside the insulating substrate, and the internal metal layer overlaps a formation region of the insulating coat layer when viewed from above.
  • An opening may be provided in the region so as to include the entire forming region of the insulating coat layer.
  • the laser beam reaches the formation position of the inner metal layer, thereby avoiding the possibility of forming a groove in the inner metal layer. be able to. This makes it possible to avoid part of the inner metal layer from being exposed to the surface, and reduce the possibility of the inner metal layer short-circuiting.
  • FIG. 10 shows an enlarged top view of a portion of the wiring board 201 according to the second embodiment.
  • FIG. 10 shows the configuration around the lead wiring portion 52 in the wiring board 201 .
  • the upper surface of the ceramic substrate 11 is provided with two lead wiring portions 52 branched from predetermined positions of the upper surface metal layer 51 .
  • the two lead wire portions 52 the one positioned on the left is referred to as a lead wire portion 52A, and the one positioned on the right side is referred to as a lead wire portion 52B.
  • a terminal portion 53 is provided at the tip of each lead wiring portion 52 .
  • the terminal portion 53A is located on the left side
  • the terminal portion 53B is located on the right side.
  • An alumina coat (insulating coat layer) 55A is provided on the lead-out wiring portion 52A so as to cross a part of the lead-out wiring portion 52A.
  • An alumina coat (insulating coat layer) 55B is provided on the lead-out wiring portion 52B so as to cross a part of the lead-out wiring portion 52B.
  • the alumina coats 55A and 55B serve as marks of cutting points when performing the wiring cutting process (laser cutting) described above after the plating process is completed.
  • a groove 61A is provided in the formation region of the lead-out wiring portion 52A.
  • a groove 61B is provided in the region where the lead-out wiring portion 52B is formed. Grooves 61A and 61B are provided to cross lead wiring portions 52A and 52B, respectively.
  • FIG. 11 is a cross-sectional view showing the configuration of the wiring board 1 along line EE shown in FIG.
  • FIG. 12 is a plan view showing pattern shapes of a solid pattern (internal metal layer) 241 and internal wiring (wiring layer) 232 provided on the first ceramic layer 21 of the wiring board 201 shown in FIG.
  • conductive patterns such as the internal wiring 232, the solid pattern 241, and the internal wiring 32 are provided inside the ceramic substrate 11. Specifically, the internal wiring 232 and the solid pattern 241 are provided on the first ceramic layer 21 , and the internal wiring 32 is provided on the base ceramic layer 20 .
  • the solid pattern 241 is provided so as to partially cover the surface of the first ceramic layer 21 .
  • the solid pattern 241 is provided in a region that overlaps the formation regions of the lead wiring portion 52A, the terminal portion 53A, and the like when viewed from above.
  • the solid pattern 241 has pattern cutouts 42 .
  • the pattern blank part 42 is formed by forming an opening in a part of the conductive pattern forming the solid pattern 41 .
  • the pattern cutout portion 42 is provided so as to include the entire formation region of the alumina coat 55 in a region overlapping with the formation region of the alumina coat 55A provided on the lead-out wiring portion 52A when viewed from above (FIG. 12). reference).
  • the irradiation region C of the laser beam irradiated during the groove forming process is within the formation region of the alumina coat 55A.
  • internal wiring 232 is provided on the first ceramic layer 21 in addition to the solid pattern 241 .
  • the internal wiring 232 is arranged so as to bypass the formation region of the alumina coat 55B so as not to overlap the formation region of the alumina coat 55B in top view (see FIG. 12).
  • the irradiation region C of the laser beam irradiated during the groove forming process is within the formation region of the alumina coat 55B.
  • the groove 61B formed by irradiating the laser beam is formed in a region that does not overlap the formation position of the internal wiring 232 when viewed from above. Therefore, when the lead-out wiring portion 52B is cut using a laser beam or the like, the possibility that the laser beam reaches the forming position of the internal wiring 232 and the internal wiring 232 is cut by the laser beam can be avoided. .
  • the wiring board 201 is provided with the internal wiring 32 between the base ceramic layer 20 and the first ceramic layer 21 .
  • the internal wiring 32 is arranged to bypass the forming regions of the alumina coats 55A and 55B so as not to overlap with the forming regions of the alumina coats 55A and 55B when viewed from above.
  • the laser beam reaches the formation position of the internal wiring 32, thereby avoiding the possibility that the internal wiring 32 is cut by the laser beam. be able to.
  • wiring board 11 ceramic substrate (insulating substrate) 20: base ceramic layer 21: first ceramic layer 22: second ceramic layer 32: internal wiring (wiring layer) 41: solid pattern (internal metal layer) 42: Pattern cut-out portion (opening) 52: lead wiring part (surface metal layer) 53: Terminal portion 55: Alumina coat (insulation coat layer) 61: groove 70: semiconductor package 71: semiconductor element 101: wiring substrate 111: ceramic substrate 201: wiring substrate 232: internal wiring (wiring layer) 241: solid pattern (inner metal layer)

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/JP2022/017319 2021-04-20 2022-04-08 配線基板 Ceased WO2022224841A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US18/264,704 US12408276B2 (en) 2021-04-20 2022-04-08 Wiring substrate
EP22791615.2A EP4329436A4 (en) 2021-04-20 2022-04-08 Wiring substrate
CN202280013239.5A CN116868696A (zh) 2021-04-20 2022-04-08 布线基板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021071065A JP7561083B2 (ja) 2021-04-20 2021-04-20 配線基板
JP2021-071065 2021-04-20

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WO2022224841A1 true WO2022224841A1 (ja) 2022-10-27

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EP (1) EP4329436A4 (enExample)
JP (1) JP7561083B2 (enExample)
CN (1) CN116868696A (enExample)
WO (1) WO2022224841A1 (enExample)

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TWI856847B (zh) * 2023-10-19 2024-09-21 矽品精密工業股份有限公司 基板結構及其製法

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JPS63224392A (ja) * 1987-03-13 1988-09-19 日本メクトロン株式会社 多層プリント配線板およびその加工法
JP2006332643A (ja) * 2005-05-23 2006-12-07 Tektronix Inc 回路要素
JP2008091560A (ja) * 2006-09-29 2008-04-17 Kyocera Corp 配線基板、多層配線基板及び電子装置、並びにこれらの製造方法
JP2017032290A (ja) 2015-07-29 2017-02-09 セイコーエプソン株式会社 パッケージベース、パッケージベースの製造方法、容器、電子デバイス、電子機器及び移動体

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JP3210838B2 (ja) 1995-07-04 2001-09-25 京セラ株式会社 半導体素子収納用パッケージの製造方法
TWI305127B (en) * 2006-10-13 2009-01-01 Phoenix Prec Technology Corp Circuit board structure capable of performing electrica tests and fabrication method thereof
JP2015082645A (ja) * 2013-10-24 2015-04-27 イビデン株式会社 フレックスリジッド配線板及びフレックスリジッド配線板の製造方法
JP2019149442A (ja) * 2018-02-27 2019-09-05 株式会社デンソーウェーブ プリント配線の製造方法、及びプリント配線

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Publication number Priority date Publication date Assignee Title
JPS63224392A (ja) * 1987-03-13 1988-09-19 日本メクトロン株式会社 多層プリント配線板およびその加工法
JP2006332643A (ja) * 2005-05-23 2006-12-07 Tektronix Inc 回路要素
JP2008091560A (ja) * 2006-09-29 2008-04-17 Kyocera Corp 配線基板、多層配線基板及び電子装置、並びにこれらの製造方法
JP2017032290A (ja) 2015-07-29 2017-02-09 セイコーエプソン株式会社 パッケージベース、パッケージベースの製造方法、容器、電子デバイス、電子機器及び移動体

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Title
See also references of EP4329436A4

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JP7561083B2 (ja) 2024-10-03
EP4329436A1 (en) 2024-02-28
US12408276B2 (en) 2025-09-02
JP2022165642A (ja) 2022-11-01
EP4329436A4 (en) 2025-06-25
US20240114629A1 (en) 2024-04-04
CN116868696A (zh) 2023-10-10

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