WO2022220191A1 - 基板の製造方法、電力用半導体装置の製造方法、および基板 - Google Patents

基板の製造方法、電力用半導体装置の製造方法、および基板 Download PDF

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Publication number
WO2022220191A1
WO2022220191A1 PCT/JP2022/017272 JP2022017272W WO2022220191A1 WO 2022220191 A1 WO2022220191 A1 WO 2022220191A1 JP 2022017272 W JP2022017272 W JP 2022017272W WO 2022220191 A1 WO2022220191 A1 WO 2022220191A1
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Prior art keywords
circuit board
metal circuit
metal
substrate
manufacturing
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PCT/JP2022/017272
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English (en)
French (fr)
Japanese (ja)
Inventor
雅之 辻野
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2023514629A priority Critical patent/JP7520215B2/ja
Publication of WO2022220191A1 publication Critical patent/WO2022220191A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Definitions

  • the present disclosure relates to a method of manufacturing a substrate, a method of manufacturing a power semiconductor device, and a substrate, and more particularly to a method of manufacturing a substrate having a metal circuit board, a method of manufacturing a semiconductor power device, and a substrate having a metal circuit board. is.
  • Patent Document 1 discloses a substrate having a mounting surface on which power semiconductor elements are to be mounted.
  • the substrate comprises a ceramic plate having a first surface and a second surface opposite to the first surface, a metal radiator plate provided on the first surface of the ceramic plate, and the ceramic plate.
  • a metal circuit board provided on the second surface.
  • the metal circuit board includes a work-hardened layer forming the mounting surface.
  • the above publication also discloses a method for manufacturing a substrate.
  • a ceramic plate having a first surface and a second surface opposite to the first surface; a metal radiator plate provided on the first surface of the ceramic plate;
  • a substrate is formed having a metal circuit board on the second surface and having a mounting surface.
  • the above-described work-hardened layer is formed by subjecting the mounting surface of the metal circuit board to shot peening.
  • the substrate is thus obtained.
  • a power semiconductor device is obtained by mounting a power semiconductor element on the mounting surface of the metal circuit board of the substrate.
  • shot peening is applied to the mounting surface of the metal circuit board.
  • This suppresses changes in the fine shape of the mounting surface due to the heat cycle of the power semiconductor device. Therefore, the bonding reliability of the power semiconductor element bonded to the mounting surface can be improved.
  • the work-hardened layer forms the mounting surface of the metal circuit board. This suppresses changes in the fine shape of the mounting surface due to heat cycles. Therefore, the bonding reliability of the power semiconductor element bonded to the mounting surface can be improved.
  • the above publication also explains the principle of suppressing the change in fine shape as described above. According to this, since the crystal orientations of the plurality of crystal grains in the polycrystal differ from each other, the behavior of thermal expansion and contraction in the direction perpendicular to the mounting surface differs among the plurality of crystal grains. Therefore, it is considered that the variation in the surface heights of the plurality of crystal grains increases after a large number of heat cycles. Shot peening is thought to suppress the crystal orientation dependence of thermal expansion and contraction. Therefore, it is considered that the shot peening process suppresses the surface height variations of the plurality of crystal grains through the heat cycle. In other words, shot peening is thought to suppress changes in the fine shape of the mounting surface at the crystal level due to the heat cycle.
  • the above publication also explains the principle that shot peening processing suppresses the crystal orientation dependence of thermal expansion and contraction as described above. According to this, shot peening introduces a large number of dislocations in the vicinity of the mounting surface. Therefore, the dislocation density in the work-hardened layer is higher than the dislocation density in the non-work-hardened layer. It is believed that this high dislocation density suppresses the crystal orientation dependence of thermal expansion and contraction.
  • One aspect of the substrate manufacturing method of the present disclosure is a substrate manufacturing method including a ceramic plate, a metal heat sink, and at least one metal circuit board.
  • the ceramic plate has a first side and a second side opposite the first side.
  • a metal heat sink is provided on the first surface of the ceramic plate.
  • At least one metal circuit board is provided on the second side of the ceramic board, with a third side facing the second side of the ceramic board and a power semiconductor board opposite the third side. and a fourth surface containing bonding regions to which the devices will be bonded.
  • One aspect of the substrate of the present disclosure is a substrate having a ceramic plate, a metal heat sink, and at least one metal circuit plate.
  • the ceramic plate has a first side and a second side opposite the first side.
  • a metal heat sink is provided on the first surface of the ceramic plate.
  • At least one metal circuit board is provided on the second side of the ceramic board, with a third side facing the second side of the ceramic board and a power semiconductor board opposite the third side. and a fourth surface containing bonding regions to which the devices will be bonded.
  • the at least one metal circuit board includes a first metal circuit board. Each of the third and fourth surfaces of the first metal circuit board is work hardened.
  • a substrate manufacturing method including a ceramic plate, a metal heat sink, and at least one metal circuit board.
  • the ceramic plate has a first side and a second side opposite the first side.
  • a metal heat sink is provided on the first surface of the ceramic plate.
  • At least one metal circuit board is provided on the second side of the ceramic board, with a third side facing the second side of the ceramic board and a power semiconductor board opposite the third side. and a fourth surface containing bonding regions to which the devices will be bonded.
  • the manufacturing method includes the steps of: a) bonding a second surface of a ceramic plate and a third surface of at least one metal circuit board; and b) a first metal circuit board included in the at least one metal circuit board.
  • step b) the fourth face of the first metal circuit board is at least partially bonded to the first metal circuit board with a shot peening area that at least partially overlaps the bonding area of the first metal circuit board. and a non-shot peened region outside the region. Shot peening is applied to the shot peened areas and not to the non-shot peened areas.
  • the substrate of the present disclosure is a substrate having a ceramic plate, a metal heat sink, and at least one metal circuit plate.
  • the ceramic plate has a first side and a second side opposite the first side.
  • a metal heat sink is provided on the first surface of the ceramic plate.
  • At least one metal circuit board is provided on the second side of the ceramic board, with a third side facing the second side of the ceramic board and a power semiconductor board opposite the third side. and a fourth surface containing bonding regions to which the devices will be bonded.
  • the at least one metal circuit board includes a first metal circuit board.
  • the fourth surface of the first metal circuit board is at least partially overlying the bond area of the first metal circuit board and at least partially outside the bond area of the first metal circuit board. and a non-work hardened region.
  • the joint reliability of both the third surface and the fourth surface of the first metal circuit board can be enhanced. According to the other aspect described above, it is possible to improve the reliability of bonding between the first metal circuit board and the power semiconductor element while avoiding a significant decrease in manufacturing efficiency.
  • FIG. 1 is a cross-sectional view schematically showing a configuration of a power semiconductor device according to Embodiment 1;
  • FIG. 2 is a cross-sectional view schematically showing the configuration of a substrate in Embodiment 1;
  • FIG. 2 is a plan view schematically showing the configuration of a substrate in Embodiment 1;
  • FIG. 4 is a partial cross-sectional view along line IV-IV of FIG. 3;
  • FIG. 4 is a flow chart schematically showing a method of manufacturing a power semiconductor device according to Embodiment 1;
  • FIG. 4 is a partial cross-sectional view schematically showing one step of the substrate manufacturing method according to Embodiment 1;
  • FIG. 4 is a partial cross-sectional view schematically showing one step of the substrate manufacturing method according to Embodiment 1;
  • FIG. 10 is a plan view schematically showing the configuration of a substrate in Embodiment 2;
  • FIG. 9 is a partial cross-sectional view along line IX-IX of FIG. 8;
  • 7 is a flow chart schematically showing a method of manufacturing a power semiconductor device according to Embodiment 2;
  • FIG. 10 is a plan view schematically showing one step of a method for manufacturing a substrate in Embodiment 2;
  • 11 is a flow chart schematically showing a method of manufacturing a power semiconductor device in Embodiment 3;
  • FIG. 11 is a plan view schematically showing the configuration of a metal plate having a portion to be shot peened in Embodiment 3;
  • FIG. 14 is a partial cross-sectional view schematically showing one step of the substrate manufacturing method in Embodiment 3, taken along the line XIV-XIV in FIG. 13;
  • FIG. 15 is a partial cross-sectional view schematically showing one step of the method for manufacturing a substrate in Embodiment 3 from the same view as in FIG. 14;
  • FIG. 10 is a plan view schematically showing the configuration of a metal plate that is not subjected to shot peening processing in Embodiment 3;
  • FIG. 17 is a partial cross-sectional view along line XVI-XVI of FIG. 16;
  • FIG. 1 is a cross-sectional view schematically showing the configuration of a power module 90 (power semiconductor device) according to the first embodiment.
  • the power module 90 has a substrate 10 and a power semiconductor element 30 mounted on the substrate 10 .
  • the substrate 10 has a heat dissipation surface F6 and a circuit board upper surface F4 opposite to the heat dissipation surface F6.
  • the power semiconductor element 30 is bonded onto the circuit board upper surface F4 of the substrate 10 via a conductive bonding layer 31 .
  • the bonding layer 31 is, for example, a solder layer.
  • the power semiconductor element 30 is, for example, a switching element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated-Gate Bipolar Transistor). , or diodes such as Schottky barrier diodes or PiN diodes.
  • a switching element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated-Gate Bipolar Transistor).
  • diodes such as Schottky barrier diodes or PiN diodes.
  • the power module 90 may further have a base plate 20 bonded onto the heat dissipation surface F6 of the substrate 10.
  • the base plate 20 may be bonded to the substrate 10 via a bonding layer 21 .
  • the bonding layer 21 is, for example, a solder layer.
  • the base plate 20 is for dissipating heat from the power semiconductor element 30 .
  • the power module may further have a case 50 surrounding the substrate 10 .
  • the case 50 is preferably made of resin.
  • a sealing material (not shown) for sealing the power semiconductor element 30 may be provided in the case 50 .
  • the case 50 may be attached to the base plate 20 , for example by means of an adhesive 51 .
  • the power module 90 may further have an external connection terminal 40 connected to at least one of the circuit board upper surface F4 of the substrate 10 and the power semiconductor element 30 .
  • a bonding layer 41 may be used for this connection, and the bonding layer 41 is, for example, a solder layer.
  • the power module 90 may further have a bonding wire 32 that connects the power semiconductor element 30 and another portion of the power module 90 (in FIG. 1, the upper surface F4 of the circuit board of the substrate 10).
  • FIG. 2 is a cross-sectional view schematically showing the configuration of the substrate 10 (FIG. 1).
  • the substrate 10 has a circuit board upper surface F4 on which the power semiconductor element 30 (FIG. 1) is to be mounted, and a heat radiation surface F6 opposite to the circuit board upper surface F4.
  • the substrate 10 has a ceramic plate 11 , a metal heat sink 12 , at least one metal circuit board 13 , a bonding layer 61 (indirect bonding), and a bonding layer 62 .
  • the ceramic plate 11 has a ceramic plate lower surface F1 (first surface) and a ceramic plate upper surface F2 (second surface opposite to the first surface).
  • the ceramic plate 11 is made of alumina, silicon nitride, or aluminum nitride, for example.
  • the metal radiator plate 12 is provided on the ceramic plate lower surface F1 of the ceramic plate 11 .
  • the metal radiator plate 12 has a radiator plate upper surface F5 facing the ceramic plate lower surface F1 of the ceramic plate 11 and a surface opposite to the radiator plate upper surface F5, and this opposite surface is the aforementioned radiator surface F6. be.
  • the metal heat sink 12 does not need to have a circuit pattern, and may consist of one simple shape (typically, a substantially rectangular shape).
  • Each of the at least one metal circuit board 13 is provided on the ceramic board upper surface F2 of the ceramic board 11 .
  • At least one metal circuit board 13 has a circuit pattern, and in this embodiment, it is a plurality of metal circuit boards 13 separated from each other.
  • Each of the metal circuit boards 13 has a circuit board lower surface F3 (third surface) facing the ceramic board upper surface F2 of the ceramic board 11 and a surface opposite to the circuit board lower surface F3. is the upper surface F4 (fourth surface) of the circuit board described above.
  • the circuit board upper surface F4 includes a bonding region RE to which the power semiconductor element 30 (Fig. 1) is to be bonded.
  • the junction region RE is a portion of the circuit board upper surface F4 that overlaps the power semiconductor element 30 in a planar layout.
  • the junction region RE has a rectangular shape. The corners of the rectangle may be chamfered to some extent. A rectangle may have long and short sides, or may be a square. It should be noted that when referring to the long side of a rectangle herein, if the rectangle is a square, the term "long side" means any side of the square.
  • the area of the metal circuit board 13 is usually smaller than the area of the metal heat sink 12 .
  • the thickness of each of the metal heat sink 12 and the metal circuit board 13 is, for example, 0.4 mm or more and 1 mm or less.
  • Metal heat sink 12 and metal circuit board 13 are made of, for example, aluminum, an aluminum alloy, copper, or a copper alloy.
  • the bonding layer 61 forms an indirect bond between the ceramic board upper surface F2 of the ceramic board 11 and the circuit board lower surface F3 of the metal circuit board 13 .
  • the joining layer 61 is made of a conductor.
  • This conductor is, for example, solder, brazing material, or a sintered body of fine metal particles.
  • the fine metal particles may be fine particles having nanometer-order sizes, that is, nanoparticles.
  • the metal fine particles may be silver (Ag) fine particles. Ag microparticles as nanoparticles, that is, Ag nanoparticles are produced, for example, by decomposition of silver oxide.
  • the bonding layer 62 forms an indirect bond between the ceramic plate lower surface F1 of the ceramic plate 11 and the radiator plate upper surface F5 of the metal radiator plate 12 .
  • the bonding layer 62 is made of a conductor. This conductor is, for example, solder, brazing material, or a sintered body of fine metal particles. This conductor may be similar to those exemplified as the conductors of bonding layer 61 .
  • FIG. 3 is a plan view schematically showing the configuration of substrate 10A in the first embodiment.
  • 4 is a partial cross-sectional view along line IV-IV of FIG. 3.
  • FIG. The substrate 10A like the substrate 10 (FIG. 2), can be used for manufacturing the power module 90 (FIG. 1), and has substantially the same features as the substrate 10 described above. Therefore, elements identical or corresponding to those described in FIG. 2 are denoted by the same reference numerals in FIGS. 3 and 4, and description thereof will not be repeated. Further features of the substrate 10A are described below.
  • the board 10A (FIG. 3) includes a metal circuit board 13a (first metal circuit board) and a metal circuit board 13c (second metal circuit board). and a metal circuit board 13b.
  • the metal circuit boards 13a to 13c may be collectively referred to as the metal circuit board 13 hereinafter.
  • the metal circuit board 13a, the metal circuit board 13b, and the metal circuit board 13c each have a joint region REa, a joint region REb, and a joint region REc. is doing.
  • the junction regions REa to REc may be collectively referred to as junction regions RE.
  • the junction region REc is smaller than the junction region REa.
  • the long side of the bonding region REc is smaller than the long side of the bonding region REa, assuming that the size comparison is performed by comparing the lengths of the long sides.
  • one dimension threshold is defined in relation to the dimension of the junction region RE.
  • the short side of the junction region REa is equal to or larger than the dimension threshold.
  • the long side of the bonding region REb is greater than or equal to the dimension threshold, and the short side of the bonding region REb is less than the dimension threshold.
  • the long side of the junction region REc is less than the dimension threshold.
  • the one dimension is, for example, 3 mm.
  • the metal circuit board 13a has a work-hardened region 13p on the circuit board lower surface F3 and a work-hardened region 13q on the circuit board upper surface F4. .
  • each of the circuit board lower surface F3 and the circuit board upper surface F4 of the metal circuit board 13a is work hardened.
  • the metal circuit board 13a may have a non-work-hardened region 13n between the work-hardened region 13p and the work-hardened region 13q.
  • the metal circuit board 13b also has a similar cross-sectional configuration.
  • the metal circuit board 13c does not have the work-hardened region 13p and the work-hardened region 13q, and consists only of the non-work-hardened region 13n.
  • the circuit board lower surface F3 and the circuit board upper surface F4 of the metal circuit board 13c are not work hardened.
  • the work-hardened region is a region made of crystals that have been work-hardened.
  • Work hardening is a phenomenon in which the resistance to further plastic deformation increases when plastic deformation is applied to a crystal.
  • the non-work-hardened region is a region composed of crystals that are not substantially work-hardened.
  • the work hardened regions are harder than the non-work hardened regions.
  • the dislocation density in the work-hardened region is higher than the dislocation density in the non-work-hardened region.
  • the work-hardened region can be formed by plastic deformation by shot peening, for example.
  • the terms "work hardening" and "non-work hardening” are used to express physical properties as described above.
  • FIG. 5 is a flow chart schematically showing a method of manufacturing the power module 90 (FIG. 1) having the substrate 10A according to the first embodiment.
  • steps up to step S140 correspond to the manufacturing method of the substrate 10A.
  • 6 and 7 are partial cross-sectional views schematically showing one step of the method of manufacturing the substrate 10A.
  • step S110 the work-hardened region 13p is formed by subjecting the circuit board lower surface F3 of the metal circuit board 13a to shot peening.
  • shot peening may be applied to the entire circuit board lower surface F3 of the metal circuit board 13a.
  • Shot peening is a process that cold works a metal surface by blasting small particles against it, thereby hardening the metal surface.
  • small glass particles 71 having a particle diameter of several hundred ⁇ m are blown from an air nozzle 70 at a pressure of about 0.3 MPa for about 30 to 60 seconds.
  • a material other than glass may be used as the small particles 71, for example, an iron-based material may be used.
  • a shot peening device other than the air nozzle 70 may be used, for example, an impeller may be used.
  • the projection angle of the small particles 71 may be optimized as appropriate.
  • small particles 71 remaining on the metal circuit board 13a are removed by, for example, air blowing.
  • a similar shot peening process is applied to the circuit board lower surface F3 of the metal circuit board 13b (FIG. 3).
  • the circuit board lower surface F3 of the metal circuit board 13c is not subjected to shot peening.
  • step S120 the upper surface F4 of the metal circuit board 13a is subjected to shot peening in the same manner as described above, thereby forming the work-hardened region 13q. be done.
  • shot peening may be applied to the entire circuit board upper surface F4 of the metal circuit board 13a.
  • a similar shot peening process is applied to the circuit board upper surface F4 of the metal circuit board 13b (FIG. 3).
  • the circuit board upper surface F4 of the metal circuit board 13c is not subjected to shot peening.
  • the order of steps S110 and S120 is arbitrary.
  • step S130 the ceramic board upper surface F2 of the ceramic board 11 and the circuit board lower surface F3 of the metal circuit board 13 are joined after the above steps S110 and S120.
  • a bonding layer 61 (indirect bonding) is formed between the ceramic plate upper surface F2 of the ceramic plate 11 and the circuit board lower surface F3 of the metal circuit board 13 .
  • Soldering or brazing, for example, is performed to form this indirect connection.
  • sintering of the metal fine particles described above may be performed.
  • application of a metal paste paste in which fine metal particles are dispersed
  • sintering of the fine metal particles by heat treatment of the metal paste may be performed.
  • the metal paste is typically Ag paste. If the size of the metal particles is sufficiently small, sintering thereof can be done at a temperature comparable to that of soldering.
  • step S130 correcting processing for correcting undulations caused by shot peening processing may be performed as necessary.
  • This corrective processing is performed by, for example, grinding or press molding.
  • step S140 the ceramic plate lower surface F1 of the ceramic plate 11 and the radiator plate upper surface F5 of the metal radiator plate 12 are joined. Specifically, a bonding layer 62 (indirect bonding) is formed between the ceramic plate lower surface F1 of the ceramic plate 11 and the radiator plate upper surface F5 of the metal radiator plate 12 in the same manner as the bonding layer 61 .
  • the order of steps S130 and S140 is arbitrary. Also, step S130 and step S140 may be performed at the same time.
  • step S150 the power semiconductor element 30 is bonded to the bonding region RE of the circuit board upper surface F4 of each metal circuit board 13 .
  • the power module 90 (FIG. 1) having the substrate 10A (FIGS. 3 and 4) is obtained.
  • the circuit board lower surface F3 and the circuit board upper surface F4 of the metal circuit board 13a are each subjected to shot peening. This suppresses changes in the fine shape due to heat cycles on both the circuit board bottom surface F3 and the circuit board top surface F4. Therefore, the bonding reliability of both the circuit board lower surface F3 and the circuit board upper surface F4 of the metal circuit board 13a can be enhanced.
  • each of the circuit board bottom surface F3 and the circuit board top surface F4 of the metal circuit board 13a is work hardened. This suppresses changes in the fine shape due to heat cycles on both the circuit board bottom surface F3 and the circuit board top surface F4. Therefore, the bonding reliability of both the circuit board lower surface F3 and the circuit board upper surface F4 of the metal circuit board 13a can be enhanced.
  • both the circuit board lower surface F3 and the circuit board upper surface F4 of the metal circuit board 13a By subjecting both the circuit board lower surface F3 and the circuit board upper surface F4 of the metal circuit board 13a to the shot peening process as described above, the shot peening process is reduced compared to the case where only one of them is subjected to the shot peening process. Warpage of the metal circuit board 13a due to peening can be suppressed. In other words, since both the circuit board lower surface F3 and the circuit board upper surface F4 of the metal circuit board 13a are work hardened, the work hardening is greater than when only one of them is work hardened. It is possible to suppress the occurrence of warping of the metal circuit board 13a due to this.
  • step S130 (Fig. 5) is performed after shot peening in step S120 (Fig. 5). If this order were reversed, the shot peening process could damage the edges of the bond between the ceramic plate top surface F2 of the ceramic plate 11 and the circuit board bottom surface F3 of the at least one metal circuit board 13. . According to the present embodiment, this damage can be avoided, so that bonding reliability can be further improved. Note that if the damage is not a problem, as a modification, the bonding in step S130 may be performed before the shot peening process in step S120.
  • the bonding in step S130 includes forming an indirect bond by the bonding layer 61 (FIG. 4).
  • the reliability of indirect bonding between the circuit board lower surface F3 of the metal circuit board 13a and the ceramic board upper surface F2 of the ceramic board 11 can be enhanced for the reasons described above.
  • the wettability of the material for indirect bonding to the circuit board lower surface F3 of the metal circuit board 13a can be enhanced by the unevenness resulting from the shot peening process.
  • the "wettability" referred to here is the wettability of a material melted by heating when soldering or brazing is performed, and the wettability of a metal paste when sintering metal fine particles is performed. Since the unevenness caused by the shot peening process is almost buried by the indirect bonding, there is almost no adverse effect on the bonding reliability of the power module 90 (FIG. 1).
  • the circuit board upper surface F4 of the metal circuit board 13c (Fig. 3) is not subjected to shot peening. Even if the shot peening process is omitted in this way, since the bonding region REc of the metal circuit board 13c is smaller than the bonding region REa of the metal circuit board 13a, the adverse effect on the bonding reliability is relatively small. As a modification, the circuit board upper surface F4 of the metal circuit board 13c (FIG. 3) may also be subjected to shot peening.
  • the circuit board lower surface F3 of the metal circuit board 13c (Fig. 3) is not subjected to shot peening. Even if the shot peening process is omitted in this way, since the bonding region REc of the metal circuit board 13c is smaller than the bonding region REa of the metal circuit board 13a, the adverse effect on the bonding reliability is relatively small. As a modification, the circuit board lower surface F3 of the metal circuit board 13c (FIG. 3) may also be subjected to shot peening.
  • the metal circuit board 13a has a non-work-hardened region 13n (Fig. 4). As a result, the metal circuit board 13a does not need to be a work-hardened region entirely in the thickness direction. Therefore, the shot peening process for forming the work-hardened region is made easier. As a modification, the non-work-hardened region 13n may disappear by deep shot peening to such an extent that the work-hardened region 13p and the work-hardened region 13p are in contact with each other.
  • FIG. 8 is a plan view schematically showing the structure of substrate 10B in the second embodiment.
  • 9 is a partial cross-sectional view along line IX-IX of FIG. 8.
  • the substrate 10B like the substrate 10 (FIG. 2), can be used for manufacturing the power module 90 (FIG. 1), and has substantially the same features as the substrate 10 described above. Therefore, the same or corresponding elements as those described in FIG. 2 are denoted by the same reference numerals in FIGS. 8 and 9, and description thereof will not be repeated. Further features of the substrate 10B are described below.
  • the board 10B (FIG. 8) includes a metal circuit board 13a (first metal circuit board) and a metal circuit board 13c (second metal circuit board). and a metal circuit board 13b.
  • the metal circuit boards 13a to 13c may be collectively referred to as the metal circuit board 13 hereinafter.
  • the metal circuit board 13a, the metal circuit board 13b, and the metal circuit board 13c each have a joint region REa, a joint region REb, and a joint region REc. is doing.
  • the junction regions REa to REc may be collectively referred to as junction regions RE.
  • the junction region REc is smaller than the junction region REa.
  • the long side of the bonding region REc is smaller than the long side of the bonding region REa, assuming that the size comparison is performed by comparing the lengths of the long sides.
  • one dimension threshold is defined in relation to the dimension of the junction region RE.
  • the short side of the junction region REa is equal to or larger than the dimension threshold.
  • the long side of the bonding region REb is greater than or equal to the dimension threshold, and the short side of the bonding region REb is less than the dimension threshold.
  • the long side of the junction region REc is less than the dimension threshold.
  • the one dimension is, for example, 3 mm.
  • a circuit board upper surface F4 of the metal circuit board 13a includes a work-hardened region 13r (FIG. 9) that at least partially overlaps the bonding region REa (FIG. 8) of the metal circuit board 13a, and a bonding region of the metal circuit board 13a that at least partially overlaps. and a non-work hardened region 13n (FIG. 9) outside REa (FIG. 8).
  • the work-hardened region 13r may be separated from the circuit board lower surface F3 in the thickness direction (longitudinal direction in FIG. 9) by a non-work-hardened region 13n. In other words, the circuit board bottom surface F3 may be entirely non-work hardened region 13n.
  • the edge of the circuit board upper surface F4 of the metal circuit board 13a is at least partially composed of the non-work-hardened region 13n (Fig. 9), preferably composed only of the non-work-hardened region 13n (Fig. 9). More specifically, a non-work-hardened region 13n is formed within a distance LS (FIG. 9) from the edge of the upper surface F4 of the metal circuit board 13a.
  • the distance LS is preferably 0.3 mm or more, and if it is 1 mm or more, the effects described later can be obtained more reliably.
  • the edge of the metal circuit board 13a and the edge of the bonding region REa are separated from each other by the distance LR (FIG. 8) on the straight line defining the distance LS (FIG. 9).
  • the distance LR is less than 1 mm, the relationship LS>LR is preferably satisfied, and when the distance LR is 0.3 mm or less, the above relationship is more preferably satisfied, and when the distance LR is zero more preferably satisfies the above relationship. Thereby, even if the distance LR is small, it is possible to sufficiently secure the distance LS.
  • the metal circuit board 13b also has a cross-sectional configuration similar to that of FIG.
  • the metal circuit board 13c does not have the work-hardened region 13r and consists only of the non-work-hardened region 13n.
  • the circuit board upper surface F4 of the metal circuit board 13c is not work-hardened.
  • FIG. 10 is a flow chart schematically showing a method of manufacturing power module 90 (FIG. 1) having substrate 10B according to the second embodiment.
  • steps up to step S240 correspond to the manufacturing method of the substrate 10B.
  • FIG. 11 is a plan view schematically showing one step of the method of manufacturing the substrate 10B.
  • step S210 the ceramic board upper surface F2 of the ceramic board 11 and the circuit board lower surface F3 of the metal circuit board 13 are joined. Specifically, a bonding layer 61 (indirect bonding) is formed between the ceramic plate upper surface F2 of the ceramic plate 11 and the circuit board lower surface F3 of the metal circuit board 13 .
  • a specific method for forming this indirect junction may be the same as the method exemplified as step S130 (FIG. 5: Embodiment 1).
  • step S220 the ceramic plate lower surface F1 of the ceramic plate 11 and the radiator plate upper surface F5 of the metal radiator plate 12 are joined. Specifically, a bonding layer 62 (indirect bonding) is formed between the ceramic plate lower surface F1 of the ceramic plate 11 and the radiator plate upper surface F5 of the metal radiator plate 12 in the same manner as the bonding layer 61 .
  • the order of steps S210 and S220 is arbitrary. Also, step S210 and step S220 may be performed at the same time.
  • step S230 the work-hardened region 13r (FIG. 9) is formed by subjecting the upper surface F4 (FIG. 9) of the metal circuit board 13a (FIG. 8) to shot peening. A similar shot peening process is applied to the upper surface F4 of the metal circuit board 13b (FIG. 8). On the other hand, shot peening is not applied to the upper surface F4 of the metal circuit board 13c (FIG. 8).
  • the shot peening area RS is defined as an area to be shot peened.
  • the non-shot peening region RN is defined as a region that will not be shot peened.
  • the shot peening process is applied to the shot peening area RS and not to the non-shot peening area RN. Specifically, shot peening is applied to the entire shot peening region RS. In addition, shot peening processing is not applied to any portion of the non-shot peening region RN.
  • the circuit board upper surface F4 of the metal circuit board 13a includes a shot peening area RS (FIG. 11) that at least partially overlaps the bonding area REa (FIG. 8) of the metal circuit board 13a, and a bonding area of the metal circuit board 13a that is at least partially and a non-shot peened region RN (FIG. 11) outside REa (FIG. 8).
  • the edge of the circuit board top surface F4 of the metal circuit board 13a consists at least partially of the non-shot peened area RN, preferably only of the non-shot peened area.
  • a non-shot peening area RN is formed within a distance LS (FIG. 11) from the edge of the upper surface F4 of the metal circuit board 13a.
  • the shot peening area RS and the non-shot peening area RN of the metal circuit board 13b may be similar to those of the metal circuit board 13a.
  • metal circuit board 13c does not have shot peening region RS, but only non-shot peening region RN.
  • a selective shot peening process by dividing the shot peening region RS and the non-shot peening region RN can be performed, for example, using a mask that exposes the shot peening region RS and covers the non-shot peening region RN.
  • a specific shot peening method the same method as described in the first embodiment may be used while applying the mask.
  • the thickness of the work-hardened region 13r of the metal circuit board 13a is preferably 10 ⁇ m or more in order to reliably obtain the effect of shot peening. Further, the thickness of the work-hardened region 13r of the metal circuit board 13a is preferably 3/4 or less of the thickness of the metal circuit board 13 in order to suppress damage to the ceramic plate 11 or suppress warping of the substrate 10B. Preferably, it is more preferably half or less. The same applies to the metal circuit board 13b.
  • step S240 the power semiconductor element 30 is bonded to the bonding region RE of the circuit board upper surface F4 of each metal circuit board 13 .
  • power module 90 FIG. 1 having substrate 10B (FIGS. 8 and 9) is obtained.
  • the circuit board upper surface F4 of the metal circuit board 13 may be smoothed as necessary. This reduces the surface roughness of the circuit board upper surface F4. If the surface roughness of the circuit board upper surface F4 when the power semiconductor element 30 is bonded to the circuit board upper surface F4 in step S240 is not excessive, this smoothing is not necessary.
  • the circuit board upper surface F4 of the metal circuit board 13a has a shot peening region RS that at least partially overlaps the bonding region REa to which the power semiconductor element 30 is to be bonded. is doing. This suppresses changes in the fine shape due to the heat cycle. Therefore, the reliability of bonding between the metal circuit board 13a and the power semiconductor element 30 can be enhanced.
  • the circuit board top surface F4 of the metal circuit board 13a has a non-shot peened region RN that is at least partially outside the bonding region REa.
  • the area of the shot peening region RS can be suppressed while suppressing the influence on the bonding reliability between the metal circuit board 13a and the power semiconductor element 30 . Therefore, it is possible to suppress a decrease in manufacturing efficiency due to shot peening.
  • the circuit board top surface F4 of the metal circuit board 13a has a work hardened region 13r (FIG. 9) that at least partially overlaps the bonding region REa (FIG. 8). This suppresses changes in the fine shape due to the heat cycle. Therefore, the bonding reliability between the metal circuit board 13a and the power semiconductor element 30 (FIG. 1) can be enhanced.
  • the circuit board top surface F4 of the metal circuit board 13a has a non-work hardened region 13n (Fig. 9) that is at least partially outside the bonding region REa (Fig. 8). As a result, the area of the work-hardened region 13r (FIG.
  • the edge of the circuit board upper surface F4 (FIG. 9) of the metal circuit board 13a is at least partially composed of the non-shot peened region RN (FIG. 11). This suppresses deterioration in the joint reliability between the metal circuit board 13a and the ceramic board 11 in the vicinity of the edge of the metal circuit board 13a due to the shot peening process. This effect is more reliably obtained when the above edge consists only of non-shot peened regions.
  • the circuit board upper surface F4 of the metal circuit board 13c is not subjected to shot peening. Even if the shot peening process is omitted in this way, since the joint region REc of the metal circuit board 13c is smaller than the joint region REa of the metal circuit board 13a as shown in FIG. 8, there is no adverse effect on the joint reliability. , relatively small.
  • FIG. 12 is a flow chart schematically showing a method of manufacturing the power module 90 (FIG. 1: Embodiment 1) according to the third embodiment.
  • substrate 10A (FIGS. 3 and 4: Embodiment 1) is formed by a method different from that of Embodiment 1 described above.
  • the third embodiment is substantially the same as the first embodiment described above. Therefore, the method of forming the substrate 10A will be mainly described below, and the other features will be denoted by the same reference numerals for the same or corresponding elements as those described in the first embodiment. Don't repeat the description.
  • a metal plate 13X (FIG. 13) larger than the metal circuit board 13a is prepared.
  • the size of the metal plate 13X is equal to or greater than the combined size of the plurality of metal circuit boards 13a.
  • the metal plate 13X has a portion from which the metal circuit board 13a is to be cut, as indicated by the phantom lines in FIG.
  • the metal plate 13X has portions from which the plurality of metal circuit plates 13a are cut out, as indicated by the phantom lines in FIG.
  • the surface of the metal plate 13X that includes the circuit board bottom surface F3 of the metal circuit board 13a may be referred to as the circuit board bottom surface F3 of the metal plate 13X.
  • the surface of the metal plate 13X that includes the portion of the metal circuit board 13a that will become the circuit board upper surface F4 is sometimes referred to as the circuit board upper surface F4 of the metal plate 13X.
  • shot peening is then applied to the circuit board lower surface F3 of the portion of the metal plate 13X that is to be cut out as the metal circuit board 13a.
  • the portion of the circuit board lower surface F3 of the metal plate 13X that is to be cut out as the metal circuit board 13a may be selectively shot peened.
  • the circuit board lower surface F3 of the metal plate 13X not only the portion where the metal circuit board 13a is to be cut out but also the outer side thereof may be shot peened. Therefore, this shot peening process does not require a special mask.
  • step S320 (FIG. 12) shot peening is applied to the circuit board upper surface F4 of the metal plate 13X which is to be cut out as the metal circuit board 13a.
  • step S320 shot peening is applied to the circuit board upper surface F4 of the metal plate 13X which is to be cut out as the metal circuit board 13a.
  • only the portion of the circuit board upper surface F4 of the metal plate 13X that is to be cut out as the metal circuit board 13a may be selectively shot peened.
  • the circuit board upper surface F4 of the metal plate 13X not only the portion where the metal circuit board 13a is to be cut out but also the outer side thereof may be shot peened. Therefore, this shot peening process does not require a special mask.
  • the order of steps S310 and S320 is arbitrary.
  • step S310 shot peening is applied to the portions to be cut out from the metal plate 13X as a plurality of metal circuit boards including one metal circuit board 13a (for example, as shown in FIG. 13).
  • shot peening is applied to the portions to be cut out from the metal plate 13X as the plurality of metal circuit boards 13a
  • the plurality of metals Shot peening can be applied to the portion that will become the circuit board. Therefore, shot peening processing is made efficient.
  • step S320 FIG. 12
  • step S330 (FIG. 12). This correction may be done by grinding or pressing.
  • shot peening is applied to the portions to be cut out from metal plate 13X as a plurality of metal circuit boards including one metal circuit board 13a ( For example, as shown in FIG. 13, when shot peening is applied to the portions to be cut out from the metal plate 13X as the plurality of metal circuit plates 13a), by correcting the one metal plate 13X, , a plurality of metal circuit boards can be corrected. Therefore, correction of undulation is made efficient.
  • step S330 may be omitted when undulation is not a particular problem.
  • Step 330 is preferably performed before step S340, which will be described later, from the viewpoint of efficiency.
  • At step S340 at least one metal circuit board 13a is cut out from the metal plate 13X.
  • a plurality of metal circuit boards for example, a plurality of metal circuit boards 13a
  • This cutting out is done, for example, by press stamping or machining.
  • the metal circuit board 13a subjected to shot peening is obtained.
  • the metal circuit board 13c (FIG. 3) is not subjected to shot peening as described in the first embodiment. A method of forming the metal circuit board 13c in the third embodiment will be described below.
  • a metal plate 13Y (FIGS. 16 and 17) larger than the metal circuit board 13c is prepared.
  • the size of the metal plate 13Y is equal to or greater than the combined size of the plurality of metal circuit boards 13c.
  • the metal plate 13Y has a portion from which the metal circuit board 13c is to be cut, as indicated by the phantom lines in FIG.
  • the metal plate 13Y has portions from which the plurality of metal circuit plates 13c are cut out, as indicated by the phantom lines in FIG.
  • At least one metal circuit board 13c is cut out from the metal plate 13Y that has not been subjected to shot peening.
  • a plurality of metal circuit boards for example, a plurality of metal circuit boards 13c
  • This cutting out is done, for example, by press stamping or machining.
  • a metal circuit board 13c not subjected to shot peening is obtained.
  • Steps S360 and S370 are performed in substantially the same manner as steps S140 and S150 (FIG. 5: Embodiment 1), respectively.
  • the order of steps S350 and S360 is arbitrary. Also, step S350 and step S360 may be performed at the same time.
  • the power module 90 (FIG. 1) having the substrate 10A (FIGS. 3 and 4) is obtained.
  • the power module 90 (FIG. 1) has the base plate 20 separate from the metal heat sink 12, but the base plate 20 is omitted and the metal heat sink 12 serves as the base. It may also function as a plate. In that case, the case 50 may be attached to the metal heat sink 12 .
  • the metal may be a pure metal or an alloy. Also, for convenience of explanation, the terms “upper surface” and “lower surface” are used, but these terms are only used to distinguish different surfaces and limit the relationship with the direction of gravity. not a thing In addition, it is possible to freely combine each embodiment, and to modify or omit each embodiment as appropriate within a technically consistent range.

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PCT/JP2022/017272 2021-04-14 2022-04-07 基板の製造方法、電力用半導体装置の製造方法、および基板 Ceased WO2022220191A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214284A (ja) * 2002-12-27 2004-07-29 Dowa Mining Co Ltd 金属−セラミックス接合基板およびその製造方法
JP2006332084A (ja) * 2005-05-23 2006-12-07 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法、および半導体装置
JP2007273661A (ja) * 2006-03-31 2007-10-18 Neomax Material:Kk 半導体装置
JP2014187088A (ja) * 2013-03-22 2014-10-02 Toshiba Corp パワー半導体装置の製造方法、パワー半導体装置
WO2021048937A1 (ja) * 2019-09-11 2021-03-18 三菱電機株式会社 半導体装置および半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214284A (ja) * 2002-12-27 2004-07-29 Dowa Mining Co Ltd 金属−セラミックス接合基板およびその製造方法
JP2006332084A (ja) * 2005-05-23 2006-12-07 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法、および半導体装置
JP2007273661A (ja) * 2006-03-31 2007-10-18 Neomax Material:Kk 半導体装置
JP2014187088A (ja) * 2013-03-22 2014-10-02 Toshiba Corp パワー半導体装置の製造方法、パワー半導体装置
WO2021048937A1 (ja) * 2019-09-11 2021-03-18 三菱電機株式会社 半導体装置および半導体装置の製造方法

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