WO2022188359A1 - 静电保护电路及半导体器件 - Google Patents

静电保护电路及半导体器件 Download PDF

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Publication number
WO2022188359A1
WO2022188359A1 PCT/CN2021/112929 CN2021112929W WO2022188359A1 WO 2022188359 A1 WO2022188359 A1 WO 2022188359A1 CN 2021112929 W CN2021112929 W CN 2021112929W WO 2022188359 A1 WO2022188359 A1 WO 2022188359A1
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Prior art keywords
terminal
pad
transistor
electrically connected
protection circuit
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PCT/CN2021/112929
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English (en)
French (fr)
Inventor
许杞安
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/844,235 priority Critical patent/US20220320074A1/en
Publication of WO2022188359A1 publication Critical patent/WO2022188359A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H10D89/813—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements specially adapted to provide an electrical current path other than the field-effect induced current path
    • H10D89/814—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements specially adapted to provide an electrical current path other than the field-effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the FET, e.g. gate coupled transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements

Definitions

  • the present application relates to, but is not limited to, an electrostatic protection circuit and a semiconductor device.
  • a clamp circuit (Clamp Circuit) including a clamp transistor (Clamp Transistor) is usually used as a protection scheme for the ESD protection circuit.
  • the static electricity will be discharged through the electrostatic protection circuit instead of flowing through the internal circuit, so as to protect the internal circuit, thereby preventing static electricity from entering the internal circuit of the integrated circuit and causing the internal circuit
  • the components are burned, and the internal circuit voltage is guaranteed to be stable.
  • the embodiment of the present application provides an electrostatic protection circuit, which is electrically connected to the first solder pad and the second solder pad.
  • the electrostatic protection circuit includes: an electrostatic discharge transistor, used for electrostatic discharge, having a control terminal, a first terminal, a A second end and a substrate end, the first end is electrically connected to the first pad, the second end is electrically connected to the second pad; a first transistor has a control end, a first end and The second terminal, the control terminal is electrically connected to the second pad, the first terminal is electrically connected to the first pad, the second terminal is electrically connected to the control terminal and the pad of the ESD transistor a bottom end; a second transistor with a control end, a first end and a second end, the control end is electrically connected to the first pad, and the first end is electrically connected to the control end of the electrostatic discharge transistor and a substrate terminal, the second terminal is electrically connected to the second pad.
  • Embodiments of the present application further provide a semiconductor device, which includes at least two pads, and the electrostatic protection circuit as described above is disposed between any two pads.
  • 1A is a schematic diagram of a circuit structure without an electrostatic protection circuit according to the first embodiment of the present application
  • FIG. 1B is a schematic diagram of a circuit structure of an electrostatic protection circuit according to a second embodiment of the present application.
  • FIG. 2 is a schematic diagram of an application of an electrostatic protection circuit according to a third embodiment of the present application.
  • FIG. 3 is a schematic diagram of an application of an electrostatic protection circuit according to a fourth embodiment of the present application.
  • FIG. 4 is a schematic diagram of an application of an electrostatic protection circuit according to a fifth embodiment of the present application.
  • FIG. 5 is a schematic diagram of the application of the electrostatic protection circuit according to the sixth embodiment of the present application.
  • FIG. 6 is a schematic diagram of a semiconductor device according to an eighth embodiment of the present application.
  • FIG. 7 is a schematic top view of a semiconductor structure forming the electrostatic discharge transistor of the semiconductor device according to the ninth embodiment of the present application.
  • FIG. 8 is a schematic top view of a semiconductor structure forming the electrostatic discharge transistor of the semiconductor device according to the tenth embodiment of the present application;
  • FIG. 9 is a schematic top view of the semiconductor structure forming the electrostatic discharge transistor of the semiconductor device according to the eleventh embodiment of the present application.
  • FIG. 10 is a schematic cross-sectional schematic diagram of the structure shown in FIG. 8 .
  • first part over or on the second part may include embodiments in which the first part and the second part are formed in direct contact, and may also include additionally forming between the first part and the second part. parts so that the first part and the second part may not be in direct contact.
  • Various components may be arbitrarily drawn in different scales for the purpose of simplicity and clarity.
  • FIG. 1A is a schematic diagram of the circuit structure of the first embodiment of the present application, please refer to FIG. 1A , the circuit has two pads, namely the first pad VPP, the second pad VDD, the first pad VPP, The second pads VDD are respectively connected to the internal circuits 10 .
  • the static electricity is generated on one of the pads (for example, the first pad VPP)
  • the static charge will flow through the internal circuit 10 and be discharged through the internal circuit 10 (the current direction is shown by the arrow in the figure), thereby causing the internal circuit 10 to be damaged. Static damage.
  • FIG. 1B is a schematic diagram of a circuit structure provided with an electrostatic protection circuit according to a second embodiment of the present application.
  • An electrostatic protection circuit 11 is set between the first pad VPP and the second pad VDD, and the internal circuit 10 is respectively connected to the second pad VPP and the second pad VDD.
  • a pad VDD and a second pad VSS are electrically connected, and the electrostatic protection circuit 11 is also electrically connected to the first pad VPP and the second pad VDD, respectively, that is, the electrostatic protection circuit 11 is connected in parallel with the internal circuit 10 .
  • the static electricity When static electricity is generated on one of the solder pads (eg, the first solder pad VPP), the static electricity will be discharged through the electrostatic protection circuit 11 and will not flow through the internal circuit 10, so as to protect the internal circuit 10, thereby protecting the internal circuit 10. Prevent static electricity from entering the internal circuit 10 of the integrated circuit, causing the components of the internal circuit 10 to be burned, and at the same time ensure that the voltage of the internal circuit 10 is stable.
  • the electrostatic protection circuit 11 can discharge static electricity, when the integrated circuit is working, the first pad VPP and the first pad VDD may not be powered on at the same time, which will cause the parasitic diode of the electrostatic protection circuit 11 to conduct electricity. is turned on, thereby affecting the function of the electrostatic protection circuit 11 .
  • the electrostatic protection circuit 11 includes an NMOS transistor.
  • the gate, source and substrate of the NMOS transistor are short-circuited and connected to the second pad VDD.
  • the drain is connected to the first pad VPP.
  • the parasitic diode D1 in the electrostatic protection circuit 11 there is a parasitic diode D1 in the electrostatic protection circuit 11.
  • the first pad VPP and the second pad VDD may not be powered on at the same time, which will cause the parasitic diode D1 of the electrostatic protection circuit to be turned on.
  • the charge is discharged through the parasitic diode D1, thereby affecting the function of the internal circuit 10.
  • the parasitic diode D1 of the electrostatic protection circuit 11 will be turned on, and the current will flow through the parasitic diode D1, thereby affecting the function of the internal circuit.
  • the present application also provides an electrostatic protection circuit, which can avoid the occurrence of conduction between the solder pads caused by not being powered on at the same time, thereby avoiding an impact on the internal circuit.
  • FIG. 2 is a schematic diagram of the application of the electrostatic protection circuit according to the third embodiment of the present application. Please refer to FIG. 2.
  • the internal circuit 20 is electrically connected to the first pad VPP and the second pad VDD, respectively, and the electrostatic protection circuit 21 is also connected to the first pad respectively.
  • VPP and the second pad VDD are electrically connected, that is, the electrostatic protection circuit 21 is connected in parallel with the internal circuit 20 .
  • the static electricity is generated on one of the pads (for example, the second pad VDD)
  • the static electricity will be discharged through the electrostatic protection circuit 21 instead of flowing through the internal circuit 20, so as to protect the internal circuit 20 and avoid The internal circuit 20 is damaged by static electricity.
  • the first pad VPP is a first power pad
  • the second pad VDD is a second power pad
  • the first bonding pad may also be a first ground bonding pad
  • the second bonding pad may also be a second ground bonding pad.
  • the electrostatic protection circuit 21 of the present application includes an electrostatic discharge transistor Mesd, a first transistor Mn1, and a second transistor Mn2.
  • the electrostatic discharge transistor Mesd is used for electrostatic discharge and has a control terminal, a first terminal, a second terminal and a substrate terminal, the first terminal is electrically connected to the first pad VPP, and the second terminal is is electrically connected to the second pad VDD.
  • the ESD transistor Mesd is an NMOS transistor, wherein the control terminal of the ESD transistor Mesd is the gate terminal of the NMOS transistor, and the first terminal of the ESD transistor Mesd is The drain terminal of the NMOS transistor, the second terminal of the ESD transistor Mesd is the source terminal of the NMOS transistor, and the substrate terminal of the ESD transistor Mesd is the substrate terminal of the NMOS transistor.
  • the first transistor Mn1 has a control terminal, a first terminal and a second terminal, the control terminal is electrically connected to the second pad VDD, the first terminal is electrically connected to the first pad VPP, so The second terminal is electrically connected to the control terminal and the substrate terminal of the electrostatic discharge transistor Mesd.
  • the first transistor Mn1 is an NMOS transistor, wherein the control terminal of the first transistor Mn1 is the gate terminal of the NMOS transistor, which is electrically connected to the second pad VDD; the The first terminal of the first transistor Mn1 is the source terminal of the NMOS transistor, which is electrically connected to the first pad VPP; the second terminal of the first transistor Mn1 is the drain terminal of the NMOS transistor, which is electrically connected to the first pad VPP. connected to the control terminal and the substrate terminal of the electrostatic discharge transistor Mesd.
  • the second transistor Mn2 has a control terminal, a first terminal and a second terminal, the control terminal is electrically connected to the first pad VPP, and the first terminal is electrically connected to the control of the electrostatic discharge transistor Mesd terminal and substrate terminal, the second terminal is electrically connected to the second pad VDD.
  • the second transistor Mn2 is an NMOS transistor, wherein the control terminal of the second transistor Mn2 is the gate terminal of the NMOS transistor, which is electrically connected to the first pad VPP; the The first end of the second transistor Mn2 is the drain end of the NMOS transistor, which is electrically connected to the control end and the substrate end of the electrostatic discharge transistor Mesd; the second end of the second transistor Mn2 is the NMOS transistor The source terminal of the tube is electrically connected to the second pad VDD.
  • the first pad VPP is powered on first, that is, when the voltage of the first pad VPP is greater than the voltage of the second pad VDD, the second transistor Mn2 is turned on, and the The control terminal of the electrostatic discharge transistor Mesd is at a low potential, that is, the substrate terminal of the electrostatic discharge transistor Mesd is at a low potential, and the parasitic diode of the electrostatic discharge transistor Mesd is reverse biased and non-conductive, thereby avoiding The charges are discharged through the parasitic diode of the electrostatic discharge transistor Mesd, which ensures the normal operation of the internal circuit 20 .
  • the second pad VDD is powered on first, that is, when the voltage of the first pad VPP is lower than the voltage of the second pad VDD, the first transistor Mn1 is turned on, and the The control terminal of the electrostatic discharge transistor Mesd is still at a low potential, that is, the substrate terminal of the electrostatic discharge transistor Mesd is at a low potential, then the parasitic diode of the electrostatic discharge transistor Mesd is reverse biased and not turned on, thereby The discharge of electric charge through the parasitic diode of the electrostatic discharge transistor Mesd is avoided, and the normal operation of the internal circuit 20 is ensured.
  • the electrostatic protection circuit of the present application can prevent charges from being discharged through the parasitic diodes of the electrostatic protection circuit when different pads are not powered on at the same time, thereby ensuring the normal operation of the internal circuit 20 and the normal operation of the electrostatic protection circuit.
  • the electrostatic protection circuit of the present application does not affect the performance of the semiconductor device, solves the problem of electrostatic protection between different pads, effectively ensures the reliability of the semiconductor device, and improves the competitiveness of the semiconductor device.
  • FIG. 3 is a schematic diagram of the application of the electrostatic protection circuit according to the fourth embodiment of the present application. Please refer to FIG. 3.
  • the substrate end of the electrostatic discharge transistor Mesd and the first electrode of the electrostatic discharge transistor Mesd One end has a first parasitic diode D1, the anode of the first parasitic diode D1 is connected to the substrate end of the electrostatic discharge transistor Mesd, and the cathode of the first parasitic diode D1 is connected to the electrostatic discharge transistor Mesd.
  • the first end is electrically connected.
  • the substrate end of the ESD transistor Mesd and the second end of the ESD transistor Mesd also have a second parasitic diode D2, and the anode of the second parasitic diode D2 is connected to the ESD transistor Mesd
  • the substrate terminal of the second parasitic diode D2 is electrically connected to the second terminal of the electrostatic discharge transistor Mesd.
  • the first pad VPP is powered on first, that is, when the voltage of the first pad VPP is greater than the voltage of the second pad VDD, the second transistor Mn2 is turned on, and the The control terminal of the ESD transistor Mesd is at a low potential, that is, the substrate terminal of the ESD transistor Mesd is at a low potential, then the first parasitic diode D1 and the second parasitic diode of the ESD transistor Mesd
  • the diode D2 is reverse biased and non-conductive, so as to prevent the discharge of electric charge through the first parasitic diode D1 and ensure the normal operation of the internal circuit 20 .
  • the second pad VDD When the circuit is working normally, when the second pad VDD is powered on first, that is, when the voltage of the first pad VPP is lower than the voltage of the second pad VDD, the first transistor Mn1 is turned on, and the The control terminal of the electrostatic discharge transistor Mesd is still at a low potential, that is, the substrate terminal of the electrostatic discharge transistor Mesd is at a low potential, then the first parasitic diode D1 and the second parasitic diode D1 of the electrostatic discharge transistor Mesd The parasitic diode D2 is reverse biased and non-conductive, so as to prevent the electric charge from being discharged through the first parasitic diode D1 and the second parasitic diode D2, thus ensuring the normal operation of the internal circuit 20 .
  • the first transistor Mn1, the second transistor Mn2 and the electrostatic discharge transistor Mesd are all NMOS transistors, while in other embodiments of the present application, the first transistor, the Both the second transistor and the electrostatic discharge transistor Mesd are PMOS transistors.
  • FIG. 4 is a schematic diagram of the application of the electrostatic protection circuit according to the fifth embodiment of the present application.
  • the first transistor Mp1 , the second transistor Mp2 and the electrostatic discharge transistor Mesd are all PMOS Tube.
  • the control terminal of the first transistor Mp1 is the gate terminal of the PMOS transistor, which is electrically connected to the second pad VDD; the first terminal of the first transistor Mp1 is the source terminal of the PMOS transistor, which is is electrically connected to the first bonding pad VPP; the second terminal of the first transistor Mp1 is the drain terminal of the PMOS transistor, which is electrically connected to the control terminal and the substrate terminal of the electrostatic discharge transistor Mesd.
  • the control terminal of the second transistor Mp2 is the gate terminal of the PMOS transistor, which is electrically connected to the first pad VPP, and the first terminal of the second transistor Mp2 is the drain terminal of the PMOS transistor, which is It is electrically connected to the control terminal and the substrate terminal of the electrostatic discharge transistor Mesd; the second terminal of the second transistor Mp2 is the source terminal of the PMOS transistor, which is electrically connected to the second pad VDD.
  • the first pad VPP When the circuit is working normally, when the first pad VPP is powered on first, that is, when the voltage of the second pad VDD is lower than the voltage of the first pad VPP, the first transistor Mp1 is turned on, and the The control terminal of the electrostatic discharge transistor Mesd is at a low potential, that is, the substrate terminal of the electrostatic discharge transistor Mesd is at a low potential, and the parasitic diode of the electrostatic discharge transistor Mesd is reverse biased and non-conductive, thereby avoiding charge
  • the parasitic diode discharge of the electrostatic discharge transistor Mesd ensures the normal operation of the internal circuit 20 .
  • the second pad VDD When the circuit is working normally, when the second pad VDD is powered on first, that is, when the voltage of the first pad VPP is lower than the voltage of the second pad VDD, the second transistor Mp2 is turned on, and the The control terminal of the electrostatic discharge transistor Mesd is still at a low potential, that is, the substrate terminal of the electrostatic discharge transistor Mesd is at a low potential, then the first parasitic diode D1 and the second parasitic diode D2 are reverse biased, It is not turned on, so as to prevent the charge from being discharged through the first parasitic diode D1 or the second parasitic diode D2 and the second transistor Mp2 , and ensure the normal operation of the internal circuit 20 .
  • the electrostatic protection circuit can prevent the charge from being discharged through the parasitic diodes of the electrostatic protection circuit, thus ensuring the normal operation of the internal circuit 20 and also ensuring the electrostatic protection circuit. of normal operation.
  • the electrostatic protection circuit of the present application does not affect the performance of the semiconductor device, solves the problem of electrostatic protection between different pads, effectively ensures the reliability of the semiconductor device, and improves the competitiveness of the semiconductor device.
  • FIG. 5 is a schematic diagram of the application of the electrostatic protection circuit according to the sixth embodiment of the present application. Please refer to FIG. 5.
  • the substrate end of the electrostatic discharge transistor Mesd and the first electrode of the electrostatic discharge transistor Mesd One end has a first parasitic diode D1, the cathode of the first parasitic diode D1 is connected to the substrate end of the electrostatic discharge transistor Mesd, and the anode of the first parasitic diode D1 is connected to the electrostatic discharge transistor Mesd.
  • the first end is electrically connected.
  • the substrate end of the ESD transistor Mesd and the second end of the ESD transistor Mesd also have a second parasitic diode D2, and the cathode of the second parasitic diode D2 is connected to the ESD transistor Mesd
  • the substrate terminal of the second parasitic diode D2 is electrically connected to the second terminal of the electrostatic discharge transistor Mesd.
  • the first pad VPP When the circuit is working normally, when the first pad VPP is powered on first, that is, when the voltage of the second pad VDD is lower than the voltage of the first pad VPP, the first transistor Mp1 is turned on, and the The control terminal of the ESD transistor Mesd is at a low potential, that is, the substrate terminal of the ESD transistor Mesd is at a low potential, and the first parasitic diode D1 and the second parasitic diode of the ESD transistor Mesd D2 is reverse biased and non-conductive, so as to prevent the charge from being discharged through the first parasitic diode D1 and the second parasitic diode D2 of the electrostatic discharge transistor Mesd, and ensure the normal operation of the internal circuit 20 .
  • the second pad VDD When the circuit is working normally, when the second pad VDD is powered on first, that is, when the voltage of the first pad VPP is lower than the voltage of the second pad VDD, the second transistor Mp2 is turned on, and the The control terminal of the electrostatic discharge transistor Mesd is still at a low potential, that is, the substrate terminal of the electrostatic discharge transistor Mesd is at a low potential, then the first parasitic diode D1 and the second parasitic diode D2 are reverse biased, It is not turned on, so as to prevent the charge from being discharged through the first parasitic diode D1 or the second parasitic diode D2 and the second transistor Mp2 , and ensure the normal operation of the internal circuit 20 .
  • the present application also provides a semiconductor device, the semiconductor device includes at least two bonding pads, and the electrostatic protection circuit as described above is disposed between any two bonding pads.
  • the semiconductor device of the present application includes two pads, which are a first pad VPP and a second pad VDD, and the electrostatic protection circuit 21 is connected to the The first pad VPP is electrically connected to the second pad VDD.
  • the semiconductor device includes three bonding pads.
  • FIG. 6 is a schematic diagram of a semiconductor device according to an eighth embodiment of the present application.
  • the semiconductor device includes a first pad VPP, a second pad VDD, and a third pad VREFCA.
  • the first electrostatic protection circuit 22 is electrically connected to the first bonding pad VPP and the second bonding pad VDD
  • the second electrostatic protection circuit 23 is electrically connected to the first bonding pad VPP and the third bonding pad VREFCA
  • the third electrostatic protection circuit 24 is electrically connected to the first bonding pad VPP and the third bonding pad VREFCA.
  • the two pads VDD and the third pad VREFCA are electrically connected.
  • the structures of the first electrostatic protection circuit 22 , the second electrostatic protection circuit 23 and the third electrostatic protection circuit 24 are the same as those of the electrostatic protection circuit 21 described above, and will not be described again.
  • the first electrostatic protection circuit 22, the second electrostatic protection circuit 23 and the third electrostatic protection circuit 24 can prevent the electric charge from being discharged through the parasitic diode of the electrostatic protection circuit, thus ensuring the normal operation of the internal circuit 20, and also ensuring the normal operation of the electrostatic protection circuit, effectively improving the reliability of the semiconductor device and improving the competitiveness of semiconductor devices.
  • FIG. 7 is a schematic top view of a semiconductor structure for forming the electrostatic discharge transistor of the semiconductor device according to the ninth embodiment of the present application.
  • the semiconductor structure for forming the ESD transistor includes: a semiconductor substrate 700 , a well region 710 , a source region 720 , a drain region 730 , and a gate 740 .
  • the semiconductor substrate 700 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, SOI or GOI, or the like. According to the actual requirements of the device, a suitable semiconductor material can be selected as the semiconductor substrate 700, which is not limited herein. Wherein, several connection pads 709 are provided in the semiconductor substrate 700 .
  • the well region 710 is disposed in the semiconductor substrate 700 .
  • the ESD transistor is an NMOS transistor, and the well region is a P-type region.
  • the source regions 720 and the drain regions 730 are alternately arranged in the well region 710 .
  • the well region 710 is a P-type region
  • the source region 720 and the drain region 730 are N-type regions.
  • the gate electrode 740 is disposed on the semiconductor substrate 700 between the source region 720 and the drain region 730 , and the gate electrode 740 is electrically connected to the semiconductor substrate 700 .
  • the gate electrode 740 is electrically connected to the connection pad 709 of the semiconductor substrate 700 through the connection pad 749, so as to realize the electrical connection between the gate electrode 740 and the semiconductor substrate 700, that is, the electrostatic discharge
  • the control terminal of the discharge transistor is electrically connected to the substrate terminal.
  • the semiconductor structure includes a source region 720, a drain region 730 and a gate 740, while in other embodiments of the present application, the semiconductor structure includes a plurality of source regions 720, a plurality of Drain regions 730 and gates 740 .
  • the semiconductor structure includes a first source region 721 , a second Two source regions 722 , a first drain region 731 , a first gate 741 and a second gate 742 .
  • the first drain region 731 is located between the first source region 721 and the second source region 722
  • the first gate 741 is located between the first source region 721 and the first drain region 731
  • the second gate electrode 742 is located between the first drain region 731 and the second source region 722 .
  • the first drain region 731 is used as a common drain region.
  • connection pads 749 of the first gate 741 and the second gate 742 are electrically connected to the connection pads 709 of the semiconductor substrate 700 , so that the first gate 741 and the second gate 742 are electrically connected to the semiconductor substrate 700 .
  • the substrate 700 is electrically connected, that is, the control terminal of the electrostatic discharge transistor is electrically connected to the substrate terminal.
  • the semiconductor structure includes a plurality of source regions, a plurality of a plurality of drain regions and a plurality of gates, the plurality of source regions and the plurality of drain regions are alternately arranged at intervals, and the gate is disposed between two adjacent source regions and drain regions.
  • the semiconductor structure includes a first source region 721 , a second source region 722 , a first drain region 731 , a second drain region 732 , a first gate 741 and a first The second gate 742 and the third gate 743 .
  • the first source regions 721 , the first drain regions 731 , the second source regions 722 , and the second drain regions 732 are alternately arranged at intervals.
  • the first gate is disposed between the first source region 721 and the first drain region 731
  • the second gate 742 is disposed between the first drain region 731 and the second source region 722
  • the third gate 743 is disposed between the second source region 722 and the second drain region 732 .
  • FIG. 8 is taken as an example to illustrate the principle that the electrostatic protection circuit of the present application can prevent the discharge of charges through the parasitic diodes of the electrostatic protection circuit.
  • FIG. 10 is a schematic cross-sectional schematic diagram of the structure shown in FIG. 8 . Please refer to FIGS. 8 and 10 .
  • the first gate 741 , the second gate 742 and the semiconductor substrate 700 of the ESD transistor are short-circuited, that is, FIG. 2
  • the control terminal and the substrate terminal of the ESD transistor Mesd shown are short-circuited, and the control terminal and the substrate terminal of the ESD transistor Mesd are equipotential.
  • first parasitic diode between the semiconductor substrate 700 of the ESD transistor and the first drain region 731 , and the semiconductor substrate 700 of the ESD transistor and the first source region 721
  • second parasitic diode between the ESD protection circuit and the second source region 722.

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Abstract

本申请提供一种静电保护电路及半导体器件，静电保护电路与第一焊垫及第二焊垫电连接，包括静电泻放晶体管，用作静电放电，具有控制端、第一端、第二端及衬底端，第一端电连接至第一焊垫，第二端电连接至第二焊垫；第一晶体管，具有控制端、第一端及第二端，控制端电连接至第二焊垫，第一端电连接至第一焊垫，第二端电连接至静电泻放晶体管的控制端及衬底端；第二晶体管具有控制端、第一端及第二端，控制端电连接至第一焊垫，第一端电连接至静电泻放晶体管的控制端及衬底端，第二端电连接至所述第二焊垫。本申请在不同焊垫不同时上电的情况下，能够避免电荷经静电保护电路的寄生二极管泻放，保证了内部电路的正常运行。

Description

静电保护电路及半导体器件
相关申请引用说明
本申请要求于2021年03月10日递交的中国专利申请号202110259393.8，申请名为“静电保护电路及半导体器件”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及但不限于一种静电保护电路及半导体器件。
背景技术
随着集成电路制造技术的迅猛发展，集成电路产品的成本迅速降低，并向着多样化、普及化发展。随着集成度提高，集成电路中半导体器件越来越小，结深(junction depth)越来越浅，栅氧层的厚度也越来越薄，这些都加速了电路设计对静电保护(ESD，Electro–Static Discharge)的需求。
在集成电路中存在多个焊垫(power)。当在其中一个焊垫上产生静电时，静电电荷会流经内部电路，经由内部电路放电，从而导致内部电路被静电损伤。
为了避免内部电路被静电损伤，通常采用包含有钳位晶体管(Clamp Transistor)的钳位电路(Clamp Circuit)作为ESD保护电路的保护方案。当在其中一个焊垫上产生静电时，静电会经静电保护电路泻放，而不会流经内部电路，从而起到对内部电路的保护作用，从而防止静电进入集成电路的内部电路，导致内部电路的元件被烧毁，同时保证内部电路电压稳定。
但是，在集成电路工作时，不同焊垫会出现不同时上电的情况，这会导致焊垫直接通过静电保护电路导通，影响集成电路的正常工作。
发明内容
本申请实施例提供了一种静电保护电路，与第一焊垫及第二焊垫电连接，所述静电保护电路包括：静电泻放晶体管，用作静电放电，具有控制端、第一端、第二端及衬底端，所述第一端电连接至所述第一焊垫，所述第二端电连接至所述第二焊垫；第一晶体管，具有控制端、第一端及第二端，所述控制端电连接至所述第二焊垫，所述第一端电连接至所述第一焊垫，所述第二端电连接至静电泻放晶体管的控制端及衬底端；第二晶体管，具有控制端、第一端及第二端，所述控制端电连接至所述第一焊垫，所述第一端电连接至所述静电泻放 晶体管的控制端及衬底端，所述第二端电连接至所述第二焊垫。
本申请实施例还提供一种半导体器件，其包括至少两个焊垫，在任意两个焊垫之间设置有如上所述的静电保护电路。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A是本申请第一实施例未设置静电保护电路的电路结构示意图；
图1B是本申请第二实施例设置静电保护电路的电路结构示意图；
图2是本申请第三实施例静电保护电路应用示意图；
图3是本申请第四实施例静电保护电路应用示意图；
图4是本申请第五实施例静电保护电路应用示意图；
图5是本申请第六实施例静电保护电路应用示意图；
图6是本申请第八实施例半导体器件的示意图；
图7是本申请第九实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图；
图8是本申请第十实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图；
图9是本申请第十一实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图；
图10是图8所示结构的截面原理示意图。
具体实施方式
应当理解，以下公开内容提供了许多用于实现本申请的不同特征的不同实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本申请。当然，这些仅仅是实例，而不旨在限制本申请。例如，元件的尺寸不限于所公开的范围或值，但可以取决于工艺条件和/或器件的期望特性。此外，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部 件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，可以以不同比例任意地绘制各个部件。
在集成电路中存在多个焊垫(power)。例如，图1A是本申请第一实施例的电路结构示意图，请参阅图1A，所述电路具有两个焊垫，分别为第一焊垫VPP、第二焊垫VDD，第一焊垫VPP、第二焊垫VDD分别与内部电路10连接。当在其中一个焊垫(例如第一焊垫VPP)上产生静电时，静电电荷会流经内部电路10，经由内部电路10放电(电流方向如图中箭头所示)，从而导致内部电路10被静电损伤。
为了避免内部电路被静电损伤，采用包含有钳位晶体管(Clamp Transistor)的钳位电路(Clamp Circuit)作为ESD保护电路的保护方案。请参阅图1B，其为本申请第二实施例设置有静电保护电路的电路结构示意图，在第一焊垫VPP与第二焊垫VDD之间设置了静电保护电路11，内部电路10分别与第一焊垫VDD及第二焊垫VSS电连接，静电保护电路11也分别与第一焊垫VPP及第二焊垫VDD电连接，即所述静电保护电路11与所述内部电路10并联。当在其中一个焊垫(例如第一焊垫VPP)上产生静电时，静电会经静电保护电路11泻放，而不会流经内部电路10，从而起到对内部电路10的保护作用，从而防止静电进入集成电路的内部电路10，导致内部电路10的元件被烧毁，同时保证内部电路10电压稳定。
虽然静电保护电路11能够进行静电泻放，但是，在集成电路工作时，第一焊垫VPP和第一焊垫VDD会出现不同时上电的情况，这会导致静电保护电路11的寄生二极管导通，从而影响静电保护电路11的功能。
具体地说，请参阅图1B，所述静电保护电路11包括一NMOS管，所述NMOS管的栅极、源极、衬底短接，并连接至第二焊垫VDD，所述NMOS管的漏极连接至第一焊垫VPP。
其中，静电保护电路11存在寄生二极管D1，在集成电路工作时，第一焊垫VPP和第二焊垫VDD会出现不同时上电的情况，这会导致静电保护电路的寄生二极管D1导通，电荷经寄生二极管D1泻放，从而影响内部电路10的功能。例如，当第二焊垫VDD先上电，而第一焊垫VPP还没上电时，静电保护电路11的寄生二极管D1就会导通，电流经寄生二极管D1，从而影响内部电 路的功能。
鉴于上述原因，本申请还提供一种静电保护电路，其能够避免焊垫不同时上电而引起的焊垫之间导通的情况发生，从而避免对内部电路产生影响。
图2是本申请第三实施例静电保护电路应用示意图，请参阅图2，内部电路20分别与第一焊垫VPP及第二焊垫VDD电连接，静电保护电路21也分别与第一焊垫VPP及第二焊垫VDD电连接，即所述静电保护电路21与所述内部电路20并联。当在其中一个焊垫(例如第二焊垫VDD)上产生静电时，静电会经静电保护电路21泻放，而不会流经内部电路20，从而起到对内部电路20的保护作用，避免内部电路20受到静电损伤。
其中，在本实施例中，第一焊垫VPP为第一电源焊垫，所述第二焊垫VDD为第二电源焊垫。在本申请其他实施例中，所述第一焊垫也可为第一接地焊垫，所述第二焊垫也可为第二接地焊垫。
本申请静电保护电路21包括静电泻放晶体管Mesd、第一晶体管Mn1、及第二晶体管Mn2。
所述静电泻放晶体管Mesd用作静电放电，其具有控制端、第一端、第二端及衬底端，所述第一端电连接至所述第一焊垫VPP，所述第二端电连接至所述第二焊垫VDD。在本实施例中，所述静电泻放晶体管Mesd为NMOS管，其中，所述静电泻放晶体管Mesd的控制端为所述NMOS管的栅极端，所述静电泻放晶体管Mesd的第一端为所述NMOS管的漏极端，所述静电泻放晶体管Mesd的第二端为所述NMOS管的源极端，所述静电泻放晶体管Mesd的衬底端为所述NMOS管的衬底端。
所述第一晶体管Mn1具有控制端、第一端及第二端，所述控制端电连接至所述第二焊垫VDD，所述第一端电连接至所述第一焊垫VPP，所述第二端电连接至静电泻放晶体管Mesd的控制端及衬底端。在本实施例中，所述第一晶体管Mn1为NMOS管，其中，所述第一晶体管Mn1的控制端为所述NMOS管的栅极端，其电连接至所述第二焊垫VDD；所述第一晶体管Mn1的第一端为所述NMOS管的源极端，其电连接至所述第一焊垫VPP；所述第一晶体管Mn1的第二端为所述NMOS管的漏极端，其电连接至静电泻放晶体管Mesd的控制端及衬底端。
所述第二晶体管Mn2具有控制端、第一端及第二端，所述控制端电连接至所述第一焊垫VPP，所述第一端电连接至所述静电泻放晶体管Mesd的控制端及衬底端，所述第二端电连接至所述第二焊垫VDD。在本实施例中，所述第二晶体管Mn2为NMOS管，其中，所述第二晶体管Mn2的控制端为所述NMOS管的栅极端，其电连接至所述第一焊垫VPP；所述第二晶体管Mn2的第一端为所述NMOS管的漏极端，其电连接至所述静电泻放晶体管Mesd的控制端及衬底端；所述第二晶体管Mn2的第二端为所述NMOS管的源极端，其电连接至所述第二焊垫VDD。
在电路正常工作时，当第一焊垫VPP先上电时，即所述第一焊垫VPP的电压大于所述第二焊垫VDD的电压时，所述第二晶体管Mn2导通，所述静电泻放晶体管Mesd的控制端为低电位，即所述静电泻放晶体管Mesd的衬底端为低电位，则所述静电泻放晶体管Mesd的寄生二极管反向偏置，不导通，从而避免电荷经所述静电泻放晶体管Mesd的寄生二极管泻放，保证了内部电路20的正常运行。
在电路正常工作时，当第二焊垫VDD先上电时，即所述第一焊垫VPP的电压小于所述第二焊垫VDD的电压时，所述第一晶体管Mn1导通，所述静电泻放晶体管Mesd的控制端依然为低电位，即所述静电泻放晶体管Mesd的衬底端为低电位，则所述静电泻放晶体管Mesd的寄生二极管反向偏置，不导通，从而避免电荷经所述静电泻放晶体管Mesd的寄生二极管泻放，保证了内部电路20的正常运行。
本申请静电保护电路在不同焊垫不同时上电的情况下，能够避免电荷经静电保护电路的寄生二极管泻放，保证了内部电路20的正常运行，且也保证了静电保护电路的正常运行。本申请静电保护电路不会对半导体器件的性能产生影响，且解决了不同焊垫之间的静电保护问题，有效地保证了半导体器件的可靠性，提高了半导体器件的竞争力。
图3是本申请第四实施例静电保护电路应用示意图，请参阅图3，在本申请第四实施例中，所述静电泻放晶体管Mesd的衬底端与所述静电泻放晶体管Mesd的第一端具有第一寄生二极管D1，所述第一寄生二极管D1的正极与所述静电泻放晶体管Mesd的衬底端连接，所述第一寄生二极管D1的负极与所 述静电泻放晶体管Mesd的第一端电连接。进一步，所述静电泻放晶体管Mesd的衬底端与所述静电泻放晶体管Mesd的第二端还具有第二寄生二极管D2，所述第二寄生二极管D2的正极与所述静电泻放晶体管Mesd的衬底端连接，所述第二寄生二极管D2的负极与所述静电泻放晶体管Mesd的第二端电连接。
在电路正常工作时，当第一焊垫VPP先上电时，即所述第一焊垫VPP的电压大于所述第二焊垫VDD的电压时，所述第二晶体管Mn2导通，所述静电泻放晶体管Mesd的控制端为低电位，即所述静电泻放晶体管Mesd的衬底端为低电位，则所述静电泻放晶体管Mesd的所述第一寄生二极管D1及所述第二寄生二极管D2反向偏置，不导通，从而避免电荷经所述第一寄生二极管D1泻放，保证了内部电路20的正常运行。
在电路正常工作时，当第二焊垫VDD先上电时，即所述第一焊垫VPP的电压小于所述第二焊垫VDD的电压时，所述第一晶体管Mn1导通，所述静电泻放晶体管Mesd的控制端依然为低电位，即所述静电泻放晶体管Mesd的衬底端为低电位，则所述静电泻放晶体管Mesd的所述第一寄生二极管D1及所述第二寄生二极管D2反向偏置，不导通，从而避免电荷经所述第一寄生二极管D1及所述第二寄生二极管D2泻放，保证了内部电路20的正常运行。
当需要经过所述静电泻放晶体管Mesd进行静电泻放时，当第一焊垫VPP上产生静电电荷时，所述第一寄生二极管D1被反向击穿，所述第二寄生二极管D2正向导通，第一焊垫VPP上产生的静电电荷经所述第二寄生二极管D2泻放。当需要经过所述静电泻放晶体管Mesd进行静电泻放时，当第二焊垫VDD上产生静电电荷时，所述第二寄生二极管D2被反向击穿，所述第一寄生二极管D1正向导通，第二焊垫VDD上产生的静电电荷经所述第一寄生二极管D1泻放，进而实现焊垫上静电电荷的泻放。
在第一实施例中，所述第一晶体管Mn1、所述第二晶体管Mn2及所述静电泻放晶体管Mesd均为NMOS管，而在本申请其他实施例中，所述第一晶体管、所述第二晶体管及所述静电泻放晶体管Mesd均为PMOS管。具体地说，请参阅图4，其为本申请第五实施例静电保护电路应用示意图，在第五实施例中，第一晶体管Mp1、第二晶体管Mp2及所述静电泻放晶体管Mesd均为PMOS管。
所述第一晶体管Mp1的控制端为所述PMOS管的栅极端，其电连接至所述第二焊垫VDD；所述第一晶体管Mp1的第一端为所述PMOS管的源极端，其电连接至所述第一焊垫VPP；所述第一晶体管Mp1的第二端为所述PMOS管的漏极端，其电连接至所述静电泻放晶体管Mesd的控制端及衬底端。
所述第二晶体管Mp2的控制端为所述PMOS管的栅极端，其电连接至所述第一焊垫VPP，所述第二晶体管Mp2的第一端为所述PMOS管的漏极端，其电连接至所述静电泻放晶体管Mesd的控制端及衬底端；所述第二晶体管Mp2的第二端为所述P MOS管的源极端，其电连接至所述第二焊垫VDD。
在电路正常工作时，当第一焊垫VPP先上电时，即所述第二焊垫VDD的电压小于所述第一焊垫VPP的电压时，所述第一晶体管Mp1导通，所述静电泻放晶体管Mesd的控制端为低电位，即所述静电泻放晶体管Mesd的衬底端为低电位，所述静电泻放晶体管Mesd的寄生二极管反向偏置，不导通，从而避免电荷经所述静电泻放晶体管Mesd的寄生二极管泻放，保证了内部电路20的正常运行。
在电路正常工作时，当第二焊垫VDD先上电时，即所述第一焊垫VPP的电压小于所述第二焊垫VDD的电压时，所述第二晶体管Mp2导通，所述静电泻放晶体管Mesd的控制端依然为低电位，即所述静电泻放晶体管Mesd的衬底端为低电位，则所述第一寄生二极管D1及所述第二寄生二极管D2反向偏置，不导通，从而避免电荷经所述第一寄生二极管D1或所述第二寄生二极管D2及所述第二晶体管Mp2泻放，保证了内部电路20的正常运行。
在该实施例中，静电保护电路在不同焊垫不同时上电的情况下，能够避免电荷经静电保护电路的寄生二极管泻放，保证了内部电路20的正常运行，且也保证了静电保护电路的正常运行。本申请静电保护电路不会对半导体器件的性能产生影响，且解决了不同焊垫之间的静电保护问题，有效地保证了半导体器件的可靠性，提高了半导体器件的竞争力。
图5是本申请第六实施例静电保护电路应用示意图，请参阅图5，在本申请第四实施例中，所述静电泻放晶体管Mesd的衬底端与所述静电泻放晶体管Mesd的第一端具有第一寄生二极管D1，所述第一寄生二极管D1的负极与所述静电泻放晶体管Mesd的衬底端连接，所述第一寄生二极管D1的正极与所 述静电泻放晶体管Mesd的第一端电连接。进一步，所述静电泻放晶体管Mesd的衬底端与所述静电泻放晶体管Mesd的第二端还具有第二寄生二极管D2，所述第二寄生二极管D2的负极与所述静电泻放晶体管Mesd的衬底端连接，所述第二寄生二极管D2的正极与所述静电泻放晶体管Mesd的第二端电连接。
在电路正常工作时，当第一焊垫VPP先上电时，即所述第二焊垫VDD的电压小于所述第一焊垫VPP的电压时，所述第一晶体管Mp1导通，所述静电泻放晶体管Mesd的控制端为低电位，即所述静电泻放晶体管Mesd的衬底端为低电位，所述静电泻放晶体管Mesd的所述第一寄生二极管D1及所述第二寄生二极管D2反向偏置，不导通，从而避免电荷经所述静电泻放晶体管Mesd的所述第一寄生二极管D1及所述第二寄生二极管D2泻放，保证了内部电路20的正常运行。
在电路正常工作时，当第二焊垫VDD先上电时，即所述第一焊垫VPP的电压小于所述第二焊垫VDD的电压时，所述第二晶体管Mp2导通，所述静电泻放晶体管Mesd的控制端依然为低电位，即所述静电泻放晶体管Mesd的衬底端为低电位，则所述第一寄生二极管D1及所述第二寄生二极管D2反向偏置，不导通，从而避免电荷经所述第一寄生二极管D1或所述第二寄生二极管D2及所述第二晶体管Mp2泻放，保证了内部电路20的正常运行。
当需要经过所述静电泻放晶体管Mesd进行静电泻放时，当第一焊垫VPP上产生静电电荷时，所述第二寄生二极管D2被反向击穿，所述第一寄生二极管D1正向导通，第一焊垫VPP上产生的静电电荷经所述第一寄生二极管D1泻放。当需要经过所述静电泻放晶体管Mesd进行静电泻放时，当第二焊垫VDD上产生静电电荷时，所述第一寄生二极管D1被反向击穿，所述第二寄生二极管D2正向导通，第二焊垫VDD上产生的静电电荷经所述第二寄生二极管D2泻放，进而实现焊垫上静电电荷的泻放。
本申请还提供了半导体器件，所述半导体器件包括至少两个焊垫，在任意两个焊垫之间设置有如上所述的静电保护电路。请继续参阅图2，在本申请第七实施例提供的半导体器件中，本申请半导体器件包括两个焊垫，分别为第一焊垫VPP与第二焊垫VDD，静电保护电路21与所述第一焊垫VPP与所述第二焊垫VDD电连接。
本申请还提供一第八实施例，在所述第八实施例中，所述半导体器件包括三个焊垫。具体地说，请参阅图6，其为本申请第八实施例的半导体器件的示意图，所述半导体器件包括第一焊垫VPP、第二焊垫VDD及第三焊垫VREFCA。第一静电保护电路22与第一焊垫VPP及第二焊垫VDD电连接，第二静电保护电路23与第一焊垫VPP及第三焊垫VREFCA电连接，第三静电保护电路24与第二焊垫VDD及第三焊垫VREFCA电连接。其中，所述第一静电保护电路22、所述第二静电保护电路23及所述第三静电保护电路24与上述的静电保护电路21结构相同，不再赘述。
当所述第一焊垫VPP、所述第二焊垫VDD及所述第三焊垫VREFCA不同时上电时，所述第一静电保护电路22、所述第二静电保护电路23及所述第三静电保护电路24能够避免电荷经静电保护电路的寄生二极管泻放，保证了内部电路20的正常运行，且也保证了静电保护电路的正常运行，有效地提高了半导体器件的可靠性，提高了半导体器件的竞争力。
图7是本申请第九实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图。请参阅图7，形成所述静电泻放晶体管的半导体结构包括：半导体衬底700、阱区710、源极区720、漏极区730、栅极740。
所述半导体衬底700可以为单晶硅衬底、Ge衬底、SiGe衬底、SOI或GOI等。可根据器件的实际需求，可以选择合适的半导体材料作为所述半导体衬底700，在此不作限定。其中，在所述半导体衬底700中设置有若干个连接垫709。
所述阱区710设置于所述半导体衬底700内。在本实施例中，所述静电泻放晶体管为NMOS晶体管，则所述阱区为P型区。
源极区720与漏极区730交替间隔排布设置在所述阱区710内。在本实施例中，由于所述阱区710为P型区，则所述源极区720与漏极区730为N型区。
所述栅极740设置在所述半导体衬底700上，且位于所述源极区720与漏极区730之间，所述栅极740与所述半导体衬底700电连接。具体地说，所述栅极740通过连接垫749与所述半导体衬底700的连接垫709电连接，以实现所述栅极740与所述半导体衬底700的电连接，即所述静电泻放晶体管的控制端与衬底端电连接。
在本实施例中，所述半导体结构包括一个源极区720、一个漏极区730及一个栅极740，而在本申请其他实施例中，所述半导体结构包括多个源极区720、多个漏极区730及多个栅极740。
图8是本申请第十实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图，请参阅图8，在本实施例中，所述半导体结构包括第一源极区721、第二源极区722、第一漏极区731、第一栅极741及第二栅极742。所述第一漏极731区位于所述第一源极区721与第二源极区722之间，所述第一栅极741位于所述第一源极区721与第一漏极区731之间，所述第二栅极742位于第一漏极区731与第二源极区722之间。在该实施例中，所述第一漏极区731作为共用漏极区使用。所述第一栅极741及所述第二栅极742的连接垫749与半导体衬底700的连接垫709电连接，以使得所述第一栅极741及所述第二栅极742与半导体衬底700电连接，即所述静电泻放晶体管的控制端与衬底端电连接。
图9是本申请第十一实施例半导体器件的形成所述静电泻放晶体管的半导体结构的俯视示意图，请参阅图9，在本实施例中，所述半导体结构包括多个源极区、多个漏极区及多个栅极，所述多个源极区与多个漏极区交替间隔排布，相邻的两个源极区及漏极区之间设置有一所述栅极。
具体地说，在本实施例中，所述半导体结构包括第一源极区721、第二源极区722、第一漏极区731、第二漏极区732、第一栅极741及第二栅极742、第三栅极743。第一源极区721、第一漏极区731、第二源极区722、第二漏极区732交替间隔排布。第一栅极设置在第一源极区721与第一漏极区731之间，第二栅极742设置在第一漏极区731与第二源极区722之间，第三栅极743设置在第二源极区722与第二漏极区732之间。以理解的是，在本申请其他实施例中，也可依据上述排布规则设置多个源极区、多个漏极区及多个栅极，此处不再赘述。
下面以图8所示结构为例，说明本申请静电保护电路能够避免电荷经静电保护电路的寄生二极管泻放的原理。图10为图8所示结构的截面原理示意图，请参阅图8及图10，静电泻放晶体管的第一栅极741、第二栅极742及半导体衬底700三者短接，即图2所示的静电泻放晶体管Mesd的控制端与衬底端短 接，静电泻放晶体管Mesd的控制端与衬底端等电位。
其中，所述静电泻放晶体管的半导体衬底700与所述第一漏极区731之间具有第一寄生二极管，所述静电泻放晶体管的半导体衬底700与所述第一源极区区721及第二源极区722之间具有第二寄生二极管，当与所述静电保护电路电连接的某一焊垫(例如，图2所示的第二焊垫VDD)先上电时，由于所述静电泻放晶体管的衬底端为低电位，所述第一寄生二极管及第二寄生二极管反向偏置，不导通，则所述静电保护电路能够避免电荷经所述第一寄生二极管及第二寄生二极管泻放，保证了内部电路的正常运行，提高了半导体器件的可靠性及竞争力。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种静电保护电路，与第一焊垫及第二焊垫电连接，所述静电保护电路包括：
    静电泻放晶体管，用作静电放电，具有控制端、第一端、第二端及衬底端，所述第一端电连接至所述第一焊垫，所述第二端电连接至所述第二焊垫；
    第一晶体管，具有控制端、第一端及第二端，所述控制端电连接至所述第二焊垫，所述第一端电连接至所述第一焊垫，所述第二端电连接至静电泻放晶体管的控制端及衬底端；
    第二晶体管，具有控制端、第一端及第二端，所述控制端电连接至所述第一焊垫，所述第一端电连接至所述静电泻放晶体管的控制端及衬底端，所述第二端电连接至所述第二焊垫。
  2. 根据权利要求1所述的静电保护电路，其中，所述第一晶体管及所述第二晶体管均为NMOS管。
  3. 根据权利要求2所述的静电保护电路，其中，所述静电泻放晶体管为NMOS管。
  4. 根据权利要求2所述的静电保护电路，其中，所述第一焊垫为第一电源焊垫，所述第二焊垫为第二电源焊垫。
  5. 根据权利要求1所述的静电保护电路，其中，所述第一晶体管及所述第二晶体管均为PMOS管。
  6. 根据权利要求5所述的静电保护电路，其中，所述静电泻放晶体管为PMOS管。
  7. 根据权利要求5所述的静电保护电路，其中，所述第一焊垫为第一接地焊垫，所述第二焊垫为第二接地焊垫。
  8. 根据权利要求1所述的静电保护电路，其中，所述静电泻放晶体管的衬底端与所述静电泻放晶体管的第一端具有第一寄生二极管，所述静电泻放晶体管的衬底端与所述静电泻放晶体管的第二端具有第二寄生二极管，当所述第一焊垫的电压大于所述第二焊垫的电压时或当所述第一焊垫的电压小于所述第二焊垫的电压时，所述第一寄生二极管与所述第二寄生二极管均不导通。
  9. 根据权利要求8所述的静电保护电路，其中，当静电发生时，所述第一寄生二极管被反向击穿，所述第二寄生二极管正向导通，以泻放静电；或者，当静电发生时，所述第一寄生二极管正向击穿，所述第二寄生二极管被反向击穿，以泻放静电。
  10. 一种半导体器件，包括至少两个焊垫，在任意两个焊垫之间设置有如权利要求1所述的静电保护电路。
  11. 根据权利要求10所述的半导体器件，形成所述静电泻放晶体管的半导体结构进一步包括：
    半导体衬底；
    阱区，设置于所述半导体衬底内；
    交替间隔排布的源极区与漏极区，设置在所述阱区内；
    栅极，设置在所述半导体衬底上，且位于所述源极区与漏极区之间，所述栅极与所述半导体衬底电连接。
  12. 根据权利要求11所述的半导体器件，其中，所述阱区为P型区，所述源极区及所述漏极区为N型区。
  13. 根据权利要求11所述的半导体器件，所述半导体结构还包括第一源极区、第二源极区、第一漏极区、第一栅极及第二栅极，所述第一漏极区位于所述第一源极区与第二源极区之间，所述第一栅极位于所述第一源极区与第一漏极区之间，所述第二栅极位于第一漏极区与第二源极区之间。
  14. 根据权利要求11所述的半导体器件，所述半导体结构还包括多个源极区、多个漏极区及多个栅极，所述多个源极区与多个漏极区交替间隔排布，相邻的两个源极区及漏极区之间设置有一所述栅极。
  15. 根据权利要求11所述的半导体器件，其中，所述栅极与所述第一晶体管的第二端及第二晶体管的第一端电连接。
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