WO2022185489A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
WO2022185489A1
WO2022185489A1 PCT/JP2021/008508 JP2021008508W WO2022185489A1 WO 2022185489 A1 WO2022185489 A1 WO 2022185489A1 JP 2021008508 W JP2021008508 W JP 2021008508W WO 2022185489 A1 WO2022185489 A1 WO 2022185489A1
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WIPO (PCT)
Prior art keywords
protective film
semiconductor device
manufacturing
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/008508
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English (en)
French (fr)
Japanese (ja)
Inventor
大助 池田
省吾 祖父江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Showa Denko Materials Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko Materials Co Ltd filed Critical Showa Denko Materials Co Ltd
Priority to PCT/JP2021/008508 priority Critical patent/WO2022185489A1/ja
Priority to CN202280017443.4A priority patent/CN116941029A/zh
Priority to US18/548,351 priority patent/US20240145256A1/en
Priority to PCT/JP2022/009364 priority patent/WO2022186372A1/ja
Priority to TW111107992A priority patent/TW202240718A/zh
Priority to KR1020237029608A priority patent/KR20230151522A/ko
Priority to JP2022554851A priority patent/JP7243934B2/ja
Publication of WO2022185489A1 publication Critical patent/WO2022185489A1/ja
Priority to JP2023031123A priority patent/JP2023060871A/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates

Definitions

  • the present disclosure relates to a method of manufacturing a semiconductor device.
  • Patent Document 1 discloses a configuration of a semiconductor device using fan-out package technology and a manufacturing method thereof.
  • a redistribution layer (RDL: Re- Distribution Layer) to manufacture each semiconductor device.
  • RDL Re- Distribution Layer
  • a semiconductor chip mounted on the semiconductor device may be damaged.
  • a semiconductor device having such a semiconductor chip cannot exhibit desired performance, and the reliability as a semiconductor device may be impaired.
  • An object of the present disclosure is to provide a manufacturing method for manufacturing a highly reliable semiconductor device by preventing damage to semiconductor elements.
  • One aspect of the present disclosure relates to a method for manufacturing a semiconductor device.
  • This method of manufacturing a semiconductor device includes steps of preparing a plurality of semiconductor elements each having a first surface on which connection terminals are formed and a second surface opposite to the first surface, and preparing a supporting member.
  • a rewiring layer is formed on the first surface of the sealing body located on the first surface side of the plurality of semiconductor elements. That is, the protective film is provided on the second surface side of the semiconductor element before the step of forming the rewiring layer. In this case, it is possible to prevent the semiconductor element or the sealing material from being damaged during the formation of the rewiring layer. Thereby, a highly reliable semiconductor device can be manufactured.
  • the above manufacturing method may further include a step of removing the protective film after the step of forming the rewiring layer.
  • the final product may not include the protective film that protects the semiconductor element and the encapsulating material in the process of manufacturing the semiconductor device and is damaged instead.
  • the manufacturing method may further include a step of forming solder balls on the rewiring layer, and may further include a step of removing the protective film after the step of forming the solder balls.
  • the semiconductor element in the process of manufacturing a semiconductor device, the semiconductor element can be protected by the protective film until later steps, thereby manufacturing a more reliable semiconductor device.
  • such a protective film may be in a form that is not included in the final product.
  • the protective film may contain an epoxy resin, and the protective film may be scraped off in the step of removing the protective film.
  • an epoxy resin for the protective film it is possible to protect the semiconductor element and the encapsulating material from chemicals used in the manufacturing process, in addition to protection from impact.
  • the above manufacturing method may further comprise a step of removing the protective film and attaching another protective film to the second surface of the sealing body on which the rewiring is formed.
  • another protective film can be provided and used as it is as the protective film of the semiconductor device to be manufactured. Therefore, it is possible to manufacture a semiconductor device capable of protecting a semiconductor element even after it is manufactured as a product.
  • FIG. 1 is a cross-sectional view showing an example of a semiconductor device manufactured by a method according to an embodiment of the present disclosure.
  • 2A to 2E are diagrams showing part of the method for manufacturing the semiconductor device shown in FIG. 3(a) to 3(d) are diagrams showing the steps of the method of manufacturing the semiconductor device shown in FIG. 1, which follow the steps of FIG. 2.
  • FIG. 4(a) to 4(d) are diagrams showing the steps of the method of manufacturing the semiconductor device shown in FIG. 1, which follow the step of FIG. 3.
  • FIGS. 5A to 5D are diagrams showing the steps following the step of FIG. 4 in the method of manufacturing the semiconductor device shown in FIG.
  • FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device manufactured by the manufacturing method according to this embodiment.
  • the semiconductor device 1 is a device having a fan-out structure, for example, and includes a semiconductor element 10, a sealing material layer 11, a protective layer 12, a rewiring layer 13, and solder balls .
  • the semiconductor device 1 is manufactured, for example, by fan-out package (FO-PKG) technology, and may be manufactured by, for example, fan-out wafer level package (FO-WLP) technology, or fan-out panel level package ( FO-PLP) technology.
  • FO-PKG fan-out package
  • FO-WLP fan-out wafer level package
  • FO-PLP fan-out panel level package
  • the sealing material layer 11 is a layer in which the semiconductor element 10 is sealed with a sealing material such as resin.
  • the protective layer 12 is a cured layer arranged on the second surface 10b of the semiconductor element 10 and the surface 11a of the sealing material layer 11, and is formed by curing a BSC film 34, which will be described later.
  • the rewiring layer 13 is a layer for widening the terminal pitch of the connection terminals 10c on the first surface 10a side of the semiconductor element 10, and is composed of, for example, an insulating portion 13a such as polyimide and a wiring portion 13b such as copper wiring.
  • the solder balls 14 are connected to terminals whose terminal pitch is widened by the rewiring layer 13 , whereby the connection terminals 10 c of the semiconductor element 10 are connected to the solder balls 14 after the pitch is changed (widened).
  • FIGS. 2 to 5 are diagrams sequentially showing a method of manufacturing the semiconductor device 1.
  • FIG. 1 the method for manufacturing a semiconductor device having a fan-out structure (face up, without a support plate) is explained in order.
  • a plurality of semiconductor elements 10 each having a first surface 10a on which connection terminals 10c are formed and a second surface 10b opposite to the first surface 10a are prepared (FIGS. 1 and 2B). ).
  • a plurality of semiconductor elements 10 are collectively formed, for example, by a normal semiconductor process, and then individualized by dicing to produce each semiconductor element 10 . Since a conventional method can be used for this manufacturing process, description thereof is omitted.
  • an adhesive layer 21 is provided on a metal carrier 20, thereby supporting members 23 for supporting a plurality of semiconductor elements 10.
  • the thickness of the carrier 20 is, for example, 0.1 mm or more and 2.0 mm or less.
  • the thickness of the carrier 20 is not limited to this.
  • the carrier 20 may have a disc-shaped wafer shape when viewed from above, or may have a rectangular panel shape.
  • a release sheet for example, manufactured by Nitto Denko Co., Ltd., trade name: Rivaalpha (registered trademark) that has adhesive strength at room temperature but loses adhesive strength when heated can be used.
  • the adhesive layer 21 is made of, for example, an acrylic pressure-sensitive adhesive.
  • FIG. A plurality of semiconductor elements 10 are arranged thereon. After that, when the semiconductor element 10 is placed on the support member 22, the semiconductor element 10 is sealed with a sealing resin (sealing material) such as epoxy resin as shown in FIG. A sealing material layer 24 (sealing body) is formed. As a result, the semiconductor element 10 is entirely covered with the sealing resin and included in the sealing material layer 24 .
  • the material for encapsulating the semiconductor element 10 may be an insulating resin other than the epoxy resin.
  • the adhesive layer 21 and the like are heated to separate the adhesive layer 21 from the semiconductor element 10 and remove the carrier 20, as shown in FIG. 2(d). At this time, the second surface 10 b of the semiconductor element 10 is exposed from the sealing material layer 24 .
  • a protective film 26 is attached to the surface (second surface) of the sealing material layer 24 where the semiconductor element 10 is exposed.
  • the protective film 26 is called, for example, a backside coat (BSC) or the like, and protects the exposed surfaces of the semiconductor element 10 and the encapsulant layer 24 from chemical contamination or the application of external force in subsequent steps. It is a protective membrane.
  • This protective film is made of, for example, an epoxy resin.
  • the protective film 26 may be curable or non-curable. When the protective film 26 has curability, it may be thermosetting or energy ray-curing.
  • a non-curable protective film-forming composition containing a polymer component such as acrylic polymer, polyimide, polyamide, or silicone polymer can be used.
  • a thermosetting protective film it may contain at least a compound having a functional group that reacts with heating.
  • a thermosetting protective film-forming composition containing a monomer (reactive group-containing polymerizable monomer), a polymer of the reactive group-containing polymerizable monomer, or a thermosetting resin such as an epoxy resin or a phenol resin is used. be able to.
  • the protective film 26 when it is an energy ray-curable protective film, it may contain at least a compound having a functional group that reacts when irradiated with an energy ray.
  • a polymer of a group-containing polymerizable monomer or an energy ray-curable protective film-forming composition containing an energy ray-curable resin such as an epoxy resin can be used.
  • These protective film-forming compositions may be used alone or in combination of two or more. Furthermore, it can be used together with a substrate such as a polyimide film.
  • the sealing material layer 24 on the protective film 26 is removed from the semiconductor device 1 as shown in FIG. Polishing is performed until the connection terminal 10c is exposed to form the sealing material layer 24a.
  • the sealing material layer 24 is polished to such an extent that the connection terminals 10c arranged on the first surface 10a side of the semiconductor element 10 are exposed to the outside from the sealing resin.
  • the connection terminals 10c of the semiconductor element 10 are exposed from the surface of the polished sealing material layer 24a and can be connected.
  • the second surface 10b side of the semiconductor element 10 is covered with the protective film 26, the surface opposite to the surfaces of the semiconductor element 10 and the sealing material layer 24a (lower surface in the drawing) is prevent being hurt.
  • a rewiring layer 28 is formed on 10a.
  • the rewiring layer 28 is a portion corresponding to the rewiring layer 13 of the semiconductor device 1 described above, and is composed of an insulating layer portion 28a such as polyimide and a wiring portion 28b such as copper wiring in the insulating layer portion 28a. .
  • the formation of the insulating layer and the formation of the wiring portion are repeated a predetermined number of times to form a wiring layer for pitch conversion.
  • the semiconductor element 10 is protected by being covered with the encapsulant layer 24a and the protective film 26, so that the semiconductor element 10 is prevented from being damaged when constructing the fine rewiring layer.
  • solder balls 30 are formed so that the connection terminals 10c of the element 10 are connected to the solder balls 30. As shown in FIG. At this time, the pitch of the solder balls 30 is formed to be wider than the terminal pitch of the connection terminals 10 c of the semiconductor element 10 .
  • the solder balls 30 correspond to the solder balls 14 in the semiconductor device 1 described above.
  • a protective tape 32 (BG tape) for protecting the solder balls 30 is further attached as shown in FIG. 3(d).
  • the protective tape 32 is made of polyolefin, for example.
  • the protective film 26 is scraped off while the solder balls 30 are protected by the protective tape 32.
  • a part of the semiconductor element 10 on the side of the second surface 10b may be cut to reduce the thickness.
  • This scraping treatment can be performed, for example, using a surface grinding machine (for example, a surface grinding machine manufactured by DISCO Corporation).
  • a step of attaching a dicing tape 36 via the BSC film 34 and removing the protective tape 32 in this state is performed.
  • the BSC film 34 is made of, for example, epoxy resin.
  • laser marking is performed on the BSC film 34 with a laser beam L to write necessary information such as a product name.
  • the BSC film 34 may be an energy ray-curable protective film. It may be cured by laser or the like.
  • the BSC film 34 constitutes a part (protective layer 12) of the semiconductor device.
  • the wafer-shaped or panel-shaped die rearrangement body shown in FIG. is diced at a predetermined location S. Then, each portion including the semiconductor element 10 is separated into individual semiconductor devices 1 . As a result, the plurality of semiconductor devices 1 shown in FIGS. 5D and 1 can be obtained from the die rearrangement body in which the plurality of semiconductor elements 10 are rearranged.
  • the sealing material layer 24 located on the first surface 10a side of the plurality of semiconductor elements 10 is formed.
  • a rewiring layer 28 is formed on the first surface of (24a). That is, the protective film 26 is provided on the second surface 10b side of the semiconductor element 10 before the step of forming the rewiring layer 28.
  • FIG. Therefore, according to this method, it is possible to prevent the semiconductor element 10 and the encapsulant layer 24 from being damaged when the rewiring layer 28 is formed. Thereby, the semiconductor device 1 having excellent reliability can be manufactured.
  • the manufacturing method according to this embodiment further includes a step of removing the protective film 26 after the step of forming the rewiring layer 28 .
  • the protective film 26 that protects the semiconductor element 10 and the encapsulant layer 24 in the process of manufacturing the semiconductor device 1 and is damaged instead can be eliminated from the final product.
  • the manufacturing method according to the present embodiment further includes a step of forming the solder balls 30 on the rewiring layer 28, and further includes a step of removing the protective film 26 after the step of forming the solder balls 30.
  • the protective film 26 may contain an epoxy resin, and the protective film 26 may be scraped off in the step of removing the protective film 26 .
  • an epoxy resin for the protective film 26 it is possible to protect the semiconductor element 10 and the encapsulant layer 24 from chemicals used in the manufacturing process, in addition to protection from impact.
  • the manufacturing method according to the present embodiment includes the step of removing the protective film 26 and attaching the BSC film 34, which is another protective film, to the second surface of the sealing material layer 24a on which the rewiring layer 28 is formed. is further provided.
  • another protective film is provided after the rewiring layer 28 is formed, and the BSC film 34 can be used as it is as the protective layer 12 of the semiconductor device 1 to be manufactured. Therefore, it is possible to manufacture a semiconductor device 1 that can protect the semiconductor element 10 even after it is manufactured as a product.

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
PCT/JP2021/008508 2021-03-04 2021-03-04 半導体装置の製造方法 Ceased WO2022185489A1 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
PCT/JP2021/008508 WO2022185489A1 (ja) 2021-03-04 2021-03-04 半導体装置の製造方法
CN202280017443.4A CN116941029A (zh) 2021-03-04 2022-03-04 半导体装置的制造方法
US18/548,351 US20240145256A1 (en) 2021-03-04 2022-03-04 Method for manufacturing semiconductor device
PCT/JP2022/009364 WO2022186372A1 (ja) 2021-03-04 2022-03-04 半導体装置の製造方法
TW111107992A TW202240718A (zh) 2021-03-04 2022-03-04 半導體裝置之製造方法
KR1020237029608A KR20230151522A (ko) 2021-03-04 2022-03-04 반도체 장치의 제조 방법
JP2022554851A JP7243934B2 (ja) 2021-03-04 2022-03-04 半導体装置の製造方法
JP2023031123A JP2023060871A (ja) 2021-03-04 2023-03-01 半導体装置の製造方法

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