WO2022183649A1 - 熔丝故障修复电路 - Google Patents
熔丝故障修复电路 Download PDFInfo
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- WO2022183649A1 WO2022183649A1 PCT/CN2021/105069 CN2021105069W WO2022183649A1 WO 2022183649 A1 WO2022183649 A1 WO 2022183649A1 CN 2021105069 W CN2021105069 W CN 2021105069W WO 2022183649 A1 WO2022183649 A1 WO 2022183649A1
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- 230000015654 memory Effects 0.000 claims abstract description 24
- 238000001514 detection method Methods 0.000 claims description 20
- 238000003491 array Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 19
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
Definitions
- the present application relates to, but is not limited to, a fuse fault repair circuit.
- OTP Time Programmable
- an electronic fuse is a type of OTP.
- an electronic fuse can be an anti-fuse (Anti-fuse).
- Electronic fuses have been widely used in the use of semiconductor memories, especially in fine-tuning circuit parameters of semiconductor memories and repairing some manufacturing problems of semiconductor memories.
- the read operation of e-fuse storage is an automatic operation that cannot be customized, that is, after the design of e-fuse storage is completed, the readout sequence will also be fixed.
- An embodiment of the present application provides a fuse fault repair circuit, including:
- a fuse array the input end of the fuse array is used to connect the power supply end, the output end of the fuse array is used to output S first logic signals, wherein the fuse array includes M fuse units, Each of the fuse units correspondingly outputs a first logic signal, S and M are both integers greater than zero, and S is less than M; the M fuse units include redundant fuse arrays and non-redundant fuse arrays, and the fuse units When the fuse array is fault-free, the redundant fuse array has no signal output, and the non-redundant fuse array outputs S first logic signals;
- a signal storage module comprising at least M storage units, each of which is used to store a first logic signal sent by a connected fuse unit;
- a scanning and repairing module which is signally connected to the signal storage module, is used to scan the storage units in the signal storage module, and when a faulty storage unit is scanned, it is determined that the first fuse unit connected to the faulty storage unit is faulty , replacing the first fuse unit with a first redundant fuse unit corresponding to the first fuse unit, the first logic signal stored in the fault storage unit is a fault signal, and the first redundant fuse unit Belonging to the redundant fuse array, the first logic signal corresponding to the first redundant fuse unit is a normal signal.
- FIG. 1 is a schematic diagram of a fuse fault repair circuit provided by some embodiments of the present application.
- FIG. 2 is a schematic diagram of a fuse fault repair circuit provided by other embodiments of the present application.
- FIG. 3 is a schematic diagram of a signal storage module provided by some embodiments of the present application.
- FIG. 4 is a schematic diagram of an electrical fuse memory provided by some embodiments of the present application.
- the first fuse unit 140 The first fuse unit 140
- OTP Time Programmable
- an electronic fuse is a type of OTP.
- the electronic fuse may be an anti-fuse (Anti-fuse).
- Anti-fuse anti-fuse
- the volume of semiconductor memory is required to be continuously reduced, but the fabrication and use of electronic fuses are easily affected by the technology. Therefore, the smaller the volume of the semiconductor memory, the higher the failure rate of the electronic fuse.
- the semiconductor memory including the electronic fuse cannot be used because of the failure, which causes great waste.
- the electronic fuse type semiconductor memory includes an anti-fuse array, and the anti-fuse array further includes a non-redundant fuse array and a redundant fuse array.
- the redundant fuse array is in a standby state and is not used, while the non-redundant fuse array is in a used state. If the non-redundant fuse array fails, it will directly cause the electronic fuse array to fail. Filament semiconductor memory failed and was discarded.
- the present application provides a fuse fault repair circuit 10, which can scan out the faulty fuse units in the non-redundant fuse array in the anti-fuse array, and then use the fuses in the redundant fuse array. unit to replace a failed fuse unit. In this way, the repair of the non-redundant fuse array is realized, and the situation of discarding the entire semiconductor memory due to the failure of the non-redundant fuse array is avoided.
- the fuse fault repair circuit 10 provided in this embodiment includes a fuse array 100 , a signal storage module 200 and a scan repair module 300 .
- the input end of the fuse array 100 is used for connecting to the power supply end, and the output end of the fuse array 100 is used for outputting S first logic signals.
- the fuse array 100 includes M fuse units 110 , each of the fuse units 110 outputs a corresponding first logic signal, S and M are both integers greater than zero, and S is less than M.
- the M fuse units 110 include a redundant fuse array 120 and a non-redundant fuse array 130. When the fuse array 100 is not faulty, the redundant fuse array 120 has no signal output, and the non-redundant fuse array 130 outputs S first logic signals. .
- FIG. 2 is a schematic diagram of the fuse array 100 when the value of M is 256.
- 256 of the fuse units 100 are arranged and distributed in 16 columns and 16 rows.
- each fuse unit 110 is marked with fn_m, wherein n is used to indicate the number of columns, and m is used to indicate the number of rows.
- f0_0 represents the fuse unit 100 in the first column and the first row
- f0_15 represents the fuse unit 100 in the 16th column and 16th row
- f15_0 represents the fuse unit 100 in the 16th column and 16th row
- f15_15 represents the fuse unit 100 in the 16th column and 16th row.
- the non-redundant fuse array 130 in the 256 fuse units 100 occupies 16 rows and 8 columns of fuse units 110, and the fuse units corresponding to the non-redundant fuse array 130 are identified as f0_0, f0_1, f0_2 ...f0_15, f1_0, f1_1, f1_2...f1_15, f2_0, f2_1, f2_2...f2_15, f3_0, f3_1, f3_2...f3_15, f4_0, f4_1, f4_2...f4_15, f5_0, f5_1, f5_2...f5_15, f6_0 , f6_1, f6_2...f6_15, f7_0, f7_1, f7_2...f7_15.
- the redundant fuse array 120 occupies the remaining 16 rows and 8 columns of fuse units 110, and the fuse units corresponding to the redundant fuse array 120 are identified as f8_0, f8_1, f8_2...
- the signal storage module 200 includes at least M storage units 210, and each storage unit 210 is configured to store a first logic signal sent by the fuse unit 110 connected. When the fuse array 100 sends out S first logic signals, the signal storage module 200 correspondingly stores the S first logic signals.
- the fuse array 100 is composed of fuse cells 110 arranged in N1 rows and L1 columns, and the at least M memory cells 210 form a memory array with N2 rows and L2 columns.
- N1, L1, N2 and L2 are all integers greater than zero, and N2 is greater than or equal to N1, and L2 is greater than or equal to L1.
- the memory cells 210 in each row are respectively used to store the first logic signal output by the fuse cells 110 in one row in the fuse array.
- FIG. 1 shows a schematic diagram of storage when the fuse units 110 in the 1st row and the 16th row in the non-redundant fuse array output the first logic signal.
- the storage unit 210 of the first row receives the clock sequence broadcast ⁇ 0>, and based on the broadcast ⁇ 0> Propagating the received first logic signal backwards in sequence.
- the storage unit 210 in the 16th row receives the clock sequence broadcast ⁇ 15>, and based on broadcast ⁇ 15>, the storage unit 210 receives the clock sequence broadcast ⁇ 15>.
- the arrived first logic signals are propagated backward in sequence.
- each row of the storage unit 210 receives the corresponding clock sequence broadcast ⁇ m>, and performs the propagation and storage of the first logic signal based on the clock sequence broadcast ⁇ m>, it is also necessary to transmit and store the first logic signal according to each first logic signal.
- the carried address code is stored correspondingly.
- each of the first logic signals carries an address code
- each of the storage units 210 is provided with an address code
- the signal storage module 200 detects that the address code carried by the first logic signal and the address code of the storage unit 210 When the address codes match, the first logic signal is stored in the storage unit 210 .
- each column of the fuse units 110 has a corresponding address code WL ⁇ n>, where n is used to indicate the number of columns.
- the address code of the fuse unit 110 in the first column is WL ⁇ 0>
- the address code of the fuse unit 110 in the second column is WL ⁇ 1>
- WL ⁇ n> is specifically a four-digit code (not shown in FIG. 1 , and WL ⁇ n> is used for identification in FIG. 1 only to briefly explain that each fuse unit 110 has a corresponding address code), that is,
- Each of the fuse units 110 has a corresponding address code WL ⁇ n>.
- each of the storage units 210 has a corresponding address code WL[3:0], the address code WL[3:0] is a four-digit code, and the address code WL[3] :0] corresponds to WL ⁇ n> one-to-one.
- the address code WL[3:0] is WL[0000]
- the address code WL[3:0] is WL[0111]
- the fuse unit 110 includes a fuse 111 , a transistor 112 and an inverter 113 .
- One end of the fuse 111 is used to connect to the power terminal (VANT shown in FIG. 1 ), the source of the transistor 112 is connected to the output of the fuse 111 , and the drain of the transistor 112 is connected to the signal storage module 200
- the input terminal of the transistor 112 is connected to the gate of the transistor 112 for receiving the address code corresponding to the fuse unit 110 .
- the transistor 112 is configured to receive the output signal of the fuse 111 , and combine the output signal of the fuse 111 with the address code corresponding to the fuse unit 110 to output the first logic signal.
- the signal storage module 200 can determine the address code of the corresponding fuse unit 110 according to the first logic signal, and then store the fuse unit 110 according to the matching result of the address code of the memory unit 210 and the fuse unit 110 the outputted first logic signal.
- the input terminal of the inverter 113 is connected to the drain of the transistor 112, and the output terminal of the inverter 113 is connected to the signal storage module 200.
- the inverter 113 is used for performing signal processing on the first logic signal after signal processing. Input to the signal storage module 200 . That is, the first logic signal is generated only after the signal output by the transistor 112 undergoes signal inversion processing by the inverter 113 , and the first logic signal is then stored by the signal storage module 200 .
- the scanning and repairing module 300 is in signal connection with the signal storage module 200 .
- the scan and repair module 300 is configured to scan the storage unit 210 in the signal storage module 300, and scan the faulty storage unit 211 , it is determined that the first fuse unit 140 connected to the faulty storage unit 211 is faulty.
- the first logic signal stored in the fault storage unit 211 is a fault signal.
- the fault signal has identifiers such as 0 and 1.
- the scan and repair module 300 detects that the identifier of the first logic signal in a certain storage unit 210 is 1 , it is determined that the certain storage unit 210 is the faulty storage unit 211 .
- the storage unit 210 has a status mark Rn_m, where n represents the identifier of the column, and m represents the identifier of the row, and the status mark is used to mark the first logic signal stored in the storage unit as normal. signal or fault signal.
- the scanning and repairing module 200 is specifically configured to scan the status flag of the storage unit 210 in the signal storage module 200 , and determine whether the storage unit is the faulty storage unit 211 according to the status flag of the storage unit 210 .
- the scan and repair module 300 is further configured to receive a scan code, and scan the storage unit 210 according to the scan code, wherein the scan code includes the address code of the storage unit 210 . That is, the scan and repair module 300 does not need to scan all the storage units 210 in the signal storage module 200, but only needs to scan the corresponding storage units 210 according to the scan code, thus reducing the work of the scan and repair module 300 load.
- the scan and repair module 300 After the scan and repair module 300 determines the faulty storage unit 211 , the scan and repair module 300 replaces the first fuse unit 140 corresponding to the faulty storage unit 211 with the first fuse unit 140 corresponding to the first fuse unit 140 Redundant fuse unit 150 .
- the first redundant fuse unit 150 belongs to the redundant fuse array, and the first logic signal corresponding to the first redundant fuse unit 150 is a normal signal. That is, after the scanning and repairing module 300 determines the faulty storage unit 211, any one or a specific fuse unit in the redundant fuse array 120 in the fuse array 100 is used to replace the faulty fuse unit in the non-redundant fuse array 130 , so as to complete the repair of the non-redundant fuse array 130 of the fuse array 100 .
- the scanning and repairing module 300 includes a scanning logic 310 and a repairing logic 320
- the scanning logic 310 is used to scan the storage unit 210 in the signal storage module 200, and when the scanning logic 310 scans the fault signal, it is determined to include
- the storage unit 210 of the fault signal is the fault storage unit 211 , and sends a repair signal to the repair logic 320 .
- the repair logic 320 determines the first redundant fuse unit 150 corresponding to the first fuse unit 140 from the redundant fuse array, and shifts the first redundant fuse unit 150 to the first redundant fuse unit 150
- the location of a fuse unit 140 completes the repair of the redundant fuse array.
- the repair logic 320 may set an instruction to determine the location of the first fuse unit 140 based on the repair signal sent by the scan logic 310 .
- the scan and repair module 300 determines the row and column where the first redundant fuse unit 150 is located according to the row and column where the first fuse unit 140 is located.
- the column where the first fuse unit 140 is located and the first redundant fuse unit 150 are located are symmetrical columns, and the row where the first fuse unit 140 is located is the same as the row where the first redundant fuse unit 150 is located. For example, as shown in FIG. 1 , if the identifier of the first fuse unit 140 is f0_0, that is, the number of columns in which the first fuse unit 140 is located is 1, then the identifier of the first redundant fuse unit 150 is f15_0. The number of columns where the first redundant fuse unit 150 is located is 16.
- the identifier of the first fuse unit 140 is f2_0, that is, the number of columns in which the first fuse unit 140 is located is 3, then the identifier of the first redundant fuse unit 150 is f13_0, and at this time, the first redundant fuse unit 150 The number of columns is 14. If the identifier of the first fuse unit 140 is f3_1, that is, the number of columns in which the first fuse unit 140 is located is 4, then the identifier of the first redundant fuse unit 150 is f12_0. At this time, the first redundant fuse unit 150 The number of columns is 13.
- the fuse fault repair circuit 10 provided in this embodiment uses the scan and repair module 300 to scan the storage unit 210 in the signal storage module 200, and when the fault storage unit 211 is scanned, the first fuse unit 140 is replaced with the first redundant fuse unit 150 corresponding to the first fuse unit 140 , thereby completing the repair of the faulty non-redundant fuse array 130 . Therefore, the fuse fault repair circuit 10 provided in this embodiment can ensure that the semiconductor memory can still be used normally when the electronic fuse is faulty, thereby avoiding a lot of waste of the electronic fuse semiconductor memory.
- the M storage units 210 include redundant storage units 220 and non-redundant storage units 230 .
- the signal storage module 200 further includes a signal detection circuit 240 , the input terminal of the signal detection circuit 240 is connected to the output terminal of the fuse array 100 , and the output terminal of the signal detection circuit 100 is connected to at least M storage units 210 .
- the signal detection circuit 100 detects that the first logic signal is a redundant signal
- the signal storage module 200 stores the first logic signal in the redundant storage unit 220 .
- the signal detection circuit 100 detects that the first logic signal is a non-redundant signal
- the signal storage module 200 stores the first logic signal in the non-redundant storage unit 230 .
- the signal detection circuit 240 receives the clock sequence broadcast ⁇ m> and WL ⁇ n>, wherein broadcast ⁇ m> is used to drive signal propagation, and WL ⁇ n> is the identifier of the first logic signal.
- broadcast ⁇ m> is used to drive signal propagation
- WL ⁇ n> is the identifier of the first logic signal.
- the signal storage module 200 stores the first logic signal into the non-redundant storage unit 230 .
- the signal storage module 200 stores the first logic signal into the redundant storage unit 220 .
- the redundant fuse unit when the non-redundant fuse array 130 is faultless, the redundant fuse unit will not replace the faulty non-redundant fuse unit, and the first logic signal output by the fuse array 100 is not redundant signal.
- the signal storage module 200 when the signal storage module 200 stores the first logic signal, no signal is stored in the redundant storage unit 220 .
- the first redundant fuse unit 150 replaces the first fuse unit 140.
- among the first logic signals output by the fuse array 100 are redundant signals. logic signal.
- the signal storage module 200 when the signal storage module 200 stores the first logic signal, a signal is stored in the redundant storage unit 220 .
- the fuse fault repair circuit 10 is correspondingly provided with a redundant signal detection unit 400 , and the redundant signal detection unit 400 is connected to the output end of the redundant storage unit 220 .
- the redundant storage unit 220 stores a signal
- the redundant signal detection unit 400 outputs a fault repair signal.
- the redundant signal detection unit 400 detects the fault repair signal, it proves that the fault in the fuse array 100 is faulty.
- the redundant fuse array 130 has failed and has been replaced and repaired by the redundant fuse array 120 .
- the fault repair signal is L1 as shown in FIG. 3 .
- the first storage unit 210 in the signal storage module 200 is further configured to receive a clock driving pulse, and when the clock driving pulse is the first pulse, the first storage unit 210 cuts off adjacent ones in a row The signal of the storage unit 210 is stored. Wherein, when the signal storage module 200 stores the first logic signal, the storage units 210 in the same row store data in sequence, and the adjacent storage unit 210 is the next unit that will store the signal.
- the signal storage module 200 discriminates and stores the first logic signal according to the storage form of the redundant storage unit 220 and the non-redundant storage unit 230, that is, when the first logic signal is The first logic signal output from the non-redundant fuse array 130 is stored in the non-redundant storage unit 230 .
- the non-redundant fuse array 130 fails and is replaced and repaired by the redundant fuse array 120
- the first logic signal output by the first redundant fuse unit 150 for replacement and repair is stored in the redundant memory unit 220.
- This embodiment is further provided with a redundant signal detection unit 400 , when the redundant signal detection unit 400 detects that a signal is stored in the redundant storage unit 220 , it outputs the fault repair signal.
- the fault repair signal can be displayed on the user interface, so that the staff knows that the fuse array 100 has completed an automatic repair, which is helpful for the staff to monitor the state of the fuse array.
- an embodiment of the present application provides an electrical fuse memory 20 .
- the electrical fuse memory 20 includes the fuse fault repair circuit 10 provided in any of the above embodiments.
- the electrical fuse memory 20 may also include elements of other configurations, which are not limited in this application.
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Abstract
本申请提供一种熔丝故障修复电路，包括熔丝阵列、信号存储模块和扫描修复模块。熔丝阵列包括冗余熔丝阵列和非冗余熔丝阵列，熔丝阵列无故障时冗余熔丝阵列无信号输出，非冗余熔丝阵列输出S个第一逻辑信号。信号存储模块中每个存储单元用于存储一个连接的熔丝单元发送的第一逻辑信号。扫描修复模块用于扫描信号存储模块中的存储单元，并在扫描到故障存储单元时，确定故障存储单元连接的第一熔丝单元发生故障，将第一熔丝单元替换为与第一熔丝单元对应的第一冗余熔丝单元。其中第一冗余熔丝单元属于冗余熔丝阵列，第一冗余熔丝单元对应的第一逻辑信号为正常信号。本申请可以对故障的熔丝阵列进行修复，以提高电子熔丝半导体存储器的利用率。
Description
本申请要求于2021年3月1日提交中国专利局、申请号为202110224959.3、申请名称为“熔丝故障修复电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请涉及但不限于一种熔丝故障修复电路。
一次可编程(One Time Programmable，OTP)是半导体存储器中的一种存储器类型，电子熔丝是OTP的一种，电子熔丝例如又可以是反熔丝(Anti-fuse)。在半导体存储器的使用中，尤其是在微调半导体存储器的电路参数和修复半导体存储器的某些制造问题等情况下，电子熔丝已经被广泛采用。电子熔丝存储与其他存储技术相比，它的读取操作是一种无法自定义的自动操作，即，电子熔丝存储器在设计完成后，读出顺序也将固定。
电子熔丝的制作和使用容易被工艺影响，但随着半导体工艺的发展，要求半导体存储器的体积不断缩小，进而引发电子熔丝的故障率不断提升。如果电子熔丝发生故障，则包含该电子熔丝的半导体存储器也会因为故障不能使用，造成极大的浪费。
发明内容
本申请实施例提供一种熔丝故障修复电路，包括：
熔丝阵列，所述熔丝阵列的输入端用于连接电源端，所述熔丝阵列的输出端用于输出S个第一逻辑信号，其中，所述熔丝阵列包括M个熔丝单元，每个所述熔丝单元对应输出一个第一逻辑信号，S和M均为大于零的整数，且S小于M；所述M个熔丝单元包括冗余熔丝阵列和非冗余熔丝阵列，所述熔丝阵列无故障时所述冗余熔丝阵列无信号输出，所述非冗余熔丝阵列输出S个所述第一逻辑信号；
信号存储模块，包括至少M个存储单元，每个所述存储单元用于存储一个连接的熔丝单元发送的第一逻辑信号；
扫描修复模块，与所述信号存储模块信号连接，用于扫描所述信号存储模块中的存储单元，并在扫描到故障存储单元时，确定所述故障存储单元连接的第一熔丝单元发生故障，将所述第一熔丝单元替换为与所述第一熔丝单元对应的第一冗余熔丝单元，所述故障存储单元中存储的第一逻辑信号为故障信号，所述第一冗余熔丝单元属于所述冗余熔丝阵列，所述第一冗余熔丝单元对应的第一逻辑信号为正常信号。
图1为本申请一些实施例提供的熔丝故障修复电路的示意图；
图2为本申请另一些实施例提供的熔丝故障修复电路的示意图；
图3为本申请一些实施例提供的信号存储模块的示意图；
图4为本申请一些实施例提供的一种电性熔丝存储器的示意图。
附图标记说明：
熔丝故障修复电路 10
熔丝阵列 100
熔丝单元 110
熔丝 111
晶体管 112
反相器 113
冗余熔丝阵列 120
非冗余熔丝阵列 130
第一熔丝单元 140
第一冗余熔丝单元 150
信号存储模块 200
存储单元 210
故障存储单元 211
冗余存储单元 220
非冗余存储单元 230
信号检测电路 240
扫描修复模块 300
扫描逻辑 310
修复逻辑 320
冗余信号检测单元 400
电性熔丝存储器 20
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
一次可编程(One Time Programmable，OTP)是半导体存储器中的一种存储器类型，电子熔丝是OTP的一种，电子熔丝例如可以是反熔丝(Anti-fuse)。随着半导体工艺的发展，要求半导体存储器的体积不断缩小，但电子熔丝的制作和使用容易被工艺影响。因此半导体存储器的体积越小，电子熔丝的故障率越高。而如果电子熔丝发生故障，则包含该电子熔丝的半导体存储器也会因为故障无法使用，这就造成了极大的浪费。
电子熔丝类半导体存储器中包括反熔丝阵列，该反熔丝阵列又包括非冗余熔丝阵列和 冗余熔丝阵列。在电子熔丝类半导体存储器无故障使用时，该冗余熔丝阵列处于备用状态，不被使用，而该非冗余熔丝阵列处于使用状态，如果该非冗余熔丝阵列出现故障，则会直接导致该电子熔丝类半导体存储器出现故障而被废弃。
因此，本申请提供一种熔丝故障修复电路10，该熔丝故障修复电路10可以扫描出反熔丝阵列中非冗余熔丝阵列中出现故障的熔丝单元，再利用冗余熔丝阵列中的熔丝单元替换出现故障的熔丝单元。这样一来就实现了非冗余熔丝阵列的修复，避免了因为非冗余熔丝阵列故障而废弃整个半导体存储器的情况。
以下详细对本申请提供的该熔丝故障修复电路10的结构和运行原理进行阐述。
请参见图1，本实施例提供的该熔丝故障修复电路10包括熔丝阵列100、信号存储模块200和扫描修复模块300。
该熔丝阵列100的输入端用于连接电源端，该熔丝阵列100的输出端用于输出S个第一逻辑信号。其中，该熔丝阵列100包括M个熔丝单元110、每个该熔丝单元110对应输出一个该第一逻辑信号，S和M均为大于零的整数，且S小于M。该M个熔丝单元110包括冗余熔丝阵列120和非冗余熔丝阵列130，该熔丝阵列100无故障时该冗余熔丝阵列120无信号输出，该非冗余熔丝阵列130输出S个该第一逻辑信号。
如图2所示为M的值为256时该熔丝阵列100的示意图，在图2中，256个该熔丝单元100呈16列、16行的方式排列分布。如图2以fn_m来标记每个熔丝单元110，其中n用于表示列数的标记，m用于表示行数的标记，例如f0_0代表第1列第1行的该熔丝单元100，f0_15代表第1列第16行的该熔丝单元100，f15_0代表第16列第1行的该熔丝单元100，f15_15代表第16列第16行的该熔丝单元100。
如图2所示，假设该256个该熔丝单元100中非冗余熔丝阵列130占有16行8列个熔丝单元110，该非冗余熔丝阵列130对应的熔丝单元标识为f0_0、f0_1、f0_2……f0_15，f1_0、f1_1、f1_2……f1_15，f2_0、f2_1、f2_2……f2_15，f3_0、f3_1、f3_2……f3_15，f4_0、f4_1、f4_2……f4_15，f5_0、f5_1、f5_2……f5_15，f6_0、f6_1、f6_2……f6_15，f7_0、f7_1、f7_2……f7_15。
对应的，该256个熔丝单元100中冗余熔丝阵列120占有剩余的16行8列个熔丝单元110，该冗余熔丝阵列120对应的熔丝单元标识为f8_0、f8_1、f8_2……f8_15，f9_0、f9_1、f9_2……f9_15，f10_0、f10_1、f10_2……f10_15，f11_0、f11_1、f11_2……f11_15，f12_0、f12_1、f12_2……f12_15，f13_0、f13_1、f13_2……f13_15，f14_0、f14_1、f14_2……f14_15，f15_0、f15_1、f15_2……f15_15。
该信号存储模块200包括至少M个存储单元210，每个该存储单元210用于存储一个连接的该熔丝单元110发送的第一逻辑信号。当该熔丝阵列100发出S个第一逻辑信号时，该信号存储模块200对应得存储该S个第一逻辑信号。
在一些实施例中，该熔丝阵列100由N1行L1列熔丝单元110排列组成，该至少M个存储单元210形成一个N2行L2列的存储阵列。其中，N1、L1、N2和L2均为大于零的整数，且N2大于或等于N1，L2大于或等于L1。在对该熔丝阵列100输出的第一逻辑信号进行存储时，每行该存储单元210分别用于存储该熔丝阵列中一行熔丝单元110输出的第一逻辑信号。
具体的，请参考图2，每行该存储单元210接收对应的时钟序列broadcast<m>，并基于该时钟序列broadcast<m>将接收到的第一逻辑信号依次向后传播，其中m用于表示行数的标记。图1中示出了非冗余熔丝阵列中第1行和第16行的熔丝单元110输出第一逻辑信号时的存储示意图。在图1中，第1行的熔丝单元110输出的第一逻辑信号在存入第1行该存储单元210时，该第1行该存储单元210接收时钟序列broadcast<0>，并基于broadcast<0>将接收到的第一逻辑信号依次向后传播。第16行的熔丝单元110输出的第一逻辑信号在存入第16行该存储单元210时，该第16行该存储单元210接收时钟序列broadcast<15>，并基于broadcast<15>将接收到的第一逻辑信号依次向后传播。
更进一步的，在每行该存储单元210接收对应的时钟序列broadcast<m>，并基于该时钟序列broadcast<m>进行第一逻辑信号的传播和存储时，还需要根据每个第一逻辑信号携带的地址编码进行对应存储。具体的，每个该第一逻辑信号携带有一个地址编码，每个该存储单元210设置有一个地址编码，该信号存储模块200检测到该第一逻辑信号携带的地址编码与该存储单元210的地址编码匹配时，将该第一逻辑信号存入该存储单元210。
如图1所示，每列该熔丝单元110都有对应的地址编码WL<n>，其中n用于表示列数的标记。第1列的熔丝单元110的地址编码为WL<0>，第2列的熔丝单元110的地址编码为WL<1>，以此类推。而WL<n>具体为四位数的编码(图1中未具体示出，图1中用WL<n>进行标识只是为了简要说明每个熔丝单元110都具有对应的地址编码)，即每个该熔丝单元110都有一个对应的地址编码WL<n>。对应的，如图1所示，每个该存储单元210都有一个对应的地址编码WL[3:0]，该地址编码WL[3:0]为四位数编码，该地址编码WL[3:0]与WL<n>一一对应。例如该地址编码WL[3:0]为WL[0000]时表示读取标识为f0_0的熔丝单元110输出的第一逻辑信号，该地址编码WL[3:0]为WL[0111]时表示读取标识为f7_0的熔丝单元110输出的第一逻辑信号。
可选的，该熔丝单元110包括熔丝111、晶体管112和反相器113。该熔丝111的一端用于连接该电源端(图1中所示的VANT)，该晶体管112的源极与该熔丝111的输出端连接，该晶体管112的漏极与该信号存储模块200的输入端连接，该晶体管112的栅极用于接收与该熔丝单元110对应的地址编码。该晶体管112用于接收该熔丝111的输出信号，并将该熔丝111的输出信号和该熔丝单元110对应的地址编码结合后输出该第一逻辑信号。因此，该信号存储模块200可以根据该第一逻辑信号确定出对应的熔丝单元110的地址编码，再根据该存储单元210和该熔丝单元110的地址编码匹配结果来存储该熔丝单元110输出的该第一逻辑信号。该反相器113的输入端与该晶体管112的漏极连接，该反相器113的输出端与该信号存储模块200连接，该反相器113用于对该第一逻辑信号进行信号处理后输入至该信号存储模块200。即，该晶体管112输出的信号经过该反相器113进行信号的反相处理后才生成该第一逻辑信号，该第一逻辑信号再由该信号存储模块200进行存储。
该扫描修复模块300与该信号存储模块200信号连接。在该信号存储模块200存储完该熔丝阵列100输出的S个第一逻辑信号后，该扫描修复模块300用于扫描该信号存储模块300中的存储单元210，并在扫描到故障存储单元211时，确定该故障存储单元211连接的第一熔丝单元140发生故障。其中，该故障存储单元211中存储的第一逻辑信号为故障信号。该故障信号例如具有0、1之类的标识，以该故障信号具有的标识为1为例，当 该扫描修复模块300检测到到某个存储单元210中的第一逻辑信号具有的标识为1时，确定该某个存储单元210为该故障存储单元211。
可选的，如图2所示，该存储单元210具有状态标记Rn_m，其中n代表列的标识，m代表行的标识，该状态标记用于标记该存储单元中存储的第一逻辑信号为正常信号或者故障信号。该扫描修复模块200具体用于扫描该信号存储模块200中的存储单元210的状态标记，根据该存储单元210的状态标记确定该存储单元是否为该故障存储单元211。假设该存储单元210的状态标记为“0”代表正常，即Rn_m＝0代表正常，该存储单元210的状态标记为“1”代表故障，即Rn_m＝1代表故障，则当该扫描修复模块300扫描到某个该存储单元210的状态标记为“1”时，即Rn_m＝1时，确定该某个该存储单元210为该故障存储单元211。
可选的，该扫描修复模块300还用于接收扫描编码，并根据该扫描编码扫描该存储单元210，其中，该扫描编码中包含该存储单元210的地址编码。即，该扫描修复模块300不必要对该信号存储模块200中的全部存储单元210进行扫描，而只需要根据该扫描编码扫描对应的存储单元210,，这样就减少了该扫描修复模块300的工作负荷。
当该扫描修复模块300确定了该故障存储单元211后，该扫描修复模块300将与该故障存储单元211对应的该第一熔丝单元140替换为与该第一熔丝单元140对应的第一冗余熔丝单元150。其中，该第一冗余熔丝单元150属于该冗余熔丝阵列，该第一冗余熔丝单元150对应的第一逻辑信号为正常信号。即，该扫描修复模块300确定该故障存储单元211后，利用该熔丝阵列100中的冗余熔丝阵列120中的任意一个或特定的熔丝单元替换非冗余熔丝阵列130中出现故障的熔丝单元，从而完成该熔丝阵列100的非冗余熔丝阵列130的修复。
可选的，该扫描修复模块300包括扫描逻辑310和修复逻辑320，该扫描逻辑310用于扫描该信号存储模块200中的存储单元210，当该扫描逻辑310扫描到该故障信号时，确定包含该故障信号的存储单元210为该故障存储单元211，并发出修复信号至该修复逻辑320。该修复逻辑320在接收到该修复信号后，从该冗余熔丝阵列确定出与该第一熔丝单元140对应的该第一冗余熔丝单元150，并移位该第一冗余熔丝单元150至该第一熔丝单元140的位置，完成该冗余熔丝阵列的修复。其中，该修复逻辑320可以设定指示以基于该扫描逻辑310发出的修复信号来确定该第一熔丝单元140所在的位置。
可选的，该扫描修复模块300在确定该第一熔丝单元140所在的行和列后，根据该第一熔丝单元140所在行和列确定该第一冗余熔丝单元150所在行和列。其中，该第一熔丝单元140所在列和该第一冗余熔丝单元150所在为对称列，该第一熔丝单元140所在的行和该第一冗余熔丝单元150所在的行相同。例如图1所示，如果该第一熔丝单元140的标识为f0_0，即该第一熔丝单元140所在的列数为1，则该第一冗余熔丝单元150的标识为f15_0，此时该第一冗余熔丝单元150所在的列数为16。如果该第一熔丝单元140的标识为f2_0，即该第一熔丝单元140所在的列数为3，则该第一冗余熔丝单元150的标识为f13_0，此时该第一冗余熔丝单元150所在的列数为14。如果该第一熔丝单元140的标识为f3_1，即该第一熔丝单元140所在的列数为4，则该第一冗余熔丝单元150的标识为f12_0，此时该第一冗余熔丝单元150所在的列数为13。
综上，本实施例提供的该熔丝故障修复电路10利用该扫描修复模块300扫描该信号存储模块200中的存储单元210，并在扫描到该故障存储单元211时将该第一熔丝单元140替换为与该第一熔丝单元140对应的第一冗余熔丝单元150，由此完成故障的非冗余熔丝阵列130的修复。因此，本实施例提供的该熔丝故障修复电路10可以在电子熔丝发生故障时保障半导体存储器仍然可以正常使用，避免了电子熔丝类半导体存储器的大量浪费。
如图2和图3所示，在一些实施例中，该M个存储单元210中包括冗余存储单元220和非冗余存储单元230。该信号存储模块200还包括信号检测电路240，该信号检测电路240的输入端连接该熔丝阵列100的输出端，该信号检测电路100的输出端连接至少M个该存储单元210。当该信号检测电路100检测到该第一逻辑信号为冗余信号时，该信号存储模块200将该第一逻辑信号存储至该冗余存储单元220。当该信号检测电路100检测到该第一逻辑信号为非冗余信号时，该信号存储模块200将该第一逻辑信号存储至该非冗余存储单元230。
如图3所示，该信号检测电路240接收该时钟序列broadcast<m>和WL<n>，其中broadcast<m>用于驱动信号传播，WL<n>为该第一逻辑信号的标识。可选的，当WL<n>＝0时，表示该第一逻辑信号属于非冗余信号，则该信号存储模块200将该第一逻辑信号存入至该非冗余存储单元230。当WL<n>＝1时，表示该第一逻辑信号属于冗余信号，则该信号存储模块200将该第一逻辑信号存入至该冗余存储单元220。
需要说明的是，当该非冗余熔丝阵列130无故障的时候，不会发生冗余熔丝单元替换故障的非冗余熔丝单元的情况，此时该熔丝阵列100输出的该第一逻辑信号均属于非冗余信号。对应的，该信号存储模块200在进行该第一逻辑信号的存储时，该冗余存储单元220没有信号存入。而当该非冗余熔丝阵列130有故障的时候，该第一冗余熔丝单元150替换该第一熔丝单元140，此时该熔丝阵列100输出的该第一逻辑信号中有属于冗余信号的逻辑信号。对应的，该信号存储模块200在进行该第一逻辑信号的存储时，该冗余存储单元220中有信号存入。
可选的，该熔丝故障修复电路10对应设置有冗余信号检测单元400，该冗余信号检测单元400与该冗余存储单元220的输出端连接。当该冗余存储单元220存储有信号时，该冗余信号检测单元400输出故障修复信号，当该冗余信号检测单元400检测到该故障修复信号时，证明该熔丝阵列100中的该非冗余熔丝阵列130发生故障，且已经被该冗余熔丝阵列120替换修复。
该故障修复信号是如图3所示的L1，该冗余信号检测单元400只要检测到L1＝1，则证明该冗余存储单元220存储有该第一逻辑信号，即证明该非冗余熔丝阵列130发生故障，且已经被该冗余熔丝阵列120替换修复。
在一些实施例中，该信号存储模块200中的该第一存储单元210还用于接收时钟驱动脉冲，当该时钟驱动脉冲为第一脉冲时，该第一存储单元210截断同行中的相邻存储单元210的信号存入。其中，该信号存储模块200在存入该第一逻辑信号时，同行的存储单元210按照顺序存入数据，该相邻存储单元210为下一个即将存入信号的单元。
如图2所示，该冗余存储单元220和该非冗余存储单元230分别接收有驱动时钟WL[2:0]&CLK，如果将该第一脉冲设定为除[111]以外的其他编码，则当WL[2:0]不等于[111] 时，例如WL[2:0]＝[000]，则该驱动时钟WL[2:0]&CLK驱动该存储单元210继续向后传播该第一逻辑信号，当WL[2:0]等于[111]时，则该存储单元210停止继续向后传播该第一逻辑信号。
综上，在本实施例中，该信号存储模块200按照该冗余存储单元220和该非冗余存储单元230的存储形式对该第一逻辑信号进行鉴别存储，即当该第一逻辑信号是由该非冗余熔丝阵列130输出的，则将该第一逻辑信号存入至该非冗余存储单元230。而当该非冗余熔丝阵列130出现故障，并由该冗余熔丝阵列120进行替换修复时，用于替换修复的该第一冗余熔丝单元150输出的该第一逻辑信号存入至该冗余存储单元220。本实施例又设置有冗余信号检测单元400，当该冗余信号检测单元400检测到该冗余存储单元220中存储有信号时输出该故障修复信号。该故障修复信号可以显示在用户界面上，由此工作人员获知该熔丝阵列100已经完成一次自动修复，有利于工作人员对熔丝阵列的状态进行监控。
请参见图4，本申请的一个实施例提供一种电性熔丝存储器20，该电性熔丝存储器20包括如上任一个实施例提供的该熔丝故障修复电路10。该电性熔丝存储器20还可以包括其他配置的元件，本申请不做限定。
本领域技术人员在考虑说明书及实践这里公开的申请后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求书指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求书来限制。
Claims (12)
- 一种熔丝故障修复电路，包括：熔丝阵列，所述熔丝阵列的输入端用于连接电源端，所述熔丝阵列的输出端用于输出S个第一逻辑信号，其中，所述熔丝阵列包括M个熔丝单元，每个所述熔丝单元对应输出一个第一逻辑信号，S和M均为大于零的整数，且S小于M；所述M个熔丝单元包括冗余熔丝阵列和非冗余熔丝阵列，所述熔丝阵列无故障时所述冗余熔丝阵列无信号输出，所述非冗余熔丝阵列输出S个所述第一逻辑信号；信号存储模块，包括至少M个存储单元，每个所述存储单元用于存储一个连接的熔丝单元发送的第一逻辑信号；扫描修复模块，与所述信号存储模块信号连接，用于扫描所述信号存储模块中的存储单元，并在扫描到故障存储单元时，确定所述故障存储单元连接的第一熔丝单元发生故障，将所述第一熔丝单元替换为与所述第一熔丝单元对应的第一冗余熔丝单元，所述故障存储单元中存储的第一逻辑信号为故障信号，所述第一冗余熔丝单元属于所述冗余熔丝阵列，所述第一冗余熔丝单元对应的第一逻辑信号为正常信号。
- 根权利要求1所述的熔丝故障修复电路，其中，所述存储单元具有状态标记，所述状态标记用于标记所述存储单元中存储的第一逻辑信号为正常信号或者故障信号；所述扫描修复模块具体用于扫描所述信号存储模块中的存储单元的状态标记，根据所述存储单元的状态标记确定所述存储单元是否为所述故障存储单元。
- 根据权利要求1所述的熔丝故障修复电路，其中，所述至少M个存储单元中包括冗余存储单元和非冗余存储单元；所述信号存储模块还包括信号检测电路，所述信号检测电路的输入端连接所述熔丝阵列的输出端，所述信号检测电路的输出端连接所述至少M个存储单元；当所述第一逻辑信号为冗余信号时，将所述第一逻辑信号存储至所述冗余存储单元；当所述第一逻辑信号为非冗余信号时，将所述第一逻辑信号存储至所述非冗余存储单元。
- 根据权利要求3所述的熔丝故障修复电路，还包括：冗余信号检测单元，与所述冗余存储单元的输出端连接；当所述冗余存储单元存储有信号时，所述冗余信号检测单元输出故障修复信号。
- 根据权利要求1所述的熔丝故障修复电路，其中，所述熔丝阵列由N1行L1列熔丝单元排列组成，所述至少M个存储单元形成一个N2行L2列的存储阵列，N2大于或等于N1，L2大于或等于L1；每行存储单元分别用于存储所述熔丝阵列中一行熔丝单元输出的第一逻辑信号。
- 根据权利要求5所述的熔丝故障修复电路，其中，所述信号存储模块中的第一存储单元还用于接收时钟驱动脉冲；当所述时钟驱动脉冲为第一脉冲时，所述第一存储单元截断同行中的相邻存储单元的信号存入，同行的存储单元按照顺序存入数据，所述相邻存储单元为下一个即将存入信号的单元。
- 根据权利要求5所述的熔丝故障修复电路，其中，所述扫描修复模块在确定所述第一熔丝单元所在的行和列后，根据所述第一熔丝单元所在行和列确定所述第一冗余熔丝单元所在行和列，其中，所述第一熔丝单元所在列和所述第一冗余熔丝单元所在列为对称列，所述第一熔丝单元所在的行和所述第一冗余熔丝单元所在的行相同，其中，所述对称列表示任意两列的列数之和等于其他任意两列的列数之和。
- 根据权利要求1所述的熔丝故障修复电路，其中，每个所述第一逻辑信号携带有一个地址编码，每个所述存储单元设置有一个地址编码；所述信号存储模块检测到所述第一逻辑信号携带的地址编码与所述存储单元的地址编码匹配时，将所述第一逻辑信号存入所述存储单元。
- 根据权利要求8所述的熔丝故障修复电路，其中，所述熔丝单元包括：熔丝，一端用于连接所述电源端；晶体管，所述晶体管的源极与所述熔丝的输出端连接，所述晶体管的漏极与所述信号存储模块的输入端连接，所述晶体管的栅极用于接收与所述熔丝单元对应的地址编码；所述晶体管用于接收所述熔丝的输出信号，并将所述熔丝的输出信号和所述熔丝单元对应的地址编码结合后输出所述第一逻辑信号。
- 根据权利要求9所述的熔丝故障修复电路，还包括：反相器，所述反相器的输入端与所述晶体管的漏极连接，所述反相器的输出端与所述信号存储模块连接，所述反相器用于对所述第一逻辑信号进行信号处理后输入至所述信号存储模块。
- 根据权利要求8所述的熔丝故障修复电路，其中，所述扫描修复模块还用于接收扫描编码，并根据所述扫描编码扫描存储单元；其中，所述扫描编码中包含存储单元的地址编码。
- 一种电性熔丝存储器，包括如权利要求1-11任一项所述的熔丝故障修复电路。
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