WO2022176563A1 - 電子機器 - Google Patents

電子機器 Download PDF

Info

Publication number
WO2022176563A1
WO2022176563A1 PCT/JP2022/003199 JP2022003199W WO2022176563A1 WO 2022176563 A1 WO2022176563 A1 WO 2022176563A1 JP 2022003199 W JP2022003199 W JP 2022003199W WO 2022176563 A1 WO2022176563 A1 WO 2022176563A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
metal layer
semiconductor substrate
porous metal
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/003199
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
孝之 今東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to JP2023500684A priority Critical patent/JP7830416B2/ja
Priority to KR1020237025731A priority patent/KR20230147601A/ko
Priority to US18/264,719 priority patent/US20240113066A1/en
Priority to EP22755886.3A priority patent/EP4297071A4/en
Priority to CN202280009141.2A priority patent/CN116711056A/zh
Publication of WO2022176563A1 publication Critical patent/WO2022176563A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/0234—Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0261—Non-optical elements, e.g. laser driver components, heaters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H10W72/223—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/234—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/255—Materials of outermost layers of multilayered bumps, e.g. material of a coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01238—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in gaseous form, e.g. by CVD or PVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01265—Thermally treating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H10W72/01338—Manufacture or treatment of die-attach connectors using blanket deposition in gaseous form, e.g. by CVD or PVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01365—Thermally treating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/232—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/322—Multilayered die-attach connectors, e.g. a coating on a top surface of a core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/342—Dispositions of die-attach connectors, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/344—Dispositions of die-attach connectors, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

Definitions

  • This disclosure relates to electronic equipment.
  • Electronic equipment that flip-chip-connects electronic circuit elements onto a substrate is sealed with resin, for example, in order to prevent the penetration of cutting water used when individualizing each electronic equipment from a semiconductor wafer.
  • the electrodes of the electronic circuit element and the electrodes of the substrate are connected by gold-tin bonding, gold-silver bonding, gold-aluminum bonding, or gold-gold bonding, and the periphery of the electronic circuit element is connected to the opposing substrate. are joined and sealed by the same connection method as the inter-electrode connection (see, for example, Patent Document 1).
  • Au-Sn gold-tin
  • Au-Ag gold-silver
  • Au-Al gold-aluminum
  • Au—Au gold-gold bonding between the chip electrode of the electronic circuit element and the internal electrode of the substrate
  • the present disclosure proposes an electronic device capable of improving airtightness.
  • An electronic device includes a semiconductor substrate, a chip, bumps, and sidewalls.
  • the bumps connect a plurality of connection pads provided on opposing main surfaces of the semiconductor substrate and the chip.
  • the sidewall portion includes a porous metal layer annularly surrounding a region where the plurality of bumps are provided, and connects the semiconductor substrate and the chip.
  • FIG. 1 is a cross-sectional explanatory diagram of an electronic device according to an embodiment of the present disclosure
  • FIG. FIG. 2 is a cross-sectional explanatory view taken along line AA shown in FIG. 1
  • FIG. 4 is an explanatory view showing a process of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure
  • FIG. 4 is an explanatory view showing a process of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure
  • FIG. 4 is an explanatory view showing a process of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure
  • FIG. 4 is an explanatory view showing a process of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure
  • FIG. 4 is an explanatory view showing a process of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure
  • FIG. 4 is an explanatory view showing a process of forming bumps and sidewalls on a semiconductor substrate according
  • FIG. 4 is an explanatory diagram showing a process of forming bumps and sidewalls on a chip according to the present disclosure
  • FIG. 4 is an explanatory diagram showing a process of forming bumps and sidewalls on a chip according to the present disclosure
  • FIG. 4 is an explanatory diagram showing a process of forming bumps and sidewalls on a chip according to the present disclosure
  • FIG. 4 is an explanatory diagram showing a process of forming bumps and sidewalls on a chip according to the present disclosure
  • FIG. 1 is a cross-sectional explanatory diagram of an electronic device according to an embodiment of the present disclosure.
  • FIG. 2 is a cross-sectional explanatory view taken along line AA shown in FIG.
  • an electronic device 1 according to the present disclosure includes a semiconductor substrate 2, a chip 3, and bumps for connecting connection pads 21 and 31 provided on opposing main surfaces of the semiconductor substrate 2 and the chip 3. 4.
  • the electronic device 1 includes a porous metal layer 51 that annularly surrounds a region where the plurality of bumps 4 are provided, and a side wall portion 5 that connects the semiconductor substrate 2 and the chip 3. Prepare.
  • the electronic device 1 also has connection pads 21 between the side wall portion 5 and the semiconductor substrate 2 . Connection pads 21 provided between side wall portion 5 and semiconductor substrate 2 are not connected to circuits inside semiconductor substrate 2 .
  • the chip 3 is, for example, a semiconductor laser, and has a plurality of connection pads 31 on one main surface of a base material of GaAs (gallium arsenide). Moreover, the chip 3 includes a semiconductor laser light-emitting portion and the like inside the base material.
  • the light emitting unit includes a plurality of two-dimensionally arranged light emitting elements that emit laser light. The light emitting elements are connected to connection pads 31 within the chip 3 .
  • the electronic component included in the chip 3 may be any electronic component other than the light emitting section of the semiconductor laser.
  • the base material of the chip 3 may be, for example, a semi-insulating base material such as InP (indium phosphide).
  • the semiconductor substrate 2 is, for example, a Si (silicon) substrate, and includes a driving circuit for driving a semiconductor laser inside.
  • the semiconductor substrate 2 has a plurality of connection pads 21 on one main surface.
  • the connection pads 21 are connected to a drive circuit inside the semiconductor substrate 2 .
  • the electronic circuit provided on the semiconductor substrate 2 may be any electronic circuit other than the driving circuit of the semiconductor laser.
  • a chip 3 is flip-chip mounted on a semiconductor substrate 2, and a driving circuit in the semiconductor substrate 2 and the chip 3, which is a semiconductor laser, are electrically connected by bumps 4. Further, in the electronic device 1 , the side wall portion 5 seals and seals the space in which the connection pads 21 and 31 and the bumps 4 are provided.
  • the chip 3 is stacked on each drive circuit via bulk metal bumps, and the connection pads 21 and 31 provided on the opposing main surfaces of the drive circuit and the chip 3 are connected by the bumps. Then, the Si wafer is diced into pieces for each electronic device.
  • connection pads 21 and 31 provided on the opposing main surfaces of the semiconductor substrate 2 and the chip 3 are connected by bumps, and the connection pads 21 and 31 that need to be sealed and the area where the bumps are provided are connected to the connection pads 21 .
  • the thermal expansion coefficients of the semiconductor substrate 2 and the chip 3 differ by, for example, 0.1 ppm/° C. or more, the following problems occur when bulk Au, Cu, solder, or the like is used as the bump material. a problem arises.
  • the semiconductor substrate 2 is heated to a high temperature of 300° C. or higher. and the chip 3, a high pressure of 100 MPa or more must be applied.
  • solder when solder is used as a bump material, it is possible to make connections with bumps at low temperature and low pressure compared to Au and Cu, but solder is inferior to Au and Cu in heat resistance and connection strength. Therefore, when the chip 3 thermally expands due to heat generated by an electronic component such as a semiconductor laser mounted on the chip 3, the bumps made of solder may cause an open failure due to the difference in coefficient of thermal expansion between the semiconductor substrate 2 and the chip 3. may occur and reduce the reliability of electronic equipment.
  • the semiconductor substrate 2 according to the present disclosure is a Si substrate and has a thermal expansion coefficient of 5.7 ppm/°C.
  • the base material of the chip 3 according to the present disclosure is GaAs and has a coefficient of thermal expansion of 2.6 ppm/°C.
  • the difference in coefficient of thermal expansion between the semiconductor substrate 2 and the chip 3 is much larger than 0.1 ppm/°C. Therefore, if the material of the bumps is bulk Au, Cu, or solder, the electronic device 1 may suffer from the above-described problems and be degraded in reliability.
  • the semiconductor substrate 2 and the chip 3 are sealed. If the coefficient of thermal expansion differs, for example, by 0.1 ppm/° C. or more, cracks will occur in the sealing portion. This reduces the airtightness of the electronic device.
  • the semiconductor substrate 2 or the chip 3 has unevenness in thickness or warps, when the semiconductor substrate 2 and the chip 3 are laminated, the semiconductor substrate 2 and the chip can only be bent by the protrusion of the plated film at the sealing portion. 3 cannot be joined.
  • the bump 4 of the electronic device 1 includes a porous metal layer 41 of Au, for example.
  • the porous metal layer 41 contains Au particles with a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m and a purity of 99.9% by weight or more.
  • the component of the porous metal layer 41 may be, for example, Cu, Ag (silver), or Pt (platinum) with a purity of 99.9% by weight or more.
  • the porous metal layer 41 containing metal particles with a particle size of 0.005 ⁇ m to 1.0 ⁇ m allows metal bonding at a temperature lower than the melting point of bulk metal due to the size effect of the particle size.
  • the porous metal layer 41 can connect the semiconductor substrate 2 and the chip 3 at a temperature of about 100° C. when the component is Au, about 250° C. when the component is Ag, and about 150° C. when the component is Cu. .
  • the electronic device 1 can reduce damage to the chip 3 due to heat, and thus can improve reliability.
  • the porous metal layer 41 has elasticity, even if the chip 3 expands with a thermal expansion coefficient different from that of the semiconductor substrate 2 due to heat generated by the semiconductor laser, for example, the porous metal layer 41 elastically deforms, thereby suppressing the occurrence of an open failure. be able to. Thereby, the reliability of the electronic device 1 can be improved as compared with, for example, the case where solder bumps are used.
  • Such an electronic device 1 stacks the chip 3 on the semiconductor substrate 2 having the bumps 4 on the upper surface thereof, and connects the porous metal layer 41 of the bumps 4 to the connection pads 31 without melting the chip 3 on the semiconductor substrate 2 . are manufactured by flip chip mounting.
  • the electronic device 1 stacks the chip 3 having the bumps 4 including the porous metal layer 41 on the bottom surface on the semiconductor substrate 2 and connects the bumps 4 to the connection pads 21 without melting the porous metal layer 41 .
  • the chip 3 may be manufactured by flip-chip mounting the chip 3 on the semiconductor substrate 2 .
  • the bumps 4 including the porous metal layer 41 may be provided on both the semiconductor substrate 2 and the chip 3 before lamination.
  • the metal film 42 is provided between the porous metal layer 41 and the connection pad 21 on the semiconductor substrate 2 side. Moreover, when the bumps 4 are provided on the chip 3 side, the metal films 42 are provided between the porous metal layers 41 and the connection pads 31 on the chip 3 side. The metal film 42 is formed between the porous metal layer 41 and the connection pads 21 on the semiconductor substrate 2 side and between the porous metal layer 41 and the connection pads 31 on the chip 3 side, at least either one of them. may be provided.
  • the pitch of the bumps 4 is fine pitched to 20 ⁇ m or less. made possible. Such fine pitching will be described later together with the process of forming the bumps 4 .
  • the bump 4 also has a metal film 42 on the side surface (side peripheral surface) of the porous metal layer 41 .
  • the material of the metal film 42 is desirably the same as that of the porous metal layer 41 .
  • the metal film 42 is preferably an Au film.
  • the bumps 4 can prevent the adjacent bumps 4 from short-circuiting due to scattering of the particles of the porous metal layer 41 .
  • the metal film 42 is not provided on the side surface of the porous metal layer 41 , the side surface of the porous metal layer 41 having a relatively soft surface is roughened, and the shape of the bumps 4 varies.
  • the bumps 4 are provided with the metal film 42 harder than the porous metal layer 41 on the side surface of the porous metal layer 41, variations in shape between the bumps 4 are suppressed, and all the bumps 4 have a uniform shape. Become. Moreover, since the side surfaces of the bumps 4 are coated with the relatively hard metal film 42, it is possible to further miniaturize the bumps and to achieve a finer pitch.
  • the bumps 4 are slightly crushed in the thickness direction, but the particles of the porous metal layer 41 leak out of the metal film 42. prevent spitting. As a result, the bump 4 has an increased particle density of the porous metal layer 41 inside the metal film 42 , so that connection resistance can be reduced.
  • the side wall portion 5 of the electronic device 1 has a structure similar to that of the bumps 4 .
  • the sidewall 5 includes a porous metal layer 51 of Au.
  • the porous metal layer 51 contains Au particles with a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m and a purity of 99.9% by weight or more.
  • the component of the porous metal layer 51 may be, for example, Cu, Ag (silver), or Pt (platinum) with a purity of 99.9% by weight or more.
  • the porous metal layer 51 is capable of metal bonding at a temperature lower than the melting point of the bulk metal due to the size effect of the particle size as described above. As a result, the electronic device 1 can reduce damage to the chip 3 due to heat during the formation of the porous metal layer 51, thereby improving reliability.
  • the porous metal layer 51 has elasticity, even if the chip 3 expands with a thermal expansion coefficient different from that of the semiconductor substrate 2 due to the heat generated by the semiconductor laser, for example, the porous metal layer 51 is elastically deformed. can be suppressed. As a result, the electronic device 1 can improve the airtightness of the areas where the connection pads 21 and 31 and the bumps 4 that need to be sealed are provided.
  • the porous metal layer 51 is elastically deformable, even if the semiconductor substrate 2 or the chip 3 is uneven in thickness or warped, for example, when the semiconductor substrate 2 and the chip 3 are bonded, the semiconductor substrate 2 and the chip 3 are not deformed. It deforms following the surface shape of the substrate 2 and the chip 3 .
  • the electronic device 1 can suppress the formation of gaps in the connecting portion between the side wall portion 5 and the semiconductor substrate 2 and the connecting portion between the side wall portion 5 and the chip 3, thereby improving airtightness. can be done.
  • the side wall portion 5 is provided so as to annularly surround the region where the connection pads 21 and 31 requiring sealing and the bumps 4 are provided.
  • the electronic device 1 can relieve mechanical stress applied to the bumps 4 provided at the corners when the semiconductor substrate 2 or the chip 3 thermally expands.
  • the electronic device 1 since the peripheral portions of the semiconductor substrate 2 and the chip 3 are sealed by the side wall portion 5, expansion and contraction of the peripheral portions of the semiconductor substrate 2 and the chip 3 due to temperature changes are prevented by the side wall portion 5. can be suppressed by As a result, the electronic device 1 can relieve mechanical stress applied to the bumps 4 provided at the corners.
  • the metal film 52 is provided between the porous metal layer 51 and the connection pad 21 on the main surface of the semiconductor substrate 2 . Moreover, when the side wall portion 5 is provided on the chip 3 side, the metal film 52 is provided between the porous metal layer 51 and the connection pads on the main surface of the chip 3 . The metal film 52 is formed between the porous metal layer 51 and the connection pads 21 on the main surface of the semiconductor substrate 2 and between the porous metal layer 51 and the connection pads on the main surface of the chip 3 . It may be provided on either side.
  • the pitch of the bumps 4 can be made finer to 20 ⁇ m or less.
  • the side wall portion 5 also includes a metal film 52 on the side surface (side peripheral surface) of the porous metal layer 51 .
  • the material of the metal film 52 is desirably the same as that of the porous metal layer 51 .
  • the metal film 52 is preferably an Au film.
  • the side wall portion 5 can prevent the adjacent bumps 4 from short-circuiting due to scattering of the particles of the porous metal layer 51 .
  • the side surface of the porous metal layer 51 having a relatively soft surface is roughened, and the side surface shape of the side wall portion 5 varies.
  • the side wall portion 5 since the metal film 52 harder than the porous metal layer 51 is provided on the side surface of the porous metal layer 51, variations in the side surface shape are suppressed, and the entire side surface has a uniform surface shape. become. Moreover, since the sidewalls 5 are coated with the relatively hard metal film 52, further miniaturization is possible.
  • Such an electronic device 1 laminates a chip 3 having no bumps 4a (see FIG. 10) on a semiconductor substrate 2 having bumps 4 on its upper surface, and the porous metal layer 41 of the bumps 4 is not melted. It is manufactured by flip-chip mounting the chip 3 on the semiconductor substrate 2 by connecting it to the connection pads 31 .
  • the electronic device 1 stacks the chip 3 provided with the bumps 4a (see FIG. 10) including the porous metal layer 41 on the lower surface on the semiconductor substrate 2 not provided with the bumps 4, and the porous metal of the bumps 4a. It may be manufactured by flip-chip mounting the chip 3 to the semiconductor substrate 2 by connecting the connection pads 21 without melting the layer 41 .
  • the bumps 4 and 4a including the porous metal layer 41 may be provided on both the semiconductor substrate 2 and the chip 3 before lamination.
  • FIG. 3 to 6 are explanatory views showing steps of forming bumps and sidewalls on a semiconductor substrate according to the present disclosure.
  • 7 to 10 are explanatory views showing steps of forming bumps and sidewalls on a chip according to the present disclosure.
  • connection pads 21 provided on the semiconductor substrate 2 at positions where the bumps 4 are to be formed later.
  • a membrane 22 is formed.
  • the upper surface of the connection pad 21 provided at the position where the side wall portion 5 is formed later that is, the position annularly surrounding the region where the bump 4 is formed later on the main surface of the semiconductor substrate 2 is provided.
  • a metal film 32 is also formed on the upper surface of the connection pad 21 .
  • a metal having the same composition as the metal film 64 (see FIG. 4) to be laminated later is selected.
  • the metal film 22 of Au is formed.
  • a photoresist layer 61 is formed on the surface of the semiconductor substrate 2 on which the connection pads 21 and the metal film 22 are provided. Thereafter, through holes 62 are formed in the photoresist layer 61 at positions where the bumps 4 are to be formed by photolithography, and the surface of the metal film 22 is exposed. At the same time, a groove 63 is formed at the position where the side wall portion 5 is to be formed, and the surface of the metal film 22 is exposed.
  • the through-holes 62 are formed so that the center-to-center spacing between adjacent through-holes 62 is 20 ⁇ m (20 ⁇ m pitch).
  • the through-holes 62 are filled with the paste 50 containing metal particles that will be the material of the porous metal layer 41 in a later step. Then, the fine structure may be damaged and collapse.
  • a metal film 64 is formed on the upper surface of the photoresist layer 61, the side surfaces of the through holes 62, the side surfaces of the grooves 63, and the upper surface of the metal film 22 by, for example, sputtering.
  • a metal having the same composition as the metal particles contained in the paste 50 that fills the through holes 62 later is selected.
  • a metal film 64 of Au is formed.
  • the photoresist layer 61 is hardened by being coated with the metal film 64 on the surface, so that when the through-hole 62 is filled with the paste 50 containing metal particles, the fine structure is prevented from collapsing. be able to.
  • the thickness of the metal film 64 formed here is too thick, the opening of the through hole 62 becomes narrow, making it difficult to fill the through hole 62 with the paste 50 containing the metal particles. Therefore, here, the thickness of the metal film 64 with respect to the depth D1 of the through hole 62, in other words, the thickness of the bump 4 formed later in the direction perpendicular to the main surface of the semiconductor substrate 2 (height D1 of the bump 4).
  • a thin (for example, less than 1 ⁇ m thick) metal film 64 is formed so that the ratio of the film thickness d1 is less than 10%.
  • the film thickness of the metal film 64 is set to 0.2 ⁇ m. As a result, even if the metal film 64 is formed, the opening of the through hole 62 can be prevented from being narrowed, so that the through hole 62 can be sufficiently filled with the paste 50 containing the metal particles in a later step. .
  • the thickness of the metal film 64 with respect to the depth D2 of the groove 63 in other words, the thickness of the side wall portion 5 to be formed later in the direction perpendicular to the main surface of the semiconductor substrate 2 (height D2 of the side wall portion 5).
  • the ratio of thickness d1 is less than 10%.
  • Au particles having a purity of 99.9% by weight or more and a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m are placed in the through holes 62 and the grooves 63 formed in the photoresist layer 61.
  • any method such as screen printing or spreading the dropped paste 50 with a spatula can be used.
  • the photoresist layer 61 is removed by lift-off using a remover or the like.
  • the Au metal film 22, the Au metal film 42, and the porous metal layer containing Au particles having a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m are formed on the surface of the connection pad 21. 41 are successively laminated to complete the bump 4 in which the Au metal film 42 is also formed on the side surface of the porous metal layer 41 .
  • an Au metal film 22, an Au metal film 52, and a porous metal layer 51 containing Au particles with a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m are formed so as to surround the region where the bumps 4 are formed.
  • the layers are successively laminated to complete the side wall portion 5 in which the metal film 52 of Au is also formed on the side surface of the porous metal layer 51 .
  • the bump 4 includes the metal film 42 having a film thickness ratio of less than 10% with respect to the height D1 of the bump 4 between the metal film 22 on the connection pad 21 and the porous metal layer 41 . Furthermore, the bump 4 is provided with a metal film 42 also on the side surface of the porous metal layer 41 .
  • the side wall portion 5 includes a metal film 52 having a film thickness ratio of less than 10% with respect to the height D2 of the side wall portion 5 between the metal film 22 on the connection pad 21 and the porous metal layer 51 . Furthermore, the side wall portion 5 is provided with the metal film 52 also on the side surface of the porous metal layer 51 .
  • the metal films 42 and 52 are formed on the upper surface of the photoresist layer 61 and through holes formed in the photoresist layer 61 in order to prevent collapse of the fine structures of the bumps 4 and the sidewall portions 5 patterned on the photoresist layer 61 . It is formed on the side surfaces of the holes 62 and grooves 63 and on the surface of the metal film 22 . As a result, the bumps 4 can have a fine pitch of 20 ⁇ m or less.
  • connection pad 21 since the metal film 22 is formed on the surface of the connection pad 21 by sputtering, even if the connection pad 21 is made of metal with a different component from the metal film 22, it is strongly bonded to the connection pad 21.
  • the metal films 42 and 52 may be formed of a metal having a different composition from the porous metal layers 41 and 51. However, when they are formed of Au having the same composition, the porous metal layers 41 and 51 have the same composition as the porous metal layers 41 and 51. are bonded to the metal films 42 and 52 with stronger bonding strength than when they are provided on other metal films different from each other.
  • the porous metal layers 41 and 51 are composed of a component other than Au (for example, Cu, Ag (silver) or Pt (platinum)
  • the metal films 42 and 52 are also made of the same metal as the porous metal layers 41 and 51 (for example, , Cu, Ag (silver) or Pt (platinum)) can be used.
  • a metal film is formed on the upper surface of the connection pads 31 provided on the chip 3 at positions where the bumps 4a are to be formed later. 32 is formed.
  • the upper surface of the connection pad 31 provided at the position where the side wall portion 5a is formed later that is, the connection provided at the position annularly surrounding the region on the main surface of the chip 3 where the bump 4a is formed later.
  • a metal film 32 is also formed on the upper surface of the pad 31 .
  • the material of the metal film 32 As the material of the metal film 32, a metal having the same composition as the metal film 74 (see FIG. 8) to be laminated later is selected. Here, a metal film 32 of Au is formed. The connection pads 31 provided at positions where the side wall portions 5a are to be formed later are not connected to circuits inside the chip 3 .
  • a photoresist layer 71 is formed on the surface of the chip 3 on which the connection pads 31 and the metal film 32 are provided. Thereafter, through holes 72 are formed in the photoresist layer 71 at positions where the bumps 4a are to be formed by photolithography, and the surface of the metal film 32 is exposed. At the same time, a groove 73 is formed at the position where the side wall portion 5a is to be formed, and the surface of the metal film 32 is exposed.
  • a metal film 74 is formed on the upper surface of the photoresist layer 71, the side surfaces of the through holes 72, the side surfaces of the grooves 73, and the upper surface of the metal film 32 by, for example, sputtering.
  • Au having the same composition as the Au particles contained in the paste 50 that fills the through holes 72 later is selected.
  • the photoresist layer 71 is hardened by being coated with the metal film 43 on the surface, so that when the through holes 72 are filled with the paste 50 containing Au particles, the fine structure is prevented from collapsing. be able to.
  • the thickness of the metal film 74 with respect to the depth D1 of the through hole 72 in other words, the thickness of the bump 4a to be formed later in the direction perpendicular to the main surface of the chip 3 (height D1 of the bump 4a)
  • a thin (for example, less than 1 ⁇ m thick) metal film 74 having a thickness d1 ratio of less than 10% is formed.
  • the film thickness of the metal film 74 is set to 0.2 ⁇ m. As a result, even if the metal film 74 is formed, the opening of the through hole 72 can be prevented from being narrowed, so that the through hole 72 can be sufficiently filled with the paste 50 containing the metal particles in a later step. .
  • the depth D2 of the groove 73 in other words, the thickness of the metal film 74 with respect to the thickness of the side wall 5a to be formed later in the direction perpendicular to the main surface of the chip 3 (height D2 of the side wall 5a)
  • the ratio of d1 becomes less than 10%.
  • Au particles having a purity of 99.9% by weight or more and a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m are placed in the through holes 72 and the grooves 73 formed in the photoresist layer 71. Fill the paste 50 containing.
  • the photoresist layer 71 is removed by lift-off using a remover or the like.
  • the Au metal film 32, the Au metal film 42, and the porous metal layer containing Au particles having a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m are formed on the surface of the connection pad 31. 41 are successively laminated to complete the bump 4a in which the metal film 42 of Au is also formed on the side surface of the porous metal layer 41.
  • an Au metal film 32, an Au metal film 52, and a porous metal layer 51 containing Au particles with a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m are formed so as to surround the region where the bumps 4a are formed.
  • Side wall portions 5a are completed in which metal films 52 of Au are also formed on the side surfaces of the porous metal layers 51 by sequentially stacking the layers.
  • the bump 4a includes the metal film 42 having a film thickness ratio of less than 10% with respect to the height D1 of the bump 4a between the metal film 22 on the connection pad 31 and the porous metal layer 41. Furthermore, the metal film 42 is also provided on the side surface of the porous metal layer 41 of the bump 4a.
  • the side wall portion 5a includes a metal film 52 having a film thickness ratio of less than 10% with respect to the height D2 of the side wall portion 5a between the metal film 32 on the connection pad 31 and the porous metal layer 51. Further, the metal film 52 is also provided on the side surface of the porous metal layer 51 of the side wall portion 5a.
  • the metal films 42 and 52 are formed on the upper surface of the photoresist layer 71 and through holes formed in the photoresist layer 71 in order to prevent collapse of the fine structures of the bumps 4a and the side wall portions 5a patterned on the photoresist layer 71. It is formed on the side surfaces of the holes 72 and grooves 73 and on the surface of the metal film 22 . As a result, the bumps 4a can have a fine pitch of 20 ⁇ m or less, like the bumps 4 on the semiconductor substrate 2 side.
  • the semiconductor substrate 2 provided with the bumps 4 and the sidewalls 5 is mounted with the chip 3 without the bumps 4a and the sidewalls 5a.
  • the chip 3 provided with the bumps 4a and the side wall portions 5a is mounted on the semiconductor substrate 2 without the semiconductor substrate 2 has been described, this is only an example.
  • the electronic device may have a configuration in which the chip 3 provided with the bumps 4a and the sidewalls 5a is mounted on the semiconductor substrate 2 provided with the bumps 4a and the sidewalls 5a.
  • the metal films 42 and 52 have a film thickness ratio of less than 10% to half of the thickness of the bumps 4 and 4a and the side wall portions 5 and 5a in the direction orthogonal to the main surfaces of the semiconductor substrate 2 and the chip 3. , preferably less than 5%.
  • the base material of the chip 3 is a base material other than Si has been described. It may be doped with impurities.
  • the chip 3 including the light emitting portion of the semiconductor laser and the semiconductor substrate 2 including the driving circuit of the semiconductor laser described above are mounted on a distance measuring device such as a ToF sensor or structured light, for example.
  • a distance measuring device such as a ToF sensor or structured light
  • the light emitting section of the semiconductor laser functions, for example, as a light source for a ToF sensor or a light source for structured light.
  • the electronic device 1 has a semiconductor substrate 2 , a chip 3 , bumps 4 and side walls 5 .
  • Bumps 4 connect a plurality of connection pads 21 and 31 provided on the main surfaces of semiconductor substrate 2 and chip 3 facing each other.
  • the sidewall portion 5 includes a porous metal layer 51 that annularly surrounds a region where the bumps 4 are provided, and connects the semiconductor substrate 2 and the chip 3 . Thereby, the electronic device 1 can improve airtightness.
  • the coefficient of thermal expansion of the chip 3 differs from that of the semiconductor substrate 2 by 0.1 ppm/°C or more.
  • the electronic device 1 can elastically deform the porous metal layer 51 of the side wall portion 5 . It is possible to suppress the occurrence of cracks and gaps.
  • the side wall portion 5 elastically deforms following the shape of the chip 3 or the semiconductor substrate 2, so airtightness can be improved.
  • the chip 3 is a semiconductor laser.
  • the semiconductor substrate 2 has a drive circuit that drives the semiconductor laser.
  • the porous metal layer 51 contains metal particles with a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m. Such a porous metal layer 51 enables metal bonding at a temperature lower than the melting point of bulk metal due to the size effect of the metal particles. As a result, in the electronic device 1, the semiconductor substrate 2 and the chip 3 are connected by the porous metal layer 51 capable of metal bonding at a relatively low temperature in the peripheral edge portion of the region where the connection pads 21 and 31 and the bumps 4 are provided. Therefore, airtightness can be improved by reducing heat damage.
  • the sidewall portion 5 is located between the porous metal layer 51 and the connection pads 21 provided on the semiconductor substrate 2 and between the porous metal layer 51 and the connection pads 31 provided on the chip 3, at least any of them. It has a metal film 52 provided on one side and the side surface of the porous metal layer 51 . As a result, the electronic device 1 can improve airtightness by preventing collapse of the porous metal layer 51 with the metal film 52 provided on the side surface of the porous metal layer 51 .
  • At least one of the Metal film 52 has a film thickness ratio of less than 10% with respect to the thickness in the direction orthogonal to the main surfaces of side wall portions 5 and 5a.
  • the grooves 63 and 73 for forming sidewall portions 5 and 5a patterned in photoresist layers 61 and 71 can be prevented from being narrowed by formation of metal film 52.
  • the grooves 63 and 73 patterned in the photoresist layers 61 and 71 can be appropriately filled with the paste 50 containing metal particles as the material of the sidewall portions 5 and 5a.
  • At least one of the Metal film 52 has a film thickness ratio of less than 10% to half of the thickness in the direction perpendicular to the main surface of side wall portions 5 and 5a.
  • the bumps 4 and 4a have a porous metal layer 41 and a metal film 42.
  • the porous metal layer 41 is made of the same material as the porous metal layer 51 of the side walls 5, 5a.
  • the metal film 42 is formed between the porous metal layer 41 and the connection pads 21 provided on the semiconductor substrate 2 and between the porous metal layer 41 and the connection pads 31 provided on the chip 3 . It is provided on one side and the side surface of the porous metal layer 41 .
  • the bumps 4, 4a and the side walls 5, 5a can be formed at the same time. Therefore, by forming the side walls 5, 5a, the semiconductor substrate 2 and the chip can be formed without adding a new step for joint sealing. 3 can be jointed and sealed.
  • the metal film 42 provided between the porous metal layer 41 and the connection pads 21 and 31 has a film thickness ratio of less than 10% with respect to the thickness of the bumps 4 and 4a in the direction perpendicular to the main surface of the semiconductor substrate 2. be.
  • This can prevent the through holes 62 and 72 for forming the bumps 4 and 4a patterned in the photoresist layers 61 and 71 from becoming narrow due to the formation of the metal film 42 .
  • the through-holes 62 and 72 patterned in the photoresist layers 61 and 71 can be appropriately filled with the paste 50 containing the metal particles as the material of the bumps 4 and 4a.
  • the metal film 42 provided between the porous metal layer 41 and the connection pads 21 and 31 has a film thickness ratio of 10% to half of the thickness of the bumps 4 and 4a in the direction perpendicular to the main surface of the semiconductor substrate 2. is less than As a result, in the case of electronic equipment in which the semiconductor substrate 2 and the chip 3 are connected by the bumps 4 and 4a, the through holes 62 and 72 for forming the bumps 4 and 4a patterned in the photoresist layers 61 and 71 are formed in the metal film 42. Forming can prevent narrowing. As a result, the through-holes 62 and 72 patterned in the photoresist layers 61 and 71 can be appropriately filled with the paste 50 containing the metal particles as the material of the bumps 4 and 4a.
  • the materials of the porous metal layers 41, 51 and the metal films 42, 43 are the same kind of metal. Thereby, the bonding strength between the porous metal layers 41 and 51 and the metal films 42 and 43 can be increased.
  • the material of the porous metal layers 41, 51 is a porous metal containing gold, silver, platinum, or copper with a purity of 99.9% by weight or more. Thereby, the connection resistance between the connection pads 21 of the semiconductor substrate 2 and the connection pads 31 of the chip 3 can be kept low.
  • the present technology can also take the following configuration.
  • a semiconductor substrate a chip; bumps for connecting a plurality of connection pads provided on opposing main surfaces of the semiconductor substrate and the chip;
  • An electronic device comprising: a sidewall portion that includes a porous metal layer that annularly surrounds a region in which the plurality of bumps are provided, and that connects the semiconductor substrate and the chip.
  • the chip is The electronic device according to (1), having a coefficient of thermal expansion different from that of the semiconductor substrate by 0.1 ppm/° C. or more.
  • the chip is is a semiconductor laser
  • the semiconductor substrate is The electronic device according to (1) or (2), further comprising a drive circuit that drives the semiconductor laser.
  • the porous metal layer is The electronic device according to any one of (1) to (3) above, containing metal particles having a particle diameter of 0.005 ⁇ m to 1.0 ⁇ m.
  • the side wall portion at least one of between the porous metal layer and connection pads provided on the semiconductor substrate and between the porous metal layer and connection pads provided on the chip;
  • the bump is a porous metal layer formed of the same material as the porous metal layer of the side wall; at least one of between the porous metal layer and the connection pads provided on the semiconductor substrate and between the porous metal layer and the connection pads provided on the chip; and a metal film provided on the side surface of the solid metal layer.
  • the metal film provided between the porous metal layer and the connection pad has a film thickness ratio of less than 10% with respect to the thickness of the bump in the direction orthogonal to the main surface. Electronics.
  • the metal film provided between the porous metal layer and the connection pad has a film thickness ratio of less than 10% to half of the thickness of the bump in the direction orthogonal to the main surface. Electronics as described.
  • Materials for the porous metal layer and the metal film are The electronic device according to any one of (5) to (10) above, which are made of the same kind of metal.
  • the material of the porous metal layer is The electronic device according to any one of (1) to (11), which is a porous metal containing gold, silver, platinum, or copper with a purity of 99.9% by weight or more.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Wire Bonding (AREA)
PCT/JP2022/003199 2021-02-19 2022-01-28 電子機器 Ceased WO2022176563A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2023500684A JP7830416B2 (ja) 2021-02-19 2022-01-28 電子機器
KR1020237025731A KR20230147601A (ko) 2021-02-19 2022-01-28 전자 기기
US18/264,719 US20240113066A1 (en) 2021-02-19 2022-01-28 Electronic device
EP22755886.3A EP4297071A4 (en) 2021-02-19 2022-01-28 Electronic device
CN202280009141.2A CN116711056A (zh) 2021-02-19 2022-01-28 电子器件

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-025311 2021-02-19
JP2021025311 2021-02-19

Publications (1)

Publication Number Publication Date
WO2022176563A1 true WO2022176563A1 (ja) 2022-08-25

Family

ID=82931539

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2022/003199 Ceased WO2022176563A1 (ja) 2021-02-19 2022-01-28 電子機器

Country Status (7)

Country Link
US (1) US20240113066A1 (https=)
EP (1) EP4297071A4 (https=)
JP (1) JP7830416B2 (https=)
KR (1) KR20230147601A (https=)
CN (1) CN116711056A (https=)
TW (1) TW202247360A (https=)
WO (1) WO2022176563A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025097274A1 (zh) * 2023-11-06 2025-05-15 江西晶弘新材料科技有限责任公司 带金属包覆结构件的三维集成封装基板结构及其制备方法

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637143A (ja) * 1992-07-15 1994-02-10 Toshiba Corp 半導体装置および半導体装置の製造方法
JPH11168116A (ja) * 1997-12-04 1999-06-22 Mitsui High Tec Inc 半導体チップ用電極バンプ
JP2000077458A (ja) * 1998-08-31 2000-03-14 Matsushita Electric Works Ltd フリップチップ実装方法
JP2003174055A (ja) * 2001-12-06 2003-06-20 Asahi Kasei Corp 微細パターン接続用回路部品およびその形成方法
JP2004214469A (ja) 2003-01-07 2004-07-29 Hitachi Ltd 電子デバイスおよびその製造方法
JP2010278139A (ja) * 2009-05-27 2010-12-09 Panasonic Corp 半導体装置及びその製造方法
WO2011114751A1 (ja) * 2010-03-19 2011-09-22 古河電気工業株式会社 導電接続部材、及び導電接続部材の作製方法
JP2011216475A (ja) * 2010-03-18 2011-10-27 Furukawa Electric Co Ltd:The 導電性ペースト、及びその製造方法、並びに導電接続部材
JP2013098514A (ja) * 2011-11-07 2013-05-20 Seiko Epson Corp 半導体装置の製造方法及び半導体装置、電子機器
JP2014090098A (ja) * 2012-10-30 2014-05-15 Fujitsu Semiconductor Ltd 半導体装置およびその製造方法
US20160300808A1 (en) * 2015-04-07 2016-10-13 United Microelectronics Corp. Stacked semiconductor device
JP2018160589A (ja) * 2017-03-23 2018-10-11 富士通株式会社 電子装置、及び電子装置の製造方法
WO2020162142A1 (ja) * 2019-02-05 2020-08-13 ソニー株式会社 発光素子組立体、マルチビームレーザチップ組立体及び光造形装置、並びに、部材組立体及びその製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2012352A4 (en) * 2006-04-24 2012-07-25 Murata Manufacturing Co ELECTRONIC COMPONENT, ELECTRONIC COMPONENT DEVICE THEREFOR AND METHOD OF MANUFACTURING THEREOF
JP5385682B2 (ja) * 2009-05-19 2014-01-08 新光電気工業株式会社 電子部品の実装構造
JP6225453B2 (ja) * 2012-05-24 2017-11-08 日亜化学工業株式会社 半導体装置
TW202541302A (zh) * 2019-02-04 2025-10-16 日商索尼半導體解決方案公司 電子裝置
US11374381B1 (en) * 2019-06-10 2022-06-28 Apple Inc. Integrated laser module
EP4191644A4 (en) * 2020-07-27 2024-02-07 Sony Semiconductor Solutions Corporation ELECTRONIC DEVICE

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637143A (ja) * 1992-07-15 1994-02-10 Toshiba Corp 半導体装置および半導体装置の製造方法
JPH11168116A (ja) * 1997-12-04 1999-06-22 Mitsui High Tec Inc 半導体チップ用電極バンプ
JP2000077458A (ja) * 1998-08-31 2000-03-14 Matsushita Electric Works Ltd フリップチップ実装方法
JP2003174055A (ja) * 2001-12-06 2003-06-20 Asahi Kasei Corp 微細パターン接続用回路部品およびその形成方法
JP2004214469A (ja) 2003-01-07 2004-07-29 Hitachi Ltd 電子デバイスおよびその製造方法
JP2010278139A (ja) * 2009-05-27 2010-12-09 Panasonic Corp 半導体装置及びその製造方法
JP2011216475A (ja) * 2010-03-18 2011-10-27 Furukawa Electric Co Ltd:The 導電性ペースト、及びその製造方法、並びに導電接続部材
WO2011114751A1 (ja) * 2010-03-19 2011-09-22 古河電気工業株式会社 導電接続部材、及び導電接続部材の作製方法
JP2013098514A (ja) * 2011-11-07 2013-05-20 Seiko Epson Corp 半導体装置の製造方法及び半導体装置、電子機器
JP2014090098A (ja) * 2012-10-30 2014-05-15 Fujitsu Semiconductor Ltd 半導体装置およびその製造方法
US20160300808A1 (en) * 2015-04-07 2016-10-13 United Microelectronics Corp. Stacked semiconductor device
JP2018160589A (ja) * 2017-03-23 2018-10-11 富士通株式会社 電子装置、及び電子装置の製造方法
WO2020162142A1 (ja) * 2019-02-05 2020-08-13 ソニー株式会社 発光素子組立体、マルチビームレーザチップ組立体及び光造形装置、並びに、部材組立体及びその製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4297071A4

Also Published As

Publication number Publication date
JP7830416B2 (ja) 2026-03-16
JPWO2022176563A1 (https=) 2022-08-25
US20240113066A1 (en) 2024-04-04
CN116711056A (zh) 2023-09-05
EP4297071A1 (en) 2023-12-27
TW202247360A (zh) 2022-12-01
EP4297071A4 (en) 2024-10-23
KR20230147601A (ko) 2023-10-23

Similar Documents

Publication Publication Date Title
TWI277187B (en) Semiconductor device and manufacturing method for the same
CN101529584B (zh) 半导体元件的安装结构体及半导体元件的安装方法
JP5570799B2 (ja) 半導体装置及びその製造方法
CN100438025C (zh) 芯片层叠型半导体装置及其制造方法
US9337165B2 (en) Method for manufacturing a fan-out WLP with package
US8786102B2 (en) Semiconductor device and method of manufacturing the same
US20040245652A1 (en) Semiconductor device, electronic device, electronic appliance, and method of manufacturing a semiconductor device
JP2001313314A (ja) バンプを用いた半導体装置、その製造方法、および、バンプの形成方法
JP3180800B2 (ja) 半導体装置及びその製造方法
JP2012069903A (ja) 半導体装置及びその製造方法
JP2012146853A (ja) 半導体装置の製造方法
TWI911222B (zh) 電子機器
WO2022176563A1 (ja) 電子機器
JP2010135501A (ja) 半導体装置の製造方法
JP5375563B2 (ja) 半導体装置の実装構造及び実装方法
JP4626445B2 (ja) 半導体パッケージの製造方法
WO2024029255A1 (ja) 電子機器
JP2012015446A (ja) 半導体装置の製造方法
JP4331179B2 (ja) 半導体装置
JP2001127102A (ja) 半導体装置およびその製造方法
JP2003031617A (ja) 半導体装置の実装構造とその製造方法
KR20100030499A (ko) 플립 칩 패키지 및 그의 제조방법
JPH09260431A (ja) フリップチップ実装の接続構造
JP2007317761A (ja) 半導体装置
JP2005150558A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22755886

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202280009141.2

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 2023500684

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 18264719

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2022755886

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2022755886

Country of ref document: EP

Effective date: 20230919