WO2022176455A1 - 窒化物半導体デバイス - Google Patents

窒化物半導体デバイス Download PDF

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WO2022176455A1
WO2022176455A1 PCT/JP2022/000941 JP2022000941W WO2022176455A1 WO 2022176455 A1 WO2022176455 A1 WO 2022176455A1 JP 2022000941 W JP2022000941 W JP 2022000941W WO 2022176455 A1 WO2022176455 A1 WO 2022176455A1
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layer
semiconductor device
nitride semiconductor
substrate
opening
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French (fr)
Japanese (ja)
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大輔 柴田
聡之 田村
学 柳原
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Panasonic Holdings Corp
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Panasonic Holdings Corp
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Priority to US18/446,284 priority patent/US20230387286A1/en
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/478—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
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    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • the present disclosure relates to nitride semiconductor devices.
  • Nitride semiconductors such as GaN (gallium nitride) are wide-gap semiconductors with a large bandgap, have a large dielectric breakdown electric field strength, and have a saturation drift velocity of electrons comparable to GaAs (gallium arsenide) semiconductors or Si (silicon) semiconductors. It has the advantage of being relatively large. For this reason, research and development of power transistors using nitride semiconductors, which are advantageous for increasing output power and increasing withstand voltage, are being conducted.
  • GaN gallium nitride
  • Patent Literature 1 discloses a vertical electric field including a regrown layer positioned to cover an opening provided in a GaN-based laminate, and a gate electrode positioned on the regrown layer along the regrown layer.
  • a field effect transistor (FET) is disclosed.
  • a channel is formed by a two-dimensional electron gas (2DEG: 2-Dimensional Electron Gas) generated in the regrown layer.
  • 2DEG 2-Dimensional Electron Gas
  • Patent Document 2 discloses a semiconductor device provided with an isolation trench for isolating the semiconductor device from other devices.
  • the present disclosure provides a nitride semiconductor device with improved off characteristics.
  • a nitride semiconductor device includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, and a first semiconductor layer disposed above the first semiconductor layer. a second semiconductor layer of conductivity type 2; a third semiconductor layer disposed above the second semiconductor layer; a first opening reaching one semiconductor layer, a part of which is arranged along the inner surface of the first opening, and another part of which is arranged above the third semiconductor layer, a semiconductor multilayer film having a channel region of a first conductivity type; a fourth semiconductor layer of the second conductivity type disposed along the upper surface of the semiconductor multilayer film; a gate electrode arranged; a source electrode arranged apart from the gate electrode; a drain electrode arranged on the lower surface side of the substrate; and a trench penetrating through the semiconductor layer to reach the first semiconductor layer, wherein the distance between the bottom of the first opening and the substrate is shorter than the distance between the bottom of the trench and the substrate.
  • FIG. 1 is a cross-sectional view of a nitride semiconductor device according to Embodiment 1.
  • FIG. FIG. 2 is a plan view of the nitride semiconductor device according to Embodiment 1.
  • FIG. 3 is a cross-sectional view of a nitride semiconductor device according to Embodiment 2.
  • FIG. 4 is a cross-sectional view of a nitride semiconductor device according to Embodiment 3.
  • FIG. FIG. 5 is a cross-sectional view of a nitride semiconductor device according to a fourth embodiment.
  • FIG. 6 is a cross-sectional view of a nitride semiconductor device according to a modification of the fourth embodiment.
  • FIG. 1 is a cross-sectional view of a nitride semiconductor device according to Embodiment 1.
  • FIG. FIG. 2 is a plan view of the nitride semiconductor device according to Embodiment 1.
  • FIG. 3 is a cross-sectional view of
  • FIG. 7 is a cross-sectional view of a nitride semiconductor device according to Embodiment 5.
  • FIG. 8 is a cross-sectional view of a nitride semiconductor device according to Modification 1 of Embodiment 5.
  • FIG. 9 is a cross-sectional view of a nitride semiconductor device according to Modification 2 of Embodiment 5.
  • FIG. 10 is a plan view of a nitride semiconductor device according to Modification 2 of Embodiment 5.
  • the isolation trench disclosed in Patent Document 2 is formed by dry etching. In the vicinity of the isolation trench, deterioration of film quality is likely to occur due to damage during dry etching.
  • the present disclosure provides a nitride semiconductor device with improved off characteristics. Specifically, the present invention provides a nitride semiconductor device capable of reducing leakage current in an off state and suppressing a decrease in breakdown voltage.
  • a nitride semiconductor device includes a substrate, a first semiconductor layer of a first conductivity type disposed above the substrate, and a first semiconductor layer disposed above the first semiconductor layer. a second semiconductor layer of conductivity type 2; a third semiconductor layer disposed above the second semiconductor layer; a first opening reaching one semiconductor layer, a part of which is arranged along the inner surface of the first opening, and another part of which is arranged above the third semiconductor layer, a semiconductor multilayer film having a channel region of a first conductivity type; a fourth semiconductor layer of the second conductivity type disposed along the upper surface of the semiconductor multilayer film; a gate electrode arranged; a source electrode arranged apart from the gate electrode; a drain electrode arranged on the lower surface side of the substrate; and a trench penetrating through the semiconductor layer to reach the first semiconductor layer, wherein the distance between the bottom of the first opening and the substrate is shorter than the distance between the bottom of the trench and the substrate.
  • a pn junction exists between the semiconductor multilayer film and the fourth semiconductor layer in the first opening. Since the fourth semiconductor layer can be formed continuously from the semiconductor multilayer film, this pn junction provides a higher quality pn junction with a higher electric field strength than the pn junction near the groove where etching damage occurs. .
  • the bottom of the first opening is closer to the substrate than the bottom of the groove. It is easy to concentrate on one opening. Therefore, electric field concentration can be received at the high-quality pn junction, and electric field concentration on the pn junction near the groove can be alleviated. This can improve the off characteristics of the nitride semiconductor device. Specifically, the leak current in the vicinity of the groove can be reduced, and the decrease in breakdown voltage can be suppressed.
  • the distance between the bottom of the fourth semiconductor layer and the substrate in the first opening may be shorter than the distance between the bottom of the groove and the substrate.
  • the pn junction in the first opening is closer to the substrate than the pn junction in the vicinity of the groove, so that the pn junction in the first opening can receive electric field concentration. Therefore, the off characteristics of the nitride semiconductor device can be improved.
  • the second semiconductor layer is provided apart from the gate electrode and penetrates through the semiconductor multilayer film and the third semiconductor layer. and the source electrode may be provided along an inner surface of the second opening.
  • the channel region and the source electrode included in the semiconductor multilayer film are in direct contact with each other, so that the contact resistance between the channel region and the source electrode can be reduced.
  • the potential of the second semiconductor layer can be fixed to the potential of the source electrode. Since current collapse is suppressed by fixing the potential of the second semiconductor layer, the dynamic characteristics of the nitride semiconductor device can be improved.
  • the first semiconductor layer is composed of a plurality of layers having different impurity concentrations, and the bottom of the first opening is the n-th layer (n is 2 or more) from the top among the plurality of layers. natural number) of layers.
  • each layer can have a suitable function by multilayering the first semiconductor layer. For example, it is possible to improve the off-characteristics while suppressing an increase in the on-resistance of the nitride semiconductor device.
  • the bottom of the groove may be located in a layer above the n-th layer.
  • the plurality of layers may be composed of two layers.
  • the impurity concentration of the n-th layer where the bottom of the first opening is located can be made higher than the impurity concentration of the layer where the bottom of the trench is located.
  • the impurity concentration of the n-th layer where the bottom of the first opening is located can be made higher than the impurity concentration of the layer where the bottom of the trench is located.
  • the bottom of the first opening is located in the n-th layer with high impurity concentration and low resistance, the layer with low impurity concentration and high resistance is located on the path of the drain current. do not do. Therefore, an increase in on-resistance can be suppressed.
  • a layer having a low impurity concentration and a high resistance is not positioned. can be subjected to electric field concentrations at Therefore, deterioration of the OFF characteristics of the nitride semiconductor device is suppressed.
  • the plurality of layers may be composed of three layers.
  • the n-th layer may be a layer having the highest impurity concentration among the plurality of layers.
  • the diffusion of the drain current in the lateral direction can be promoted through the layer with the highest impurity concentration, so the on-resistance reduction effect can be maximized.
  • the uppermost layer among the plurality of layers may be a layer having a lower impurity concentration of the first conductivity type than the n-th layer.
  • the bottom of the groove may be located in the n-th layer.
  • reverse conduction deterioration deterioration of the off-characteristics of the nitride semiconductor device. According to the nitride semiconductor device according to this aspect, reverse conduction deterioration can be suppressed.
  • the bottom of the groove may be located on the uppermost layer.
  • the top layer may contain C or Fe.
  • the nitride semiconductor device further includes an insulating film provided along the inner surface of the trench, and a field provided above the insulating film so as to protrude into the trench. and a plate.
  • the field plate may be electrically connected to the source electrode.
  • the effect of dispersing the electric field concentrated on the terminal end to the field plate can be maximized, so that the effect of alleviating the electric field concentration on the pn junction near the groove can be further enhanced.
  • the smaller angle between the sidewalls of the groove and the plane parallel to the main surface of the substrate may be less than 90°.
  • the groove is provided in a ring shape that collectively surrounds the first opening, the semiconductor multilayer film, the fourth semiconductor layer, the gate electrode and the source electrode in a plan view
  • the semiconductor layer 1 may include a high-resistance region provided in a ring shape along the bottom of the trench and into which an impurity is introduced.
  • an interface level is formed at the interface between the insulating film and the first semiconductor layer, which may result in the formation of a leakage current path.
  • a leak current flows through this path, degrading the OFF characteristics.
  • the leakage current can be suppressed by the high resistance region, so that the OFF characteristics can be improved.
  • the impurity contained in the high resistance region may be Mg, B or Fe.
  • the high resistance region may include an end surface of the nitride semiconductor device.
  • the end face of the nitride semiconductor device is formed by, for example, dicing. Damage caused by dicing may create a leakage current path.
  • the leakage current can be suppressed by the high resistance region, so that the OFF characteristics can be improved.
  • each figure is a schematic diagram and is not necessarily strictly illustrated. Therefore, for example, scales and the like do not necessarily match in each drawing. Moreover, in each figure, substantially the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted or simplified.
  • the x-axis, y-axis and z-axis indicate three axes of a three-dimensional orthogonal coordinate system.
  • the x-axis and the y-axis are directions parallel to the first side of the rectangle and the second side orthogonal to the first side, respectively, when the substrate has a rectangular shape in plan view.
  • the z-axis is the thickness direction of the substrate.
  • the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate.
  • the thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the “longitudinal direction”.
  • a direction parallel to the main surface of the substrate may be referred to as a "lateral direction”.
  • the side of the substrate on which the gate electrode and the source electrode are provided (the positive side of the z-axis) is regarded as the “upper side” or the “upper side”
  • the side of the substrate on which the drain electrode is provided (the negative side of the z-axis) is regarded as the “upper side”. side) as "lower” or "lower”.
  • the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the stacking structure. It is used as a term defined by a relative positional relationship. Also, the terms “above” and “below” are used only when two components are spaced apart from each other and there is another component between them, as well as when two components are spaced apart from each other. It also applies when two components are in contact with each other and are placed in close contact with each other.
  • planar view means when viewed from a direction perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, when the main surface of the substrate is viewed from the front. .
  • ordinal numbers such as “first” and “second” do not mean the number or order of components, unless otherwise specified, to avoid confusion between components of the same kind and to distinguish them. It is used for the purpose of
  • AlGaN represents a ternary mixed crystal Al x Ga 1-x N (0 ⁇ x ⁇ 1).
  • multi-element mixed crystals are abbreviated by the arrangement of their constituent element symbols, eg, AlInN, GaInN, and the like.
  • AlxGa1 - xyInyN (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, and 0 ⁇ x+y ⁇ 1), which is an example of a nitride semiconductor, is abbreviated as AlGaInN.
  • FIG. 1 is a cross-sectional view of a nitride semiconductor device 1 according to this embodiment.
  • FIG. 2 is a plan view of nitride semiconductor device 1 according to the present embodiment.
  • FIG. 1 shows a cross section taken along line II of FIG.
  • the transistor portion 2 and the terminal portion 3 are schematically shown separately.
  • the nitride semiconductor device 1 includes a transistor portion 2 and a termination portion 3.
  • the nitride semiconductor device 1 includes a substrate 10, a drift layer 12, a first underlayer 14, a second underlayer 16, a gate opening 18, a semiconductor multilayer film 20, a threshold value It comprises an adjustment layer 24 , a source opening 26 , a source electrode 28 , a gate electrode 30 and a drain electrode 32 .
  • the semiconductor multilayer film 20 is a laminate of an electron transit layer 21 and an electron supply layer 22, and includes a two-dimensional electron gas (2DEG) 23 as a channel region.
  • Nitride semiconductor device 1 also includes groove portion 40 provided in terminal portion 3 .
  • the transistor section 2 is a region containing FETs, and is a region containing the center of the nitride semiconductor device 1 as shown in FIG. Specifically, the transistor section 2 is a region in which the second base layer 16, the gate opening 18, the semiconductor multilayer film 20, the threshold adjustment layer 24, the gate electrode 30 and the source electrode 28 are arranged in plan view. .
  • each component arranged in the transistor section 2 is omitted.
  • a plurality of source electrodes 28 elongated in one direction in plan view are arranged in stripes, and gate electrodes 30, threshold adjustment layers 24, and gate openings 18 are arranged between adjacent source electrodes 28.
  • a plurality of source electrodes 28 having a hexagonal shape in plan view may be arranged so as to be planarly filled with a gap therebetween.
  • the terminal portion 3 is a region other than the transistor portion 2 and is provided in a ring shape surrounding the transistor portion 2 .
  • the second underlying layer 16 , the gate opening 18 , the semiconductor multilayer film 20 , the threshold adjustment layer 24 , the gate electrode 30 and the source electrode 28 are not arranged in the terminal portion 3 .
  • the nitride semiconductor device 1 is a device having a laminated structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, nitride semiconductor device 1 has a heterostructure of an AlGaN film and a GaN film.
  • a high-concentration two-dimensional electron gas 23 is generated at the heterointerface by spontaneous polarization or piezoelectric polarization on the (0001) plane. Therefore, even in an undoped state, a sheet carrier concentration of 1 ⁇ 10 13 cm ⁇ 2 or more can be obtained at the interface.
  • the nitride semiconductor device 1 is a field effect transistor (FET) using a two-dimensional electron gas 23 generated at the AlGaN/GaN heterointerface as a channel.
  • FET field effect transistor
  • the nitride semiconductor device 1 is a so-called vertical FET.
  • the nitride semiconductor device 1 is a normally-off FET.
  • the source electrode 28 is grounded (that is, the potential is 0V), and the drain electrode 32 is given a positive potential.
  • the potential applied to the drain electrode 32 is, for example, 100 V or more and 1200 V or less, but is not limited thereto.
  • gate electrode 30 is applied with 0V or a negative potential (eg, -5V).
  • gate electrode 30 is applied with a positive potential (for example, +5 V).
  • Nitride semiconductor device 1 may be a normally-on FET.
  • the substrate 10 is a substrate made of a nitride semiconductor, and has a first principal surface 10a and a second principal surface 10b facing each other, as shown in FIG.
  • the first main surface 10a is the main surface (upper surface) on which the drift layer 12 is formed.
  • the first main surface 10a substantially coincides with the c-plane.
  • the second main surface 10b is the main surface (lower surface) on which the drain electrode 32 is formed.
  • the planar view shape of the substrate 10 is, for example, a rectangle, but is not limited to this.
  • the substrate 10 is, for example, a substrate made of n + -type GaN having a thickness of 300 ⁇ m and a carrier concentration of 1 ⁇ 10 18 cm ⁇ 3 .
  • n-type and p-type indicate conductivity types of semiconductors.
  • the n + type represents a state in which an n-type dopant is added to a semiconductor at a high concentration, ie, so-called heavy doping.
  • n ⁇ type represents a state in which an n-type dopant is added to a semiconductor at a low concentration, ie, so-called light doping.
  • p + type and p ⁇ type The same is true for p + type and p ⁇ type.
  • N-type, n + -type and n - -type are examples of the first conductivity type.
  • P-type, p + -type and p - -type are examples of the second conductivity type.
  • the second conductivity type is a conductivity type opposite in polarity to the first conductivity type.
  • the substrate 10 does not have to be a nitride semiconductor substrate.
  • the substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, or the like.
  • Drift layer 12 is an example of a first conductivity type first nitride semiconductor layer disposed above substrate 10 .
  • the drift layer 12 is, for example, a film made of n ⁇ -type GaN with a thickness of 8 ⁇ m.
  • the donor concentration of the drift layer 12 is, for example, in the range of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less, and is 1 ⁇ 10 16 cm ⁇ 3 as an example.
  • the carbon concentration (C concentration) of the drift layer 12 is in the range of 1 ⁇ 10 15 cm ⁇ 3 to 2 ⁇ 10 17 cm ⁇ 3 .
  • the drift layer 12 is provided in contact with the first main surface 10a of the substrate 10, for example.
  • the drift layer 12 is formed on the first main surface 10a of the substrate 10 by, for example, crystal growth such as metal-organic vapor phase epitaxy (MOVPE).
  • MOVPE metal-organic vapor phase epitaxy
  • the first underlayer 14 is an example of a second conductivity type second nitride semiconductor layer disposed above the drift layer 12 .
  • the first underlayer 14 is, for example, a film made of p-type GaN having a thickness of 400 nm and a carrier concentration of 1 ⁇ 10 17 cm ⁇ 3 .
  • the first underlayer 14 is provided in contact with the upper surface of the drift layer 12 .
  • the first underlayer 14 is formed on the drift layer 12 by, for example, crystal growth such as the MOVPE method. Note that the first underlayer 14 may be formed by injecting magnesium (Mg) into a deposited undoped GaN film. Undoping will be explained later.
  • Mg magnesium
  • the first underlayer 14 suppresses leak current between the source electrode 28 and the drain electrode 32 .
  • the potential of the drain electrode 32 becomes higher than that of the source electrode 28.
  • a depletion layer extends in the drift layer 12 .
  • the potential of the drain electrode 32 is higher than that of the source electrode 28 both in the OFF state and the ON state. Therefore, the nitride semiconductor device 1 can have a high withstand voltage.
  • the first underlying layer 14 is in contact with the source electrode 28, as shown in FIG. Therefore, the first underlying layer 14 is fixed at the same potential as the source electrode 28 .
  • the second underlying layer 16 is an example of a third nitride semiconductor layer provided above the first underlying layer 14 .
  • the second underlayer 16 is a high resistance layer having a higher resistance than the first underlayer 14 .
  • the second underlying layer 16 is made of an insulating or semi-insulating nitride semiconductor.
  • the second underlayer 16 is, for example, a film made of undoped GaN with a thickness of 200 nm.
  • the second underlayer 16 is provided in contact with the first underlayer 14 .
  • the second underlayer 16 is formed on the first underlayer 14 by, for example, crystal growth such as the MOVPE method.
  • the second underlayer 16 is doped with carbon (C). Specifically, the carbon concentration of the second underlayer 16 is higher than the carbon concentration of the first underlayer 14 .
  • the second underlayer 16 may contain silicon (Si) or oxygen (O) mixed during film formation.
  • the carbon concentration of the second underlayer 16 is higher than the silicon concentration (Si concentration) or the oxygen concentration (O concentration).
  • the carbon concentration of the second underlayer 16 is, for example, 3 ⁇ 10 17 cm ⁇ 3 or more, but may be 1 ⁇ 10 18 cm ⁇ 3 or more.
  • the silicon concentration or oxygen concentration of the second underlayer 16 is, for example, 5 ⁇ 10 16 cm ⁇ 3 or less, but may be 2 ⁇ 10 16 cm ⁇ 3 or less.
  • the second underlayer 16 may be formed by ion implantation of magnesium (Mg), iron (Fe), boron (B), or the like, other than carbon.
  • Mg magnesium
  • Fe iron
  • B boron
  • Other ion species may be used as long as they are ion species capable of realizing high resistance of GaN.
  • the nitride semiconductor device 1 does not include the second underlying layer 16, the electron transit layer 21 and the p-type first underlying layer 14 are interposed between the source electrode 28 and the drain electrode 32.
  • the formation of a parasitic npn structure can be suppressed by providing the high-resistance second base layer 16 , and malfunction of the nitride semiconductor device 1 can be suppressed.
  • a layer for suppressing diffusion of p-type impurities such as Mg from the first underlayer 14 may be provided on the upper surface of the second underlayer 16 .
  • an AlGaN layer having a thickness of 20 nm may be provided on the second underlayer 16 .
  • the gate opening 18 is an example of a first opening that penetrates the second underlying layer 16 and the first underlying layer 14 and reaches the drift layer 12 .
  • the gate opening 18 penetrates both the second underlayer 16 and the first underlayer 14 .
  • a bottom portion 18 a of the gate opening 18 is part of the upper surface of the drift layer 12 .
  • the bottom portion 18a is located below the lower surface of the first underlayer 14.
  • the lower surface of the first underlayer 14 corresponds to the interface between the first underlayer 14 and the drift layer 12 .
  • the bottom portion 18a is parallel to the first major surface 10a of the substrate 10, for example.
  • the gate opening 18 is formed such that the opening area increases as the distance from the substrate 10 increases. Specifically, the sidewall 18b of the gate opening 18 is obliquely inclined. As shown in FIG. 1, the cross-sectional shape of the gate opening 18 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.
  • the inclination angle of the side wall 18b with respect to the bottom portion 18a is, for example, in the range of 30° or more and 45° or less.
  • the smaller the tilt angle the closer the side wall 18b is to the c-plane, so the film quality of the electron transit layer 21 formed along the side wall 18b by crystal regrowth can be improved.
  • the larger the tilt angle the more the gate opening 18 is prevented from becoming too large, and the size reduction of the nitride semiconductor device 1 is realized.
  • the gate opening 18 is formed on the first main surface 10a of the substrate 10 by successively forming the drift layer 12, the first underlayer 14, and the second underlayer 16 in this order. It is formed by removing a portion of each of the second underlayer 16 and the first underlayer 14 so as to expose the drift layer 12 roughly. At this time, by removing the surface layer portion of the drift layer 12 by a predetermined thickness, the bottom portion 18 a of the gate opening portion 18 is formed below the lower surface of the first underlying layer 14 .
  • the removal of the second underlayer 16 and the first underlayer 14 is performed by resist coating and patterning, and dry etching. Specifically, after patterning the resist, baking is performed so that the edges of the resist are slanted. By performing dry etching after that, the gate opening 18 is formed so that the side wall 18b is slanted so that the shape of the resist is transferred.
  • a part of the semiconductor multilayer film 20 is arranged along the inner surface of the gate opening 18 and another part is arranged above the second underlying layer 16 .
  • the semiconductor multilayer film 20 is a laminated film of an electron transit layer 21 and an electron supply layer 22 .
  • the electron transit layer 21 is an example of a first regrowth layer provided along the inner surface of the gate opening 18 . Specifically, part of the electron transit layer 21 is provided along the bottom 18 a and sidewalls 18 b of the gate opening 18 , and the other part of the electron transit layer 21 is provided on the upper surface of the second underlying layer 16 . is provided.
  • the electron transit layer 21 is, for example, a film made of undoped GaN with a thickness of 150 nm.
  • the electron transit layer 21 may be made n-type by Si doping instead of undoping.
  • the electron transit layer 21 is in contact with the drift layer 12 at the bottom 18a and sidewalls 18b of the gate opening 18.
  • the electron transit layer 21 is in contact with the end face of each of the first underlying layer 14 and the second underlying layer 16 at the sidewall 18 b of the gate opening 18 . Furthermore, the electron transit layer 21 is in contact with the upper surface of the second underlayer 16 .
  • the electron transit layer 21 is formed by crystal re-growth after forming the gate opening 18 .
  • the electron transit layer 21 has a channel region. Specifically, a two-dimensional electron gas 23 is generated near the interface between the electron transit layer 21 and the electron supply layer 22 . Two-dimensional electron gas 23 functions as a channel of electron transit layer 21 . In FIG. 1, the two-dimensional electron gas 23 is schematically illustrated by broken lines. The two-dimensional electron gas 23 bends along the interface between the electron transit layer 21 and the electron supply layer 22 , that is, along the inner surface of the gate opening 18 .
  • an AlN film having a thickness of about 1 nm may be provided as a second regrowth layer between the electron transit layer 21 and the electron supply layer 22 .
  • the AlN film can suppress alloy scattering and improve channel mobility.
  • the electron supply layer 22 is an example of a third regrowth layer provided along the inner surface of the gate opening 18 .
  • the electron transit layer 21 and the electron supply layer 22 are provided in this order from the substrate 10 side.
  • the electron supply layer 22 is formed in a shape along the upper surface of the electron transit layer 21 with a substantially uniform thickness.
  • the electron supply layer 22 is, for example, a film made of undoped AlGaN with a thickness of 50 nm.
  • the electron supply layer 22 is formed by crystal regrowth following the step of forming the electron transit layer 21 .
  • the electron supply layer 22 forms an AlGaN/GaN heterointerface with the electron transit layer 21 . As a result, a two-dimensional electron gas 23 is generated within the electron transit layer 21 .
  • the electron supply layer 22 supplies electrons to the channel region (that is, the two-dimensional electron gas 23) formed in the electron transit layer 21.
  • the threshold adjustment layer 24 is an example of a second conductivity type fourth nitride semiconductor layer arranged along the upper surface of the semiconductor multilayer film 20 . Specifically, the threshold adjustment layer 24 is provided between the gate electrode 30 and the electron supply layer 22 . The threshold value adjustment layer 24 is formed in a shape along the upper surface of the electron supply layer 22 with a substantially uniform thickness.
  • the threshold adjustment layer 24 is, for example, a nitride semiconductor layer made of p-type GaN or AlGaN having a thickness of 100 nm and a carrier concentration of 1 ⁇ 10 17 cm ⁇ 3 .
  • the threshold adjustment layer 24 is formed by regrowth by the MOVPE method subsequent to the step of forming the electron supply layer 22 and patterning.
  • the threshold adjustment layer 24 raises the potential of the conduction band edge of the channel portion. Therefore, the threshold voltage of nitride semiconductor device 1 can be increased. Therefore, the nitride semiconductor device 1 can be realized as a normally-off FET. That is, when a potential of 0 V is applied to gate electrode 30, nitride semiconductor device 1 can be turned off.
  • the source opening 26 is an example of a second opening that penetrates the semiconductor multilayer film 20 and the second underlying layer 16 to reach the first underlying layer 14 at a position away from the gate opening 18 .
  • the source opening 26 is arranged at a position distant from the gate electrode 30 in plan view.
  • a bottom portion 26 a of the source opening 26 is part of the upper surface of the first underlayer 14 . As shown in FIG. 1 , the bottom portion 26 a is located below the bottom surface of the second underlayer 16 . The bottom surface of the second underlayer 16 corresponds to the interface between the second underlayer 16 and the first underlayer 14 . The bottom portion 26a is parallel to the first major surface 10a of the substrate 10, for example.
  • the source opening 26 is formed so that the opening area is constant regardless of the distance from the substrate 10 .
  • sidewalls 26b of source opening 26 are perpendicular to bottom 26a. That is, the cross-sectional shape of the source opening 26 is rectangular.
  • the source opening 26 may be formed so that the opening area increases as the distance from the substrate 10 increases.
  • the sidewall 26b of the source opening 26 may be obliquely slanted.
  • the cross-sectional shape of the source opening 26 may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid.
  • the inclination angle of the side wall 26b with respect to the bottom portion 26a may be, for example, in the range of 30° or more and 60° or less.
  • sidewalls 26 b of source opening 26 may have a greater slope angle than sidewalls 18 b of gate opening 18 .
  • the contact area between the source electrode 28 and the electron transit layer 21 (two-dimensional electron gas 23) is increased, thereby facilitating ohmic connection.
  • the two-dimensional electron gas 23 is exposed on the sidewall 26b of the source opening 26 and connected to the source electrode 28 at the exposed portion.
  • the source opening 26 may be formed, for example, following the step of forming the threshold adjusting layer 24 (i.e., the crystal regrowth step), such that the first underlying layer 14 is exposed in a different region than the gate opening 18 . It is formed by etching the adjustment layer 24 , the electron supply layer 22 , the electron transit layer 21 and the second underlayer 16 . At this time, the surface layer portion of the first underlying layer 14 is also removed, so that the bottom portion 26 a of the source opening 26 is formed below the lower surface of the second underlying layer 16 .
  • the source opening 26 is formed into a predetermined shape by, for example, photolithographic patterning and dry etching.
  • the source electrode 28 is arranged apart from the gate electrode 30 .
  • the source electrode 28 is provided along the inner surface of the source opening 26 .
  • the source electrode 28 is connected to each of the electron supply layer 22 , the electron transit layer 21 and the first underlying layer 14 .
  • the source electrode 28 is ohmic-connected to each of the electron transit layer 21 and the electron supply layer 22 .
  • Source electrode 28 is in direct contact with two-dimensional electron gas 23 at sidewall 26b. Thereby, the contact resistance between the source electrode 28 and the two-dimensional electron gas 23 (channel) can be reduced.
  • the source electrode 28 is formed using a conductive material such as metal.
  • a material such as Ti/Al that can be ohmic-connected to the n-type GaN layer by heat treatment can be used.
  • the source electrode 28 is formed, for example, by patterning a conductive film formed by sputtering or vapor deposition.
  • the gate electrode 30 is arranged above the threshold adjustment layer 24 . Specifically, the gate electrode 30 is provided in contact with the upper surface of the threshold adjustment layer 24 so as to cover the gate opening 18 .
  • the gate electrode 30 is formed, for example, in a shape along the upper surface of the threshold value adjustment layer 24 with a substantially uniform film thickness. Alternatively, the gate electrode 30 may be formed so as to fill the concave portion of the upper surface of the threshold adjustment layer 24 .
  • the gate electrode 30 is formed using a conductive material such as metal.
  • the gate electrode 30 is formed using palladium (Pd).
  • a material that is Schottky-connected to the p-type GaN layer can be used, such as a nickel (Ni)-based material, tungsten silicide (WSi), gold (Au), or the like.
  • the gate electrode 30 is formed by patterning a conductive film formed by, for example, sputtering or vapor deposition after the threshold adjustment layer 24 is formed, the source opening 26 is formed, or the source electrode 28 is formed. be.
  • the drain electrode 32 is provided on the lower surface side of the substrate 10 , that is, on the side opposite to the drift layer 12 . Specifically, the drain electrode 32 is provided in contact with the second main surface 10b of the substrate 10 .
  • the drain electrode 32 is formed using a conductive material such as metal.
  • a material such as Ti/Al which is ohmically connected to the n-type GaN layer can be used.
  • the drain electrode 32 is formed, for example, by patterning a conductive film deposited by sputtering or vapor deposition.
  • the second base layer 16, the semiconductor multilayer film 20, and the threshold adjustment layer 24 are not provided in the terminal portion 3.
  • the second underlying layer 16, the semiconductor multilayer film 20, and the threshold adjustment layer 24 are removed at the termination portion 3 at the same time as the source opening portion 26 is formed.
  • the top surface of the first underlying layer 14 is positioned at the same height as the bottom portion 26 a of the source opening 26 .
  • “same height” means that the distances from the first main surface 10a of the substrate 10 are the same.
  • a groove portion 40 is provided in the terminal end portion 3 .
  • the groove portion 40 is an isolation trench for partitioning and isolating the transistor portion 2 .
  • the groove portion 40 penetrates the first underlayer 14 and reaches the drift layer 12 .
  • the groove portion 40 has a bottom portion 40a and side walls 40b.
  • the groove portion 40 is a stepped portion having sidewalls 40b only on the transistor portion 2 side. That is, the bottom portion 40a of the groove portion 40 is connected to the end face of the nitride semiconductor device 1. As shown in FIG.
  • the groove portion 40 is provided in a ring shape surrounding the transistor portion 2, as shown in FIG.
  • a bottom portion 40 a of the groove portion 40 is part of the upper surface of the drift layer 12 . As shown in FIG. 1, the bottom portion 40a is located below the lower surface of the first underlayer 14. As shown in FIG. The bottom portion 40a is parallel to the first main surface 10a of the substrate 10, for example.
  • the groove part 40 is formed so that the opening area is constant regardless of the distance from the substrate 10 .
  • sidewalls 40b of groove 40 are perpendicular to bottom 40a. That is, the cross-sectional shape of the groove portion 40 is rectangular.
  • the trench 40 is formed, for example, by performing dry etching with a different etching mask following the dry etching process for forming the source opening 26 .
  • the trench 40 may be formed by dry etching.
  • the distance between the bottom 18a of the gate opening 18 and the first main surface 10a of the substrate 10 is D1.
  • the distance between the bottom portion 24a of the threshold adjustment layer 24 and the first main surface 10a of the substrate 10 is defined as D2.
  • the distance between the bottom portion 40a of the groove portion 40 and the first main surface 10a of the substrate 10 is defined as D3.
  • the distance D1 is shorter than the distance D3.
  • the distance D2 is shorter than the distance D3. That is, D1 ⁇ D2 ⁇ D3 is established.
  • the difference between the distance D1 and the distance D3 is 0.05 ⁇ m or more and 1 ⁇ m or less. More preferably, it is 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • the off characteristics of the nitride semiconductor device 1 can be improved. Specifically, it is as follows.
  • the transistor section 2 When the transistor section 2 is in the off state, a high voltage is applied between the drain electrode 32 and the source electrode 28 such that the potential on the drain electrode 32 side is higher than that on the source electrode 28 side. Therefore, in the off state, a high electric field is generated in the longitudinal direction of nitride semiconductor device 1 .
  • both the distances D1 and D2 are shorter than the distance D3, the electric field tends to concentrate on the gate opening 18 of the transistor section 2 rather than on the terminal section 3 .
  • a concentrated electric field can be received by the pn junction between the threshold adjustment layer 24 and the semiconductor multilayer film 20 .
  • This pn junction has higher quality and higher electric field strength than the pn junction between the first underlying layer 14 and the drift layer 12 in the vicinity of the groove 40 where etching damage occurs. Since the pn junction having a high electric field intensity can receive the electric field concentration, the electric field concentration on the pn junction near the trench 40 can be alleviated. Thereby, the off characteristics of the nitride semiconductor device 1 can be improved. Specifically, the leak current in the vicinity of the groove portion 40 can be reduced, and the decrease in breakdown voltage can be suppressed. As the difference between the distance D1 and the distance D3 increases, the electric field concentration in the vicinity of the groove 40 can be alleviated.
  • the second embodiment differs from the first embodiment in that the drift layer has a two-layer structure.
  • the following description focuses on the differences from the first embodiment, and omits or simplifies the description of the common points.
  • FIG. 3 is a cross-sectional view of nitride semiconductor device 101 according to the present embodiment. As shown in FIG. 3 , nitride semiconductor device 101 includes drift layer 112 instead of drift layer 12 compared to nitride semiconductor device 1 according to the first embodiment.
  • the drift layer 112 is composed of a plurality of layers with different impurity concentrations.
  • the plurality of layers is composed of two layers.
  • the drift layer 112 has a high concentration layer 112a and a low concentration layer 112b.
  • the high-concentration layer 112a and the low-concentration layer 112b are continuously formed on the substrate 10 by, for example, crystal growth such as the MOVPE method.
  • the high-concentration layer 112a is an example of the n-th layer from the top among the plurality of layers. n is a natural number of 2 or more. In this embodiment, n is two. High-concentration layer 112 a is provided in contact with first main surface 10 a of substrate 10 . The bottom portion 18a of the gate opening portion 18 is located in the high-concentration layer 112a.
  • the high-concentration layer 112a is, for example, a film made of n + -type GaN with a thickness of 7 ⁇ m.
  • the impurity concentration (donor concentration) of the high-concentration layer 112a is, for example, in the range of 3 ⁇ 10 15 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less, and is 1.5 ⁇ 10 16 cm ⁇ 3 as an example. .
  • the low-concentration layer 112b is an example of a layer located above the n-th layer.
  • low-concentration layer 112b is the uppermost layer in drift layer 112, and is provided between high-concentration layer 112a and first underlayer 14 in contact with each other.
  • the low-concentration layer 112b has a lower impurity concentration than the high-concentration layer 112a.
  • a bottom portion 40a of the groove portion 40 is located in the low-concentration layer 112b.
  • the low-concentration layer 112b is, for example, a film made of n ⁇ -type GaN with a thickness of 1 ⁇ m.
  • the impurity concentration (donor concentration) of the low-concentration layer 112b is, for example, in the range of 1 ⁇ 10 15 cm ⁇ 3 or more and 3 ⁇ 10 16 cm ⁇ 3 or less, and is 9 ⁇ 10 15 cm ⁇ 3 as an example.
  • the OFF state is achieved.
  • a high voltage is applied to the drain electrode 32 at , extension of the depletion layer into the drift layer 112 is promoted. Thereby, the breakdown voltage of the nitride semiconductor device 101 can be increased.
  • the distance D3 is shorter than either of the distances D1 and D2
  • the OFF characteristics of the nitride semiconductor device 101 can be improved as in the first embodiment. .
  • the bottom 18a of the gate opening 18 is located within the high-concentration layer 112a.
  • the drain current in the ON state flows from the drain electrode 32 to the source electrode 28 through the substrate 10 , the high-concentration layer 112 a and the two-dimensional electron gas 23 . Since the low-concentration layer 112b with high resistance does not exist on the path of the drain current, the on-resistance can be reduced.
  • the third embodiment differs from the second embodiment in the number of drift layers.
  • the following description focuses on the differences from the second embodiment, and omits or simplifies the description of the common points.
  • FIG. 4 is a cross-sectional view of a nitride semiconductor device 201 according to this embodiment. As shown in FIG. 4 , nitride semiconductor device 201 includes drift layer 212 instead of drift layer 112 compared to nitride semiconductor device 101 according to the second embodiment.
  • the drift layer 212 is composed of a plurality of layers with different impurity concentrations.
  • the plurality of layers is composed of three layers.
  • the drift layer 212 has a high-concentration layer 112a, an ultra-high-concentration layer 212c, and a low-concentration layer 112b.
  • High-concentration layer 112a and low-concentration layer 112b are the same as in the second embodiment.
  • the high-concentration layer 112a, the ultra-high-concentration layer 212c, and the low-concentration layer 112b are continuously formed on the substrate 10 by, for example, crystal growth such as the MOVPE method.
  • the ultra-high concentration layer 212c is an example of the n-th layer among the multiple layers. That is, in the present embodiment, the high-concentration layer 112a is a layer located below the n-th layer. n is two. The super high concentration layer 212c is provided between the high concentration layer 112a and the low concentration layer 112b in contact with each other. The ultra-high concentration layer 212 c is the layer with the highest impurity concentration among the plurality of layers forming the drift layer 212 .
  • the ultra-high concentration layer 212c is, for example, a film made of n + -type GaN with a thickness of 0.2 ⁇ m.
  • the impurity concentration (donor concentration) of the ultra-high concentration layer 212c is, for example, in the range of 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less, and is 1 ⁇ 10 17 cm ⁇ 3 as an example.
  • the bottom 18a of the gate opening 18 is located in the ultra-high concentration layer 212c. Since the ultra-high concentration layer 212c has a high impurity concentration and a low resistance, the drain current passing through the bottom portion 18a of the gate opening 18 diffuses laterally in the ultra-high concentration layer 212c. That is, the lateral diffusion of the drain current in the drift layer 212 is promoted, so that the on-resistance of the nitride semiconductor device 201 can be reduced.
  • the low-concentration layer 112b and the first underlying layer 14 are connected, so extension of the depletion layer into the drift layer 212 is promoted. Therefore, the breakdown voltage of nitride semiconductor device 201 can be increased. Further, the nitride semiconductor device 201 can improve the off characteristics as in the first embodiment.
  • the impurity concentration of the uppermost layer of the drift layer is different from that in the second embodiment.
  • the following description focuses on the differences from the second embodiment, and omits or simplifies the description of the common points.
  • FIG. 5 is a cross-sectional view of a nitride semiconductor device 301 according to this embodiment. As shown in FIG. 5 , nitride semiconductor device 301 includes drift layer 312 instead of drift layer 112 compared to nitride semiconductor device 101 according to the second embodiment.
  • the drift layer 312 is composed of a plurality of layers with different impurity concentrations.
  • the plurality of layers is composed of two layers.
  • the drift layer 312 has a low resistance layer 312a and a high resistance layer 312b.
  • Low-resistance layer 312a is substantially the same as drift layer 12 according to the first embodiment.
  • the low resistance layer 312a and the high resistance layer 312b are continuously formed on the substrate 10 by crystal growth such as MOVPE, for example.
  • the high-resistance layer 312 b is the uppermost layer among the multiple layers forming the drift layer 312 .
  • the high resistance layer 312b is arranged between the low resistance layer 312a and the first underlying layer 14 in contact with each other.
  • the high-resistance layer 312b is a layer having a lower impurity concentration of the first conductivity type than the low-resistance layer 312a.
  • the high-resistance layer 312b is, for example, a layer having higher resistance than both the low-resistance layer 312a and the first underlying layer 14 .
  • the high resistance layer 312b is made of, for example, an insulating or semi-insulating nitride semiconductor.
  • the impurity concentration (donor concentration) of the high resistance layer 312b is, for example, 1 ⁇ 10 16 cm ⁇ 3 or less.
  • the high resistance layer 312b is, for example, a film made of undoped GaN with a thickness of 200 nm.
  • the high resistance layer 312b contains carbon (C) or iron (Fe).
  • the carbon concentration or iron concentration of the high resistance layer 312b is, for example, in the range of 2 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less, and is 1 ⁇ 10 18 cm ⁇ 3 as an example. Note that other elements may be used as long as they are elements capable of increasing the resistance of GaN.
  • the bottom 40a of the groove 40 is located in the high resistance layer 312b. That is, the bottom portion 40a of the groove portion 40 is part of the upper surface of the high resistance layer 312b. This makes it easier for the depletion layer to extend in the lateral direction of the high-resistance layer 312b in the vicinity of the trench 40, thereby making it possible to alleviate the electric field. Therefore, the off characteristics of the nitride semiconductor device 301 can be improved.
  • FIG. 6 is a cross-sectional view of a nitride semiconductor device 302 according to a modification of this embodiment. As shown in FIG. 6, the nitride semiconductor device 302 has a trench 340 penetrating the high resistance layer 312b. That is, the bottom 340a of the groove 340 is part of the upper surface of the low resistance layer 312a. The bottom portion 340a is located below the interface between the high resistance layer 312b and the low resistance layer 312a.
  • the provision of the high resistance layer 312b prevents the pn junction between the first underlying layer 14 and the low resistance layer 312a during the reverse conduction operation of the transistor section 2. can make it difficult for current to flow through As a result, reverse conduction deterioration is suppressed, so deterioration of the OFF characteristics of the nitride semiconductor device 301 or 302 can be suppressed.
  • Embodiment 5 Next, Embodiment 5 will be described.
  • the fifth embodiment differs from the second embodiment in that a field plate is provided.
  • the following description focuses on the differences from the second embodiment, and omits or simplifies the description of the common points.
  • FIG. 7 is a cross-sectional view of a nitride semiconductor device 401 according to this embodiment.
  • nitride semiconductor device 401 includes an insulating film 436 and a field plate 438 in addition to the configuration of nitride semiconductor device 101 according to the second embodiment.
  • the insulating film 436 is provided along the inner surface of the trench 40 .
  • the insulating film 436 includes components other than the field plate 438 and the source electrode 28 (specifically, the gate electrode 30, the threshold adjustment layer 24, the semiconductor multilayer film 20, the first underlying layer 14 and the drift layer). 112) are provided for electrical isolation.
  • the insulating film 436 is formed by forming a film on the entire upper surface of the gate electrode 30 and the trench 40 after forming the gate electrode 30 and patterning so as to expose only a portion of the source electrode 28 . That is, the insulating film 436 has a contact hole for electrically connecting the source electrode 28 and the field plate 438 .
  • the insulating film 436 is, for example, a silicon oxide film, a silicon nitride film, or an aluminum oxide film.
  • the field plate 438 is provided above the insulating film 436 so as to protrude into the groove 40 . That is, the field plate 438 overlaps the bottom portion 40a of the groove portion 40 in plan view.
  • the field plate 438 is formed using a conductive material such as metal.
  • the field plate 438 can be made of the same material as the source electrode 28 .
  • field plate 438 is electrically connected to source electrode 28 . That is, the field plate 438 is supplied with the same potential as the source electrode 28 .
  • the electric field in the OFF state tends to concentrate at the intersection between the bottom portion 40 a and the side wall 40 b of the groove portion 40 , that is, at the corner portion of the groove portion 40 .
  • the field plate 438 is provided so as to protrude from the groove 40 , part of the electric field concentrated at the intersection of the bottom 40 a and the side wall 40 b can be dispersed to the protruding portion of the field plate 438 .
  • a pn junction including etching damage exists in the vicinity of the intersection between the bottom portion 40a and the side wall 40b, the off-characteristics of the nitride semiconductor device 401 are improved by alleviating the electric field concentration on the pn junction. can do.
  • the present invention is not limited to this.
  • the side wall 40b may be slanted.
  • FIG. 8 is a cross-sectional view of a nitride semiconductor device 402 according to Modification 1 of the present embodiment. As shown in FIG. 8 , nitride semiconductor device 402 includes trench 440 instead of trench 40 .
  • the groove portion 440 has a bottom portion 40a and sidewalls 440b.
  • Bottom portion 40 a is the same as in the second embodiment and the like, and is part of the upper surface of low-concentration layer 112 b of drift layer 112 .
  • the bottom portion 40 a is a surface parallel to the first main surface 10 a of the substrate 10 .
  • the side wall 440b is obliquely inclined with respect to the bottom portion 40a. As shown enlarged in FIG. 8, the tilt angle ⁇ is less than 90°. For example, the tilt angle ⁇ is 30° or more and 85° or less. Note that the inclination angle ⁇ is the smaller angle between the side wall 440b and the plane parallel to the first main surface 10a of the substrate 10 .
  • the coverage of the insulating film 436 formed along the inner surface of the trench 440 improves, so that the effect of alleviating electric field concentration on the pn junction near the trench 440 can be enhanced. Further, as the inclination angle .theta.
  • FIG. 9 is a cross-sectional view of a nitride semiconductor device 403 according to Modification 2 of the present embodiment.
  • FIG. 10 is a plan view of a nitride semiconductor device 403 according to Modification 2 of the present embodiment. 9 shows a cross section taken along line IX-IX in FIG.
  • the nitride semiconductor device 403 includes a drift layer 412 instead of the drift layer 112 compared to the nitride semiconductor device 402 according to Modification 1 of the present embodiment.
  • the drift layer 412 includes a high concentration layer 112a, a low concentration layer 112b, and a high resistance region 412d. High-concentration layer 112a and low-concentration layer 112b are the same as in the second embodiment.
  • the high resistance region 412d is a region into which impurities are introduced.
  • the high-resistance region 412d is a region having a higher resistance than its surroundings due to the introduction of impurities.
  • Impurities are eg magnesium (Mg), boron (B) or iron (Fe).
  • the high resistance region 412d is formed, for example, by ion implantation after the trench 40 is formed.
  • the high-resistance region 412d is provided in a ring shape along the bottom portion 40a of the groove portion 440, as shown in FIG. Specifically, the high resistance region 412 d includes the end surface of the nitride semiconductor device 403 .
  • a plurality of nitride semiconductor devices 403 are produced at the same time by singulating a semiconductor wafer. Specifically, crystal growth of each nitride semiconductor layer, formation of openings, regrowth of crystals of the nitride semiconductor film, formation of trenches 440, and formation of high-resistance regions 412d (ion implantation) on a semiconductor wafer (substrate 10). , and the formation of the source electrode 28 , the gate electrode 30 and the drain electrode 32 , the semiconductor wafer is singulated to form a plurality of nitride semiconductor devices 403 . Singulation is performed, for example, by dicing. At this time, dicing is performed along the high resistance region 412d. That is, the end face cut by dicing is the end face of the nitride semiconductor device 403, and the high resistance region 412d includes the end face.
  • the high-resistance region 412d is formed to include this end surface, so it is possible to suppress the occurrence of leak current.
  • Such a high-resistance region 412d may be formed in the groove portion 40 of the nitride semiconductor device according to Embodiments 1 to 4 and each modification.
  • the off characteristics of the nitride semiconductor device 401, 402 or 403 can be improved by providing the field plate 438.
  • the field plate 438 is electrically connected to the source electrode 28 in the present embodiment and modifications, the present invention is not limited to this.
  • the field plate 438 may be insulated from the source electrode 28 and may be separately supplied with the same potential as the source electrode 28 or a different potential.
  • the insulating film 436 is not provided with a contact hole for electrically connecting the source electrode 28 and the field plate 438 .
  • the nitride semiconductor device according to the configuration of the first, third or fourth embodiment or modifications thereof may include insulating film 436 and field plate 438 , and may include trench 440 .
  • the source opening 26 may not be provided.
  • the source electrode 28 is provided on the upper surface of the semiconductor multilayer film 20 at a position away from the threshold adjustment layer 24 .
  • the drift layer 12 may have a graded structure in which the impurity concentration (donor concentration) is gradually reduced from the substrate 10 side to the first underlayer 14 side.
  • the donor concentration may be controlled by Si as a donor, or by carbon as an acceptor that compensates for Si.
  • the number of layers of the drift layer was described as two or three layers, but the number of layers may be four or more.
  • the termination portion 3 does not have to include the end surface of the nitride semiconductor device 1 .
  • the termination portion 3 is a portion for separating the transistor portion 2 from other devices.
  • Another element may be arranged in a region adjacent to the terminal portion 3 of the transistor portion 2 .
  • another element is a pn diode utilizing a pn junction between the drift layer 12 and the first underlying layer 14 .
  • the nitride semiconductor device 1 may include a transistor portion 2, a termination portion 3, and a pn diode.
  • the first conductivity type may be p-type, p + type, or p ⁇ type
  • the second conductivity type may be n type, n + type, or n ⁇ type.
  • the present disclosure can be used as a nitride semiconductor device with improved off characteristics, and can be used, for example, in power devices such as power transistors used in power circuits of consumer equipment such as televisions.

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  • Junction Field-Effect Transistors (AREA)
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