WO2022172609A1 - Ａｉモジュール - Google Patents

Ａｉモジュール Download PDF

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Publication number
WO2022172609A1
WO2022172609A1 PCT/JP2021/047358 JP2021047358W WO2022172609A1 WO 2022172609 A1 WO2022172609 A1 WO 2022172609A1 JP 2021047358 W JP2021047358 W JP 2021047358W WO 2022172609 A1 WO2022172609 A1 WO 2022172609A1
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Prior art keywords
semiconductor chip
processing units
main surface
view
plan
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English (en)
French (fr)
Japanese (ja)
Inventor
幸嗣 小畑
勝 笹子
雅通 中川
達也 可部
寛之 後明
正朋 三橋
豊 園田
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Priority to US18/264,194 priority Critical patent/US20240038726A1/en
Priority to CN202180093204.2A priority patent/CN116830267A/zh
Priority to JP2022581225A priority patent/JPWO2022172609A1/ja
Publication of WO2022172609A1 publication Critical patent/WO2022172609A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/501—Inductive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/293—Configurations of stacked chips characterised by non-galvanic coupling between the chips, e.g. capacitive coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/859—Bump connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

  • This disclosure relates to AI modules.
  • Patent Document 1 discloses a multi-layer semiconductor stack in which a plurality of semiconductor dies having functional units such as processor cores are stacked.
  • the present disclosure provides an AI module capable of performing AI-based calculations with low power consumption.
  • An AI module includes a first semiconductor chip, the first semiconductor chip includes a plurality of first processing units each of which performs a predetermined operation, and a plurality of second processing units each including a memory. and a processing unit, wherein the plurality of first processing units and the plurality of second processing units are arranged in a checkered pattern or stripes in plan view.
  • computation based on AI can be performed with low power consumption.
  • FIG. 1 is a perspective view showing an overview of an AI module according to an embodiment.
  • FIG. 2 is a cross-sectional view of the AI module according to the embodiment.
  • 3A is a plan view showing the layout of the base chip of the AI module according to the embodiment;
  • FIG. 3B is a plan view showing the layout of the first semiconductor chip and the third semiconductor chip of the AI module according to the embodiment;
  • FIG. 3C is a plan view showing the layout of the second semiconductor chip and the fourth semiconductor chip of the AI module according to the embodiment;
  • FIG. FIG. 4 is a cross-sectional view showing a stacked state of four semiconductor chips of the AI module according to the embodiment.
  • FIG. 5 is a cross-sectional view showing a connection portion of a through electrode for power supply of the AI module according to the embodiment.
  • FIG. 6 is a flow chart showing the method of manufacturing the AI module according to the embodiment.
  • FIG. 7 is a plan view showing the layout of the base chip and each semiconductor chip of the AI module according to Modification 1 of the embodiment.
  • FIG. 8 is a plan view showing the layout of the base chip and each semiconductor chip of the AI module according to Modification 2 of the embodiment.
  • FIG. 9 is a cross-sectional view showing a stacked state of four semiconductor chips of an AI module according to Modification 2 of the embodiment.
  • FIG. 10 is a plan view showing the layout of the base chip and each semiconductor chip of the AI module according to Modification 3 of the embodiment.
  • FIG. 11 is a cross-sectional view showing a stacked state of four semiconductor chips of an AI module according to Modification 3 of the embodiment.
  • FIG. 12 is a plan view showing the layout of the base chip and each semiconductor chip of the AI module according to Modification 4 of the embodiment.
  • FIG. 13 is a cross-sectional view of an AI module according to Modification 5 of the embodiment.
  • FIG. 14 is a cross-sectional view of an AI module according to Modification 6 of the embodiment.
  • An AI module includes a first semiconductor chip, the first semiconductor chip includes a plurality of first processing units each of which performs a predetermined operation, and a plurality of second processing units each including a memory.
  • the plurality of first processing sections and the plurality of second processing sections are arranged in a checkered pattern or stripes in plan view.
  • the first processing unit that performs calculations and the second processing unit that includes a memory are arranged side by side in one semiconductor chip. distance can be shortened. As a result, the data movement distance between the first processing unit and the second processing unit is shortened, so power consumption can be reduced.
  • each of the plurality of first processing units may perform the calculation based on a machine learning model.
  • the AI module according to one aspect of the present disclosure further includes a second semiconductor chip stacked on the first semiconductor chip, and the second semiconductor chip includes a plurality of a third processing unit; and a plurality of fourth processing units each including a memory, and wherein the plurality of third processing units and the plurality of fourth processing units have a checkered pattern or stripes in plan view may be arranged in a pattern.
  • each of the plurality of third processing units may perform the calculation based on a machine learning model.
  • the first semiconductor chip may further include a first communication unit
  • the second semiconductor chip may further include a second communication unit that communicates with the first communication unit
  • TSV Through Silicon Via
  • each of the first communication unit and the second communication unit may include a coil-shaped antenna. Further, for example, the first communication unit and the second communication unit may perform the communication by magnetically coupling the mutual antennas.
  • a TSV may be used as the communication section.
  • the plurality of first processing units correspond to the plurality of third processing units on a one-to-one basis, and in plan view, the corresponding third processing
  • the plurality of second processing sections may correspond to the plurality of fourth processing sections on a one-to-one basis, and may overlap the corresponding fourth processing sections in plan view.
  • the first communication unit may overlap one of the plurality of second processing units in plan view, or the second communication unit may overlap the plurality of fourth processing units in plan view. may overlap one of the
  • a memory is formed by repeatedly arranging a predetermined pattern including wiring and a storage section. For this reason, it is easy to meet the restrictions for using near field coupling communication, such as removing the pattern only from the portion that overlaps with the coil-shaped antenna.
  • the second processing section, the fourth processing section, and the respective coil-shaped antennas are arranged so as to overlap each other in a plan view, so an area dedicated to the antenna is provided. Instead, it is possible to use proximity magnetic field coupling communication. Therefore, miniaturization of the semiconductor chip and reduction in power consumption can be realized.
  • the plurality of first processing units correspond to the plurality of fourth processing units on a one-to-one basis, and in plan view, the corresponding fourth processing
  • the plurality of second processing sections may correspond to the plurality of third processing sections on a one-to-one basis, and may overlap the corresponding third processing sections in plan view.
  • the first and third processing units that perform arithmetic generate more heat.
  • the first processing section and the third processing section are arranged so as not to overlap each other in plan view, heat is not concentrated locally, and heat can be efficiently dissipated. can.
  • the first semiconductor chip further includes one or more fifth processing units each including a memory
  • the second semiconductor chip further includes one or more sixth processing units each including a memory.
  • the one or more fifth processing units may correspond to the one or more sixth processing units on a one-to-one basis, and may overlap the corresponding sixth processing units in plan view.
  • the first communication unit overlaps one of the one or more fifth processing units in plan view
  • the second communication unit overlaps the one or more sixth processing units in plan view. may overlap one of the
  • the fifth processing unit, the sixth processing unit, and the respective coil-shaped antennas are arranged so as to overlap each other in a plan view, near-field coupling communication can be performed without providing an area dedicated to antennas. can be used. Therefore, miniaturization of the semiconductor chip and reduction in power consumption can be realized.
  • the first semiconductor chip further includes a first semiconductor substrate having a first main surface and a second main surface facing each other, and the plurality of first processing units and the plurality of second processing units is provided at a position closer to the first main surface than the second main surface of the first semiconductor substrate, and the second semiconductor chip further has a third main surface and a fourth main surface facing back to each other. wherein the plurality of third processing units and the plurality of fourth processing units are provided at a position closer to the third main surface than the fourth main surface of the second semiconductor substrate
  • the first semiconductor chip and the second semiconductor chip may be stacked such that the first main surface and the third main surface face each other.
  • the AI module according to each aspect described above is formed.
  • only one type of semiconductor chip is required, which contributes to simplification of design and cost reduction.
  • the AI module according to one aspect of the present disclosure further includes a third semiconductor chip stacked on the second semiconductor chip, and a fourth semiconductor chip stacked on the third semiconductor chip,
  • the third semiconductor chip includes a third semiconductor substrate having a fifth main surface and a sixth main surface facing each other, a plurality of seventh processing units each performing a predetermined operation, and a plurality of wherein the plurality of seventh processing sections and the plurality of eighth processing sections are positioned closer to the fifth main surface than to the sixth main surface of the third semiconductor substrate.
  • the fourth semiconductor chip having a seventh main surface and an eighth main surface facing each other; includes a plurality of ninth processing units that perform predetermined operations, and a plurality of tenth processing units each including a memory, wherein the plurality of ninth processing units and the plurality of tenth processing units are configured to 4 semiconductor substrate, provided at a position closer to the seventh main surface than the eighth main surface, and arranged in a checkered pattern or stripes in plan view, the third semiconductor chip and the third semiconductor chip;
  • the 4 semiconductor chips are stacked so that the fifth main surface and the seventh main surface face each other, and the second semiconductor chip and the third semiconductor chip are stacked so that the fourth main surface and the sixth main surface You may laminate
  • the AI module according to one aspect of the present disclosure may further include through electrodes penetrating through the first semiconductor chip for supplying power to the second semiconductor chip.
  • each figure is a schematic diagram and is not necessarily strictly illustrated. Therefore, for example, scales and the like do not necessarily match in each drawing. Moreover, in each figure, the same code
  • the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the stacking structure. It is used as a term defined by a relative positional relationship. Also, the terms “above” and “below” are used only when two components are spaced apart from each other and there is another component between the two components, as well as when two components are spaced apart from each other. It also applies when two components are in contact with each other and are placed in close contact with each other. In the following description of each embodiment, the direction in which the semiconductor chips are stacked with respect to the base chip is defined as “upward”, and the opposite direction is defined as “downward”.
  • ordinal numbers such as “first” and “second” do not mean the number or order of constituent elements unless otherwise specified, so as to avoid confusion between constituent elements of the same kind and to distinguish them from each other. It is used for the purpose of
  • FIG. 1 is a perspective view showing an overview of an AI module 1 according to this embodiment.
  • the AI module 1 shown in FIG. 1 is a device that performs calculations based on AI.
  • AI-based calculations include, for example, natural language processing, voice recognition processing, image recognition processing, recommendation processing, and control processing for various devices. Computation is performed based on, for example, machine learning or deep learning.
  • the AI module 1 includes an interposer 10, a base chip 20, and one or more semiconductor chips 100.
  • the AI module 1 includes a first semiconductor chip 101 , a second semiconductor chip 102 , a third semiconductor chip 103 and a fourth semiconductor chip 104 as one or more semiconductor chips 100 .
  • the interposer 10, base chip 20 and one or more semiconductor chips 100 are stacked in this order. It should be noted that FIG. 1 only schematically represents the positional relationship of each element, and does not illustrate the thickness of each element, for example. Also, although the one or more semiconductor chips 100 are illustrated as not in contact with each other, in reality, the one or more semiconductor chips 100 are in direct contact with adjacent ones. Alternatively, one or more semiconductor chips 100 may be in contact with each member with a member (for example, an insulating film) interposed therebetween.
  • a member for example, an insulating film
  • the interposer 10 is a relay component that relays electrical connection between the base chip 20 and a substrate (not shown).
  • the base chip 20 is an SoC (System on a Chip) supported by the interposer 10. A specific configuration of the base chip 20 will be described later with reference to FIG. 3A.
  • SoC System on a Chip
  • Each of the one or more semiconductor chips 100 includes a processing unit that performs AI-based calculations and a processing unit that includes a memory for storing programs or data necessary for calculations or calculation results.
  • Semiconductor chip 100 is also called a die. A specific configuration of one or more semiconductor chips 100 will be described later with reference to FIGS. 3B, 3C and 4. FIG.
  • FIG. 2 is a cross-sectional view of the AI module 1 according to this embodiment. Note that in the cross-sectional view shown in FIG. 2, the semiconductor substrate is not shaded to indicate the cross-section from the viewpoint of visibility of the drawing. The same applies to other cross-sectional views to be described later.
  • the AI module 1 further includes a DAF (Die Attach Film) 30, a plurality of through electrodes 40, a plurality of bump electrodes 50, a plurality of bonding pads 60, and a plurality of bonding wires 70. And prepare.
  • the number of each of the through electrode 40, the bump electrode 50, the bonding pad 60 and the bonding wire 70 may be one.
  • the DAF 30 is an adhesive film that bonds the interposer 10 and the base chip 20 together.
  • the through electrodes 40 are electrodes for supplying power to one or more semiconductor chips 100 .
  • the through electrode 40 penetrates at least one of the one or more semiconductor chips 100 .
  • a specific example of the through electrode 40 will be described later with reference to FIG.
  • the bump electrodes 50 are connected to the through electrodes 40 .
  • the bump electrode 50 is formed using, for example, a metal such as gold or an alloy such as solder.
  • the bump electrodes 50 not only supply power to the one or more semiconductor chips 100 via the through electrodes 40 but also support and fix the one or more semiconductor chips 100 .
  • the plurality of bump electrodes 50 may include those mainly having the function of supporting and fixing the semiconductor chip 100 without having the function of supplying power.
  • An insulating resin member may be provided between the base chip 20 and the first semiconductor chip 101 so as to fill the spaces between the plurality of bump electrodes 50 .
  • the bonding pads 60 are conductive terminal portions provided on the main surface of the base chip 20, and are portions to which the bonding wires 70 are connected.
  • the bonding pad 60 is part of a wiring pattern formed using a metal such as gold, copper, aluminum, or an alloy.
  • the bonding wires 70 are conductive wires that electrically connect the interposer 10 and the base chip 20 .
  • the bonding wires 70 are metal wires formed using metals or alloys such as gold, copper, and aluminum, for example.
  • the bonding wires 70 are provided for power supply or data transmission/reception to the base chip 20 and one or more semiconductor chips 100 .
  • FIG. 3A is a plan view showing the layout of the base chip 20 of the AI module 1 according to this embodiment.
  • the base chip 20 includes multiple operation blocks 210 and multiple memory blocks 220 .
  • the plurality of operation blocks 210 and the plurality of memory blocks 220 are arranged in a checkered pattern in plan view.
  • Each of the plurality of calculation blocks 210 is an example of a processing section that executes a predetermined calculation.
  • the predetermined operations include AI-based operations.
  • the predetermined operation may include logical operations other than AI. That is, at least one of the plurality of operation blocks 210 is an AI accelerator circuit that performs AI-based operations.
  • operation block 210 performs at least one of convolution operations, matrix operations, and pooling operations. Arithmetic block 210 performs operations based on the machine learning model.
  • the arithmetic block 210 may include a logarithmic processing circuit.
  • the logarithmic processing circuit performs operations on logarithmically quantized input data. Specifically, the logarithmic processing circuit performs a convolution operation on logarithmically quantized input data.
  • the multiplication processing included in the convolution operation can be executed by addition processing by converting the data to be operated into the logarithmic domain. As a result, speeding up of calculation based on AI is realized.
  • the calculation performed by the calculation block 210 may include an error diffusion method using dither.
  • operational block 210 may include a dither circuit.
  • the dither circuit performs calculations using error diffusion techniques. As a result, even with a small number of bits, it is possible to suppress the deterioration of the accuracy of calculation.
  • One or more operation blocks 210 among the plurality of operation blocks 210 may be an operation circuit that performs logical operation.
  • Each of the plurality of memory blocks 220 includes memory.
  • Memory block 220 includes, for example, SRAM (Static Random Access Memory).
  • the memory block 220 stores data and/or calculation results used in the calculations of the calculation block 210 .
  • the memory included in the memory block 220 may be a DRAM (Dynamic Random Access Memory) or a NAND flash memory.
  • the base chip 20 includes a CPU (Central Processing Unit) 230, a DSP (Digital Signal Processor) 240, an ISP (Image Signal Processor) 250, a functional circuit 260, and peripheral device inputs. It comprises output interfaces 270 and 280 and a memory interface 290 . Note that the base chip 20 may not include at least one of these components. Also, the arrangement of each component is not limited to the example shown in FIG. 3A.
  • the CPU 230 is a processor that controls the AI module 1 as a whole. Specifically, the CPU 230 transmits and receives data and signals between the base chip 20 and one or more semiconductor chips 100, and executes operations and instructions.
  • the DSP 240 is a processor that performs digital signal processing related to AI-based calculations.
  • the ISP 250 is a signal processing circuit that processes image signals or video signals.
  • the function circuit 260 is a circuit that realizes a predetermined function executed by the AI module 1.
  • the peripheral device input/output interfaces 270 and 280 are interfaces for transmitting and receiving data and signals with devices other than the AI module 1 .
  • the peripheral input/output interface 270 may be, but is not limited to, a QSPI (Quad Serial Peripheral Interface), a GPIO (General Purpose Input/Output), or a debug interface.
  • the peripheral device input/output interface 280 is MIPI (Mobile Industry Processor Interface) or PCIe (Peripheral Component Interconnect-Express), but is not limited to these.
  • the memory interface 290 is a DRAM interface provided outside the AI module 1 .
  • the memory interface 290 is an interface conforming to the LPDDR (Low Power Double Data Rate) standard, but is not limited to this.
  • Active region 21 is a region including one of the two main surfaces of the semiconductor substrate forming base chip 20 .
  • a first semiconductor chip 101, a second semiconductor chip 102, a third semiconductor chip 103 and a fourth semiconductor chip 104 are provided as the plurality of semiconductor chips 100.
  • FIG. The first semiconductor chip 101, the second semiconductor chip 102, the third semiconductor chip 103, and the fourth semiconductor chip 104 are stacked above the base chip 20 in this order.
  • FIG. 3B is a plan view showing the layout of the first semiconductor chip 101 and the third semiconductor chip 103 of the AI module 1 according to this embodiment.
  • FIG. 3C is a plan view showing the layout of the second semiconductor chip 102 and the fourth semiconductor chip 104 of the AI module 1 according to this embodiment. 3B and 3C both show a planar layout when each semiconductor chip is viewed from above in a state of being stacked on the base chip 20.
  • FIG. 3B is a plan view showing the layout of the first semiconductor chip 101 and the third semiconductor chip 103 of the AI module 1 according to this embodiment.
  • FIG. 3C is a plan view showing the layout of the second semiconductor chip 102 and the fourth semiconductor chip 104 of the AI module 1 according to this embodiment.
  • 3B and 3C both show a planar layout when each semiconductor chip is viewed from above in a state of being stacked on the base chip 20.
  • FIG. 4 is a cross-sectional view showing a stacked state of four semiconductor chips of the AI module 1 according to the embodiment. Specifically, FIG. 4 shows the stacked state of the first semiconductor chip 101, the second semiconductor chip 102, the third semiconductor chip 103, and the fourth semiconductor chip 104. As shown in FIG.
  • the first semiconductor chip 101 includes a plurality of operation blocks 211 and a plurality of memory blocks 221, as shown in FIGS. 3B and 4.
  • the calculation block 211 is an example of a first processing unit that executes predetermined calculations such as AI-based calculations.
  • Operational block 211 is, for example, the same as operational block 210 and performs operations based on a machine learning model.
  • the memory block 221 is an example of a second processing section including memory.
  • Memory block 221 is, for example, the same as memory block 220 and includes SRAM.
  • the first semiconductor chip 101 includes a first semiconductor substrate 111 and a first active area 121 .
  • the first semiconductor substrate 111 has a front main surface 111a and a back main surface 111b facing each other.
  • the front main surface 111a is an example of a first main surface.
  • the back main surface 111b is an example of a second main surface.
  • the first semiconductor substrate 111 is, for example, a silicon substrate.
  • the first active area 121 is an area in which a plurality of operation blocks 211 and a plurality of memory blocks 221 are provided.
  • the first active region 121 is a region including the front main surface 111a. That is, the plurality of operation blocks 211 and the plurality of memory blocks 221 are provided at positions closer to the front main surface 111a than the back main surface 111b.
  • the "active area” is an operating area where the main functions of the semiconductor chip are exhibited.
  • a plurality of circuit elements such as transistors, capacitors, inductors, resistors or diodes are formed in the active area.
  • An operation block and a memory block are formed by electrically connecting a plurality of circuit elements with wiring.
  • the second semiconductor chip 102 includes multiple operation blocks 212 and multiple memory blocks 222, as shown in FIGS. 3C and 4 .
  • the calculation block 212 is an example of a third processing unit that executes predetermined calculations such as AI-based calculations.
  • the calculation block 212 is the same as the calculation block 211, for example, and performs calculations based on the machine learning model.
  • Memory block 222 is an example of a fourth processing unit that includes memory. Memory block 222 is, for example, the same as memory block 221 and includes SRAM.
  • the second semiconductor chip 102 includes a second semiconductor substrate 112 and a second active area 122 .
  • the second semiconductor substrate 112 has a front main surface 112a and a back main surface 112b facing each other.
  • the front main surface 112a is an example of a third main surface.
  • the back main surface 112b is an example of a fourth main surface.
  • the second semiconductor substrate 112 is, for example, a silicon substrate.
  • the second active area 122 is an area in which a plurality of operation blocks 212 and a plurality of memory blocks 222 are provided.
  • the second active region 122 is a region including the front main surface 112a. That is, the plurality of operation blocks 212 and the plurality of memory blocks 222 are provided at positions closer to the front main surface 112a than the back main surface 112b.
  • the third semiconductor chip 103 includes a plurality of operation blocks 213 and a plurality of memory blocks 223, as shown in FIGS. 3B and 4.
  • the calculation block 213 is an example of a seventh processing unit that executes predetermined calculations such as AI-based calculations.
  • the calculation block 213 is the same as the calculation block 211, for example, and performs calculations based on the machine learning model.
  • the memory block 223 is an example of an eighth processing unit including memory.
  • Memory block 223 is, for example, the same as memory block 221 and includes SRAM.
  • the third semiconductor chip 103 includes a third semiconductor substrate 113 and a third active area 123 .
  • the third semiconductor substrate 113 has a front main surface 113a and a back main surface 113b facing each other.
  • the front main surface 113a is an example of a fifth main surface.
  • the back main surface 113b is an example of a sixth main surface.
  • the third semiconductor substrate 113 is, for example, a silicon substrate.
  • the third active area 123 is an area in which a plurality of operation blocks 213 and a plurality of memory blocks 223 are provided. Specifically, the third active region 123 is a region including the front main surface 113a. That is, the plurality of operation blocks 213 and the plurality of memory blocks 223 are provided at positions closer to the front main surface 113a than the back main surface 113b.
  • the fourth semiconductor chip 104 includes a plurality of operation blocks 214 and a plurality of memory blocks 224, as shown in FIGS. 3C and 4.
  • the calculation block 214 is an example of a ninth processing unit that executes predetermined calculations such as AI-based calculations. Arithmetic block 214 is, for example, the same as computational block 211 and performs computations based on machine learning models.
  • Memory block 224 is an example of a tenth processing unit that includes memory. Memory block 224 is, for example, the same as memory block 221 and includes SRAM.
  • the fourth semiconductor chip 104 includes a fourth semiconductor substrate 114 and a fourth active area 124 .
  • the fourth semiconductor substrate 114 has a front main surface 114a and a back main surface 114b facing each other.
  • the front main surface 114a is an example of a seventh main surface.
  • the back main surface 114b is an example of an eighth main surface.
  • the fourth semiconductor substrate 114 is, for example, a silicon substrate.
  • the fourth active area 124 is an area in which a plurality of operation blocks 214 and a plurality of memory blocks 224 are provided. Specifically, the fourth active region 124 is a region including the front main surface 114a. That is, the plurality of operation blocks 214 and the plurality of memory blocks 224 are provided at positions closer to the front main surface 114a than the back main surface 114b.
  • the first semiconductor chip 101 and the third semiconductor chip 103 have the same layout.
  • the plurality of operation blocks 211 and the plurality of memory blocks 221 are arranged in a checker pattern (matrix or grid is synonymous) in plan view.
  • the operation blocks 211 and the memory blocks 221 are alternately arranged one by one along the row direction (horizontal direction) and the column direction (vertical direction).
  • a plurality of operation blocks 211 and memory blocks 221 may be alternately arranged along at least one of the row direction and the column direction.
  • the second semiconductor chip 102 and the fourth semiconductor chip 104 have the same layout.
  • the plurality of operation blocks 212 and the plurality of memory blocks 222 are arranged in a checkered pattern (matrix or grid is also synonymous) in plan view.
  • the arrangement of the operation blocks 210 and the memory blocks 220 included in the base chip 20 is also the same as the arrangement of the operation blocks 212 and the memory blocks 222 included in the second semiconductor chip 102 .
  • the plurality of operation blocks 211 of the first semiconductor chip 101 correspond one-to-one to the plurality of memory blocks 222 of the second semiconductor chip 102, and overlap the corresponding memory blocks 222 in plan view.
  • the plurality of memory blocks 221 of the first semiconductor chip 101 correspond one-to-one to the plurality of operation blocks 212 of the second semiconductor chip 102, and overlap the corresponding operation blocks 212 in plan view. In other words, the operation blocks and the memory blocks do not overlap in plan view.
  • one operation block and the other memory block overlap in plan view, and the operation blocks and the memory blocks do not overlap.
  • one operation block and the other memory block overlap in plan view, and the operation blocks and the memory blocks do not overlap.
  • the base chip 20 and the first semiconductor chip 101 one operation block and the other memory block overlap in plan view, and the operation blocks and the memory blocks do not overlap.
  • each of the second semiconductor chip 102 and the fourth semiconductor chip 104 has a configuration in which the first semiconductor chip 101 (or the third semiconductor chip 103) is turned over.
  • the first semiconductor chip 101 and the second semiconductor chip 102 are stacked such that their front main surfaces 111a and 112a face each other.
  • the third semiconductor chip 103 and the fourth semiconductor chip 104 are stacked such that their front main surfaces 113a and 114a face each other.
  • the second semiconductor chip 102 and the third semiconductor chip 103 are stacked such that their back side main surfaces 112b and 113b face each other.
  • the AI module 1 by stacking a plurality of semiconductor chips 100, it is possible to increase the computing power and memory capacity. Further, since the operation block and the memory block are adjacent to each other in each of the semiconductor chips 100 and the base chip 20, the data movement distance can be shortened, and power consumption can be reduced.
  • two adjacent semiconductor chips 100 are configured so that one operation block overlaps the other memory block.
  • operation blocks that tend to generate heat do not overlap each other, heat is not concentrated locally, and heat can be efficiently dissipated.
  • each of the base chip 20 and the plurality of semiconductor chips 100 includes a communication section for transmitting and receiving data and signals to and from each other.
  • communication is performed by proximity magnetic field coupling communication.
  • the base chip 20 and the plurality of semiconductor chips 100 each include an antenna magnetically coupled to each other.
  • the active area 21 of the base chip 20 is provided with a coil-shaped antenna 130 .
  • a coil-shaped antenna 131 is provided in the first active region 121 of the first semiconductor chip 101 .
  • a coil-shaped antenna 132 is provided in the second active region 122 of the second semiconductor chip 102 .
  • a coil-shaped antenna 133 is provided in the third active region 123 of the third semiconductor chip 103 .
  • a coil-shaped antenna 134 is provided in the fourth active region 124 of the fourth semiconductor chip 104 .
  • each active area is provided with a communication control circuit for wireless communication.
  • the antennas 130 to 134 can communicate by magnetic field coupling with each other.
  • the antennas 130 to 134 are provided at positions overlapping each other in plan view.
  • the antennas 130 to 134 are provided so that their coil axes are common.
  • Each of the antennas 130-134 is, for example, a pattern antenna formed into a coil by metal wiring in the corresponding active area.
  • each of the first semiconductor substrate 111, the second semiconductor substrate 112 and the third semiconductor substrate 113 is, for example, 15 ⁇ m.
  • the thickness of the fourth semiconductor substrate 114 is, for example, 100 ⁇ m.
  • the distance (the height of the bump electrode 50) between the back side main surface 111b of the first semiconductor substrate 111 and the front side main surface of the base chip 20 is, for example, 20 ⁇ m. Therefore, the distance between the antenna 130 of the base chip 20 and the antenna 134 of the fourth semiconductor chip 104, which is the farthest antenna, is about 65 ⁇ m, which is set within a range in which near field coupling communication can be performed. Note that these dimensions are merely examples and are not particularly limited.
  • FIG. 5 is a cross-sectional view showing the connecting portion of the through electrode for power supply of the AI module 1 according to the present embodiment. Two through electrodes 41 and 42 are shown in FIG.
  • the through electrode 41 is a through electrode for supplying power to the third semiconductor chip 103 and the fourth semiconductor chip 104, and is the same as the through electrode 40 shown in FIG.
  • the through electrode 41 is a so-called TSV.
  • the through electrode 41 is formed using conductive polysilicon or a metal material such as copper.
  • the through electrode 41 is connected to a terminal portion 143 provided in the third active region 123 and a terminal portion 144 provided in the fourth active region 124 .
  • Each of the terminal portions 143 and 144 is part of a wiring pattern formed using a metal such as gold, copper, aluminum, or an alloy. Power is supplied to the operation block and the memory block via the terminal section 143 or 144 .
  • the through electrode 42 is a through electrode for supplying power to the first semiconductor chip 101 and the second semiconductor chip 102 .
  • the through electrode 42 is a so-called TSV.
  • the through electrode 42 is formed using conductive polysilicon or a metal material such as copper.
  • the through electrode 42 is connected to the terminal portion 141 provided in the first active region 121 and the terminal portion 142 provided in the second active region 122 .
  • Each of the terminal portions 141 and 142 is part of a wiring pattern formed using a metal such as gold, copper, aluminum, or an alloy. Power is supplied to the operation block and the memory block via the terminal section 141 or 142 .
  • the through electrodes 41 for the third semiconductor chip 103 and the fourth semiconductor chip 104 and the through electrodes 42 for the first semiconductor chip 101 and the second semiconductor chip 102 are separately provided. As a result, power can be supplied to each semiconductor chip with sufficient accuracy.
  • the through electrode 42 may not be provided, and the through electrode 41 may also be connected to the terminal portions 141 and 142 . In this case, the terminal portions 141 to 144 are provided at positions overlapping each other in plan view.
  • FIG. 6 is a flow chart showing the manufacturing method of the AI module 1 according to this embodiment.
  • a plurality of (here, four) semiconductor wafers provided with a plurality of operation blocks and a plurality of memory blocks are prepared (S10).
  • the operation block and memory block can be formed by a semiconductor process such as a CMOS process, for example.
  • polishing is, for example, at least one of back grinding (BG) processing and CMP (Chemical Mechanical Polishing).
  • the insulating process is, for example, deposition of an insulating film such as a silicon oxide film.
  • the back side main surface (top surface or bottom surface) of one of the stacks is polished and insulated. Processing is performed (S30). As a result, a stack of four semiconductor wafers corresponding to the first semiconductor chip 101, the second semiconductor chip 102, the third semiconductor chip 103, and the fourth semiconductor chip 104 is formed.
  • through electrodes 40 are formed (S40). Specifically, after forming a through-hole by removing a part of the semiconductor wafer by etching, the inner surface of the through-hole is protected with an insulating film, and the through-electrode 40 is formed by filling the through-hole with a conductive material. Form.
  • a rewiring layer is formed on the back main surface 111b of the first semiconductor chip 101 to form the bump electrodes 50 (S50).
  • the stack of semiconductor wafers is singulated (S60). Thereby, a plurality of stacked bodies of the first semiconductor chip 101, the second semiconductor chip 102, the third semiconductor chip 103, and the fourth semiconductor chip 104 can be formed. Note that the surface on which the rewiring layer is not formed may be polished before singulation.
  • the individualized laminate is stacked on the base chip 20 (S70).
  • the AI module 1 shown in FIG. 2 is manufactured. Note that the manufacturing method shown here is merely an example, and is not particularly limited.
  • Modifications 1 to 4 differ from the embodiment in the layout of operation blocks and memory blocks.
  • Modifications 5 and 6 differ from the embodiment in the number of stacked semiconductor chips. The following description focuses on the differences from the first embodiment, and omits or simplifies the description of the common points.
  • FIG. 7 is a plan view showing the layout of the base chip 320 and each semiconductor chip of the AI module according to this modification.
  • “#1" represents the first layer (that is, base chip) of the operation block and memory block.
  • “#2" to “#5" represent the stacking order of the semiconductor chips when the base chip is the first layer. The same applies to FIGS. 8, 10 and 12, which will be described later.
  • the plurality of operation blocks and the plurality of memory blocks are arranged in stripes.
  • one operation block and one memory block are alternately arranged along the row direction.
  • the operation block and the memory block each have blocks of the same kind arranged in series along the column direction.
  • a plurality of operation blocks and memory blocks may be alternately arranged along the row direction.
  • the base chip 320, the second semiconductor chip 302 and the fourth semiconductor chip 304 have the same layout, and the first semiconductor chip 301 and the third semiconductor chip 303 have the same layout.
  • the cross section along line IV-IV in FIG. 7 becomes the same as the cross section shown in FIG. Therefore, as in the embodiment, since the operation blocks that tend to generate heat do not overlap each other, the heat is not concentrated locally, and the heat can be efficiently dissipated. Further, since the operation block and the memory block are adjacent to each other in each semiconductor chip and base chip 420, the data movement distance can be shortened, and power consumption can be reduced.
  • FIG. 8 is a plan view showing the layout of the base chip 420 and each semiconductor chip of the AI module according to this modification.
  • FIG. 9 is a cross-sectional view showing a stacked state of four semiconductor chips of an AI module according to this modification.
  • FIG. 9 shows a cross section along line IX-IX in FIG.
  • the plurality of operation blocks and the plurality of memory blocks are arranged in stripes.
  • the arrangement of the plurality of operation blocks and the plurality of memory blocks are the same. is. That is, the plurality of operation blocks 211 of the first semiconductor chip 401 correspond one-to-one to the plurality of operation blocks 212 of the second semiconductor chip 402, and overlap the corresponding operation blocks 212 in plan view. Similarly, the plurality of memory blocks 221 of the first semiconductor chip 401 correspond one-to-one to the plurality of memory blocks 222 of the second semiconductor chip 402, and overlap the corresponding memory blocks 222 in plan view. In other words, the operation blocks overlap each other and the memory blocks overlap each other in plan view.
  • the operation blocks and the memory blocks overlap each other.
  • the operation blocks and the memory blocks overlap each other.
  • the operation blocks and the memory blocks overlap each other.
  • the base chip 420 and the first semiconductor chip 401 operation blocks and memory blocks overlap each other.
  • a communication unit is provided at a position overlapping the memory block in plan view.
  • the memory block 221 and the coiled antenna 131 overlap.
  • the second semiconductor chip 402, the third semiconductor chip 403, and the fourth semiconductor chip 404 as well.
  • the antennas 131 to 134 and the memory blocks 221 to 224 overlap each other in plan view.
  • An antenna (not shown) provided on the base chip 420 similarly overlaps the antennas 131 to 134 in plan view.
  • the memory blocks 221 to 224 are usually formed by repeatedly arranging a predetermined pattern including wiring and memory portions. Therefore, it is easy to change the design, such as removing the repeated pattern from only the portions overlapping the antennas 131-134.
  • the communication section can be arranged so as to overlap the memory block, there is no need to provide a dedicated area for the communication section in a plan view, and the miniaturization of the semiconductor chip, that is, the miniaturization of the AI module can be achieved. can be realized. Moreover, power consumption can be reduced by using proximity magnetic field coupling communication. In addition, as in the embodiment and modification 1, power consumption can be reduced by shortening the data movement distance.
  • FIG. 10 is a plan view showing the layout of the base chip 520 and each semiconductor chip of the AI module according to this modification.
  • FIG. 11 is a cross-sectional view showing a stacked state of two semiconductor chips of an AI module according to this modification.
  • FIG. 11 shows a cross section along line XI--XI in FIG.
  • the first semiconductor chip 501 includes multiple memory blocks 521 in addition to the configuration of the first semiconductor chip 101 .
  • the number of memory blocks 521 may be only one, or may be three or more.
  • Memory block 521 is an example of a fifth processing unit that includes memory.
  • a plurality of memory blocks 521 are provided in the center of the first semiconductor chip 501 .
  • the plurality of memory blocks 521 are provided in the center in the row direction within the arrangement area of 4 rows and 4 columns configured by the operation blocks 211 and the memory blocks 221 .
  • each of the plurality of memory blocks 521 has a rectangular shape elongated in the column direction in plan view, and is arranged continuously in the column direction.
  • the plurality of memory blocks 521 may have a rectangular shape elongated in the row direction, and may be arranged continuously in the row direction at the center in the column direction within an arrangement area of 4 rows and 4 columns.
  • the operation block 211 and the memory block 221 may be arranged so as to surround the memory block 521 on the top, bottom, left, and right.
  • the memory blocks 521 may be arranged diagonally.
  • the second semiconductor chip 502 includes a plurality of memory blocks 522 in addition to the configuration of the second semiconductor chip 102 . Note that the number of memory blocks 522 may be only one, or may be three or more. Memory block 522 is an example of a sixth processing unit that includes memory.
  • the shape, number and arrangement of the multiple memory blocks 522 are the same as the multiple memory blocks 521 .
  • the plurality of memory blocks 522 correspond to the plurality of memory blocks 521 one-to-one, and overlap the corresponding memory blocks 521 in plan view.
  • the third semiconductor chip 503 includes a plurality of memory blocks 523 in addition to the configuration of the third semiconductor chip 103 .
  • the number of memory blocks 523 may be only one, or may be three or more.
  • Memory block 523 is an example of a processing unit that includes memory. The shape, number and arrangement of the plurality of memory blocks 523 are the same as those of the plurality of memory blocks 521 .
  • the fourth semiconductor chip 504 includes a plurality of memory blocks 524 in addition to the configuration of the fourth semiconductor chip 104 .
  • the number of memory blocks 524 may be only one, or may be three or more.
  • Memory block 524 is an example of a processing unit that includes memory.
  • the shape, number and arrangement of the plurality of memory blocks 524 are the same as those of the plurality of memory blocks 521 .
  • the plurality of memory blocks 524 correspond to the plurality of memory blocks 523 on a one-to-one basis, and overlap the corresponding memory blocks 523 in plan view.
  • the base chip 520 includes a plurality of memory blocks 525 in addition to the configuration of the base chip 20 shown in FIG. 3A. Note that the number of memory blocks 525 may be only one, or may be three or more. The shape, number and arrangement of the plurality of memory blocks 525 are the same as those of the plurality of memory blocks 521 .
  • a communication unit is provided at a position overlapping the memory blocks 521 to 524 in plan view.
  • the memory block 521 and the coiled antenna 131 overlap.
  • the antennas 131-134 and the memory blocks 521-524 overlap each other in plan view.
  • An antenna (not shown) provided on the base chip 520 similarly overlaps the antennas 131 to 134 in plan view.
  • the communication section can be arranged overlapping the memory blocks 521 to 524 in the same manner as in Modification 2, so there is no need to provide a dedicated area for the communication section in a plan view, and the size of the semiconductor chip can be reduced.
  • a miniaturization of the AI module can be realized.
  • power consumption can be reduced by using proximity magnetic field coupling communication.
  • power consumption can be reduced by shortening the data movement distance.
  • this modification as in the embodiment and modification 1, since the operation blocks do not overlap each other in a plan view, heat is not concentrated locally, and heat can be efficiently dissipated.
  • FIG. 12 is a plan view showing the layout of the base chip 620 and each semiconductor chip of the AI module according to this modification.
  • a first semiconductor chip 601, a second semiconductor chip 602, a third semiconductor chip 603, a fourth semiconductor chip 604, and a base chip 620 are respectively the first semiconductor chip 401 and the second semiconductor chip 401 according to Modification 1. It has a configuration in which a memory block 521, 522, 523, 524 or 525 is added to each of the second semiconductor chip 402, the third semiconductor chip 403, the fourth semiconductor chip 404 and the base chip 420. FIG. In this case, an effect similar to that of Modification 3 can be obtained.
  • FIG. 13 is a cross-sectional view of an AI module 700 according to this modification.
  • the AI module 700 differs in the number of laminated semiconductor chips from the AI module 1 according to the embodiment.
  • the AI module 700 has two semiconductor chips 100 .
  • the two semiconductor chips 100 and the base chip 20 may be combinations of the semiconductor chips and base chips shown in Modifications 1 to 4, respectively.
  • the AI module 700 shown in FIG. 13 is formed, for example, by omitting step S30 in the manufacturing method shown in FIG.
  • FIG. 14 is a cross-sectional view of an AI module 800 according to this modification.
  • the AI module 800 differs in the number of laminated semiconductor chips from the AI module 1 according to the embodiment.
  • AI module 800 comprises only one semiconductor chip 100 .
  • the semiconductor chip 100 and the base chip 20 may each be a combination of the first semiconductor chip and the base chip shown in Modifications 1-4.
  • the AI module 800 shown in FIG. 14 is formed, for example, by omitting steps S20 to S40 in the manufacturing method shown in FIG.
  • an AI module may not include a base chip and an interposer.
  • the AI module may be a single semiconductor chip itself.
  • the AI module may be the base chip itself, and may not include a semiconductor chip stacked on the base chip.
  • the number and arrangement of operation blocks and memory blocks provided in each semiconductor chip are not limited to the examples shown in the embodiment and modifications.
  • the numbers of operation blocks and memory blocks may be different from each other.
  • the shape of the operation block and the memory block may be different from each other.
  • the shape of the operation block and the memory block may be rectangular or polygonal instead of square.
  • the arrangement of operation blocks and memory blocks in the first semiconductor chip may be different from the arrangement of operation blocks and memory blocks in the third semiconductor chip.
  • the arrangement of operation blocks and memory blocks in the second semiconductor chip may be different from the arrangement of operation blocks and memory blocks in the fourth semiconductor chip.
  • the first semiconductor chip 101 and the second semiconductor chip 102 according to the embodiment may be combined with the third semiconductor chip and the fourth semiconductor chip according to any one of the modifications 1-4.
  • the communication unit has shown an example including a magnetically coupled coiled antenna, but is not limited to this.
  • the communication unit may perform wired communication using the through electrodes.
  • the present disclosure can be used as an AI module that can perform AI-based calculations with low power consumption, and can be used, for example, in various electrical appliances and computer equipment.

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