JPWO2022172609A1 - - Google Patents

Info

Publication number
JPWO2022172609A1
JPWO2022172609A1 JP2022581225A JP2022581225A JPWO2022172609A1 JP WO2022172609 A1 JPWO2022172609 A1 JP WO2022172609A1 JP 2022581225 A JP2022581225 A JP 2022581225A JP 2022581225 A JP2022581225 A JP 2022581225A JP WO2022172609 A1 JPWO2022172609 A1 JP WO2022172609A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2022581225A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2022172609A1 publication Critical patent/JPWO2022172609A1/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/501—Inductive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/293—Configurations of stacked chips characterised by non-galvanic coupling between the chips, e.g. capacitive coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/859—Bump connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Medical Informatics (AREA)
  • Data Mining & Analysis (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Artificial Intelligence (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2022581225A 2021-02-10 2021-12-21 Pending JPWO2022172609A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021019828 2021-02-10
PCT/JP2021/047358 WO2022172609A1 (ja) 2021-02-10 2021-12-21 Ａｉモジュール

Publications (1)

Publication Number Publication Date
JPWO2022172609A1 true JPWO2022172609A1 (https=) 2022-08-18

Family

ID=82838666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022581225A Pending JPWO2022172609A1 (https=) 2021-02-10 2021-12-21

Country Status (4)

Country Link
US (1) US20240038726A1 (https=)
JP (1) JPWO2022172609A1 (https=)
CN (1) CN116830267A (https=)
WO (1) WO2022172609A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12557301B2 (en) 2022-08-10 2026-02-17 Changxin Memory Technologies, Inc. Method for fabricating semiconductor structure, semiconductor structure, and semiconductor device
CN117636917A (zh) * 2022-08-10 2024-03-01 长鑫存储技术有限公司 半导体结构和半导体器件

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5499581A (en) * 1978-01-24 1979-08-06 Nippon Telegr & Teleph Corp <Ntt> Arrangement decision device
JPH04137757A (ja) * 1990-09-28 1992-05-12 Fujitsu Ltd ウエハスケール集積回路装置の製造方法
JPH07219919A (ja) * 1994-01-28 1995-08-18 Mitsubishi Electric Corp 数値演算処理装置
JP2012156186A (ja) * 2011-01-24 2012-08-16 Keio Gijuku 積層型半導体集積回路装置
WO2012157167A1 (ja) * 2011-05-17 2012-11-22 パナソニック株式会社 三次元集積回路、プロセッサ、半導体チップおよび三次元集積回路の製造方法
JP2015176435A (ja) * 2014-03-17 2015-10-05 国立研究開発法人産業技術総合研究所 Ｌｓｉチップ積層システム
US20180173600A1 (en) * 2016-12-21 2018-06-21 Invensas Corporation Self Healing Compute Array
JP2019505065A (ja) * 2015-11-30 2019-02-21 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ ニューロシナプティック・チップ３次元集積回路の形成方法、ニューロシナプティック・チップ３次元集積装置およびニューロシナプティック・チップ３次元集積回路
US20190318230A1 (en) * 2018-04-17 2019-10-17 Samsung Electronics Co., Ltd. Neuromorphic circuit having 3d stacked structure and semiconductor device having the same
WO2021009586A1 (ja) * 2019-07-12 2021-01-21 株式会社半導体エネルギー研究所 積和演算回路と記憶装置を有する半導体装置、電子部品、および電子機器

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8330489B2 (en) * 2009-04-28 2012-12-11 International Business Machines Corporation Universal inter-layer interconnect for multi-layer semiconductor stacks

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5499581A (en) * 1978-01-24 1979-08-06 Nippon Telegr & Teleph Corp <Ntt> Arrangement decision device
JPH04137757A (ja) * 1990-09-28 1992-05-12 Fujitsu Ltd ウエハスケール集積回路装置の製造方法
JPH07219919A (ja) * 1994-01-28 1995-08-18 Mitsubishi Electric Corp 数値演算処理装置
JP2012156186A (ja) * 2011-01-24 2012-08-16 Keio Gijuku 積層型半導体集積回路装置
WO2012157167A1 (ja) * 2011-05-17 2012-11-22 パナソニック株式会社 三次元集積回路、プロセッサ、半導体チップおよび三次元集積回路の製造方法
JP2015176435A (ja) * 2014-03-17 2015-10-05 国立研究開発法人産業技術総合研究所 Ｌｓｉチップ積層システム
JP2019505065A (ja) * 2015-11-30 2019-02-21 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ ニューロシナプティック・チップ３次元集積回路の形成方法、ニューロシナプティック・チップ３次元集積装置およびニューロシナプティック・チップ３次元集積回路
US20180173600A1 (en) * 2016-12-21 2018-06-21 Invensas Corporation Self Healing Compute Array
US20190318230A1 (en) * 2018-04-17 2019-10-17 Samsung Electronics Co., Ltd. Neuromorphic circuit having 3d stacked structure and semiconductor device having the same
WO2021009586A1 (ja) * 2019-07-12 2021-01-21 株式会社半導体エネルギー研究所 積和演算回路と記憶装置を有する半導体装置、電子部品、および電子機器

Also Published As

Publication number Publication date
WO2022172609A1 (ja) 2022-08-18
US20240038726A1 (en) 2024-02-01
CN116830267A (zh) 2023-09-29

Similar Documents

Publication Publication Date Title
BR112023005462A2 (https=)
BR112023012656A2 (https=)
BR112021014123A2 (https=)
BR112023009656A2 (https=)
BR112022009896A2 (https=)
BR112021017747A2 (https=)
BR112022024743A2 (https=)
JPWO2022172609A1 (https=)
BR112022026905A2 (https=)
BR112023011738A2 (https=)
BR112023004146A2 (https=)
BR112023006729A2 (https=)
BR102021018859A2 (https=)
BR102021015500A2 (https=)
BR102021007058A2 (https=)
BR102020022030A2 (https=)
BR112023016292A2 (https=)
BR112023011539A2 (https=)
BR112023011610A2 (https=)
BR112023008976A2 (https=)
BR102021020147A2 (https=)
BR102021018926A2 (https=)
BR102021018167A2 (https=)
BR102021017576A2 (https=)
BR102021016837A2 (https=)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230508

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20240723

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20241217