WO2022160635A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2022160635A1
WO2022160635A1 PCT/CN2021/109730 CN2021109730W WO2022160635A1 WO 2022160635 A1 WO2022160635 A1 WO 2022160635A1 CN 2021109730 W CN2021109730 W CN 2021109730W WO 2022160635 A1 WO2022160635 A1 WO 2022160635A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
barrier
substrate
layers
barrier layer
Prior art date
Application number
PCT/CN2021/109730
Other languages
English (en)
French (fr)
Inventor
胡勇
张则瑞
李大利
罗鑫
Original Assignee
京东方科技集团股份有限公司
绵阳京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 绵阳京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180002053.5A priority Critical patent/CN115152029A/zh
Priority to GB2216331.5A priority patent/GB2610497A/en
Priority to US17/789,543 priority patent/US11930665B2/en
Publication of WO2022160635A1 publication Critical patent/WO2022160635A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors

Definitions

  • the present disclosure relates to the field of display technology, for example, to a display panel, a manufacturing method thereof, and a display device.
  • the screen-to-body ratio the ratio of the area of the display screen to the area of the front panel of the display device. Therefore, the concept of full screen appears, for example, optical devices such as image collectors and cameras in the display device are arranged below the display screen to increase the ratio between the area of the display screen and the area of the front panel of the display device , and make the ratio approach 100%.
  • a display substrate has a display area and a peripheral area; the display substrate includes: a substrate, a first blocking wall, a second blocking wall and a connecting part.
  • the first blocking wall and the second blocking wall are located on one side of the substrate and are located in the peripheral area; the second blocking wall is away from the display area relative to the first blocking wall;
  • the height of the second retaining wall is greater than the height of the first retaining wall.
  • the connecting portion is located between the first blocking wall and the second blocking wall, the connecting portion connects the first blocking wall and the second blocking wall, and the height of the connecting portion is smaller than the height of the connecting portion The height of the first retaining wall; wherein, at least part of the first retaining wall, the connecting portion and the second retaining wall is an integral structure.
  • the first barrier wall includes multiple layers of first barrier layers stacked in sequence
  • the second barrier wall includes multiple layers of second barrier layers stacked in sequence; the total number of second barrier layers is greater than that of the first barrier layer.
  • a layer of the connecting layer connects a layer of the first barrier layer and a layer of the second barrier layer.
  • the first blocking wall is close to a sidewall of one side of the display area, gradually moves away from the display area in a direction away from the substrate, and is in the shape of a slope or a step;
  • the part of the side wall of the side wall away from the display area that is not connected to the connection part gradually approaches the display area in the direction away from the substrate, and is in the shape of a slope or a step.
  • the part of the side wall of the second retaining wall on the side close to the display area that is not connected to the connection part is gradually moved away from the display area in a direction away from the substrate, and
  • the second retaining wall is in the shape of a slope or a step; the side wall on the side away from the display area is gradually approached to the display area in the direction away from the substrate, and the second retaining wall is in the shape of a slope or a step.
  • the slope of the part of the side wall on the side away from the display area that is not connected to the connecting portion of the first blocking wall is smaller than that of the second blocking wall on the side close to the display area. The slope of the portion of the side wall that is not connected to the connecting portion.
  • a slope of a side wall of the first blocking wall on a side close to the display area is smaller than a slope of a side wall on a side of the second blocking wall away from the display area.
  • the part of the side wall of the second retaining wall on the side close to the display area that is not connected to the connection part is gradually moved away from the display area in a direction away from the substrate;
  • the part of the side wall of the second retaining wall on the side close to the display area that is not connected with the connecting part is in the shape of a slope or a step.
  • the display area includes a main display area and an auxiliary display area; the light transmittance of the part of the display substrate located in the auxiliary display area is greater than that of the part of the display substrate located in the main display area light transmittance.
  • the display substrate further includes: a plurality of first sub-pixels and a plurality of second sub-pixels disposed on one side of the substrate.
  • the plurality of first sub-pixels are located in the main display area.
  • the second sub-pixel includes: a pixel driving circuit and a light-emitting device.
  • the light-emitting device is disposed on a side of the pixel driving circuit away from the substrate, the light-emitting device is located in the auxiliary display area, and the light-emitting device is coupled to the pixel driving circuit.
  • at least one of the pixel driving circuits is located outside the auxiliary display area.
  • the display substrate further includes: a plurality of flat layers disposed between the pixel driving circuit and the light emitting device and stacked in sequence.
  • the first barrier layers other than the one or two first barrier layers farthest from the substrate in the multi-layer first barrier layers are respectively the same layer as part of the flat layers in the multi-layer flat layers and/or, the second barrier layers except one or two second barrier layers farthest from the substrate in the multi-layer second barrier layers are flat with all of the multi-layer flat layers The layers are set on the same layer respectively.
  • the display substrate further includes: at least one wire layer, and the wire layer includes at least one light-transmitting wire; one of the pixel driving circuits located in the peripheral region is connected to a corresponding one of the all the pixels through a light-transmitting wire. the light emitting device is coupled.
  • at least one layer of the flat layer is arranged between the at least one wire layer as a whole and the pixel driving circuit; at least one layer of the flat layer is arranged between the at least one wire layer as a whole and the light-emitting device. flat layer.
  • At least one layer of the flat layer is disposed between two adjacent layers of the wire layers.
  • the flat layer between the entirety of the at least one wire layer and the pixel driving circuit is a first flat layer, and the number of layers of the first flat layer is one or two.
  • the multi-layer first barrier layers include a first first barrier layer disposed in the same layer as one layer of the first flat layer, and the multi-layer first barrier layers
  • the second barrier layer includes a first second barrier layer disposed on the same layer as one of the first flat layers
  • the at least one connection layer includes a first connection layer; the first connection layer connects the the first first barrier layer and the first second barrier layer.
  • the multi-layer first barrier layer when the number of layers of the first flat layer is two, the multi-layer first barrier layer further includes a second layer of the first flat layer disposed in the same layer as another layer of the first flat layer. a barrier layer, the multi-layer second barrier layer further includes a second second barrier layer disposed at the same layer as another first flat layer, and the at least one connection layer further includes a second connection layer layer; the second connection layer connects the second first barrier layer and the second second barrier layer.
  • the flat layer between two adjacent conductive layers is a second flat layer.
  • the number of the wire layers is three, the flat layer between the two adjacent wire layers close to the substrate is the first and second flat layers, and the adjacent two layers away from the substrate are the first and second flat layers.
  • the flat layer between the wire layers is a second second flat layer.
  • the multi-layer first barrier layer includes a third first barrier layer arranged in the same layer as the first second flat layer, and a fourth barrier layer arranged in the same layer as the second second flat layer first barrier layer.
  • the multi-layer second barrier layer includes a third second barrier layer arranged in the same layer as the first second flat layer, and a fourth barrier layer arranged in the same layer as the second second flat layer second barrier layer.
  • the at least one connection layer includes a third connection layer and a fourth connection layer; the third connection layer connects the third first barrier layer and the third first barrier layer Two barrier layers, the fourth connection layer connects the fourth first barrier layer and the fourth second barrier layer.
  • the at least one connection layer includes a third connection layer; the third connection layer connects the third first barrier layer and the third second barrier layer; the third connection layer The fourth first barrier layer is disconnected from the fourth second barrier layer.
  • the display substrate further includes: a pixel defining layer disposed on a side of the multi-layer planar layer away from the substrate; and a pixel defining layer disposed on a side of the pixel defining layer away from the substrate Multiple support pads on the surface.
  • a first barrier layer farthest from the substrate in the multi-layer first barrier layers is disposed in the same layer as the pixel defining layer or the plurality of support pads; in the multi-layer second barrier layers
  • a second barrier layer farthest from the substrate is disposed on the same layer as the pixel defining layer or the plurality of support pads.
  • the multi-layer first barrier layers when a layer of the first barrier layer farthest from the substrate in the multi-layer first barrier layers is disposed in the same layer as the plurality of support pads, the multi-layer first barrier layers A second first barrier layer farthest from the substrate is disposed in the same layer as the pixel defining layer; when the second barrier layer farthest from the substrate among the multiple second barrier layers When a plurality of support pads are arranged in the same layer, a second barrier layer of the second barrier layer which is far away from the substrate is arranged in the same layer as the pixel defining layer.
  • the multi-layer first barrier layer further includes a fifth first barrier layer disposed in the same layer as the pixel defining layer or the plurality of support pads.
  • the flat layer between the entirety of the at least one wire layer and the light-emitting device is a third flat layer, and the number of the third flat layer is one layer;
  • the multi-layer second barrier layer further includes A fifth second barrier layer disposed on the same layer as the third planarization layer, and a sixth second barrier layer disposed on the same layer as the pixel defining layer or the plurality of support pads.
  • the fifth second barrier layer and the sixth second barrier layer are both disconnected from the fifth first barrier layer.
  • the display substrate further includes: a barrier layer, one end of the barrier layer extends between two adjacent layers of the first barrier layer, and the other end of the barrier layer extends to two adjacent layers Between the flat layers; the first barrier layer overlapped by one end of the barrier layer and the flat layer overlapped by the other end of the barrier layer are arranged in the same layer.
  • the orthographic projection of the first barrier layer on the substrate overlapped by one end of the barrier layer is the same as the orthographic projection of the first barrier layer on the substrate at the other end of the barrier layer away from the substrate.
  • the barrier layer is disposed on the same layer as at least one of the multilayer wire layers.
  • the display substrate further comprises: an encapsulation layer disposed on a side of the plurality of first sub-pixels and the plurality of second sub-pixels away from the substrate; the encapsulation layer is configured to The plurality of first subpixels and the plurality of second subpixels are packaged on the substrate.
  • the encapsulation layer includes: a first inorganic layer; an organic layer disposed on a side of the first inorganic layer away from the substrate; and a second inorganic layer disposed on a side of the organic layer away from the substrate .
  • first retaining wall and the second retaining wall are used to block the organic layer; the first inorganic layer covers the first retaining wall and the second retaining wall, and the second retaining wall The inorganic layer covers the first retaining wall and the second retaining wall.
  • a first barrier layer closest to the substrate is connected to a second barrier layer closest to the substrate through a layer of the connecting layer
  • a second layer of the first barrier layer close to the substrate is connected to a second layer of the second barrier layer close to the substrate through a layer of the connection layer to form a second communication part.
  • the display substrate further includes: a voltage signal line arranged on one side of the substrate, the voltage signal line is located in the peripheral area and is arranged around the display area; among the voltage signal lines, the voltage signal line is far from the display area.
  • the region is located between the first communication part and the second communication part, and the voltage signal line is far from the orthographic projection of the edge of the display area on the substrate, and the first communication part is located close to the between the orthographic projection of the edge of the display area on the substrate and the orthographic projection of the edge of the first communicating portion away from the display area on the substrate.
  • the multi-layer first barrier layers are disposed in at least one of the following manners: a layer of the multi-layer first barrier layers farthest from the substrate covers the multi-layer first barrier layers The second layer of the first barrier layer that is far away from the substrate faces the side of the second barrier wall; or, the second layer of the plurality of first barrier layers that is far away from the substrate a first barrier layer covering the side of the third layer of the first barrier layer that is far away from the substrate and faces the second barrier wall.
  • the multilayered second barrier layers are disposed in at least one of the following manners: a second barrier layer of the multilayered second barrier layers farthest from the substrate covers the multilayered second barrier layers The second barrier layer in the second barrier layer, which is far away from the substrate, faces the side of the first barrier wall; or, the second barrier layer in the multi-layer second barrier layer is far away from the substrate. a second barrier layer covering the side of the third layer of the second barrier layer far away from the substrate in the multilayer second barrier layers facing the first barrier wall; or, in the multilayer second barrier layer A third second barrier layer away from the substrate covers the side of the fourth second barrier layer away from the substrate in the multilayer second barrier layers facing the first barrier wall.
  • connection layer, the first barrier layer and the second barrier layer connected thereto are disposed in the same layer.
  • a manufacturing method of a display substrate includes: providing a substrate; forming on one side of the substrate a first retaining wall, a connecting part and a second retaining wall which are located in the peripheral area and are sequentially away from the display area; wherein, the The height of the second blocking wall is greater than the height of the first blocking wall; the height of the connecting portion is less than the height of the first blocking wall; the first blocking wall, the connecting portion and the second blocking wall At least part of the three is an integral structure.
  • the first barrier wall includes multiple layers of first barrier layers stacked in sequence
  • the second barrier wall includes multiple layers of second barrier layers stacked in sequence
  • the total number of second barrier layers is greater than that of the first barrier layer.
  • the connecting portion includes at least one connecting layer; the total number of the connecting layers is less than the total number of the first barrier layers;
  • At least one first barrier layer of the substrate and at least one second barrier layer adjacent to the substrate among the multiple second barrier layers are connected by at least one connecting layer.
  • one layer of the connecting layer connects one layer of the first barrier layer and one layer of the second barrier layer, and the connecting layer is connected to the first barrier layer and the second barrier layer. It is formed by the same patterning process.
  • a display device comprising: the display substrate as described in any one of the above embodiments.
  • the peripheral area of the display substrate includes a binding area, and the binding area is located on a side of the second barrier wall away from the display area.
  • the display device further comprises: a touch driving chip located in the binding area of the display substrate; a touch grid structure located in the display area of the display substrate; and connecting the touch driving chip and the touch control Multiple signal transmission lines in grid structure.
  • the plurality of signal transmission lines are located on one side of the first retaining wall and the second retaining wall far from the substrate as a whole, and the orthographic projection of the plurality of signal transmission lines on the substrate and the connection layer The orthographic projections on the substrate partially overlap.
  • FIG. 1 is a structural diagram of a display device according to some embodiments of the present disclosure
  • FIG. 2 is a structural diagram of another display device provided by some embodiments of the present disclosure.
  • FIG. 3 is a partial structural diagram of a display device according to some embodiments of the present disclosure.
  • FIG. 4 is a structural diagram of a display substrate according to some embodiments of the present disclosure.
  • FIG. 5 is a partial structural diagram of a display substrate according to some embodiments of the present disclosure.
  • FIG. 6 is a partial structural diagram of another display substrate provided by some embodiments of the present disclosure.
  • FIG. 7 is a partial structural diagram of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 8 is a partial structural diagram of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 9 is a partial structural diagram of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 10 is a partial structural diagram of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 11 is a partial structural diagram of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 12 is a partial structural diagram of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 13 is a partial structural diagram of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 14 is a partial structural diagram of still another display substrate provided by some embodiments of the present disclosure.
  • FIG. 15 is a flowchart of a method for fabricating a display substrate provided by some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C”, and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally construed to mean “when” or “at” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that" or “if a [statement or event] is detected” are optionally interpreted to mean “in determining" or “in response to determining" or “on detection of [recited condition or event]” or “in response to detection of [recited condition or event]”.
  • perpendicular As used herein, “perpendicular,” “equal,” and “equal” include the stated conditions as well as conditions that approximate the stated conditions within a range of acceptable deviations, wherein the acceptable deviations
  • the range is as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, the limitations of the measurement system).
  • vertical includes absolutely vertical and approximately vertical, wherein the acceptable deviation range of approximately vertical can also be a deviation within 5°, for example.
  • “Equal” includes both absolute equality and approximate equality, where the difference between the two being equal within acceptable deviations of approximate equality, for example, is less than or equal to 5% of either.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
  • example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the display device 1000 includes a display substrate 100 , a touch grid structure 200 , a touch driving chip 300 , and a plurality of signal transmission lines 400 .
  • the display apparatus 1000 further includes an optical device 500 .
  • the types of the above-mentioned optical device 500 include multiple types, which can be selected and set according to actual needs.
  • the above-mentioned optical device 500 may be a camera, an infrared receiver or an infrared transmitter, or the like.
  • the display substrate 100 has a display area A and a peripheral area B. Wherein, the portion of the display substrate 100 located in the display area A can perform image display.
  • the present disclosure does not limit the setting position of the peripheral area B.
  • the peripheral area B may be located on one side, two sides, or three sides of the display area A, etc.
  • the peripheral area B may also be located at the periphery of the display area A.
  • the display area A includes a main display area A1 and an auxiliary display area A2.
  • the area of the main display area A1 may be larger than that of the auxiliary display area A2.
  • the number of the auxiliary display areas A2 may be one or more, and may be selected and set according to actual needs.
  • the above-mentioned positional relationship between the main display area A1 and the auxiliary display area A2 includes various types, which can be selected and set according to actual needs.
  • the auxiliary display area A2 is located beside the main display area A1, that is, a part of the boundary of the auxiliary display area A2 overlaps with a part of the boundary of the main display area A1.
  • the shape of the auxiliary display area A2 may be, for example, a rectangle, a rectangle with rounded corners, a teardrop shape, or a semicircle.
  • the main display area A1 may be located at the periphery of the auxiliary display area A2, that is, the main display area A1 surrounds the auxiliary display area A2.
  • the shape of the auxiliary display area A2 may be, for example, a circle, an ellipse, a rectangle, or the like.
  • the light transmittance of the portion of the display substrate 100 located in the auxiliary display area A2 is greater than the light transmittance of the portion of the display substrate 100 located in the main display area A1 . In this way, when the external light passes through the part of the display substrate 100 located in the auxiliary display area A2 and enters the optical device 500 to make the optical device 500 work, the blocking of the external light can be reduced, and the working performance of the optical device 500 can be improved.
  • the peripheral area B includes at least one binding area B1.
  • the structure of the display device 1000 is illustrated by taking the optical device 500 as a camera, the number of auxiliary display areas A2 being one, the number of binding areas B1 being one, and the auxiliary display area A2 being located beside the main display area A1 as an example. Sexual description.
  • the optical device 500 is disposed on the non-light exit side of the display substrate 100 and is located in the auxiliary display area A2 of the display substrate 100 . External light can pass through the display substrate 100 and be incident on the optical device 500 , so that the optical device 500 can work.
  • the above-mentioned touch grid structure 200 may be disposed on the light-emitting side of the display substrate 100 and located in the display area A of the display substrate 100 . That is, the optical device 500 and the touch grid structure 200 are located on opposite sides of the display substrate 100 .
  • the user can use the touch grid structure 200 to control the image to be displayed on the display substrate 100 , so that the display device 1000 has both a display function and a touch function.
  • the touch driving chip 300 may be disposed in the binding area B1 and located on the same side of the display substrate 100 as the touch grid structure 200 .
  • the touch driving chip 300 can transmit the touch driving signal to the touch grid structure 200 , and can also receive the touch sensing signal transmitted by the touch grid structure 200 , so that the user can realize the display control through the touch grid structure 200 . Control of the image to be displayed by the substrate 100 .
  • the plurality of signal transmission lines 400 are located on the same side of the display substrate 100 as the touch grid structure 200 and the touch driving chip 300 .
  • One end of each signal transmission line 400 extends into the display area A and is electrically connected to the touch grid structure 200 ; the other end of each signal transmission line 400 extends into the binding area B1 and is electrically connected to the touch driving chip 300 .
  • the touch driving chip 300 and the touch grid structure 200 can realize the transmission of the touch driving signal and the touch sensing signal through the signal transmission line 400 .
  • the touch grid structure 200 is located in the display area A, and the touch driving chip 300 is located in the binding area B1, which means that the signal transmission line 400 needs to pass through the peripheral area B to realize the touch grid structure 200 and the Electrical connection between touch driver chips 300 .
  • the portion of the display substrate 100 located in the display area A can perform image display.
  • the part of the display substrate 100 located in the main display area A1 may present a picture taken by the user, and the part of the display substrate 100 located in the auxiliary display area A2 may present a black picture , which clearly shows the position of the optical device 500 .
  • the part of the display substrate 100 located in the main display area A1 and the part located in the auxiliary display area A2 can overall present a picture taken by the user.
  • the display substrate 100 includes the substrate 1 .
  • the types of the substrate 1 include multiple types, which can be selected and set according to actual needs.
  • the substrate 1 may be a rigid substrate.
  • the rigid substrate can be, for example, a glass substrate or a PMMA (Polymethyl methacrylate, polymethyl methacrylate) substrate or the like.
  • the substrate 1 may be a flexible substrate.
  • the flexible substrate can be, for example, a PET (Polyethylene terephthalate, polyethylene terephthalate) substrate, a PI (Polyimide, polyimide) substrate or a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate ethylene glycol formate) substrate, etc.
  • the display substrate 100 further includes: a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2 disposed on one side of the substrate 1 .
  • the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 may cooperate with each other, so that the display substrate 100 can perform image display.
  • each first subpixel P1 includes a pixel driving circuit and a light emitting device.
  • the light emitting device may be located on a side of the pixel driving circuit away from the substrate 1 and is electrically connected to the pixel driving circuit, and the pixel driving circuit is configured to provide a driving voltage to the light emitting device to control the light emitting state of the light emitting device.
  • each second sub-pixel P2 includes a pixel driving circuit 21 and a light-emitting device 22 .
  • the light emitting device 22 may be located on the side of the pixel driving circuit 21 away from the substrate 1 , and is electrically connected to the pixel driving circuit 21 .
  • the pixel driving circuit 21 is configured to provide a driving voltage to the light-emitting device 22 to control the light-emitting state of the light-emitting device 22 .
  • the structure of the pixel driving circuit included in the first sub-pixel P1 may be the same as the structure of the pixel driving circuit 21 included in the second sub-pixel P2.
  • the structure of the light-emitting device included in the first sub-pixel P1 may be the same as the structure of the light-emitting device 22 included in the second sub-pixel P2.
  • the structure of the pixel driving circuit 21 may include various structures, which are not limited in the present disclosure.
  • the structure of the pixel driving circuit 21 can be "6T1C", “7T1C”, “6T2C” or “7T2C”, etc.; wherein, “T” represents a thin film transistor, and the number in front of "T” represents a thin film transistor The number, "C” represents the storage capacitor, and the number before “C” represents the number of the storage capacitor.
  • the thin film transistor included in the pixel driving circuit 21 may be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure.
  • the structure of the light emitting device 22 may include various structures, which are not limited in the present disclosure.
  • the structure of the light-emitting device 22 may be an OLED (Organic Light Emitting Diode, organic light-emitting diode) device, or may be a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) device.
  • the light emitting manner of the light emitting device 22 may be top emitting light, or bottom light emitting.
  • Some embodiments of the present disclosure are schematically illustrated by taking the thin film transistor in the pixel driving circuit 21 as a top gate structure thin film transistor, the light emitting device 22 as an OLED light emitting device, and the light emitting method of the light emitting device 22 as top light.
  • the pixel driving circuit in the first sub-pixel P1 can be electrically connected with the corresponding light-emitting device through the connection structure
  • the pixel driving circuit 21 in the second sub-pixel P2 can be electrically connected with the corresponding light-emitting device through the connection structure 11
  • the light-emitting device 22 is electrically connected. This design is beneficial to reduce the difficulty of wiring.
  • the plurality of first sub-pixels P1 included in the display substrate 100 are located in the main display area A1 .
  • each light-emitting device 22 is located in the auxiliary display area A2, and at least one pixel driving circuit 21 is located outside the auxiliary display area A2.
  • pixel driving circuit 21 in the plurality of second sub-pixels P2 is located outside the auxiliary display area A2, or the pixel driving circuit 21 in each second sub-pixel P2 is located outside the auxiliary display area A2.
  • auxiliary display area A2 may be, for example, located in the peripheral area B and/or the main display area A1.
  • the one pixel driving circuit 21 located outside the auxiliary display area A2 may be located in the peripheral area B or the main display area A1. .
  • the pixel driving circuit 21 in each second sub-pixel P2 is located outside the auxiliary display area A2, that is, when a plurality of pixel driving circuits 21 are located outside the auxiliary display area A2, the The plurality of pixel driving circuits 21 may all be located in the peripheral area B, or may all be located in the main display area A1 , and may also be partially located in the peripheral area B and partially located in the main display area A1 .
  • the pixel driving circuits 21 in the plurality of second sub-pixels P2 are arranged in the peripheral area B and/or the main display area A1
  • the plurality of pixel driving circuits 21 may be arranged in the peripheral area B and/or the main display area.
  • the pixel driving circuit 21 is mainly composed of metal lines, the metal lines can have a strong blocking effect on light.
  • the number of pixel driving circuits 21 arranged in the auxiliary display area A2 can be reduced, so that the external light transmits through the display substrate 100 and is located in the auxiliary display area A2.
  • the occlusion of external light can be reduced, the light transmittance through the display substrate 100 can be increased, and the working performance of the optical device 500 can be improved.
  • the display substrate further includes: an encapsulation layer 3 disposed on the side of the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 away from the substrate 1 ; the encapsulation layer 3 It is configured to encapsulate a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2 on the substrate 1 .
  • the orthographic projections of the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2 on the substrate 1 are located within the orthographic projection range of the encapsulation layer 3 on the substrate 1 .
  • the encapsulation layer 3 can be used to form a good encapsulation effect on the light-emitting device included in the first sub-pixel P1 and the light-emitting device 22 included in the second sub-pixel P2, so as to avoid external water vapor and/or oxygen, etc.
  • the light emitting device included in the pixel P1 and the light emitting device 22 included in the second sub-pixel P2 cause erosion, thereby affecting the luminous efficiency and service life.
  • the encapsulation layer 3 may include: a first inorganic layer 31 , an organic layer 32 disposed on a side of the first inorganic layer 31 away from the substrate 1 , and an organic layer 32 disposed on the organic layer 31 .
  • the layer 32 is the second inorganic layer 33 on the side remote from the substrate 1 .
  • the first inorganic layer 31 and/or the second inorganic layer 33 can be made of, for example, an inorganic insulating material and formed by a deposition process; the organic layer 32 can be formed by, for example, an organic insulating material and formed by an inkjet printing process.
  • the display substrate 100 further includes: a first retaining wall 4 and a second retaining wall 5 .
  • the first blocking wall 4 and the second blocking wall 5 are used to block a part of the encapsulation layer 3 .
  • the second barrier wall 5 is far away from the display area A relative to the first barrier wall 4
  • the first barrier wall 4 is far away from the display area A relative to the at least one pixel driving circuit 21 disposed in the peripheral area B. That is, in the display substrate 100 , the pixel driving circuit 21 , the first blocking wall 4 , and the second blocking wall 5 disposed in the peripheral area B are away from the display area A in sequence.
  • the first blocking wall 4 and the second blocking wall 5 may be arranged on the edge of the display substrate 100 and arranged in a ring shape.
  • the first blocking wall 4 surrounds the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2
  • the second blocking wall 5 surrounds the first blocking wall 4 .
  • the first inorganic layer 31 may cover the first blocking wall 4 and the second blocking wall 5 while covering the plurality of first sub-pixels P1 and the plurality of second sub-pixels P2, so as to form a better encapsulation effect.
  • the organic layer 32 may be located within the range defined by the first blocking wall 4 , that is, the orthographic projection of the organic layer 32 on the substrate 1 is located within the orthographic projection range of the first blocking wall 4 on the substrate 1 .
  • the first blocking wall 4 can block the organic layer 32 in the encapsulation layer 3 to ensure a good encapsulation effect.
  • the height of the second retaining wall 5 is greater than the height of the first retaining wall 4 .
  • the height of the second retaining wall 5 may be the vertical distance between the end of the second retaining wall 5 away from the substrate 1 and the substrate 1 .
  • the height of the first retaining wall 4 may be the vertical distance between the end of the first retaining wall 4 away from the substrate 1 and the substrate 1 .
  • the second retaining wall 5 is used to further block the organic layer 32, thereby improving the blocking effect on the organic layer 32, thereby improving the packaging.
  • the second inorganic layer 33 may cover the organic layer 32 and the first inorganic layer 31, and cover the first retaining wall 4 and the second retaining wall 5 while covering the first inorganic layer 31, so as to form a better encapsulation effect.
  • the orthographic projection of the organic layer 32 on the substrate 1 it is located within the orthographic projection range of the first retaining wall 4 on the substrate 1, and the first inorganic layer 31 and the second inorganic layer 33 are opposite to the first The retaining wall 4 and the second retaining wall 5 form a covering, so that the portions of the first inorganic layer 31 and the second inorganic layer 33 beyond the organic layer 32 can be in contact.
  • the display substrate 100 further includes a connecting portion 15 between the first blocking wall 4 and the second blocking wall 5 , and the connecting portion 15 connects the first blocking wall 4 and the second blocking wall Wall 5; wherein, at least part of the first retaining wall 4, the connecting portion 15 and the second retaining wall 5 is an integral structure.
  • first blocking wall 4 the connecting portion 15 and the second blocking wall 5 is an integral structure, for example, it may be a part of the first blocking wall 4 , a part of the connecting portion 15 and the second blocking wall A part of the wall 5 is a one-piece structure.
  • the height of the connecting portion 15 is smaller than the height of the first retaining wall 4 .
  • the height of the connection portion 15 may be the vertical distance between the end of the connection portion 15 away from the substrate 1 and the substrate 1
  • the height of the first retaining wall 4 may be the end of the first retaining wall 4 away from the substrate 1 . Vertical distance from substrate 1.
  • a gap is formed between the first retaining wall 4 and the second retaining wall 5, and the first retaining wall 4 and the second retaining wall 5 are connected by the connecting portion 15, which can reduce the gap between the first retaining wall 4 and the second retaining wall 5. and the level difference between the second retaining wall 5 and the gap.
  • the signal transmission line 400 in the display device 1000 can be prepared and formed by, for example, a photolithography process. That is, in the process of forming the signal transmission line 400 on the light-emitting side of the display substrate 100 (that is, the side of the packaging layer 3 away from the substrate 1 ), a deposition process can be used to form a conductive material film, and then the conductive material film is far away from the substrate. One side of 1 is coated with photoresist, and then the photoresist is exposed and developed, and the conductive material film is patterned to obtain the signal transmission line 400 .
  • a photolithography process that is, in the process of forming the signal transmission line 400 on the light-emitting side of the display substrate 100 (that is, the side of the packaging layer 3 away from the substrate 1 ).
  • a deposition process can be used to form a conductive material film, and then the conductive material film is far away from the substrate.
  • One side of 1 is coated with photoresist, and then the photoresist is exposed
  • the orthographic projection of the signal transmission line 400 on the substrate 1 will be connected to the connection portion 15
  • the orthographic projections on the substrate 1 overlap, that is, part of the signal transmission line 400 will cover the gap between the first blocking wall 4 and the second blocking wall 5 (as shown in FIGS. 7-12 ).
  • the signal transmission line 400 can be reduced.
  • the thickness of the photoresist in the gap so that in the process of exposing and developing the photoresist, the photoresist can be avoided in the gap, and then in the process of patterning the conductive material film, it can be avoided Residues of conductive materials are formed, which ultimately avoids the short circuit of the signal transmission line 400 , so as to improve the yield of the display device 1000 .
  • the first barrier wall 4 includes multiple layers of first barrier layers 41 stacked in sequence
  • the second barrier wall 5 includes multiple layers of second barrier layers 51 stacked sequentially.
  • the total number of layers of the second barrier layer 51 is greater than the total number of layers of the first barrier layer 41 .
  • the first retaining wall 4 is constituted by multiple layers of the first barrier layer 41
  • the second retaining wall 5 is constituted by multiple layers of the second barrier layer 51, which can effectively increase the heights of the first retaining wall 4 and the second retaining wall 5. , which is beneficial to ensure the blocking and leveling effect of the organic layer 32 in the encapsulation layer 3 , and to ensure the good encapsulation effect of the encapsulation layer 3 .
  • the connecting portion 15 includes at least one connecting layer 10 , and the total number of the connecting layers 10 is less than the total number of the first barrier layers 41 .
  • connection layer 10 connects a first barrier layer 41 and a second barrier layer 51 .
  • connection layer 10 and the first barrier layer 41 and the second barrier layer 51 connected thereto are provided in the same layer.
  • the first retaining wall 4 , the second retaining wall 5 and the connecting layer 10 may be, for example, an integral structure.
  • the sidewall of the first blocking wall 4 is close to the side wall of the display area A, and gradually moves away from the display area A in the direction Z away from the substrate 1 .
  • the side wall of the first blocking wall 4 on the side close to the display area A may be in the shape of a slope as shown in FIG. 7 to FIG. 14 , or may be in the shape of a step.
  • the portion of the side wall of the first blocking wall 4 on the side away from the display area A that is not connected to the connecting portion 15 gradually approaches the display in the direction Z away from the substrate 1 District A.
  • the part of the side wall on the side of the first blocking wall 4 away from the display area A that is not connected to the connecting portion 15 may be in the shape of a slope as shown in FIGS. 7-8 and 11-14, or may be For example, it has a stepped shape as shown in FIGS. 9 to 10 .
  • the part of the side wall of the second retaining wall 5 on the side close to the display area A that is not connected to the connecting portion 15 is gradually moved away from the display in the direction Z away from the substrate 1 District A.
  • the part of the side wall on the side close to the display area A of the second retaining wall 5 that is not connected to the connecting part 15 may be in the shape of a slope as shown in FIGS. 11 to the stepped shape shown in Fig. 14 .
  • the second blocking wall 5 is located away from the sidewall of the side of the display area A, and gradually approaches the display area A in the direction away from the substrate 1 .
  • the side wall of the second blocking wall 5 on the side away from the display area A may be in the shape of a slope, such as shown in FIGS. 7 to 14 , or may be in the shape of a step.
  • the slope of the part of the side wall of the side wall of the first retaining wall 4 away from the display area A that is not connected to the connecting part 15 (that is, the elevation difference h1 of this part and the The ratio of the horizontal distance L 1 ) is smaller than the slope of the part of the side wall of the second retaining wall 5 close to the display area A that is not connected to the connecting part 15 (that is, the elevation difference h 2 of this part and the level of the part ratio of distance L2 ) .
  • the slope of the side wall on the side of the first retaining wall 4 close to the display area A that is, the ratio of the height difference h 3 of the side wall to the horizontal distance L 3 of the side wall
  • the slope of the side wall of the second retaining wall 5 away from the display area A ie, the ratio of the height difference h 4 of the side wall to the horizontal distance L 4 of the side wall.
  • the size of the display substrate 100 can be reduced by relatively increasing the slope of the side wall of the second blocking wall 5 away from the display area A, thereby saving materials and reducing manufacturing costs.
  • the calculation method of the slope is not only applicable to the part of the side wall of the first retaining wall 4 on the side away from the display area A that is not connected to the connecting portion 15, and the side of the second retaining wall 5 close to the display area A side. At least one of the part of the wall that is not connected to the connecting portion 15 , the side wall of the first blocking wall 4 on the side close to the display area A, and the side wall on the side of the second blocking wall 5 away from the display area A is slope-shaped.
  • the calculation method of the slope is also the same. Be applicable.
  • the depth of the gap formed between the first retaining wall 4 and the second retaining wall 5 in the direction Z away from the substrate 1 will also increase.
  • the level difference between the first retaining wall 4 and the gap can also be reduced, as well as the second retaining wall 5 and the level difference between this gap.
  • a multi-layer first sub-pixel can be disposed in the peripheral area B.
  • the first blocking wall 4 formed by the barrier layer 41 and the second blocking wall 5 formed by the multi-layer second barrier layer 51 can achieve a blocking effect on a part of the encapsulation layer 3 and ensure the encapsulation effect of the encapsulation layer 3 .
  • the light-emitting device 22 and the pixel driving circuit 21 above the optical device 500 are separated, and the electrical connection between the two is realized through at least one layer of wires, and the light-emitting device 22 and the pixel driving circuit 21 are separated.
  • an insulating layer is provided between the wires and the wires, between the wires of two adjacent layers, and between the wires and the pixel driving circuit, the thickness of the portion of the display substrate 100 located in the display area A will increase.
  • the first retaining wall 4 composed of the multi-layer first barrier layers 41 and the second retaining wall 5 composed of the multi-layer second barrier layers 51 can still achieve the blocking effect on a part of the encapsulation layer 3, thereby ensuring the protection of the packaging layer 3. encapsulation effect.
  • the gap between the first retaining wall 4 and the second retaining wall 5 is lined with The orthographic projection on the bottom 1 overlaps with the orthographic projection of at least one connecting layer 10 on the substrate 1, which can effectively reduce the step difference between the first retaining wall 4 and the gap, and reduce the second retaining wall 5 and the level difference between the gap.
  • the display substrate 100 is applied to the display device 1000 , the residual conductive material of the signal transmission line 400 can be effectively avoided, thereby avoiding short circuit of the signal transmission line 400 , and improving the yield of the display device 1000 .
  • the display substrate 100 further includes a multi-layer planarization layer 7 .
  • the multi-layer flat layer 7 is disposed between the pixel driving circuit 21 and the light emitting device 22 in the peripheral region B, and is stacked in sequence.
  • the first barrier layers 41 other than one or two layers of the first barrier layers 41 farthest from the substrate 1 in the multilayer first barrier layers 41 are respectively the same layer as part of the flat layers 7 in the multilayer flat layers 7 . and/or, the second barrier layers 51 except the one or two second barrier layers 51 farthest from the substrate 1 among the multilayer second barrier layers 51 , and all the planar layers in the multilayer planar layer 7 7 are set on the same layer.
  • some of the flat layers 7 in the multi-layer flat layers 7 may be some flat layers 7 in the multi-layer flat layers 7 .
  • the display substrate 100 further includes a pixel defining layer 8 disposed on the side of the multilayer flat layer 7 that is generally away from the substrate 1; and, the pixel defining layer 8 is disposed away from the substrate.
  • the first barrier layer 41 farthest from the substrate 1 among the multi-layer first barrier layers 41 is disposed in the same layer as the pixel defining layer 8 or the plurality of supporting pads 16 ; and/or, in the multi-layer second barrier layer 51 A second barrier layer 51 farthest from the substrate 1 is disposed on the same layer as the pixel defining layer 8 or the plurality of support pads 16 .
  • the pixel defining layer 8 has a plurality of openings, and at least a part of a light emitting device 22 is disposed in each opening.
  • the pixel defining layer 8 By setting the pixel defining layer 8 in this way, the light-emitting regions of each of the first sub-pixels P1 and the second sub-pixels P2 can be defined.
  • the second barrier layer 41 in the multilayer first barrier layer 41 is farthest away from the substrate.
  • a first barrier layer 41 of 1 is disposed in the same layer as the pixel defining layer 8 .
  • the second barrier layer 51 farthest from the substrate 1 in the multilayer second barrier layers 51 is disposed in the same layer as the plurality of support pads 16
  • the second barrier layer 51 in the multilayer second barrier layer 51 farthest from the substrate 1 is disposed in the same layer.
  • the second blocking layer 51 is disposed in the same layer as the pixel defining layer 8 .
  • the display substrate 100 further includes at least one wire layer 6 , each wire layer 6 includes at least one light-transmitting wire 61 , and a pixel driving circuit 21 in the peripheral area B passes through A light-transmitting wire 61 is electrically connected to a corresponding one of the light-emitting devices 22 . That is, one end of the light-transmitting wire 61 can extend into the peripheral area B and be electrically connected to the pixel driving circuit 21 (for example, electrically connected to the pixel driving circuit 21 through the connection structure 11 ); the other end of the light-transmitting wire 61 can extend into the auxiliary display
  • the area A2 is electrically connected to the corresponding light emitting device 22 .
  • the pixel driving circuit 21 located in the peripheral area B provides a driving voltage to the corresponding light-emitting device 22 through the light-transmitting wire 61 to control the light-emitting state of the corresponding light-emitting device 22 .
  • the number of the light-transmitting wires 61 may be equal to the number of the pixel driving circuits 21 located in the peripheral region B. As shown in FIG.
  • the number of layers of the wire layer 6 may be two or three.
  • the number of layers of the wire layer 6 is three. This design can provide sufficient space for the wiring arrangement of the light-transmitting wires 61 , thereby preventing interference between each light-transmitting wire 61 .
  • At least one flat layer 7 (that is, the above-mentioned insulating layer) is disposed between the above-mentioned at least one wire layer 6 as a whole and the pixel driving circuit 21 ; There is at least one flat layer 7 (ie, the above-mentioned insulating layer). This design can ensure the flatness and continuity of the wire layer 6 .
  • an insulating layer needs to be provided between two adjacent layers of wire layers 6 .
  • At least one flat layer 7 (ie, the above-mentioned insulating layer) is disposed between two adjacent conductor layers 6 .
  • the number of the above-mentioned flat layers 7 is related to the total number of the conductor layers 6 .
  • the total number of layers of the wire layers 6 is one layer, that is, the light-transmitting wires 61 are arranged in the same layer.
  • each light-transmitting wire 61 can be connected to the pixel driving circuit 21 in the peripheral area B, for example, through the connection structure 11; and each light-transmitting wire 61 is also electrically connected to the corresponding light-emitting device 22 in the auxiliary display area A2 .
  • the display substrate 100 may include three layers of the planarization layers 7 stacked in sequence.
  • the total number of layers of the wire layers 6 is multiple layers, that is, a plurality of light-transmitting wires 61 are located in multiple layers, and each wire layer 6 includes at least one light-transmitting wire 61 adjacent to At least one flat layer 7 is disposed between the two conductor layers 6 .
  • the total number of conductor layers 6 is three.
  • each light-transmitting wire 61 can be connected, for example, through the connection structure 11 to the corresponding pixel driving circuit 21 in the peripheral area B; and each light-transmitting wire 61 is also electrically connected to the corresponding light-emitting device 22 in the auxiliary display area A2. connect.
  • only one flat layer 7 may be disposed between each adjacent two layers of wire layers 6;
  • only one flat layer 7 may be provided; for example, only one flat layer 7 may be provided between the connection structure 11 and the pixel driving circuit 21 ;
  • a flat layer 7 is provided. Therefore, the display substrate 100 may include five layers of the planarization layers 7 stacked in sequence.
  • one of the conductor layers 6 may be electrically connected to the light-emitting device 22 capable of emitting red light, and the other layer of conductor layers 6 may be electrically connected to the light-emitting device 22 capable of emitting green light.
  • the light-emitting devices 22 are electrically connected to each other, and the last wire layer 6 may be electrically connected to the light-emitting devices 22 capable of emitting blue light.
  • the "same layer” mentioned in the various embodiments of the present disclosure refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • the above-mentioned plurality of light-transmitting wires 61 can be simultaneously fabricated and formed in one patterning process, which is beneficial to simplify the fabrication process of the display substrate 100 .
  • the above-mentioned light-transmitting wires 61 may be formed of a conductive material with high light transmittance.
  • the conductive material may include, for example, Indium Tin Oxide (ITO for short), Indium Zinc Oxide (IZO for short), Indium Gallium Zinc Oxide (IGZO for short), and the like.
  • the light-transmitting wires 61 to connect the corresponding pixel driving circuits 21 and the light-emitting devices 22, it is beneficial to further improve the light transmittance of the portion of the display substrate 100 located in the auxiliary display area A2, and improve the working performance of the optical device 500.
  • the flat layer 7 between at least one wire layer 6 as a whole and the pixel driving circuit 21 is the first flat layer 71 ;
  • the two barrier layers 51 are connected to the corresponding first barrier layers 41 through a connecting layer 10 .
  • At least one wire layer 6 is directly electrically connected to the pixel driving circuit 21 as a whole, and only one flat layer 7 is provided between the at least one wire layer 6 and the pixel driving circuit 21, for example, the above-mentioned first flat layer 71
  • the number of layers is one layer.
  • At least one wire layer 6 is electrically connected to the pixel driving circuit 21 through the connection structure 11 as a whole, and only one flat layer is provided between the at least one wire layer 6 and the connection structure 11 as a whole.
  • Layer 7. For example, only one flat layer 7 is provided between the connection structure 11 and the pixel driving circuit 21, and the number of layers of the first flat layer 71 is two.
  • the flat layer 7 between two adjacent conductor layers 6 is the second flat layer 72 ; in the multilayer second barrier layers 51 , the same layer as at least one second flat layer 72 The provided at least one second barrier layer 51 is connected to the corresponding at least one first barrier layer 41 through at least one connecting layer 10 .
  • the flat layer 7 between at least one wire layer 6 as a whole and the light emitting device 22 is a third flat layer 73 ; the multilayered second barrier layer 51 further includes at least one flat layer 73 . At least one second barrier layer 51 is provided on the same layer as the third flat layer 73 . Exemplarily, the number of layers of the third flat layer 73 may be one layer.
  • the wire layer 6 has three layers in total, and the wire layer 6 is electrically connected to the pixel driving circuit 21 through the connection structure 11 as a whole.
  • a flat layer 7 is arranged between the entire wire layer 6 and the connection structure 11 , a flat layer 7 is arranged between the connection structure 11 and the pixel driving circuit 21 , and a flat layer 7 is arranged between every two adjacent layers of wire layers 6 .
  • a flat layer 7 is arranged between the whole wire layer 6 and the light emitting device 22 . That is, the number of layers of the first flat layer 71 is two, the number of layers of the second flat layer 72 is two, and the number of layers of the third flat layer 73 is one.
  • the first barrier wall 4 includes five layers of the first barrier layers 41 stacked in sequence.
  • the five layers of the first barrier layers 41 may be connected with the two layers of the first flat layer 71 and the two layers of the second layer along the direction Z away from the substrate 1 in sequence.
  • the flat layer 72 and the pixel defining layer 8 (or the support pad 16 ) are arranged in the same layer;
  • the second barrier wall 5 includes six layers of the second barrier layers 51 stacked in sequence.
  • the direction Z is arranged in the same layer as the two first flat layers 71 , the two second flat layers 72 , the third flat layer 73 and the pixel defining layer 8 (or the support pad 16 ) in sequence.
  • the display substrate 100 may include, for example, the four-layer connection layer 10 shown in FIG. 7 .
  • the two flat layers 72 are disposed on the same layer.
  • the first layer of connection layer 10 connects the first layer of the first barrier layer 41 and the first layer of the second barrier layer 51 to form an integrated structure;
  • the second layer of The connection layer 10 connects the second layer of the first barrier layer 41 and the second layer of the second barrier layer 51 to form an integral structure;
  • the third layer of connection layer 10 connects the third layer of the first barrier layer 41 and the third layer of the second barrier layer 51 , in an integrated structure;
  • the fourth connecting layer 10 connects the fourth first barrier layer 41 and the fourth second barrier layer 51 to form an integrated structure;
  • the fifth second barrier layer 51 and the sixth second barrier layer 51 are all disconnected from the fifth first barrier layer 41 .
  • the fifth layer of the first barrier layer 41 in the first barrier wall 4 and the fifth layer of the second barrier layer 51 and the sixth layer of the second barrier layer 51 in the second barrier wall 5 form the first barrier wall 4 and the second barrier layer 51 Gap between retaining walls 5.
  • the orthographic projection of the first connecting layer 10 on the substrate 1, the orthographic projection of the second connecting layer 10 on the substrate 1, the orthographic projection of the third connecting layer 10 on the substrate 1, the fourth connecting layer The orthographic projection of 10 on the substrate 1 and the orthographic projection of the above-mentioned gap on the substrate 1 overlap.
  • the step difference between the first retaining wall 4 and the gap is the thickness of the fifth layer of the first barrier layer 41
  • the step difference between the second retaining wall 5 and the gap is the thickness of the fifth layer of the second barrier layer 51 , the first barrier layer 41 .
  • the display substrate 100 may also include, for example, the three-layer connection layer 10 shown in FIG. 8 .
  • the three-layer connection layer 10 may be connected with two layers of the first flat layer 71 and two layers of the first layer of the second layer, for example, along the direction Z away from the substrate 1 , respectively.
  • the flat layer 72 is provided in the same layer.
  • the first layer of connection layer 10 connects the first layer of the first barrier layer 41 and the first layer of the second barrier layer 51 to form an integrated structure;
  • the second layer of The connection layer 10 connects the second layer of the first barrier layer 41 and the second layer of the second barrier layer 51 to form an integral structure;
  • the third layer of connection layer 10 connects the third layer of the first barrier layer 41 and the third layer of the second barrier layer 51.
  • the fourth layer of the second barrier layer 51, the fifth layer of the second barrier layer 51, the sixth layer of the second barrier layer 51 are integral with the fourth layer of the first barrier layer 41 and the fifth layer of the first barrier layer 41 Disconnect as a whole.
  • the sixth second barrier layer 51 forms a gap between the first blocking wall 4 and the second blocking wall 5 .
  • the level difference between the first blocking wall 4 and the gap is the sum of the thicknesses of the fourth layer of the first barrier layer 41 and the fifth layer of the first barrier layer 41
  • the level difference between the second blocking wall 5 and the gap is the sum of the thicknesses of the fourth second barrier layer 51 , the fifth second barrier layer 51 and the sixth second barrier layer 51 .
  • the display substrate 100 may also include, for example, two connecting layers 10 as shown in FIG. 9 .
  • the two connecting layers 10 may be disposed on the same layer as the two first flat layers 71 along the direction Z away from the substrate 1 .
  • the first layer of connection layer 10 connects the first layer of the first barrier layer 41 and the first layer of the second barrier layer 51 to form an integrated structure;
  • the second layer of The connection layer 10 connects the second layer of the first barrier layer 41 and the second layer of the second barrier layer 51 to form an integral structure;
  • the layer 51 and the sixth layer of the second barrier layer 51 are entirely disconnected from the third layer of the first barrier layer 41 , the fourth layer of the first barrier layer 41 , and the fifth layer of the first barrier layer 41 .
  • the fourth second barrier layer 51 , the fifth second barrier layer 51 , and the sixth second barrier layer 51 form a gap between the first retaining wall 4 and the second retaining wall 5 .
  • the orthographic projection of the first connecting layer 10 on the substrate 1, the orthographic projection of the second connecting layer 10 on the substrate 1, and the orthographic projection of the above-mentioned gap on the substrate 1 overlap.
  • the step difference between the first blocking wall 4 and the gap is the sum of the thicknesses of the third first blocking layer 41 , the fourth first blocking layer 41 , and the fifth first blocking layer 41 , and the second blocking layer
  • the step difference between the wall 5 and the gap is the sum of the thicknesses of the third second barrier layer 51 , the fourth second barrier layer 51 , the fifth second barrier layer 51 , and the sixth second barrier layer 51 .
  • the first barrier wall 4 includes a fifth layer of the first barrier layer 41 arranged on the same layer as the pixel defining layer 8
  • the second barrier wall 5 includes a sixth layer that is arranged on the same layer as the pixel defining layer 8 .
  • the first barrier wall 4 may further include, for example, a sixth layer of the first barrier layer 41 disposed on the same layer as the support pad 16
  • the second barrier wall 5 may also include, for example, the same layer as the support pad 16 .
  • the seventh layer of the second barrier layer 51 is provided, and the sixth layer of the first barrier layer 41 is disconnected from the seventh layer of the second barrier layer 51 .
  • the depth of the gap formed between the first retaining wall 4 and the second retaining wall 5 can be increased as much as possible while effectively avoiding the residual conductive material of the signal transmission line 400, so as to further improve the gap between the first retaining wall 4 and the second retaining wall 5.
  • the blocking and leveling effect of the second retaining wall 5 on the organic layer 32 further ensures the good encapsulation effect of the encapsulation layer 3 .
  • the multilayer first barrier layer 41 is provided in at least one of the following ways:
  • the first barrier layer 41 farthest from the substrate 1 among the multilayer first barrier layers 41 covers the second layer of the first barrier layer 41 farthest from the substrate 1 among the multilayer first barrier layers 41 facing the second barrier wall 5; or, the second layer of the first barrier layer 41 far away from the substrate 1 in the multi-layer first barrier layer 41 covers the third layer of the first barrier layer 41 in the multi-layer first barrier layer 41 far away from the substrate 1
  • the layer 41 faces the side of the second retaining wall 5 .
  • the above setting is performed in at least one manner.
  • the setting may be performed according to only one of the manners, or, for example, the setting may be combined with two or more manners at the same time.
  • only one layer of the first barrier layer 41 farthest from the substrate 1 in the multi-layer first barrier layers 41 covers a second layer of the multi-layer first barrier layer 41 farthest away from the substrate 1 .
  • the first barrier layer 41 faces the side of the second barrier wall 5 .
  • only the second layer of the first barrier layer 41 far away from the substrate 1 in the multi-layer first barrier layers 41 covers the third layer of the multi-layer first barrier layer 41 far away from the substrate 1 .
  • a first barrier layer 41 of the substrate 1 faces the side of the second barrier wall 5 .
  • a layer of the first barrier layer 41 farthest from the substrate 1 in the multi-layer first barrier layers 41 covers a second layer of the multi-layer first barrier layer 41 farthest away from the substrate 1 .
  • the first barrier layer 41 faces the side of the second retaining wall 5; the second layer of the first barrier layer 41 in the multi-layer first barrier layer 41 is far away from the substrate 1, and covers the third layer of the first barrier layer 41 far away from the substrate 1.
  • a first barrier layer 41 of the substrate 1 faces the side of the second barrier wall 5 .
  • the multilayer second barrier layer 51 is provided in at least one of the following ways:
  • the second barrier layer 51 farthest from the substrate 1 in the multilayer second barrier layers 51 covers the second barrier layer 51 farthest from the substrate 1 among the multilayer second barrier layers 51 facing the first barrier wall 4 side; or, the second barrier layer 51 in the second layer of the second barrier layer 51 away from the substrate 1 covers the third layer of the second barrier layer in the multi-layer second barrier layer 51 away from the substrate 1
  • the layer 51 faces the side of the first retaining wall 4; or, the third layer of the second barrier layer 51 in the multi-layer second barrier layer 51 far away from the substrate 1 covers the fourth layer in the multi-layer second barrier layer 51 far away from the substrate
  • One second barrier layer 51 of 1 faces the side of the first barrier wall 4 .
  • the above setting is performed in at least one manner.
  • the setting may be performed according to only one of the manners, or, for example, the setting may be combined with two or more manners at the same time.
  • only one second barrier layer 51 farthest from the substrate 1 in the multilayer second barrier layers 51 covers a second barrier layer 51 in the multilayer second barrier layer 51 that is farthest from the substrate 1 .
  • the second barrier layer 51 faces the side of the first barrier wall 4 .
  • the second barrier layer 51 of the second barrier layers 51 that is far away from the substrate 1 covers the third barrier layer 51 of the second barrier layers 51 that is far away from the substrate 1 .
  • the second barrier layer 51 faces the side of the first barrier wall 4 .
  • the third layer of the second barrier layer 51 far away from the substrate 1 in the multilayer second barrier layer 51 covers the fourth layer of the second barrier layer 51 far away from the substrate 1 .
  • the second barrier layer 51 faces the side of the first barrier wall 4 .
  • the second barrier layer 51 of the multilayer second barrier layers 51 which is far away from the substrate 1 , covers the third layer of the second barrier layers 51 that is far away from the substrate 1 .
  • a second barrier layer 51 faces the side of the first retaining wall 4 ; the third layer of the second barrier layer 51 in the multi-layer second barrier layer 51 is far from the substrate 1 , and covers the fourth layer of the multi-layer second barrier layer 51 .
  • a second barrier layer 51 away from the substrate 1 faces the side of the first barrier wall 4 .
  • the second barrier layer 51 of the multilayer second barrier layers 51 that is farthest from the substrate 1 covers a second barrier layer 51 of the multilayer second barrier layers 51 that is farthest from the substrate 1 .
  • the second barrier layer 51 faces the side of the first retaining wall 4; the second barrier layer 51 in the second barrier layer 51 is far away from the substrate 1, and covers the third barrier layer 51 in the multi-layer second barrier layer 51 away from the substrate 1.
  • a second barrier layer 51 of the substrate 1 faces the side of the first retaining wall 4; a third layer of the second barrier layer 51 in the multilayer second barrier layer 51 is far from the substrate 1, covering the multilayer second barrier layer The fourth layer of the second barrier layer 51 in 51 that is far away from the substrate 1 faces the side of the first barrier wall 4 .
  • a first barrier layer 41 closest to the substrate 1 is connected to a second layer closest to the substrate 1 through a connecting layer 10 .
  • the barrier layer 51 is used to form the first communication part 12, and the second layer of the first barrier layer 41 adjacent to the substrate 1 is connected to the second layer of the second barrier layer 51 adjacent to the substrate 1 through a layer of connection layer 10 to form a second layer of the barrier layer 51.
  • Communication part 13 is used to form the first communication part 12, and the second layer of the first barrier layer 41 adjacent to the substrate 1 is connected to the second layer of the second barrier layer 51 adjacent to the substrate 1 through a layer of connection layer 10 to form a second layer of the barrier layer 51.
  • the display substrate 100 further includes a voltage signal line 14 disposed on one side of the substrate 1 .
  • the voltage signal lines 14 are located in the peripheral area B and arranged around the display area A.
  • the region of the voltage signal line 14 away from the display area A is located between the first communication part 12 and the second communication part 13, and the orthographic projection of the edge of the voltage signal line 14 away from the display area A on the substrate 1 is located in the first connection part 13. Between the orthographic projection of the edge of the portion 12 close to the display area A on the substrate 1 and the orthographic projection of the edge of the first communicating portion 12 away from the display area A on the substrate 1 .
  • the first communication part 12 is an organic insulating layer and the voltage signal line 14 is a metal layer
  • the voltage signal line 14 is a metal layer
  • the display substrate further includes a barrier layer 9 .
  • one end of the barrier layer 9 extends between two adjacent first barrier layers 41 , the other end of the barrier layer 9 extends between two adjacent flat layers 7 , and one end of the barrier layer 9 overlaps
  • the connected first barrier layer 41 is disposed in the same layer as the flat layer 7 overlapped with the other end of the barrier layer 9 .
  • each thin film is formed in sequence. That is, the thin film formed earlier is close to the substrate 1 , and the thin film formed later is far from the substrate 1 . Therefore, the barrier layer 9 is formed later than the first barrier layer 41 and the flat layer 7 with which it overlaps.
  • the barrier layer 9 by setting the barrier layer 9, not only can the barrier layer 9 be used to reduce the level difference between the first barrier wall 4 and the multilayer flat layer 7, and the rate of change of the level difference can be reduced, but also the barrier layer 9 can be used to block the first block.
  • Layer the first barrier layer 41 and the first flat layer 7 to avoid mutual contact between the two to form a water-oxygen channel, thereby preventing water vapor from entering the display area A, which is beneficial to improve the ability to block water vapor and prevent water vapor from entering the display area A. resulting in packaging failure.
  • the barrier layer 9 is disposed on the same layer as at least one of the wire layers 6 described above.
  • the barrier layer 9 may be provided in the same layer as the conductor layer 6 .
  • the barrier layer 9 may be disposed on the same layer as one of the conductor layers 6 . This is beneficial to simplify the manufacturing method of the display substrate 100 .
  • the orthographic projection of the first barrier layer 41 farthest from the substrate 1 among the above-mentioned multilayer first barrier layers 41 on the substrate 1 is located in the multilayer first barrier layer 41
  • the second layer of the first barrier layer 41 away from the substrate 1 is within the orthographic projection range on the substrate 1 .
  • the orthographic projection area of the first barrier layer 41 farthest from the substrate 1 on the substrate 1 is smaller than the orthographic projection area of the second layer of the first barrier layer 41 farthest from the substrate 1 on the substrate 1,
  • the first barrier layer 41 farthest from the substrate 1 only covers a part of the second first barrier layer 41 farthest from the substrate 1 .
  • the orthographic projection of the first barrier layer 41 on which one end of the barrier layer 9 is overlapped on the substrate 1 is on the substrate 1 with the flat layer 7 on the side away from the substrate 1 at the other end of the barrier layer 9 orthographic projection, tangent or overlapping.
  • the step difference of the thin film included in the display substrate 100 in the transition region between the peripheral region B and the display region A can be small, so as to ensure the yield of the signal transmission line 400 formed subsequently.
  • the structure of the touch grid structure 200 in the display device 1000 may include various structures, and settings may be selected according to actual needs.
  • the touch grid structure 200 may include: a plurality of conductive bridges arranged in an array, and a plurality of rows of first touch sub-electrodes.
  • Each row of the first touch sub-electrodes may include, for example, a plurality of first touch sub-electrodes spaced along the first direction X, and in each row of the first touch sub-electrodes, each adjacent two first touch sub-electrodes It is electrically connected to a conductive bridge through a via hole, so that the plurality of rows of first touch sub-electrodes and the plurality of conductive bridges constitute a plurality of first touch electrodes.
  • the touch grid structure 200 may further include: a plurality of second touch electrodes extending along the second direction Y, and each second touch electrode may include, for example, a plurality of The second touch sub-electrode.
  • each of the second touch electrodes is an integral structure.
  • each first touch electrode is electrically connected to the touch driving chip 500 through a signal transmission line 400
  • each second touch electrode is electrically connected to the touch driving chip 500 through a signal transmission line 400 . connect.
  • the signal transmission line 400 included in the display device 1000 may be disposed on the same layer as the above-mentioned conductive bridge. Such a design is beneficial to simplify the manufacturing process of the display device 1000 .
  • the above-mentioned display device 1000 can be, for example, any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Some embodiments of the present disclosure further provide a manufacturing method of the display substrate 100 according to any of the above embodiments. Please refer to FIG. 15, the manufacturing method includes S1-S2.
  • first blocking wall 4 Form the first blocking wall 4, the connecting portion 15 and the second blocking wall 5 which are located in the peripheral area B and are in turn away from the display area A on one side of the substrate 1; wherein, the height of the second blocking wall 5 is greater than that of the first blocking wall 5
  • the height of the retaining wall 4; the height of the connecting part 15 is smaller than the height of the first retaining wall 4; the first retaining wall 4, the connecting part 15 and the second retaining wall 5 are at least partially integrated.
  • the first barrier wall 4 includes multiple layers of first barrier layers 41 stacked in sequence
  • the second barrier wall 5 includes multiple layers of second barrier layers 51 stacked sequentially; the total number of layers of the second barrier layers 51 is greater than that of the second barrier layer 51 .
  • the total number of layers of a barrier layer 41 is greater than that of the second barrier layer 51 .
  • the connecting part 15 includes at least one connecting layer 10 , and the total number of the connecting layers 10 is less than the total number of the first barrier layers 41 ; at least one layer of the first barrier layer 41 close to the substrate 1 among the multiple first barrier layers 41 and at least one second barrier layer 51 adjacent to the substrate 1 among the multiple second barrier layers 51 is connected by at least one connecting layer 10 .
  • connection layer 10 connects a layer of first barrier layer 41 and a layer of second barrier layer 52, and the connection layer 10 and the first barrier layer 41 and the second barrier layer 51 connected thereto can be patterned at the same time, for example Process formed.
  • the manufacturing methods of the display substrate 100 in the above-mentioned embodiments are used to prepare the display substrate 100 provided by any of the foregoing embodiments.
  • the display substrate 100 manufactured by this manufacturing method has the same beneficial effects as the display substrate 100 in any of the above-mentioned embodiments, and will not be repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板，具有显示区和周边区；所述显示基板包括：衬底、第一挡墙、第二挡墙和连接部。第一挡墙和第二挡墙位于衬底的一侧、且位于周边区；第二挡墙相对于第一挡墙远离显示区；第二挡墙的高度大于第一挡墙的高度。连接部位于第一挡墙与第二挡墙之间，连接部连接第一挡墙与第二挡墙，且连接部的高度小于第一挡墙的高度。其中，第一挡墙、连接部和第二挡墙三者的至少部分为一体结构。

Description

显示面板及其制作方法、显示装置
本申请要求于2021年01月28日提交的、申请号为202110121161.6的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，例如涉及一种显示面板及其制作方法、显示装置。
背景技术
随着科学技术的不断发展，用户对显示装置的屏占比(显示屏的面积与显示装置的前面板的面积的比例)有着越来越高的追求。因此，出现了全面屏的概念，例如，将显示装置中的图像采集器和摄像头等光学器件设置在显示屏的下方，以增大显示屏的面积与显示装置的前面板的面积之间的比例，并使得该比例趋近于100％。
发明内容
一方面，提供一种显示基板。所述显示基板具有显示区和周边区；所述显示基板包括：衬底、第一挡墙、第二挡墙和连接部。所述第一挡墙和所述第二挡墙位于所述衬底的一侧、且位于所述周边区；所述第二挡墙相对于所述第一挡墙远离所述显示区；所述第二挡墙的高度大于所述第一挡墙的高度。所述连接部位于所述第一挡墙与所述第二挡墙之间，所述连接部连接所述第一挡墙与所述第二挡墙，且所述连接部的高度小于所述第一挡墙的高度；其中，所述第一挡墙、所述连接部和所述第二挡墙三者的至少部分为一体结构。
在一些实施例中，所述第一挡墙包括依次层叠的多层第一阻挡层，所述第二挡墙包括依次层叠的多层第二阻挡层；第二阻挡层的总层数大于第一阻挡层的总层数；所述连接部包括至少一层连接层；所述连接层的总层数小于所述第一阻挡层的总层数。
在一些实施例中，所述多层第一阻挡层中靠近所述衬底的至少一层第一阻挡层和所述多层第二阻挡层中靠近所述衬底的至少一层第二阻挡层，通过至少一层连接层连接。
在一些实施例中，一层所述连接层连接一层所述第一阻挡层和一层所述第二阻挡层。
在一些实施例中，所述第一挡墙靠近所述显示区一侧的侧壁，在远离所述衬底的方向上逐渐远离所述显示区，且呈斜坡状或阶梯状；所述第一挡墙远离所述显示区一侧的侧壁中未与所述连接部连接的部分，在远离所述衬底 的方向上逐渐靠近所述显示区，且呈斜坡状或阶梯状。
在一些实施例中，所述第二挡墙靠近所述显示区一侧的侧壁中未与所述连接部连接的部分，在远离所述衬底的方向上逐渐远离所述显示区，且呈斜坡状或阶梯状；所述第二挡墙远离所述显示区一侧的侧壁，在远离所述衬底的方向上逐渐靠近所述显示区，且呈斜坡状或阶梯状。
在一些实施例中，所述第一挡墙远离所述显示区一侧的侧壁中未与所述连接部连接的部分的坡度，小于所述第二挡墙靠近所述显示区一侧的侧壁中未与所述连接部连接的部分的坡度。
在一些实施例中，所述第一挡墙靠近所述显示区一侧的侧壁的坡度，小于所述第二挡墙远离所述显示区一侧的侧壁的坡度。
在一些实施例中，所述第二挡墙靠近所述显示区一侧的侧壁中未与所述连接部连接的部分，在远离所述衬底的方向上逐渐远离所述显示区；所述第二挡墙靠近所述显示区一侧的侧壁中未与所述连接部连接的部分呈斜坡状或阶梯状。
在一些实施例中，所述显示区包括主显示区和辅助显示区；所述显示基板位于所述辅助显示区的部位的光线透过率大于所述显示基板位于所述主显示区的部位的光线透过率。
在一些实施例中，所述显示基板还包括：设置于所述衬底一侧的多个第一子像素和多个第二子像素。所述多个第一子像素位于所述主显示区。第二子像素包括：像素驱动电路和发光器件。所述发光器件设置于所述像素驱动电路远离所述衬底的一侧，所述发光器件位于所述辅助显示区，所述发光器件与所述像素驱动电路耦接。所述多个第二子像素中，至少一个所述像素驱动电路位于所述辅助显示区以外。
在一些实施例中，所述显示基板还包括：设置于所述像素驱动电路与所述发光器件之间，且依次层叠的多层平坦层。其中，所述多层第一阻挡层中除最远离所述衬底的一层或两层第一阻挡层以外的第一阻挡层，与所述多层平坦层中的部分平坦层分别同层设置；和/或，所述多层第二阻挡层中除最远离所述衬底的一层或两层第二阻挡层以外的第二阻挡层，与所述多层平坦层中的全部平坦层分别同层设置。
在一些实施例中，所述显示基板还包括：至少一层导线层，导线层包括至少一条透光导线；位于所述周边区的一个所述像素驱动电路通过一条透光导线与相应的一个所述发光器件耦接。其中，所述至少一层导线层整体与所述像素驱动电路之间设置有至少一层所述平坦层；所述至少一层导线层整体 与所述发光器件之间设置有至少一层所述平坦层。
在一些实施例中，相邻两层所述导线层之间设置有至少一层所述平坦层。
在一些实施例中，所述至少一层导线层整体与所述像素驱动电路之间的所述平坦层为第一平坦层，所述第一平坦层的层数为一层或两层。当所述第一平坦层的层数为一层时，所述多层第一阻挡层中包括与一层所述第一平坦层同层设置的第一个第一阻挡层，所述多层第二阻挡层中包括与一层所述第一平坦层同层设置的第一个第二阻挡层，所述至少一层连接层包括第一个连接层；所述第一个连接层连接所述第一个第一阻挡层与所述第一个第二阻挡层。
在一些实施例中，当所述第一平坦层的层数为两层时，所述多层第一阻挡层中还包括与另一层所述第一平坦层同层设置的第二个第一阻挡层，所述多层第二阻挡层中还包括与另一层所述第一平坦层同层设置的第二个第二阻挡层，所述至少一层连接层还包括第二个连接层；所述第二个连接层连接所述第二个第一阻挡层与所述第二个第二阻挡层。
在一些实施例中，相邻两层所述导线层之间的所述平坦层为第二平坦层。所述导线层的层数为三层，靠近所述衬底的相邻两层所述导线层之间的所述平坦层为第一个第二平坦层，远离所述衬底的相邻两层所述导线层之间的所述平坦层为第二个第二平坦层。所述多层第一阻挡层中包括与所述第一个第二平坦层同层设置的第三个第一阻挡层，以及与所述第二个第二平坦层同层设置的第四个第一阻挡层。所述多层第二阻挡层中包括与所述第一个第二平坦层同层设置的第三个第二阻挡层，以及与所述第二个第二平坦层同层设置的第四个第二阻挡层。
在一些实施例中，所述至少一层连接层包括第三个连接层以及第四个连接层；所述第三个连接层连接所述第三个第一阻挡层与所述第三个第二阻挡层，所述第四个连接层连接所述第四个第一阻挡层与所述第四个第二阻挡层。
在一些实施例中，所述至少一层连接层包括第三个连接层；所述第三个连接层连接所述第三个第一阻挡层与所述第三个第二阻挡层；所述第四个第一阻挡层与所述第四个第二阻挡层之间断开。
在一些实施例中，所述显示基板还包括：设置于所述多层平坦层远离所述衬底一侧的像素界定层；以及，设置于所述像素界定层远离所述衬底一侧的表面上的多个支撑垫。其中，所述多层第一阻挡层中最远离所述衬底的一层第一阻挡层与所述像素界定层或所述多个支撑垫同层设置；所述多层第二阻挡层中最远离所述衬底的一层第二阻挡层与所述像素界定层或所述多个支 撑垫同层设置。
在一些实施例中，当所述多层第一阻挡层中最远离所述衬底的一层第一阻挡层与所述多个支撑垫同层设置时，所述多层第一阻挡层中第二远离所述衬底的一层第一阻挡层与所述像素界定层同层设置；当所述多层第二阻挡层中最远离所述衬底的一层第二阻挡层与所述多个支撑垫同层设置时，所述多层第二阻挡层中第二远离所述衬底的一层第二阻挡层与所述像素界定层同层设置。
在一些实施例中，所述多层第一阻挡层中还包括与所述像素界定层或所述多个支撑垫同层设置的第五个第一阻挡层。所述至少一层导线层整体与所述发光器件之间的所述平坦层为第三平坦层，所述第三平坦层的层数为一层；所述多层第二阻挡层中还包括与所述第三平坦层同层设置的第五个第二阻挡层，以及与所述像素界定层或所述多个支撑垫同层设置的第六个第二阻挡层。其中，所述第五个第二阻挡层、所述第六个第二阻挡层均与所述第五个第一阻挡层断开。
在一些实施例中，所述显示基板还包括：阻隔层，所述阻隔层的一端延伸至相邻两层所述第一阻挡层之间，所述阻隔层的另一端延伸至相邻两层所述平坦层之间；所述阻隔层的一端所搭接的所述第一阻挡层与所述阻隔层的另一端所搭接的所述平坦层同层设置。
在一些实施例中，所述阻隔层的一端所搭接的所述第一阻挡层在所述衬底上的正投影与位于所述阻隔层的另一端远离所述衬底一侧的所述平坦层在所述衬底上的正投影，相切或相交叠。
在一些实施例中，当所述显示基板包括多层导线层时，所述阻隔层与所述多层导线层中的至少一层同层设置。
在一些实施例中，所述显示基板还包括：设置于所述多个第一子像素和所述多个第二子像素远离所述衬底一侧的封装层；所述封装层被配置为将所述多个第一子像素和所述多个第二子像素封装在所述衬底上。所述封装层包括：第一无机层；设置于所述第一无机层远离所述衬底一侧的有机层；以及，设置于所述有机层远离所述衬底一侧的第二无机层。其中，所述第一挡墙和所述第二挡墙用于对所述有机层进行阻挡；所述第一无机层覆盖所述第一挡墙和所述第二挡墙，所述第二无机层覆盖所述第一挡墙和所述第二挡墙。
在一些实施例中，所述多层第一阻挡层中，最靠近所述衬底的一层第一阻挡层通过一层所述连接层连接最靠近所述衬底的一层第二阻挡层以形成第一连通部，第二靠近所述衬底的一层第一阻挡层通过一层所述连接层连接第 二靠近所述衬底的一层第二阻挡层以形成第二连通部。所述显示基板还包括：设置于所述衬底一侧的电压信号线，所述电压信号线位于所述周边区且围绕所述显示区设置；所述电压信号线中远离所述显示区的区域位于所述第一连通部与所述第二连通部之间，且所述电压信号线远离所述显示区的边缘在所述衬底上的正投影，位于所述第一连通部靠近所述显示区的边缘在所述衬底上的正投影与所述第一连通部远离所述显示区的边缘在所述衬底上的正投影之间。
在一些实施例中，所述多层第一阻挡层按照以下至少一种方式设置：所述多层第一阻挡层中最远离所述衬底的一层第一阻挡层，覆盖所述多层第一阻挡层中第二远离所述衬底的一层第一阻挡层朝向所述第二挡墙的侧面；或者，所述多层第一阻挡层中第二远离所述衬底的一层第一阻挡层，覆盖所述多层第一阻挡层中第三远离所述衬底的一层第一阻挡层朝向所述第二挡墙的侧面。
在一些实施例中，所述多层第二阻挡层按照以下至少一种方式设置：所述多层第二阻挡层中最远离所述衬底的一层第二阻挡层，覆盖所述多层第二阻挡层中第二远离所述衬底的一层第二阻挡层朝向所述第一挡墙的侧面；或者，所述多层第二阻挡层中第二远离所述衬底的一层第二阻挡层，覆盖所述多层第二阻挡层中第三远离所述衬底的一层第二阻挡层朝向所述第一挡墙的侧面；或者，所述多层第二阻挡层中第三远离所述衬底的一层第二阻挡层，覆盖所述多层第二阻挡层中第四远离所述衬底的一层第二阻挡层朝向所述第一挡墙的侧面。
在一些实施例中，所述连接层和与其连接的所述第一阻挡层、所述第二阻挡层三者同层设置。
另一方面，提供一种显示基板的制作方法。所述显示基板具有显示区和周边区。所述制作方法包括：提供衬底；在所述衬底的一侧形成位于所述周边区、且依次远离所述显示区的第一挡墙、连接部和第二挡墙；其中，所述第二挡墙的高度大于所述第一挡墙的高度；所述连接部的高度小于所述第一挡墙的高度；所述第一挡墙、所述连接部和所述第二挡墙三者的至少部分为一体结构。
在一些实施例中，所述第一挡墙包括依次层叠的多层第一阻挡层，所述第二挡墙包括依次层叠的多层第二阻挡层；第二阻挡层的总层数大于第一阻挡层的总层数；所述连接部包括至少一层连接层；所述连接层的总层数小于所述第一阻挡层的总层数；所述多层第一阻挡层中靠近所述衬底的至少一层 第一阻挡层和所述多层第二阻挡层中靠近所述衬底的至少一层第二阻挡层，通过至少一层连接层连接。其中，一层所述连接层连接一层所述第一阻挡层和一层所述第二阻挡层，所述连接层和与其连接的所述第一阻挡层、所述第二阻挡层三者通过同一次构图工艺形成。
再一方面，提供一种显示装置，包括：如上述任一实施例中所述的显示基板。
在一些实施例中，所述显示基板的周边区包括绑定区，所述绑定区位于所述第二挡墙远离所述显示区的一侧。所述显示装置还包括：位于所述显示基板的绑定区的触控驱动芯片；位于所述显示基板的显示区的触控网格结构；以及连接所述触控驱动芯片和所述触控网格结构的多条信号传输线。所述多条信号传输线位于所述第一挡墙和所述第二挡墙整体远离所述衬底的一侧，所述多条信号传输线在所述衬底上的正投影与所述连接层在所述衬底上的正投影部分重叠。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本公开一些实施例提供的一种显示装置的结构图；
图2为本公开一些实施例提供的另一种显示装置的结构图；
图3为本公开一些实施例提供的一种显示装置的局部结构图；
图4为本公开一些实施例提供的一种显示基板的结构图；
图5为本公开一些实施例提供的一种显示基板的局部结构图；
图6为本公开一些实施例提供的另一种显示基板的局部结构图；
图7为本公开一些实施例提供的又一种显示基板的局部结构图；
图8为本公开一些实施例提供的又一种显示基板的局部结构图；
图9为本公开一些实施例提供的又一种显示基板的局部结构图；
图10为本公开一些实施例提供的又一种显示基板的局部结构图；
图11为本公开一些实施例提供的又一种显示基板的局部结构图；
图12为本公开一些实施例提供的又一种显示基板的局部结构图；
图13为本公开一些实施例提供的又一种显示基板的局部结构图；
图14为本公开一些实施例提供的又一种显示基板的局部结构图；
图15为本公开一些实施例提供的一种显示基板的制作方法的流程图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是 “当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开一些实施例提供了一种显示装置1000。请参阅图1～图3，该显示装置1000包括显示基板100、触控网格结构200、触控驱动芯片300、多条信号传输线400。
在一些示例中，请参阅图1和图3，显示装置1000还包括光学器件500。
需要说明的是，上述光学器件500的类型包括多种，可以根据实际需要选择设置。示例性的，上述光学器件500可以为摄像头、红外接收器或红外发射器等。
在一些示例中，请参阅图4，该显示基板100具有显示区A和周边区B。其中，显示基板100中位于显示区A的部位能够进行图像显示。
需要说明的是，本公开对周边区B的设置位置不做限制。例如，周边区 B可以位于显示区A的一侧、两侧或三侧等。又例如，周边区B也可以位于显示区A的周边。
在一些示例中，请继续参阅图4，显示区A包括主显示区A1和辅助显示区A2。例如，主显示区A1的面积可以大于辅助显示区A2的面积。
需要说明的是，辅助显示区A2的数量可以为一个，也可以为多个，具体可以根据实际需要选择设置。上述主显示区A1和辅助显示区A2之间的位置关系包括多种，可以根据实际需要选择设置。
示例性的，请继续参阅图4，辅助显示区A2位于主显示区A1的旁边，也即，辅助显示区A2的边界的一部分与主显示区A1的边界的一部分重叠。此时，辅助显示区A2的形状例如可以为矩形、圆角矩形、水滴形或半圆形等。
示例性的，主显示区A1可以位于辅助显示区A2的周边，也即，主显示区A1对辅助显示区A2形成了包围。此时，辅助显示区A2的形状例如可以为圆形、椭圆形或矩形等。
在一些示例中，显示基板100位于辅助显示区A2的部位的光线透过率大于显示基板100位于主显示区A1的部位的光线透过率。这样设计，可以在外界光线透过显示基板100位于辅助显示区A2的部位，入射至光学器件500以使得光学器件500进行工作的过程中，减少对外界光线的遮挡，提高光学器件500的工作性能。
在一些示例中，请继续参阅图4，周边区B包括至少一个绑定区B1。示例性的，显示区A和绑定区B1之间可以具有间隙。
下面，以光学器件500为摄像头、辅助显示区A2的数量为一个、绑定区B1的数量为一个、且辅助显示区A2位于主显示区A1的旁边为例，对显示装置1000的结构进行示意性说明。
在一些示例中，请参阅图3，光学器件500设置在显示基板100的非出光侧，且位于显示基板100的辅助显示区A2。外界光线能够透过显示基板100，入射至光学器件500，使得光学器件500能够进行工作。
在一些示例中，请继续参阅图3，上述触控网格结构200可以设置在显示基板100的出光侧、且位于显示基板100的显示区A。也即，光学器件500和触控网格结构200位于显示基板100的相对两侧。
这样设计，用户便可以利用该触控网格结构200实现对显示基板100所要显示的图像的控制，使得显示装置1000同时具有显示功能和触控功能。
在一些示例中，请参阅图2，触控驱动芯片300可以设置在绑定区B1内，且与触控网格结构200位于显示基板100的同一侧。触控驱动芯片300可以 向触控网格结构200传输触控驱动信号，也可以接收触控网格结构200所传输的触控感测信号，使得用户能够通过触控网格结构200实现对显示基板100所要显示的图像的控制。
在一些示例中，请继续参阅图2，多条信号传输线400与触控网格结构200、触控驱动芯片300位于显示基板100的同一侧。每条信号传输线400的一端伸入显示区A、并与触控网格结构200电连接；每条信号传输线400的另一端伸入绑定区B1、并与触控驱动芯片300电连接。这样触控驱动芯片300和触控网格结构200便可以通过信号传输线400实现触控驱动信号及触控感测信号的传输。
此时，由于触控网格结构200位于显示区A，触控驱动芯片300位于绑定区B1，这也就意味着，信号传输线400需要穿过周边区B，实现触控网格结构200与触控驱动芯片300之间的电连接。
在一些示例中，在光学器件500未工作的过程中，显示基板100位于显示区A的部位能够进行图像显示。
在一些示例中，在光学器件500工作(例如用户自拍)的过程中，显示基板100位于主显示区A1的部分可以呈现用户自拍的画面，显示基板100位于辅助显示区A2的部分可以呈现黑色画面，较为明确地显示出光学器件500所在位置。
在另一些示例中，在光学器件500工作(例如用户自拍)的过程中，显示基板100位于主显示区A1的部分和位于辅助显示区A2的部分可以整体呈现用户自拍的画面。
下面结合附图对本公开一些实施例提供的显示基板100的结构进行示意性说明。
在一些实施例中，请参阅图4，显示基板100包括衬底1。
需要说明的是，衬底1的类型包括多种，可以根据实际需要选择设置。
示例性的，衬底1可以为刚性衬底。该刚性衬底例如可以为玻璃衬底或PMMA(Polymethyl methacrylate，聚甲基丙烯酸甲酯)衬底等。
示例性的，衬底1可以为柔性衬底。该柔性衬底例如可以为PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)衬底、PI(Polyimide，聚酰亚胺)衬底或PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)衬底等。
在一些实施例中，请继续参阅图4，显示基板100还包括：设置于衬底1一侧的多个第一子像素P1和多个第二子像素P2。其中，多个第一子像素P1 和多个第二子像素P2可以相互配合，使得显示基板100能够进行图像显示。
在一些示例中，每个第一子像素P1包括像素驱动电路和发光器件。发光器件可以位于像素驱动电路远离衬底1的一侧，且与像素驱动电路电连接，像素驱动电路被配置为提供驱动电压至发光器件，以控制该发光器件的发光状态。
请参阅图4和图5，每个第二子像素P2包括像素驱动电路21和发光器件22。发光器件22可以位于像素驱动电路21远离衬底1的一侧，且与像素驱动电路21电连接。像素驱动电路21被配置为提供驱动电压至发光器件22，以控制该发光器件22的发光状态。
需要说明的是，第一子像素P1所包括的像素驱动电路的结构，可以与第二子像素P2所包括的像素驱动电路21的结构相同。示例性的，第一子像素P1所包括的发光器件的结构，可以与第二子像素P2所包括的发光器件22的结构相同。
示例性的，像素驱动电路21的结构可以包括多种，本公开对此不作限制。例如，像素驱动电路21的结构可以为“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构；其中，“T”表示为薄膜晶体管，位于“T”前面的数字表示为薄膜晶体管的个数，“C”表示为存储电容器，“C”前面的数字表示为存储电容器的个数。又例如，像素驱动电路21所包括的薄膜晶体管可以为底栅结构的薄膜晶体管，或者为顶栅结构的薄膜晶体管。
示例性的，发光器件22的结构可以包括多种，本公开对此不作限制。例如，发光器件22的结构可以为OLED(OrganicLight Emitting Diode，有机发光二极管)器件，也可以为QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)器件。又例如，发光器件22的出光方式可以为顶出光，或者为底出光。
本公开一些实施例以像素驱动电路21中的薄膜晶体管为顶栅结构的薄膜晶体管、发光器件22为OLED发光器件、发光器件22的出光方式为顶出光为例进行示意性说明。
在一些示例中，请参阅图5，第一子像素P1中的像素驱动电路可以通过连接结构与相应的发光器件电连接，第二子像素P2中的像素驱动电路21可以通过连接结构11与相应的发光器件22电连接。这样设计，有利于降低布线难度。
在一些示例中，请参阅图4，显示基板100所包括的多个第一子像素P1位于主显示区A1。显示基板100所包括的多个第二子像素P2中，各发光器 件22位于辅助显示区A2，至少一个像素驱动电路21位于辅助显示区A2以外。
示例性的，多个第二子像素P2中仅一个像素驱动电路21位于辅助显示区A2以外，或者每个第二子像素P2中的像素驱动电路21位于辅助显示区A2以外。
需要说明的是，上述位于辅助显示区A2以外，例如可以是位于周边区B和/或主显示区A1。
示例性的，当多个第二子像素P2中仅一个像素驱动电路21位于辅助显示区A2以外时，该位于辅助显示区A2以外的一个像素驱动电路21可以位于周边区B或主显示区A1。
示例性的，当每个第二子像素P2中的像素驱动电路21位于辅助显示区A2以外，也即，多个像素驱动电路21位于辅助显示区A2以外时，该位于辅助显示区A2以外的多个像素驱动电路21可以均位于周边区B，也可以均位于主显示区A1，还可以一部分位于周边区B，另一部分位于主显示区A1。
示例性的，若多个第二子像素P2中的像素驱动电路21设置在周边区B和/或主显示区A1，则多个像素驱动电路21可以设置在周边区B和/或主显示区A1中靠近辅助显示区A2的一侧，且多个像素驱动电路21依次排列或者呈阵列状排列。
由于像素驱动电路21主要由金属线路构成，该金属线路能够对光线形成较强的阻挡效果。上述一些示例通过将至少一个像素驱动电路21设置在辅助显示区A2以外，可以减小设置在辅助显示区A2的像素驱动电路21的数量，从而在外界光线透过显示基板100位于辅助显示区A2的部位，入射至光学器件500以使得光学器件500进行工作的过程中，可以减少对外界光线的遮挡，增加透过显示基板100的光线透过率，提高光学器件500的工作性能。
在一些实施例中，请参阅图4～图6，显示基板还包括：设置于多个第一子像素P1和多个第二子像素P2远离衬底1一侧的封装层3；封装层3被配置为将多个第一子像素P1和多个第二子像素P2封装在衬底1上。
在一些示例中，多个第一子像素P1和多个第二子像素P2在衬底1上的正投影位于封装层3在衬底1上的正投影范围内。这样设计，可以利用封装层3对第一子像素P1所包括的发光器件和第二子像素P2所包括的发光器件22形成良好的封装效果，避免外界水蒸气和/或氧气等对第一子像素P1所包括的发光器件和第二子像素P2所包括的发光器件22造成侵蚀，从而影响发光效率及使用寿命。
在一些示例中，请参阅图4和图7～图14，封装层3可以包括：第一无机层31、设置于第一无机层31远离衬底1一侧的有机层32、以及设置于有机层32远离衬底1一侧的第二无机层33。第一无机层31和/或第二无机层33例如可以采用无机绝缘材料，并采用沉积工艺制备形成；有机层32例如可以采用有机绝缘材料，并采用喷墨打印工艺制备形成。
基于此，在一些实施例中，请继续参阅图4和图7～图14，显示基板100还包括：第一挡墙4和第二挡墙5。第一挡墙4和第二挡墙5用于对封装层3的一部分进行阻挡。
在一些示例中，第二挡墙5相对于第一挡墙4远离显示区A，第一挡墙4相对于设置于周边区B的至少一个像素驱动电路21远离显示区A。也即，在显示基板100中，设置于周边区B的像素驱动电路21、第一挡墙4、第二挡墙5依次远离显示区A。
示例性的，请参阅图4，第一挡墙4和第二挡墙5可以设置于显示基板100的边缘，并呈环状设置。其中，第一挡墙4对多个第一子像素P1和多个第二子像素P2形成包围，第二挡墙5对第一挡墙4形成包围。
第一无机层31例如可以在覆盖多个第一子像素P1和多个第二子像素P2的同时，覆盖第一挡墙4和第二挡墙5，以形成较好的封装效果。
有机层32例如可以位于第一挡墙4所限定的范围内，也即，有机层32在衬底1上的正投影，位于第一挡墙4在衬底1上的正投影范围内。这也就意味着，第一挡墙4能够对封装层3中的有机层32进行阻挡，以确保良好的封装效果。
示例性的，第二挡墙5的高度大于第一挡墙4的高度。其中，上述第二挡墙5的高度可以是第二挡墙5远离衬底1的一端与衬底1之间的垂直距离。上述第一挡墙4的高度可以是第一挡墙4远离衬底1的一端与衬底1之间的垂直距离。
需要说明的是，由于制备形成有机层32的工艺，不可避免地会具有一定的误差，这样可能会使得第一挡墙4未对有机层32形成良好的阻挡。上述示例通过将第二挡墙5的高度设置为大于第一挡墙4的高度，从而利用第二挡墙5对有机层32形成进一步的阻挡，提高对有机层32的阻挡效果，进而提高封装层3的封装效果。
示例性的，第二无机层33可以覆盖有机层32和第一无机层31，且在覆盖第一无机层31的同时，覆盖第一挡墙4和第二挡墙5，以形成较好的封装效果。
需要说明的是，由于有机层32在衬底1上的正投影，位于第一挡墙4在衬底1上的正投影范围内，且第一无机层31和第二无机层33对第一挡墙4和第二挡墙5形成了覆盖，因此，第一无机层31和第二无机层33中超出有机层32的部位可以形成接触。
在一些示例中，请参阅图7～图14，显示基板100还包括位于第一挡墙4和第二挡墙5之间的连接部15，连接部15连接第一挡墙4和第二挡墙5；其中，第一挡墙4、连接部15和第二挡墙5三者的至少部分为一体结构。
需要说明的是，上述第一挡墙4、连接部15和第二挡墙5三者的至少部分为一体结构，例如可以是第一挡墙4的一部分、连接部15的一部分和第二挡墙5的一部分为一体结构。
示例性的，连接部15的高度小于第一挡墙4的高度。其中，上述连接部15的高度可以是连接部15远离衬底1的一端与衬底1之间的垂直距离，上述第一挡墙4的高度可以是第一挡墙4远离衬底1的一端与衬底1之间的垂直距离。
上述一些示例中，第一挡墙4和第二挡墙5之间形成了间隙，通过连接部15连接第一挡墙4和第二挡墙5，可以减小第一挡墙4和该间隙之间的段差，以及第二挡墙5和该间隙之间的段差。
在此基础上，显示装置1000中的信号传输线400例如可以采用光刻工艺制备形成。也即，在显示基板100的出光侧(也即封装层3远离衬底1的一侧)形成信号传输线400的过程中，可以采用沉积工艺形成导电材料薄膜，然后在该导电材料薄膜远离衬底1的一侧涂覆光刻胶，之后对该光刻胶进行曝光、显影，并对导电材料薄膜进行图案化，得到信号传输线400。此时，由于信号传输线400需要穿过周边区B，实现触控网格结构200与触控驱动芯片300之间的连接，因此，信号传输线400在衬底1上的正投影会与连接部15在衬底1上的正投影相交叠，也即，部分信号传输线400会覆盖第一挡墙4和第二挡墙5之间的间隙(如图7～图12所示)。
上述一些示例，通过减小第一挡墙4和该间隙之间的段差以及第二挡墙5和该间隙之间的段差，使得采用光刻工艺制备形成信号传输线400的过程中，可以减小光刻胶在该间隙内的厚度，这样在对光刻胶进行曝光、显影的过程中，可以避免在该间隙内残留光刻胶，进而在对导电材料薄膜进行图案化的过程中，可以避免形成导电材料残留，最终避免信号传输线400出现短路的情况，以提高显示装置1000的良率。
在一些实施例中，请参阅图7～图13，第一挡墙4包括依次层叠的多层第 一阻挡层41，第二挡墙5包括依次层叠的多层第二阻挡层51。
需要说明的是，第一挡墙4所包括的多层第一阻挡层41和第二挡墙5所包括的多层第二阻挡层51的设置方法包括多种，可以根据实际需要选择设置。
在一些示例中，第二阻挡层51的总层数大于第一阻挡层41的总层数。
上述一些示例通过设置多层第一阻挡层41构成第一挡墙4，设置多层第二阻挡层51构成第二挡墙5，可以有效增加第一挡墙4和第二挡墙5的高度，进而有利于确保对封装层3中的有机层32的阻挡、流平效果，确保封装层3的良好封装效果。
在一些示例中，请继续参阅图7～图13，连接部15包括至少一层连接层10，连接层10的总层数小于第一阻挡层41的总层数。
示例性的，多层第一阻挡层41中靠近衬底的至少一层第一阻挡层41和多层第二阻挡层51中靠近衬底的至少一层第二阻挡层51，通过至少一层连接层10连接。例如，一层连接层10连接一层第一阻挡层41和一层第二阻挡层51。
示例性的，连接层10和与其连接的第一阻挡层41、第二阻挡层51三者同层设置。第一挡墙4、第二挡墙5和连接层10例如可以呈一体结构。
在一些示例中，请参阅图7～图14，第一挡墙4靠近显示区A一侧的侧壁，在远离衬底1的方向Z上逐渐远离显示区A。
示例性的，第一挡墙4靠近显示区A一侧的侧壁，可以呈例如图7～图14所示的斜坡状，或者可以呈阶梯状。
在一些示例中，请继续参阅图7～图14，第一挡墙4远离显示区A一侧的侧壁中未与连接部15连接的部分，在远离衬底1的方向Z上逐渐靠近显示区A。
示例性的，第一挡墙4远离显示区A一侧的侧壁中未与连接部15连接的部分，可以呈例如图7～图8和图11～图14所示的斜坡状，或者可以呈例如图9～图10所示的阶梯状。
在一些示例中，请继续参阅图7～图14，第二挡墙5靠近显示区A一侧的侧壁中未与连接部15连接的部分，在远离衬底1的方向Z上逐渐远离显示区A。
示例性的，第二挡墙5靠近显示区A一侧的侧壁中未与连接部15连接的部分，可以呈例如图8～图10所示的斜坡状，或者可以呈例如图7和图11～图14所示的阶梯状。
在一些示例中，请继续参阅图7～图14，第二挡墙5远离显示区A一侧的 侧壁，在远离衬底1的方向上逐渐靠近显示区A。
示例性的，第二挡墙5远离显示区A一侧的侧壁，可以呈例如图7～图14所示的斜坡状，或者可以呈阶梯状。
在一些示例中，请参阅图14，第一挡墙4远离显示区A一侧的侧壁中未与连接部15连接的部分的坡度(也即，该部分的高程差h 1与该部分的水平距离L 1的比值)，小于第二挡墙5靠近显示区A一侧的侧壁中未与连接部15连接的部分的坡度(也即，该部分的高程差h 2与该部分的水平距离L 2的比值)。
上述一些示例通过相对增大第二挡墙5靠近显示区A一侧的侧壁中未与连接部15连接的部分的坡度，能够进一步地确保第二挡墙5对封装层3中的有机层32的阻挡、流平效果，从而进一步地确保封装层3的良好封装效果。
在一些示例中，请参阅图14，第一挡墙4靠近显示区A一侧的侧壁的坡度(也即，该侧壁的高程差h 3与该侧壁的水平距离L 3的比值)，小于第二挡墙5远离显示区A一侧的侧壁的坡度(也即，该侧壁的高程差h 4与该侧壁的水平距离L 4的比值)。
上述一些示例通过相对增大第二挡墙5远离显示区A一侧的侧壁的坡度，能够减小显示基板100的尺寸，从而节省材料，降低制作成本。
容易理解的是，坡度的计算方式并非仅仅适用于第一挡墙4远离显示区A一侧的侧壁中未与连接部15连接的部分、第二挡墙5靠近显示区A一侧的侧壁中未与连接部15连接的部分、第一挡墙4靠近显示区A一侧的侧壁、第二挡墙5远离显示区A一侧的侧壁四者中的至少一者呈斜坡状的情况，当第一挡墙4远离显示区A一侧的侧壁中未与连接部15连接的部分、第二挡墙5靠近显示区A一侧的侧壁中未与连接部15连接的部分、第一挡墙4靠近显示区A一侧的侧壁、第二挡墙5远离显示区A一侧的侧壁四者中的至少一者呈阶梯状时，该坡度的计算方式也同样适用。
需要说明的是，在增大第一挡墙4以及第二挡墙5的高度后，第一挡墙4和第二挡墙5之间形成的间隙在远离衬底1的方向Z上的深度也会增大。通过至少一层连接层10连通对应的至少一层第一阻挡层41和至少一层第二阻挡层51，同样可以减小第一挡墙4和该间隙之间的段差，以及第二挡墙5和该间隙之间的段差。
由此，本公开一些实施例提供的显示基板100，在将上述多个第二子像素P2中的至少一个像素驱动电路21设置在周边区B后，可以在周边区B设置由多层第一阻挡层41构成的第一挡墙4以及由多层第二阻挡层51构成的第二挡墙5，以实现对封装层3的一部分的阻挡效果，确保封装层3的封装效果。
需要说明的是，对于将光学器件500设置在显示基板100的下方，将光学器件500上方的发光器件22和像素驱动电路21分离，通过至少一层导线实现两者的电连接，并且在发光器件和导线之间、相邻两层导线之间以及导线和像素驱动电路之间设置绝缘层的情况，会导致显示基板100位于显示区A的部分厚度增大，而本公开一些实施例中的由多层第一阻挡层41构成的第一挡墙4以及由多层第二阻挡层51构成的第二挡墙5，依然能够实现对封装层3的一部分的阻挡效果，从而确保封装层3的封装效果。
而且，通过设置至少一层连接层10连通对应的至少一层第一阻挡层41和至少一层第二阻挡层51，此时第一挡墙4和第二挡墙5之间的间隙在衬底1上的正投影，与至少一层连接层10在衬底1上的正投影相重叠，可以有效减小第一挡墙4和该间隙之间的段差，以及减小第二挡墙5和该间隙之间的段差。这样在将显示基板100应用至显示装置中1000的情况下，可以有效避免信号传输线400的导电材料残留，进而避免信号传输线400出现短路的情况，提高显示装置1000的良率。
在一些实施例中，请参阅图5和图6，显示基板100还包括多层平坦层7。多层平坦层7设置于位于周边区B的像素驱动电路21与发光器件22之间，且依次层叠。
其中，多层第一阻挡层41中除最远离衬底1的一层或两层第一阻挡层41以外的第一阻挡层41，与多层平坦层7中的部分平坦层7分别同层设置；和/或，多层第二阻挡层51中除最远离衬底1的一层或两层第二阻挡层51以外的第二阻挡层51，与多层平坦层7中的全部平坦层7分别同层设置。
需要说明的是，多层平坦层7中的部分平坦层7可以是多层平坦层7中的某几层平坦层7。
在一些示例中，请继续参阅图5和图6，显示基板100还包括设置于多层平坦层7整体远离衬底1一侧的像素界定层8；以及，设置于像素界定层8远离衬底1一侧的表面上的多个支撑垫16。
其中，多层第一阻挡层41中最远离衬底1的一层第一阻挡层41与像素界定层8或多个支撑垫16同层设置；和/或，多层第二阻挡层51中最远离衬底1的一层第二阻挡层51与像素界定层8或多个支撑垫16同层设置。
示例性的，像素界定层8具有多个开口，每个开口内设置有一个发光器件22的至少一部分。这样设置像素界定层8，可以对各第一子像素P1和第二子像素P2的发光区域进行界定。
示例性的，当多层第一阻挡层41中最远离衬底1的一层第一阻挡层41 与多个支撑垫16同层设置时，多层第一阻挡层41中第二远离衬底1的一层第一阻挡层41与像素界定层8同层设置。
当多层第二阻挡层51中最远离衬底1的一层第二阻挡层51与多个支撑垫16同层设置时，多层第二阻挡层51中第二远离衬底1的一层第二阻挡层51与像素界定层8同层设置。
在一些示例中，请继续参阅图5和图6，显示基板100还包括至少一层导线层6，每层导线层6包括至少一条透光导线61，位于周边区B的一个像素驱动电路21通过一条透光导线61与相应的一个发光器件22电连接。也即，透光导线61的一端可以伸入周边区B并与像素驱动电路21电连接(例如通过连接结构11与像素驱动电路21电连接)；透光导线61的另一端可以伸入辅助显示区A2，与相应的发光器件22电连接。位于周边区B的像素驱动电路21通过透光导线61向相应的发光器件22提供驱动电压，控制相应的发光器件22的发光状态。
示例性的，透光导线61的数量可以与位于周边区B的像素驱动电路21的数量相等。
示例性的，导线层6的层数可以为两层或三层。例如，导线层6的层数为三层。这样设计，能够为透光导线61的走线排布提供充足的空间，从而防止每条透光导线61之间形成干扰。
需要说明的是，由于像素驱动电路21与相应的发光器件22通过透光导线61电连接，因此，像素驱动电路21和导线层6之间需要设置绝缘层，导线层6和发光器件22之间需要设置绝缘层。
示例性的，上述至少一层导线层6整体与像素驱动电路21之间设置有至少一层平坦层7(也即上述绝缘层)；上述至少一层导线层6整体与发光器件22之间设置有至少一层平坦层7(也即上述绝缘层)。这样设计，可以确保导线层6的平整性及连续性。
需要说明的是，当显示基板100包括多层导线层6时，相邻两层导线层6之间需要设置绝缘层。
示例性的，相邻两层导线层6之间设置有至少一层平坦层7(也即上述绝缘层)。
需要说明的是，上述平坦层7的数量，与导线层6的总层数相关。
在一些示例中，请参阅图5，导线层6的总层数为一层，也即，透光导线61为同层设置。在此基础上，每条透光导线61例如可以通过连接结构11与位于周边区B的像素驱动电路21连接；以及每条透光导线61还与位于辅助 显示区A2的对应发光器件22电连接。此时，上述导线层6和连接结构11之间例如可以仅设置一层平坦层7；上述连接结构11和像素驱动电路21之间例如可以仅设置一层平坦层7；上述导线层6和发光器件22之间例如可以仅设置一层平坦层7。因此，显示基板100可以包括依次层叠的三层平坦层7。
在另一些示例中，请参阅图6，导线层6的总层数为多层，也即，多条透光导线61位于多层，每层导线层6包括至少一条透光导线61，相邻两层导线层6之间设置有至少一层平坦层7。
示例性的，导线层6的总层数为三层。在此基础上，每条透光导线61例如可以通过连接结构11与位于周边区B的对应像素驱动电路21连接；以及每条透光导线61还与位于辅助显示区A2的对应发光器件22电连接。此时，上述三层导线层6中，每相邻的两层导线层6之间例如可以仅设置有一层平坦层7；最靠近像素驱动电路21的一层导线层6和连接结构11之间例如可以仅设置一层平坦层7；连接结构11和像素驱动电路21之间例如可以仅设置一层平坦层7；最靠近发光器件22的一层导线层6和发光器件22之间例如可以仅设置有一层平坦层7。因此，显示基板100可以包括依次层叠的五层平坦层7。
示例性的，在导线层6的总层数为三层时，其中一层导线层6可以均与能够发红色光的发光器件22电连接，另外一层导线层6可以均与能够发绿色光的发光器件22电连接，最后一层导线层6可以均与能够发蓝色光的发光器件22电连接。
容易理解的是，本公开各实施例中提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以在一次构图工艺中，同时制备形成上述多条透光导线61，有利于简化显示基板100的制备工艺。
示例性的，上述透光导线61可以采用具有较高光线透过率的导电材料形成。导电材料例如可以包括氧化铟锡(Indium Tin Oxide，简称ITO)、氧化铟锌(Indium Zinc Oxide，简称IZO)或氧化铟镓锌(Indium Gallium Zinc Oxide，简称IGZO)等。
上述一些示例中，通过采用透光导线61连接相应的像素驱动电路21和发光器件22，有利于进一步提高显示基板100位于辅助显示区A2的部分的 光线透过率，提高光学器件500的工作性能。
在一些示例中，至少一层导线层6整体与像素驱动电路21之间的平坦层7为第一平坦层71；多层第二阻挡层51中，与第一平坦层71同层设置的第二阻挡层51通过一层连接层10连接对应的第一阻挡层41。
示例性的，至少一层导线层6整体直接与像素驱动电路21电连接，至少一层导线层6整体与像素驱动电路21之间例如仅设置一层平坦层7，则上述第一平坦层71的层数为一层。
示例性的，请参阅图5和图6，至少一层导线层6整体通过连接结构11与像素驱动电路21电连接，至少一层导线层6整体与连接结构11之间例如仅设置一层平坦层7，连接结构11与像素驱动电路21之间例如仅设置一层平坦层7，则上述第一平坦层71的层数为两层。
在一些示例中，请参阅图6，相邻两层导线层6之间的平坦层7为第二平坦层72；多层第二阻挡层51中，与至少一层第二平坦层72同层设置的至少一层第二阻挡层51通过至少一层连接层10连接对应的至少一层第一阻挡层41。
在一些示例中，请继续参阅图6，至少一层导线层6整体与发光器件22之间的平坦层7为第三平坦层73；多层第二阻挡层51中，还包括与至少一层第三平坦层73同层设置的至少一层第二阻挡层51。示例性的，第三平坦层73的层数可以是一层。
示例性的，请继续参阅图6，导线层6的总层数为三层，导线层6整体通过连接结构11与像素驱动电路21电连接。导线层6整体与连接结构11之间设置一层平坦层7，连接结构11与像素驱动电路21之间设置一层平坦层7，每相邻两层导线层6之间设置一层平坦层7，导线层6整体与发光器件22之间设置一层平坦层7。也即，第一平坦层71的层数为两层，第二平坦层72的层数为两层，第三平坦层73的层数为一层。除此之外，像素界定层8的层数为一层，多个支撑垫16的层数为一层。因此，第一挡墙4包括依次层叠的五层第一阻挡层41，五层第一阻挡层41例如可以沿远离衬底1的方向Z依次与两层第一平坦层71、两层第二平坦层72和像素界定层8(或支撑垫16)同层设置；第二挡墙5包括依次层叠的六层第二阻挡层51，六层第二阻挡层51例如可以沿远离衬底1的方向Z依次与两层第一平坦层71、两层第二平坦层72、一层第三平坦层73和像素界定层8(或支撑垫16)同层设置。
在此基础上，显示基板100可以包括例如图7所示的四层连接层10，四层连接层10例如可以沿远离衬底1的方向Z分别与两层第一平坦层71、两层 第二平坦层72同层设置。此时，沿垂直于衬底1且远离衬底1的方向Z，第一层连接层10连接第一层第一阻挡层41和第一层第二阻挡层51，呈一体结构；第二层连接层10连接第二层第一阻挡层41和第二层第二阻挡层51，呈一体结构；第三层连接层10连接第三层第一阻挡层41和第三层第二阻挡层51，呈一体结构；第四层连接层10连接第四层第一阻挡层41和第四层第二阻挡层51，呈一体结构；第五层第二阻挡层51、第六层第二阻挡层51均与第五层第一阻挡层41断开。
第一挡墙4中的第五层第一阻挡层41和第二挡墙5中的第五层第二阻挡层51、第六层第二阻挡层51形成了第一挡墙4和第二挡墙5之间的间隙。第一层连接层10在衬底1上的正投影、第二层连接层10在衬底1上的正投影、第三层连接层10在衬底1上的正投影、第四层连接层10在衬底1上的正投影以及上述间隙在衬底1上的正投影，相重叠。此时，第一挡墙4和该间隙之间的段差为第五层第一阻挡层41的厚度，第二挡墙5和该间隙之间的段差为第五层第二阻挡层51、第六层第二阻挡层51的厚度之和。
或者，显示基板100也可以包括例如图8所示的三层连接层10，三层连接层10例如可以沿远离衬底1的方向Z分别与两层第一平坦层71、第一层第二平坦层72同层设置。此时，沿垂直于衬底1且远离衬底1的方向Z，第一层连接层10连接第一层第一阻挡层41和第一层第二阻挡层51，呈一体结构；第二层连接层10连接第二层第一阻挡层41和第二层第二阻挡层51，呈一体结构；第三层连接层10连接第三层第一阻挡层41和第三层第二阻挡层51，呈一体结构；第四层第二阻挡层51、第五层第二阻挡层51、第六层第二阻挡层51整体与第四层第一阻挡层41、第五层第一阻挡层41整体断开。
第一挡墙4中的第四层第一阻挡层41、第五层第一阻挡层41和第二挡墙5中的第四层第二阻挡层51、第五层第二阻挡层51、第六层第二阻挡层51形成了第一挡墙4和第二挡墙5之间的间隙。第一层连接层10在衬底1上的正投影、第二层连接层10在衬底1上的正投影、第三层连接层10在衬底1上的正投影以及上述间隙在衬底1上的正投影，相重叠。此时，第一挡墙4和该间隙之间的段差为第四层第一阻挡层41、第五层第一阻挡层41的厚度之和，第二挡墙5和该间隙之间的段差为第四层第二阻挡层51、第五层第二阻挡层51、第六层第二阻挡层51的厚度之和。
又或者，显示基板100也可以包括例如图9所示的两层连接层10，两层连接层10例如可以沿远离衬底1的方向Z分别与两层第一平坦层71同层设置。此时，沿垂直于衬底1且远离衬底1的方向Z，第一层连接层10连接第 一层第一阻挡层41和第一层第二阻挡层51，呈一体结构；第二层连接层10连接第二层第一阻挡层41和第二层第二阻挡层51，呈一体结构；第三层第二阻挡层51、第四层第二阻挡层51、第五层第二阻挡层51、第六层第二阻挡层51整体与第三层第一阻挡层41、第四层第一阻挡层41、第五层第一阻挡层41整体断开。
第一挡墙4中的第三层第一阻挡层41、第四层第一阻挡层41、第五层第一阻挡层41和第二挡墙5中的第三层第二阻挡层51、第四层第二阻挡层51、第五层第二阻挡层51、第六层第二阻挡层51形成了第一挡墙4和第二挡墙5之间的间隙。第一层连接层10在衬底1上的正投影、第二层连接层10在衬底1上的正投影以及上述间隙在衬底1上的正投影，相重叠。此时，第一挡墙4和该间隙之间的段差为第三层第一阻挡层41、第四层第一阻挡层41、第五层第一阻挡层41的厚度之和，第二挡墙5和该间隙之间的段差为第三层第二阻挡层51、第四层第二阻挡层51、第五层第二阻挡层51、第六层第二阻挡层51的厚度之和。
需要说明的是，在第一挡墙4包括与像素界定层8同层设置的第五层第一阻挡层41，以及第二挡墙5包括与像素界定层8同层设置的第六层第二阻挡层51的情况下，第一挡墙4例如还可以包括与支撑垫16同层设置的第六层第一阻挡层41，以及第二挡墙5例如还可以包括与支撑垫16同层设置的第七层第二阻挡层51，第六层第一阻挡层41与第七层第二阻挡层51断开。
上述一些示例中，通过控制至少一层连接层10整体的厚度，也即，控制第一挡墙4顶部和第二挡墙5顶部分别到至少一层连接层10整体的顶部之间的垂直距离，能够在有效避免信号传输线400的导电材料残留的同时，尽可能地增大第一挡墙4和第二挡墙5之间所形成的间隙的深度，以进一步地提高第一挡墙4和第二挡墙5对有机层32的阻挡、流平效果，从而进一步确保封装层3的良好封装效果。
在一些实施例中，多层第一阻挡层41按照以下至少一种方式设置：
多层第一阻挡层41中最远离衬底1的一层第一阻挡层41，覆盖多层第一阻挡层41中第二远离衬底1的一层第一阻挡层41朝向第二挡墙5的侧面；或者，多层第一阻挡层41中第二远离衬底1的一层第一阻挡层41，覆盖多层第一阻挡层41中第三远离衬底1的一层第一阻挡层41朝向第二挡墙5的侧面。
需要说明的是，上述按照至少一种方式设置，例如可以是仅按照其中一种方式设置，又例如可以是同时按照两种以上的方式组合设置。
在一些示例中，请参阅图8，仅多层第一阻挡层41中最远离衬底1的一层第一阻挡层41，覆盖多层第一阻挡层41中第二远离衬底1的一层第一阻挡层41朝向第二挡墙5的侧面。
在另一些示例中，请参阅图9和图10，仅多层第一阻挡层41中第二远离衬底1的一层第一阻挡层41，覆盖多层第一阻挡层41中第三远离衬底1的一层第一阻挡层41朝向第二挡墙5的侧面。
在又一些示例中，请参阅图11，多层第一阻挡层41中最远离衬底1的一层第一阻挡层41，覆盖多层第一阻挡层41中第二远离衬底1的一层第一阻挡层41朝向第二挡墙5的侧面；多层第一阻挡层41中第二远离衬底1的一层第一阻挡层41，覆盖多层第一阻挡层41中第三远离衬底1的一层第一阻挡层41朝向第二挡墙5的侧面。
在一些实施例中，多层第二阻挡层51按照以下至少一种方式设置：
多层第二阻挡层51中最远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第二远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面；或者，多层第二阻挡层51中第二远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第三远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面；或者，多层第二阻挡层51中第三远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第四远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面。
需要说明的是，上述按照至少一种方式设置，例如可以是仅按照其中一种方式设置，又例如可以是同时按照两种以上的方式组合设置。
在一些示例中，请参阅图7，仅多层第二阻挡层51中最远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第二远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面。
在另一些示例中，请参阅图8，仅多层第二阻挡层51中第二远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第三远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面。
在又一些示例中，请参阅图9，仅多层第二阻挡层51中第三远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第四远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面。
在又一些示例中，请参阅图10，多层第二阻挡层51中第二远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第三远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面；多层第二阻挡层51中第三远离衬底1的一 层第二阻挡层51，覆盖多层第二阻挡层51中第四远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面。
在又一些示例中，请参阅图11，多层第二阻挡层51中最远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第二远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面；多层第二阻挡层51中第二远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第三远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面；多层第二阻挡层51中第三远离衬底1的一层第二阻挡层51，覆盖多层第二阻挡层51中第四远离衬底1的一层第二阻挡层51朝向第一挡墙4的侧面。
在一些实施例中，请参阅图12，多层第一阻挡层41中，最靠近衬底1的一层第一阻挡层41通过一层连接层10连接最靠近衬底1的一层第二阻挡层51以形成第一连通部12，第二靠近衬底1的一层第一阻挡层41通过一层连接层10连接第二靠近衬底1的一层第二阻挡层51以形成第二连通部13。
显示基板100还包括设置于衬底1一侧的电压信号线14。电压信号线14位于周边区B且围绕显示区A设置。
电压信号线14中远离显示区A的区域位于第一连通部12与第二连通部13之间，且电压信号线14远离显示区A的边缘在衬底1上的正投影，位于第一连通部12靠近显示区A的边缘在衬底1上的正投影与第一连通部12远离显示区A的边缘在衬底1上的正投影之间。
需要说明的是，由于第一连通部12为有机绝缘层，电压信号线14为金属层，上述一些示例通过控制电压信号线14仅覆盖部分第一连通部12，能够避免有机绝缘层产生的水汽受到金属层的阻隔，从而能够顺利散出，在此基础上，随着时间的增长，即使水汽的产生量上升，水汽的积累量也不会显著上升，从而避免了电压信号线14因水汽的积累量过大而被顶起的情况，也即，避免了显示基板100出现剥离的问题。
在一些实施例中，请参阅图13，显示基板还包括阻隔层9。
在一些示例中，阻隔层9的一端延伸至相邻两层第一阻挡层41之间，阻隔层9的另一端延伸至相邻两层平坦层7之间，并且阻隔层9的一端所搭接的第一阻挡层41与阻隔层9的另一端所搭接的平坦层7同层设置。
需要说明的是，由于在制备形成显示基板100的过程中，各薄膜按照先后顺序依次形成。也即，在先形成的薄膜靠近衬底1，在后形成的薄膜远离衬底1。因此，阻隔层9相比其所搭接的第一阻挡层41和平坦层7在后形成。
上述一些示例中，通过设置阻隔层9，不仅可以利用阻隔层9减小第一挡 墙4和多层平坦层7之间的段差，减小段差变化率，还可以利用阻隔层9阻隔第一层第一阻挡层41与第一层平坦层7，避免两者之间相互接触进而形成水氧通道，进而避免水汽进入显示区A内，有利于提升阻隔水汽能力，避免由于水汽进入显示区A而造成封装失效。
在一些示例中，阻隔层9与上述导线层6中的至少一层同层设置。
也即，在导线层6的层数为一层时，阻隔层9可以与该导线层6同层设置。在导线层6的层数为多层时，阻隔层9可以与其中一层导线层6同层设置。这样有利于简化显示基板100的制备方法。
在一些示例中，请继续参阅图13，上述多层第一阻挡层41中最远离衬底1的一层第一阻挡层41在衬底1上的正投影，位于多层第一阻挡层41中第二远离衬底1的一层第一阻挡层41在衬底1上的正投影范围内。此时，最远离衬底1的一层第一阻挡层41在衬底1上的正投影面积小于第二远离衬底1的一层第一阻挡层41在衬底1上的正投影面积，最远离衬底1的一层第一阻挡层41仅对第二远离衬底1的一层第一阻挡层41的一部分进行了覆盖。
在一些示例中，阻隔层9的一端所搭接的第一阻挡层41在衬底1上的正投影，与阻隔层9的另一端远离衬底1一侧的平坦层7在衬底1上的正投影，相切或相交叠。这样设计，可以使得显示基板100所包括的薄膜在周边区B和显示区A的过渡区域的段差较小，确保后续形成的信号传输线400的良率。
在一些实施例中，显示装置1000中的触控网格结构200的结构可以包括多种，可以根据实际需要选择设置。
示例性的，请参阅图2，触控网格结构200可以包括：呈阵列状设置的多个导电搭桥，以及多行第一触控子电极。每行第一触控子电极例如可以包括沿第一方向X间隔设置的多个第一触控子电极，每行第一触控子电极中，每相邻的两个第一触控子电极与一个导电搭桥通过过孔电连接，以使上述多行第一触控子电极和上述多个导电搭桥构成多个第一触控电极。
示例性的，请继续参阅图2，触控网格结构200还可以包括：沿第二方向Y延伸的多个第二触控电极，每个第二触控电极例如可以包括多个串接的第二触控子电极。示例性的，每个第二触控电极为一体结构。
示例性的，请继续参阅图2，每个第一触控电极通过一条信号传输线400与触控驱动芯片500电连接，每个第二触控电极通过一条信号传输线400与触控驱动芯片500电连接。
示例性的，显示装置1000所包括的信号传输线400可以和上述导电搭桥同层设置。这样设计，有利于简化显示装置1000的制备工艺。
需要说明的是，上述显示装置1000例如可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开一些实施例还提供了一种如上述任一实施例所述的显示基板100的制作方法。请参阅图15，该制作方法包括S1～S2。
S1、提供衬底1。
S2、在衬底1的一侧形成位于周边区B、且依次远离显示区A的第一挡墙4、连接部15和第二挡墙5；其中，第二挡墙5的高度大于第一挡墙4的高度；连接部15的高度小于第一挡墙4的高度；第一挡墙4、连接部15和第二挡墙5三者的至少部分为一体结构。
在一些示例中，第一挡墙4包括依次层叠的多层第一阻挡层41，第二挡墙5包括依次层叠的多层第二阻挡层51；第二阻挡层51的总层数大于第一阻挡层41的总层数。
连接部15包括至少一层连接层10，连接层10的总层数小于第一阻挡层41的总层数；多层第一阻挡层41中靠近衬底1的至少一层第一阻挡层41和多层第二阻挡层51中靠近衬底1的至少一层第二阻挡层51，通过至少一层连接层10连接。
其中，一层连接层10连接一层第一阻挡层41和一层第二阻挡层52，连接层10和与其连接的第一阻挡层41、第二阻挡层51三者例如可以通过同一次构图工艺形成。
上述一些实施例中的显示基板100的制作方法，用于制备得到前述任一实施例提供的显示基板100。采用该制作方法制成的显示基板100与上述任一实施例中的显示基板100所能实现的有益效果相同，在此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (33)

  1. 一种显示基板，具有显示区和周边区；所述显示基板包括：
    衬底；
    位于所述衬底的一侧、且位于所述周边区的第一挡墙和第二挡墙；所述第二挡墙相对于所述第一挡墙远离所述显示区；所述第二挡墙的高度大于所述第一挡墙的高度；以及，
    位于所述第一挡墙与所述第二挡墙之间的连接部，所述连接部连接所述第一挡墙与所述第二挡墙，且所述连接部的高度小于所述第一挡墙的高度；
    其中，所述第一挡墙、所述连接部和所述第二挡墙三者的至少部分为一体结构。
  2. 根据权利要求1所述的显示基板，其中，
    所述第一挡墙包括依次层叠的多层第一阻挡层，所述第二挡墙包括依次层叠的多层第二阻挡层；第二阻挡层的总层数大于第一阻挡层的总层数；
    所述连接部包括至少一层连接层；所述连接层的总层数小于所述第一阻挡层的总层数。
  3. 根据权利要求2所述的显示基板，其中，
    所述多层第一阻挡层中靠近所述衬底的至少一层第一阻挡层和所述多层第二阻挡层中靠近所述衬底的至少一层第二阻挡层，通过至少一层连接层连接。
  4. 根据权利要求2或3所述的显示基板，其中，
    一层所述连接层连接一层所述第一阻挡层和一层所述第二阻挡层。
  5. 根据权利要求1～4中任一项所述的显示基板，其中，
    所述第一挡墙靠近所述显示区一侧的侧壁，在远离所述衬底的方向上逐渐远离所述显示区，且呈斜坡状或阶梯状；
    所述第一挡墙远离所述显示区一侧的侧壁中未与所述连接部连接的部分，在远离所述衬底的方向上逐渐靠近所述显示区，且呈斜坡状或阶梯状。
  6. 根据权利要求1～5中任一项所述的显示基板，其中，
    所述第二挡墙靠近所述显示区一侧的侧壁中未与所述连接部连接的部分，在远离所述衬底的方向上逐渐远离所述显示区，且呈斜坡状或阶梯状；
    所述第二挡墙远离所述显示区一侧的侧壁，在远离所述衬底的方向上逐渐靠近所述显示区，且呈斜坡状或阶梯状。
  7. 根据权利要求1～6中任一项所述的显示基板，其中，
    所述第一挡墙远离所述显示区一侧的侧壁中未与所述连接部连接的部分的坡度，小于所述第二挡墙靠近所述显示区一侧的侧壁中未与所述连接部连 接的部分的坡度。
  8. 根据权利要求1～7中任一项所述的显示基板，其中，
    所述第一挡墙靠近所述显示区一侧的侧壁的坡度，小于所述第二挡墙远离所述显示区一侧的侧壁的坡度。
  9. 根据权利要求1～8中任一项所述的显示基板，其中，所述显示区包括主显示区和辅助显示区；
    所述显示基板位于所述辅助显示区的部位的光线透过率大于所述显示基板位于所述主显示区的部位的光线透过率。
  10. 根据权利要求9所述的显示基板，还包括：
    设置于所述衬底一侧的多个第一子像素和多个第二子像素；
    所述多个第一子像素位于所述主显示区；
    第二子像素包括：
    像素驱动电路；以及，
    设置于所述像素驱动电路远离所述衬底一侧的发光器件，所述发光器件位于所述辅助显示区，所述发光器件与所述像素驱动电路耦接；
    其中，所述多个第二子像素中，至少一个所述像素驱动电路位于所述辅助显示区以外。
  11. 根据权利要求10所述的显示基板，还包括：
    设置于所述像素驱动电路与所述发光器件之间，且依次层叠的多层平坦层；
    其中，所述多层第一阻挡层中除最远离所述衬底的一层或两层第一阻挡层以外的第一阻挡层，与所述多层平坦层中的部分平坦层分别同层设置；和/或，
    所述多层第二阻挡层中除最远离所述衬底的一层或两层第二阻挡层以外的第二阻挡层，与所述多层平坦层中的全部平坦层分别同层设置。
  12. 根据权利要求11所述的显示基板，还包括：
    至少一层导线层，导线层包括至少一条透光导线；位于所述周边区的一个所述像素驱动电路通过一条透光导线与相应的一个所述发光器件耦接；
    其中，所述至少一层导线层整体与所述像素驱动电路之间设置有至少一层所述平坦层；所述至少一层导线层整体与所述发光器件之间设置有至少一层所述平坦层。
  13. 根据权利要求12所述的显示基板，其中，
    相邻两层所述导线层之间设置有至少一层所述平坦层。
  14. 根据权利要求12或13所述的显示基板，其中，
    所述至少一层导线层整体与所述像素驱动电路之间的所述平坦层为第一平坦层，所述第一平坦层的层数为一层或两层；
    当所述第一平坦层的层数为一层时，所述多层第一阻挡层中包括与一层所述第一平坦层同层设置的第一个第一阻挡层，所述多层第二阻挡层中包括与一层所述第一平坦层同层设置的第一个第二阻挡层，所述至少一层连接层包括第一个连接层；所述第一个连接层连接所述第一个第一阻挡层与所述第一个第二阻挡层。
  15. 根据权利要求14所述的显示基板，其中，
    当所述第一平坦层的层数为两层时，所述多层第一阻挡层中还包括与另一层所述第一平坦层同层设置的第二个第一阻挡层，所述多层第二阻挡层中还包括与另一层所述第一平坦层同层设置的第二个第二阻挡层，所述至少一层连接层还包括第二个连接层；所述第二个连接层连接所述第二个第一阻挡层与所述第二个第二阻挡层。
  16. 根据权利要求14或15所述的显示基板，其中，
    相邻两层所述导线层之间的所述平坦层为第二平坦层；
    所述导线层的层数为三层，靠近所述衬底的相邻两层所述导线层之间的所述平坦层为第一个第二平坦层，远离所述衬底的相邻两层所述导线层之间的所述平坦层为第二个第二平坦层；
    所述多层第一阻挡层中包括与所述第一个第二平坦层同层设置的第三个第一阻挡层，以及与所述第二个第二平坦层同层设置的第四个第一阻挡层；
    所述多层第二阻挡层中包括与所述第一个第二平坦层同层设置的第三个第二阻挡层，以及与所述第二个第二平坦层同层设置的第四个第二阻挡层。
  17. 根据权利要求16所述的显示基板，其中，
    所述至少一层连接层包括第三个连接层以及第四个连接层；所述第三个连接层连接所述第三个第一阻挡层与所述第三个第二阻挡层，所述第四个连接层连接所述第四个第一阻挡层与所述第四个第二阻挡层。
  18. 根据权利要求16所述的显示基板，其中，
    所述至少一层连接层包括第三个连接层；所述第三个连接层连接所述第三个第一阻挡层与所述第三个第二阻挡层；所述第四个第一阻挡层与所述第四个第二阻挡层之间断开。
  19. 根据权利要求17或18所述的显示基板，还包括：
    设置于所述多层平坦层远离所述衬底一侧的像素界定层；以及，
    设置于所述像素界定层远离所述衬底一侧的表面上的多个支撑垫；
    其中，所述多层第一阻挡层中最远离所述衬底的一层第一阻挡层与所述像素界定层或所述多个支撑垫同层设置；
    所述多层第二阻挡层中最远离所述衬底的一层第二阻挡层与所述像素界定层或所述多个支撑垫同层设置。
  20. 根据权利要求19所述的显示基板，其中，
    当所述多层第一阻挡层中最远离所述衬底的一层第一阻挡层与所述多个支撑垫同层设置时，所述多层第一阻挡层中第二远离所述衬底的一层第一阻挡层与所述像素界定层同层设置；
    当所述多层第二阻挡层中最远离所述衬底的一层第二阻挡层与所述多个支撑垫同层设置时，所述多层第二阻挡层中第二远离所述衬底的一层第二阻挡层与所述像素界定层同层设置。
  21. 根据权利要求19或20所述的显示基板，其中，
    所述多层第一阻挡层中还包括与所述像素界定层或所述多个支撑垫同层设置的第五个第一阻挡层；
    所述至少一层导线层整体与所述发光器件之间的所述平坦层为第三平坦层，所述第三平坦层的层数为一层；
    所述多层第二阻挡层中还包括与所述第三平坦层同层设置的第五个第二阻挡层以及与所述像素界定层或所述多个支撑垫同层设置的第六个第二阻挡层；
    其中，所述第五个第二阻挡层、所述第六个第二阻挡层均与所述第五个第一阻挡层断开。
  22. 根据权利要求11～21中任一项所述的显示基板，还包括：
    阻隔层，所述阻隔层的一端延伸至相邻两层所述第一阻挡层之间，所述阻隔层的另一端延伸至相邻两层所述平坦层之间；
    所述阻隔层的一端所搭接的所述第一阻挡层与所述阻隔层的另一端所搭接的所述平坦层同层设置。
  23. 根据权利要求22所述的显示基板，其中，
    所述阻隔层的一端所搭接的所述第一阻挡层在所述衬底上的正投影与位于所述阻隔层的另一端远离所述衬底一侧的所述平坦层在所述衬底上的正投影，相切或相交叠。
  24. 根据权利要求22或23所述的显示基板，其中，
    当所述显示基板包括多层导线层时，所述阻隔层与所述多层导线层中的 至少一层同层设置。
  25. 根据权利要求10～24中任一项所述的显示基板，还包括：
    设置于所述多个第一子像素和所述多个第二子像素远离所述衬底一侧的封装层；所述封装层被配置为将所述多个第一子像素和所述多个第二子像素封装在所述衬底上；
    所述封装层包括：
    第一无机层；
    设置于所述第一无机层远离所述衬底一侧的有机层；以及，
    设置于所述有机层远离所述衬底一侧的第二无机层；
    其中，所述第一挡墙和所述第二挡墙用于对所述有机层进行阻挡；
    所述第一无机层覆盖所述第一挡墙和所述第二挡墙，所述第二无机层覆盖所述第一挡墙和所述第二挡墙。
  26. 根据权利要求2～25中任一项所述的显示基板，其中，
    所述多层第一阻挡层中，最靠近所述衬底的一层第一阻挡层通过一层所述连接层连接最靠近所述衬底的一层第二阻挡层以形成第一连通部，第二靠近所述衬底的一层第一阻挡层通过一层所述连接层连接第二靠近所述衬底的一层第二阻挡层以形成第二连通部；
    所述显示基板还包括：
    设置于所述衬底一侧的电压信号线，所述电压信号线位于所述周边区且围绕所述显示区设置；
    所述电压信号线中远离所述显示区的区域位于所述第一连通部与所述第二连通部之间，且所述电压信号线远离所述显示区的边缘在所述衬底上的正投影，位于所述第一连通部靠近所述显示区的边缘在所述衬底上的正投影与所述第一连通部远离所述显示区的边缘在所述衬底上的正投影之间。
  27. 根据权利要求2～26中任一项所述的显示基板，其中，所述多层第一阻挡层按照以下至少一种方式设置：
    所述多层第一阻挡层中最远离所述衬底的一层第一阻挡层，覆盖所述多层第一阻挡层中第二远离所述衬底的一层第一阻挡层朝向所述第二挡墙的侧面；或者，
    所述多层第一阻挡层中第二远离所述衬底的一层第一阻挡层，覆盖所述多层第一阻挡层中第三远离所述衬底的一层第一阻挡层朝向所述第二挡墙的侧面。
  28. 根据权利要求2～27中任一项所述的显示基板，其中，所述多层第二 阻挡层按照以下至少一种方式设置：
    所述多层第二阻挡层中最远离所述衬底的一层第二阻挡层，覆盖所述多层第二阻挡层中第二远离所述衬底的一层第二阻挡层朝向所述第一挡墙的侧面；或者，
    所述多层第二阻挡层中第二远离所述衬底的一层第二阻挡层，覆盖所述多层第二阻挡层中第三远离所述衬底的一层第二阻挡层朝向所述第一挡墙的侧面；或者，
    所述多层第二阻挡层中第三远离所述衬底的一层第二阻挡层，覆盖所述多层第二阻挡层中第四远离所述衬底的一层第二阻挡层朝向所述第一挡墙的侧面。
  29. 根据权利要求2～28中任一项所述的显示基板，其中，
    所述连接层和与其连接的所述第一阻挡层、所述第二阻挡层三者同层设置。
  30. 一种显示基板的制作方法，所述显示基板具有显示区和周边区；所述制作方法包括：
    提供衬底；
    在所述衬底的一侧形成位于所述周边区、且依次远离所述显示区的第一挡墙、连接部和第二挡墙；
    其中，所述第二挡墙的高度大于所述第一挡墙的高度；所述连接部的高度小于所述第一挡墙的高度；所述第一挡墙、所述连接部和所述第二挡墙三者的至少部分为一体结构。
  31. 根据权利要求30所述的制作方法，其中，
    所述第一挡墙包括依次层叠的多层第一阻挡层，所述第二挡墙包括依次层叠的多层第二阻挡层；第二阻挡层的总层数大于第一阻挡层的总层数；
    所述连接部包括至少一层连接层；所述连接层的总层数小于所述第一阻挡层的总层数；
    所述多层第一阻挡层中靠近所述衬底的至少一层第一阻挡层和所述多层第二阻挡层中靠近所述衬底的至少一层第二阻挡层，通过至少一层连接层连接；
    其中，一层所述连接层连接一层所述第一阻挡层和一层所述第二阻挡层，所述连接层和与其连接的所述第一阻挡层、所述第二阻挡层三者通过同一次构图工艺形成。
  32. 一种显示装置，包括：如权利要求1～29中任一项所述的显示基板。
  33. 根据权利要求32所述的显示装置，其中，所述显示基板的周边区包括绑定区，所述绑定区位于所述第二挡墙远离所述显示区的一侧；所述显示装置还包括：
    位于所述显示基板的绑定区的触控驱动芯片；
    位于所述显示基板的显示区的触控网格结构；以及，
    连接所述触控驱动芯片和所述触控网格结构的多条信号传输线，所述多条信号传输线位于所述第一挡墙和所述第二挡墙整体远离所述衬底的一侧，所述多条信号传输线在所述衬底上的正投影与所述连接层在所述衬底上的正投影部分重叠。
PCT/CN2021/109730 2021-01-28 2021-07-30 显示面板及其制作方法、显示装置 WO2022160635A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202180002053.5A CN115152029A (zh) 2021-01-28 2021-07-30 显示面板及其制作方法、显示装置
GB2216331.5A GB2610497A (en) 2021-01-28 2021-07-30 Display panel and manufacturing method therefor, and display apparatus
US17/789,543 US11930665B2 (en) 2021-01-28 2021-07-30 Display substrate and manufacturing method thereof, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110121161.6 2021-01-28
CN202110121161.6A CN114824120A (zh) 2021-01-28 2021-01-28 一种显示基板及显示装置

Publications (1)

Publication Number Publication Date
WO2022160635A1 true WO2022160635A1 (zh) 2022-08-04

Family

ID=82496078

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/109730 WO2022160635A1 (zh) 2021-01-28 2021-07-30 显示面板及其制作方法、显示装置

Country Status (4)

Country Link
US (2) US11930665B2 (zh)
CN (2) CN114824120A (zh)
GB (1) GB2610497A (zh)
WO (1) WO2022160635A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110197844B (zh) * 2019-06-20 2021-01-12 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN211350693U (zh) * 2019-11-26 2020-08-25 昆山国显光电有限公司 显示面板及显示装置
CN111798759A (zh) * 2020-07-17 2020-10-20 京东方科技集团股份有限公司 柔性显示装置及电子设备
CN112018159A (zh) * 2020-08-27 2020-12-01 京东方科技集团股份有限公司 触控显示面板
CN112233559A (zh) * 2020-10-30 2021-01-15 云谷（固安）科技有限公司 显示面板及显示面板制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102277705B1 (ko) * 2017-06-30 2021-07-14 엘지디스플레이 주식회사 표시 장치
KR20200137071A (ko) * 2019-05-28 2020-12-09 삼성디스플레이 주식회사 표시 장치
CN111192911B (zh) 2020-02-19 2022-06-17 成都京东方光电科技有限公司 一种显示面板及显示装置
CN112018161B (zh) 2020-09-08 2022-07-19 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN112349867B (zh) * 2020-10-27 2024-04-23 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN211350693U (zh) * 2019-11-26 2020-08-25 昆山国显光电有限公司 显示面板及显示装置
CN111798759A (zh) * 2020-07-17 2020-10-20 京东方科技集团股份有限公司 柔性显示装置及电子设备
CN112018159A (zh) * 2020-08-27 2020-12-01 京东方科技集团股份有限公司 触控显示面板
CN112233559A (zh) * 2020-10-30 2021-01-15 云谷（固安）科技有限公司 显示面板及显示面板制造方法

Also Published As

Publication number Publication date
GB202216331D0 (en) 2022-12-21
CN114824120A (zh) 2022-07-29
US11930665B2 (en) 2024-03-12
US11903253B2 (en) 2024-02-13
GB2610497A (en) 2023-03-08
CN115152029A (zh) 2022-10-04
US20230345793A1 (en) 2023-10-26
US20220238618A1 (en) 2022-07-28

Similar Documents

Publication Publication Date Title
US11980071B2 (en) Display substrate and display device
WO2022068383A1 (zh) 显示面板及显示装置
WO2016145771A1 (zh) 阵列基板及其制作方法以及显示装置
US12004387B2 (en) Display substrate and manufacturing method thereof, and display device
WO2021147082A1 (zh) 显示基板及其制备方法
WO2023004647A1 (zh) 显示基板、显示装置
EP4050658B1 (en) Display substrate, preparation method therefor, and display device
JP7482900B2 (ja) 表示基板及びその製造方法
WO2022160635A1 (zh) 显示面板及其制作方法、显示装置
US20230012412A1 (en) Display substrate and method of manufacturing the same, and display device
CN113035901B (zh) 透光显示面板及其制备方法、显示面板
WO2023279255A1 (zh) 显示面板及显示装置
US20240155872A1 (en) Display Substrate and Preparation Method Therefor, and Display Device
WO2023092606A1 (zh) 显示基板及其制作方法、显示装置
WO2022170479A1 (zh) 显示基板及其制作方法、显示装置
TW202329083A (zh) 顯示裝置以及顯示面板
CN117044427A (zh) 显示面板、显示母板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21922231

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 202216331

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20210730

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21922231

Country of ref document: EP

Kind code of ref document: A1