WO2023004647A1 - 显示基板、显示装置 - Google Patents

显示基板、显示装置 Download PDF

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Publication number
WO2023004647A1
WO2023004647A1 PCT/CN2021/109063 CN2021109063W WO2023004647A1 WO 2023004647 A1 WO2023004647 A1 WO 2023004647A1 CN 2021109063 W CN2021109063 W CN 2021109063W WO 2023004647 A1 WO2023004647 A1 WO 2023004647A1
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WIPO (PCT)
Prior art keywords
isolation
layer
area
substrate
insulating layer
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PCT/CN2021/109063
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English (en)
French (fr)
Inventor
谢春燕
蔡宝鸣
张嵩
贾立
高涛
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/109063 priority Critical patent/WO2023004647A1/zh
Priority to CN202180002013.0A priority patent/CN116324949A/zh
Priority to CN202110985487.3A priority patent/CN113629120A/zh
Priority to CN202122024622.6U priority patent/CN216648312U/zh
Publication of WO2023004647A1 publication Critical patent/WO2023004647A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of display technology, and specifically relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Organic Light Emitting Diode
  • an embodiment of the present disclosure provides a display substrate, including a display area, an aperture area located in the display area, and a frame area located between the display area and the aperture area, and the frame area is at least It includes a first isolation region, the first isolation region includes at least one signal line group and at least one organic insulating layer stacked, and at least two first isolation grooves are arranged in the at least one organic insulating layer, and the at least two The at least one organic insulating layer is separated by two first isolation grooves, the at least two first isolation grooves are arranged at intervals along the direction away from the opening area, and the at least one signal line group is on the front side of the frame area.
  • the projection is located between the at least two first isolation grooves in the orthographic projection of the frame area.
  • the first isolation region includes at least two signal line groups stacked, and the orthographic projections of the at least two signal line groups on the frame region at least partially overlap.
  • At least one of the first isolation grooves is provided with a first barrier layer.
  • At least one second isolation groove is further provided in the at least one organic insulating layer, the at least one second isolation groove has an undercut structure, and a light-emitting device is stacked on the at least one organic insulating layer. layer, the second isolation groove isolates the light emitting layer.
  • the at least one second isolation groove is located between the at least two first isolation grooves.
  • an encapsulation structure and an isolation dam are stacked on the first isolation region, the encapsulation structure includes at least an organic layer, and the isolation dam is located in the first isolation region close to the opening region. On the side, the isolation dam isolates the organic layer from the open region.
  • the frame area further includes a second isolation area, the second isolation area is located between the first isolation area and the opening area, and the second isolation area includes at least two The spaced isolation columns are arranged at intervals, and a third isolation groove is formed between the adjacent isolation columns, and the third isolation groove has an undercut structure.
  • a fourth isolation groove is further formed between adjacent isolation columns, and a second barrier layer is disposed on the fourth isolation groove.
  • the isolation column is disposed on the same layer as the at least one organic insulating layer.
  • an encapsulation structure and an isolation dam are stacked on the first isolation region, the encapsulation structure includes at least an organic layer, and the isolation dam is located in the first isolation region close to the opening region. On the side, the isolation dam isolates the organic layer from the second isolation region, and a protective layer is disposed on the second isolation region.
  • a surface of the protective layer on a side away from the second isolation region is flush with a surface of the package structure on a side away from the first isolation region.
  • a light-shielding layer is disposed on the protective layer.
  • the light-shielding layer adopts a metal layer or an opaque black inorganic coating.
  • a buffer layer is disposed between the light shielding layer and the protective layer.
  • a gap is provided on a side of the buffer layer close to the opening area, and the light shielding layer fills the gap.
  • an embodiment of the present disclosure further provides a display device, including the aforementioned display substrate.
  • FIG. 1 is a schematic structural view of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view showing a substrate according to an embodiment of the present disclosure
  • FIG. 3 is a first schematic diagram showing the wiring of the signal line group in the first isolation area in the substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram showing the second winding of the signal line group in the first isolation area in the substrate according to an embodiment of the present disclosure
  • FIG. 5 is a cross-sectional view of a display module according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram showing an active layer formed on a substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram showing the formation of a gate electrode and a first gate line on a substrate according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram showing a capacitor electrode and a second gate line formed on a substrate according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram showing an inorganic insulating layer formed on a substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram showing a source electrode, a drain electrode, and a data line formed on a substrate according to an embodiment of the present disclosure
  • FIG. 11 is a first schematic diagram showing a first organic insulating layer formed on a substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram showing a second organic insulating layer formed on a substrate according to an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram showing a second isolation groove, a third isolation groove, and a fourth isolation groove formed on a substrate according to an embodiment of the present disclosure
  • FIG. 14 is a schematic diagram showing an anode formed on a substrate according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram showing a pixel definition layer formed on a substrate according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of an embodiment of the present disclosure showing a light-emitting layer and a cathode formed on a substrate;
  • FIG. 17 is a schematic diagram of an embodiment of the present disclosure showing a package structure formed on a substrate
  • FIG. 18 is a schematic diagram showing a protective layer formed on a substrate according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of an embodiment of the present disclosure showing a light-shielding layer formed on a substrate
  • 20 is an enlarged view showing signal line groups in a substrate according to an embodiment of the present disclosure
  • FIG. 21 is an enlarged view of an embodiment of the present disclosure showing that the substrate is formed with spacers;
  • FIG. 22 is a schematic diagram showing an isolation dam formed on a substrate according to an embodiment of the present disclosure.
  • FIG. 23 is a second schematic diagram showing the first organic insulating layer formed on the substrate according to an embodiment of the present disclosure.
  • FIG. 24 is an enlarged view showing spacers in a substrate according to an embodiment of the present disclosure.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • An embodiment of the present disclosure provides a display substrate, including a display area, an aperture area, and a frame area between the display area and the aperture area, the frame area includes at least a first isolation area, and the first isolation area
  • the region includes a base, at least one inorganic insulating layer disposed on the base, at least one organic insulating layer disposed on the side of the at least one inorganic insulating layer away from the base, and disposed on the at least one organic insulating layer away from the
  • the packaging structure on the side of the substrate, the packaging structure includes at least one organic material layer
  • the display substrate includes at least two first isolation grooves, the at least two first isolation grooves penetrate through the at least one organic insulating layer, and the at least The two first isolation grooves at least include a first edge groove and a second edge groove, the bottom wall of which is in the first isolation groove whose orthographic projection of the substrate overlaps with the orthographic projection of the organic material layer on the substrate,
  • the first isolation groove closest to the side of the display area
  • the first isolation groove closest to the display area is the second edge groove
  • the display substrate further includes at least one signal line group arranged on the base, and the at least one signal line
  • the orthographic projection of the group on the base is located between the orthographic projection of the first edge groove bottom wall on the base and the orthographic projection of the second edge groove bottom wall on the base.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of a display substrate according to an embodiment of the present disclosure. Taking FIG. 2 as an example to illustrate the cross-sectional view along the line A-A in FIG. 1 .
  • the display substrate in the embodiment of the present disclosure may be an OLED display substrate or a QLED display substrate. The description is made by taking an example in which the display substrate of the embodiment of the present disclosure may be an OLED display substrate. As shown in FIG.
  • the main structure of the display substrate includes a display area 100 , a frame area 200 and an opening area 300 , and the frame area 200 is located between the display area 100 and the opening area 300 .
  • the frame area 200 surrounds the opening area 300 and can be used to block the water and oxygen pathway from the opening area 300 to the display area 100 .
  • the position of the opening area 300 in the display area 100 is not limited, and the shape is also not limited. It can be a circle as shown in FIG. 1 , or an ellipse or other polygons such as a square and a rhombus.
  • the display region 100 may include at least one gate line and at least one data line.
  • the gate lines can be used to transmit gate electric signals
  • the data lines can be used to transmit data electric signals.
  • At least one gate line extends along a first direction (eg, a horizontal direction), and the at least one gate line may be parallel to each other.
  • At least one data line extends along a second direction (eg, a vertical direction), and the at least one data line may be parallel to each other.
  • the first direction is different from the second direction.
  • the first direction is perpendicular to the second direction.
  • the gate line and the data line define at least one sub-pixel.
  • the display area 100 may include a base, a driving structure layer disposed on the base, and a light emitting structure layer disposed on the driving structure layer, the driving structure layer mainly includes at least one thin film transistor (Thin Film Transistor, TFT), the light emitting structure layer mainly includes at least one anode, at least one light emitting layer and at least one cathode.
  • TFT Thin Film Transistor
  • the anode in the light emitting structure layer is connected to the drain electrode in the thin film transistor, the data line is connected to the source electrode in the thin film transistor, and the gate line is connected to the gate in the thin film transistor.
  • the thin film transistor can be turned on or off by the gate electric signal applied by the gate line connected to it, and can be transmitted to the anode by the data electric signal provided by the data line connected to it.
  • the sub-pixels of the display area 100 may display images according to the data electrical signal applied to the anode.
  • the source and drain of the thin film transistor can be exchanged according to the type of the thin film transistor, which will not be repeated in the embodiments of the present disclosure.
  • the opening area 300 includes at least one through hole or blind hole, the various structural film layers and substrates of the through hole are removed, most of the structural film layers in the blind hole are removed, and the through hole or blind hole can be used It is used to set corresponding hardware, such as camera, sensor and other hardware.
  • the above-mentioned structural film layers may include various film layers in the driving structural layer, various film layers in the light emitting structural layer, and the like.
  • the driving structure layers of the sub-pixels in the display area 100 mainly include a buffer layer disposed on the substrate and a thin film transistor disposed on the buffer layer.
  • the light emitting structure layer mainly includes an anode connected to the drain electrode of the thin film transistor, a pixel defining layer defining a pixel opening area, a light emitting layer, a cathode formed on the light emitting layer and an encapsulation structure.
  • the light emitting layer at least covers the pixel opening area. For example, the light emitting layer covers the entire pixel opening area or the entire sub-pixel.
  • the frame region 200 of the display substrate in the embodiment of the present disclosure includes at least a first isolation region 400 .
  • the first isolation region 400 includes a substrate 10, at least one inorganic insulating layer 18 disposed on the substrate 10, and at least one organic insulating layer disposed on the side of the at least one inorganic insulating layer 18 away from the substrate 10.
  • the encapsulation structure 38 includes at least one organic material layer
  • the signal line group 3 includes at least one signal line
  • at least one organic insulating layer 600 is set
  • the bottom walls of at least two first isolation grooves 1 are located on the surface of the inorganic insulating layer 18 away from the substrate 10; or, the bottom walls of at least two first isolation grooves 1 are located on the inorganic insulating layer 18 , that is, the bottom walls of at least two first isolation trenches 1 are overcut into the inorganic insulating layer 18 .
  • this embodiment shows that the regions of the substrate except the opening area 300 are all provided with a base, and that the bases in the substrate are all provided on the same layer, and are prepared from the same material through the same manufacturing process.
  • the substrate in the display area 100 and the substrate 10 in the frame area 200 are arranged in the same layer, and are prepared from the same material through the same manufacturing process.
  • the organic insulating layer in the display region 100 and the organic insulating layer 600 in the frame region 200 are arranged in the same layer, and are prepared from the same material through the same manufacturing process.
  • the inorganic insulating layer in the display area 100 and the inorganic insulating layer 18 in the frame area 200 are arranged in the same layer, and are prepared from the same material through the same manufacturing process.
  • the first isolation region 400 has two edges in the base orthographic projection, and the edge of the two edges on the side close to the display area 100 is the same as the edge of the first edge groove 101 in the base orthographic projection close to the display area 100.
  • the edges overlap; the edge of the two edges near the opening area 300 overlaps with the edge of the second edge groove 102 on the base orthographic projection near the opening area 300 .
  • the first isolation trench 1 includes at least one side wall and a bottom wall.
  • the first edge groove 101 includes two side walls and a bottom wall; the second edge groove 102 includes two side walls and a bottom wall.
  • the embodiment of the present disclosure shows that the orthographic projection of the signal line group 3 in the substrate on the substrate 10 is located between the orthographic projection of the bottom wall of the first edge groove 101 on the substrate 10 and the orthographic projection of the bottom wall of the second edge groove 102 on the substrate 10, avoiding the first isolation
  • the slot 1 affects the routing of the signal line group 3 , so that the signal line group 3 is routed in the first isolation area 400 , reducing the area of the frame area 200 and realizing a narrow frame design.
  • the embodiment of the present disclosure shows that the first isolation trench 1 in the substrate may be a ring structure surrounding the opening region 300 .
  • the first isolation groove 1 can be used to isolate the organic insulating layer 600 in the frame area 200 , blocking the path of water and oxygen intruding from the opening area 300 to the display area through the organic insulating layer 600 .
  • the organic insulating layer 600 may use an organic material, for example, resin, polysiloxane-based material, acrylic-based material, or polyimide-based material.
  • the first isolation region 400 may include at least one organic insulating layer 600, for example, the first isolation region 400 includes one, two, three or other stacked layers.
  • the number of organic insulating layers 600 At least one organic insulating layer 600 in the first isolation region 400 can be provided in the same layer as at least one of the organic insulating layers in the display region, and can be formed by using the same material and using the same process.
  • the first isolation trench 1 may penetrate all the organic insulating layers 600 in the first isolation region 400, completely isolating the organic insulating layers 600 in the first isolation region 400; Alternatively, the first isolation trench 1 may penetrate a part of the organic insulating layer 600 in the first isolation region 400 to isolate part of the organic insulating layer 600 in the first isolation region 400 .
  • the first isolation region 400 includes a first organic insulating layer 21 and a second organic insulating layer 24 stacked, and the first organic insulating layer 21 is located between the second organic insulating layer 24 and the substrate.
  • the first isolation groove 1 runs through the first organic insulating layer 21 and the second organic insulating layer 24, that is, the depth of the first isolation groove 1 is not less than the sum of the thicknesses of the first organic insulating layer 21 and the second organic insulating layer 24, as shown in Figure 2 shown.
  • the first isolation region 400 may include at least one signal line group 3 , for example, the first isolation region 400 includes two, three or other number of signal line groups 3 stacked.
  • FIG. 3 is a first schematic diagram showing the wiring of the signal line group in the first isolation area in the substrate according to an embodiment of the present disclosure.
  • Fig. 3 illustrates the winding of the signal line group 3 in the embodiment of the present disclosure by taking the first isolation region 400 including three signal line groups 3 stacked as an example.
  • the embodiment of the present disclosure shows that the substrate is a rectangular structure, including opposite short sides and opposite long sides.
  • the center of the opening region 300 in the display substrate is located on the center line of the short side of the display substrate.
  • the embodiment of the present disclosure shows that the first isolation region 400 of the substrate includes three stacked signal line groups 3, and the three signal line groups 3 are the first signal line group 301, the second signal line group 302 and the third signal line group 302 and the third signal line group respectively.
  • Line set 303 The third signal line group 303 is located on the side of the signal line group 3 away from the substrate 10 , and the organic insulating layer 600 is disposed on the side of the third signal line group 303 away from the substrate 10 and covers the third signal line group 303 .
  • the three signal line groups 3 bypass the opening area 300 in the first isolation area 400 in the form of winding.
  • the embodiment of the present disclosure has no limitation on the first signal line group 301 , the second signal line group 302 and the third signal line group 303 .
  • the first signal line group 301 may be the first gate line
  • the second signal line group 302 may be the second gate line
  • the third signal line group 303 may be the first data line.
  • FIG. 20 is an enlarged view showing signal line groups in a substrate according to an embodiment of the present disclosure.
  • at least one signal line group 3 is provided with a barrier layer 42 on the side away from the substrate 10, and the barrier layer 42 covers at least one signal line group 3 to prevent at least one signal line group 3 from being corrosion.
  • the barrier layer 42 may use inorganic materials.
  • the barrier layer 42 may be a continuous film layer, and the barrier layer 42 covers the entire layer of the signal line group 3 , as shown in FIG. 20 .
  • the blocking layer may include at least one patterned film layer, and at least one patterned film layer covers at least one signal line in the signal line group 3 .
  • the embodiment of the present disclosure shows that the distance from the edge of the frame region 200 away from the hole region 300 to the edge of the frame region 200 close to the hole region 300 in the substrate may be less than 0.4 mm.
  • the distance from the edge of the frame area 200 away from the opening area 300 to the edge of the frame area 200 close to the opening area 300 is 0.2-0.3 mm.
  • FIG. 4 is a second schematic diagram showing the wiring of the signal line group in the first isolation area in the substrate according to an embodiment of the present disclosure.
  • FIG. 4 illustrates the wiring of the signal line groups 3 in the embodiment of the present disclosure by taking the frame area 200 including three signal line groups 3 stacked as an example.
  • the embodiment of the present disclosure shows that the substrate is a rectangular structure, including opposite short sides and opposite long sides.
  • the embodiment of the present disclosure shows that the center of the opening region 300 in the display substrate is not located on the center line of the short side of the display substrate.
  • the first isolation region 400 of the substrate includes three stacked signal line groups 3, and the three signal line groups 3 are the first signal line group 301, the second signal line group 302 and the third signal line group 302 and the third signal line group respectively.
  • Line set 303 the sub-pixels in the display area 100 are driven on both sides, which can eliminate the display unevenness caused by the driving of the pixels around the opening area 300 .
  • the embodiment of the present disclosure shows that the space occupied by the winding of the signal line group 3 in the substrate is smaller than that of the first isolation region 400 , and the winding of the signal line group 3 will not increase the space of the frame region 200 .
  • the embodiment of the present disclosure shows that after the substrate increases the pixel density, the number of signal line groups 3 will increase. In the orthographic projection of the signal line group 3 , the space occupied by the winding of the signal line group 3 is smaller than that of the first isolation area 400 , and no additional space of the frame area 200 will be occupied.
  • Orthographic projections of the two signal line groups 3 on the substrate 10 are at least partially overlapped, thereby reducing the space occupied by the signal line groups 3 for winding in the frame area 200 .
  • the orthographic projection of the signal line group 3 on the substrate 10 refers to the projection between the signal lines located at two opposite edges of the signal line group 3 in the signal line group 3 .
  • the areas where at least two signal line groups 3 are located overlap at least partially in the orthographic projection of the substrate 10.
  • the first isolation region 400 includes the first signal line group 301, the second signal line group 301, and the second signal line group that are stacked.
  • the third signal line group 303 the orthographic projection of the area where the first signal line group 301 is located on the substrate 10 and the orthographic projection of the area where the second signal line group 302 is located on the substrate at least partially overlap; or, the first signal line group
  • the orthographic projections of the signal lines in at least two signal line groups 3 on the substrate 10 overlap at least partially.
  • the first isolation region 400 includes a stacked first signal line group 301, a second signal line group 302, and a third signal line group 303.
  • the first signal line group 301 includes at least one first signal line
  • the second signal line group Group 302 includes at least one second signal line
  • third signal line group 303 includes at least one third signal line.
  • the orthographic projection of at least one first signal line in the first signal line group 301 on the substrate 10 at least partially overlaps the orthographic projection of at least one second signal line in the second signal line group 302 on the substrate; or, the first signal line group
  • the orthographic projection of at least one first signal line in 301 on the substrate and the orthographic projection of at least one third signal line in the third signal line group 303 on the substrate 10 at least partially overlap; or, at least one of the first signal lines in the second signal line group 302
  • the orthographic projections of the two signal lines on the substrate 10 at least partially overlap with the orthographic projections of at least one third signal line in the third signal line group 303 on the substrate 10 .
  • FIG. 23 is a second schematic diagram showing a first organic insulating layer formed on a substrate according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure shows that the first isolation region 400 of the substrate includes three stacked signal line groups 3 , and the three signal line groups 3 are sequentially stacked first signal line groups. group 301 , a second signal line group 302 and a third signal line group 303 .
  • the third signal line group 303 is located on the side of the signal line group 3 away from the substrate 10 .
  • An organic insulating layer 600 is disposed on the side of the third signal line group 303 away from the substrate 10 , and the organic insulating layer 600 covers the third signal line group 303 .
  • At least two first isolation trenches 1 and at least one second isolation trench 2 are disposed in the organic insulating layer 600 .
  • the orthographic projection of the third signal line group 303 on the substrate 10 does not overlap with the bottom of the first isolation trench 1 and the bottom of the second isolation trench 2 .
  • the first isolation trench 1 includes at least one side wall and a bottom wall, and the first barrier layer 37 is disposed on at least one side wall and the bottom wall of the first isolation trench 1 .
  • the first barrier layer 37 can be used to block water and oxygen intruding from the opening region 300 from intruding into the display region 100 through the organic insulating layer 600 .
  • the first barrier layer 37 may be referred to as a first passivation layer.
  • the first barrier layer 37 may use a metal oxide material or an inorganic material.
  • the inorganic material may be materials such as silicon nitride or silicon oxide
  • the metal oxide material may be materials such as aluminum oxide, hafnium oxide, and tantalum oxide.
  • the inorganic insulating layer 18 is first formed on the substrate 10, and then the organic insulating layer 600 is formed on the inorganic insulating layer 18, and a penetrating organic insulating layer 600 is formed in the organic insulating layer 600.
  • the first isolation trench 1 of the insulating layer 600, and finally the first barrier layer 37 is formed on the first isolation trench 1, so that the first barrier layer 37 is in contact with the bottom wall and at least one sidewall of the first isolation trench 1, and the inorganic insulating layer 18 is not in contact with at least one sidewall of the first isolation groove 1 .
  • At least one second isolation trench 2 is further disposed in at least one organic insulating layer 600 , and the at least one second isolation trench 2 has a first undercut structure.
  • the first isolation region 400 further includes a light-emitting layer stacked on at least one organic insulating layer 600 , and the second isolation groove 2 can isolate the light-emitting layer.
  • the undercut structure in the second isolation groove 2 has poor coverage, so that the light-emitting layer of the frame area 200 is disconnected at the second isolation groove 2, which can block the light-emitting layer from the opening.
  • the water and oxygen intruding from the hole area 300 enters the path of the display area through the light-emitting layer.
  • the embodiment of the present disclosure shows that the second isolation trench 2 in the substrate includes side edges, and the first barrier layer 37 extends to the side edge of the second isolation trench 2 and protrudes from the side edge of the second isolation trench 2 edge, forming the first undercut structure.
  • the light-emitting layer when it is formed by evaporation, it may be disconnected due to the poor step coverage of the first undercut structure. The disconnected light-emitting layer will cover the bottom wall of the second isolation groove 2, blocking the path of water and oxygen intruding from the opening area 300 to the display area through the light-emitting layer, and improving the reliability of the display panel.
  • the second isolation trench 2 may penetrate a part of the organic insulating layer 600 in the frame region 400 .
  • the first isolation region 400 includes a first organic insulating layer 21 and a second organic insulating layer 24 stacked, and the first organic insulating layer 21 is located between the second organic insulating layer 24 and the substrate 10 .
  • the second isolation groove 2 runs through the second organic insulating layer 24 and extends to the surface of the first organic insulating layer 21 , that is, the depth of the second isolation groove 2 is equal to the thickness of the second organic insulating layer 24 , as shown in FIG. 2 .
  • the orthographic projection of at least one second isolation groove 2 on the substrate 10 is located between the orthographic projection of the first edge groove 101 on the substrate 10 and the orthographic projection of the second edge groove 102 on the substrate 10 .
  • the second isolation groove 2 only penetrates a part of the organic insulating layer in the frame area, so that the second isolation groove 2 will not block the winding of the signal line group 3, and then the orthographic projection of at least one second isolation groove 2 in the frame area 200 is consistent with the signal Orthographic projections of the line groups 3 on the frame area 200 are at least partially overlapped, so as to realize a narrow frame design.
  • the orthographic projection of the at least one second isolation trench 2 on the substrate 10 overlaps with the orthographic projection of the organic material layer 383 in the package structure 38 on the substrate 10 .
  • the encapsulation structure 38 includes a first inorganic material layer 381 , a second inorganic material layer 382 and a layer between the first inorganic material layer 381 and the second inorganic material layer 382 at least one organic material layer 383.
  • the packaging structure 38 can be used to protect the light emitting unit.
  • the embodiment of the present disclosure shows that during the process of forming the encapsulation structure on the light emitting unit by the substrate, in order to prevent the encapsulation structure material in the display area 100 from flowing into the opening area 300 .
  • the embodiment of the present disclosure shows that an isolation dam 6 may be disposed on the first isolation region 400 of the substrate, and the isolation dam 6 is disposed on a side of the organic insulating layer 600 in the first isolation region 400 away from the substrate 10 .
  • the orthographic projection of the isolation dam 6 on the substrate 10 is located between the orthographic projection of the first edge groove 101 on the substrate 10 and the orthographic projection of the second edge groove 102 on the substrate 10 .
  • the isolation dam 6 isolates the organic material layer 383 in the encapsulation structure 38 from the opening area 300 to prevent the organic material layer 383 from flowing into the opening area 300 .
  • the isolation dam 6 may be formed in the same layer as the pixel definition layer in the display region 200 , using the same material and using the same process.
  • the display area 200 further includes a spacer layer, and the isolation dam 6 and the spacer layer in the display area 200 can be arranged in the same layer, formed with the same material and through the same process.
  • the display area 200 further includes a spacer layer, and the isolation dam 6 includes a first isolation layer and a second isolation layer that are laminated. Formed by the same process, the second isolation layer and the spacer layer in the display region 200 are disposed on the same layer, using the same material and formed by the same process.
  • FIG. 22 is a schematic diagram showing an isolation dam formed on a substrate according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure shows that at least two isolation dams 6 may be disposed on the first isolation region 400 of the substrate, and at least two isolation dams 6 are disposed in the first isolation region 400
  • the organic insulating layer 600 is away from the side of the substrate 10 .
  • At least two isolation dams 6 may be arranged at intervals.
  • the orthographic projections of at least two isolation dams 6 on the substrate 10 are located between the orthographic projections of the first edge groove 101 on the substrate 10 and the orthographic projections of the second edge groove 102 on the substrate 10 .
  • At least two isolation dams 6 isolate the organic material layer 383 in the encapsulation structure 38 from the opening area 300 to prevent the organic material layer 383 from flowing into the opening area 300 .
  • the height relationship between the at least two isolation dams 6 is not limited, as long as the at least two isolation dams 6 can prevent the organic material layer 383 from flowing into the opening region 300 .
  • the heights between the at least two isolation dams 6 are equal; or, the height of one of the at least two isolation dams 6 is greater than the height of the other of the at least two isolation dams 6 .
  • the frame region 200 further includes a second isolation region 500 located between the first isolation region 400 and the opening region 300 .
  • the second isolation region 500 includes at least two isolation columns 25, a third isolation groove 5 is formed between adjacent isolation columns 25, the third isolation groove 5 includes side edges, and a second barrier is provided on the side of the isolation columns 25 away from the substrate 10.
  • Layer 40, the second barrier layer 40 protrudes from the side of the third isolation groove 5 to form a second undercut structure.
  • the light-emitting layer when the light-emitting layer is formed by evaporation, it may be disconnected due to poor step coverage of the second undercut structure.
  • the disconnected light-emitting layer will cover the bottom wall of the third isolation groove 5, blocking the path of water and oxygen intruding from the opening area 300 to the display area through the light-emitting layer, and improving the reliability of the display panel.
  • the third isolation groove 5 can absorb the stress generated during the formation of the hole area 300 , and at the same time prevent the cracks generated when the hole area 300 is drilled from extending to the display area 100 , thereby blocking the cracks.
  • the second barrier layer 40 may be referred to as a second passivation layer.
  • the isolation column 25 may be disposed in the same layer as at least one of the organic insulating layers 600 of the first isolation region 400 , and formed using the same material and through the same process.
  • the first isolation region 400 includes a stacked first organic insulating layer 21 and a second organic insulating layer 24, and the isolation columns 25 and the second organic insulating layer 24 are arranged on the same layer, using the same material and formed by the same process, as shown in FIG. 2.
  • the spacer column 25 and the first organic insulating layer 21 are arranged in the same layer, and are formed by using the same material and using the same process.
  • the isolation column 25 includes a first organic film layer and a second organic film layer stacked, the first organic film layer and the first organic insulating layer 21 are arranged on the same layer, and are formed using the same material and through the same process, and the second organic film layer layer and the second organic insulating layer 24 are provided in the same layer, using the same material and formed by the same process.
  • FIG. 21 is an enlarged view showing the isolation pillars formed on the substrate according to an embodiment of the present disclosure.
  • the isolation column 25 can be disposed on the same layer as the signal line group 3 , and formed by using the same material and through the same process.
  • the cross section of the spacer 25 is I-shaped
  • the spacer 25 includes a first metal layer, a second metal layer and a third metal layer stacked, the first metal layer and the third metal layer are made of titanium metal, the second The metal layer adopts metal aluminum.
  • the cross-section of the isolation column 25 is I-shaped.
  • the luminescent layer Since the coverage of the I-shaped isolation column 25 is poor, when the luminescent layer is formed by evaporation, the luminescent layer will be disconnected at the isolation column 25, blocking the intrusion from the opening area 300. The path of water and oxygen invading into the display area through the light-emitting layer improves the reliability of the display panel.
  • FIG. 24 is an enlarged view showing spacers in a substrate according to an embodiment of the present disclosure.
  • the substrate 10 adopts a multilayer flexible substrate structure.
  • the substrate 10 adopts a double-layer flexible substrate structure.
  • the base 10 includes a first flexible base 1001, a first isolation layer 1002 disposed on the first flexible base 1001, a second flexible base 1003 disposed on the side of the first isolation layer 1002 away from the first flexible base 1001, and a second flexible base 1003 disposed on the second
  • the flexible substrate 1003 is away from the second isolation layer 1004 on the side of the first flexible substrate 1001 .
  • the first flexible substrate 1001 and the second flexible substrate 1003 may use flexible substrate materials, such as polyimide (PI).
  • the first isolation layer 1002 and the second isolation layer 1004 may use inorganic insulating materials.
  • the isolation post 25 may be disposed on the same layer as the second flexible substrate 1003 and the second isolation layer 1004 , and formed by using the same material and through the same process.
  • a third isolation groove 5 is formed between adjacent isolation columns 25.
  • the third isolation groove 5 includes side edges.
  • the second isolation layer 1004 protrudes from the side edges of the third isolation groove 5 to form a second undercut structure.
  • the light-emitting layer 28 when it is formed by evaporation, it may be disconnected due to the poor step coverage of the second undercut structure.
  • the disconnected light-emitting layer 28 will cover the bottom wall of the third isolation groove 5, blocking the path of water and oxygen intruding from the opening area 300 to the display area through the light-emitting layer 28, thereby improving the reliability of the display panel.
  • the third isolation groove 5 can absorb the stress generated during the formation of the hole area 300 , and at the same time prevent the cracks generated when the hole area 300 is drilled from extending to the display area 100 , thereby blocking the cracks.
  • the depth of the third isolation groove 5 is not limited, as long as the third isolation groove 5 can block the path of water and oxygen intruding from the opening area 300 to the display area through the light emitting layer 28 .
  • the bottom wall of the third isolation groove 5 is located on the surface of the first isolation layer 1002; or, the bottom wall of the third isolation groove 5 is located in the second flexible substrate 1003, that is, the third isolation groove 5 does not penetrate the second flexible substrate 1003 .
  • At least one fourth isolation groove 4 may also be formed between adjacent isolation columns 25, the fourth isolation groove 4 includes at least one side wall and a bottom wall, and the fourth isolation groove A second barrier layer 40 is provided on at least one side wall and at least one bottom wall of 4 .
  • the second barrier layer 40 can be used to block water and oxygen intruding from the opening area 300 from intruding into the display area 100 through the isolation pillars 25 .
  • the second barrier layer 40 can be disposed in the same layer as the first barrier layer 37 , and can be prepared from the same material through the same manufacturing process.
  • the second barrier layer 40 may employ a metal oxide material or an inorganic material.
  • the inorganic material may be materials such as silicon nitride or silicon oxide
  • the metal oxide material may be materials such as aluminum oxide, hafnium oxide, and tantalum oxide.
  • the third isolation groove 5 and the fourth isolation groove 4 may be arranged in multiple ways.
  • the third isolation trenches 5 and the fourth isolation trenches 4 are arranged alternately along the direction close to the opening area 300 , as shown in FIG. 2 .
  • the third isolation grooves 5 are arranged continuously along the direction close to the hole area 300 ; and the fourth isolation grooves 4 are continuously arranged along the direction close to the hole area 300 .
  • a protective layer 33 may be provided on the side of the second isolation region 500 away from the substrate 10. At least part of the protection layer 33 covers the first inorganic material layer 381 and the second inorganic material layer 382 on the second isolation region 500 .
  • the protection layer 33 can fill up the second isolation region 500 to relieve the stress of the second isolation region 500 and improve product reliability.
  • the protective layer 33 may use an organic material.
  • an organic material for example, resin.
  • the protection layer 33 can fill up the second isolation region 500 to reduce the gap between the surface of the packaging structure 38 and the package structure 38 .
  • the thickness between the surface of the protective layer 33 on the side away from the substrate 10 in the second isolation region 500 and the surface on the side of the substrate 10 close to the encapsulation structure 38 is the same as that from the surface on the side of the encapsulation structure 38 in the display area 100 away from the substrate 10 to the substrate 10
  • the thickness ratio between the surfaces on the side close to the encapsulation structure 38 is 0.8-1.2.
  • the protection layer 33 may also be partially located in the first isolation region 400, at least partially overlap or be flush with the encapsulation structure 38 in the first isolation region 400, and make up for the encapsulation structure 38 at the edge of the first isolation region 400. thinning.
  • a cover plate is arranged on the display substrate.
  • An ink area is arranged on the cover plate, and the ink area covers the middle frame area of the display substrate. Due to the tolerance of the size and position of the ink area prepared on the cover plate and the tolerance of the lamination accuracy of the glass cover plate and the display substrate, the area of the ink area is larger than the area of the frame area, thus restricting the narrow frame of the opening area. the design of.
  • the display substrate of the embodiment of the present disclosure may further include a light-shielding layer 36 , at least part of the light-shielding layer 36 is located in the frame region 200 .
  • the light shielding layer 36 is located in the frame area 200 .
  • the light shielding layer 36 is located on a side of the protective layer 33 away from the substrate 10 .
  • the light shielding layer 36 covers the first isolation region 400 and the second isolation region 500 .
  • the light shielding layer 36 can shield the signal line group 3 in the first isolation region 400 to prevent light reflection.
  • the light shielding layer 36 covers the entire frame area 200 .
  • the light-shielding layer 36 may be a metal layer or an opaque black organic coating or black inorganic coating.
  • FIG. 5 is a cross-sectional view of a display module according to an embodiment of the disclosure.
  • an embodiment of the present disclosure provides a display module.
  • the display module includes a display substrate 700 and a cover plate 800 stacked on the display substrate 700 .
  • a camera 900 is arranged in the opening area of the display substrate 700 .
  • the cover plate 800 covers the camera 900 .
  • the frame of the display module is b.
  • the light-shielding layer 36 is set on the display substrate 700, so that the setting of the light-shielding layer 36 is not affected by the ink tolerance and bonding tolerance of the cover plate 800.
  • the frame b of the display module can be equivalent to the frame area 200 of the display substrate 700, so as to minimize the frame of the display module.
  • the frame b of the display module may be less than 0.5 mm.
  • the width of the light-shielding layer 36 may be 0.3 mm, and the frame b of the display module may be 0.3-0.4 mm.
  • a buffer layer 34 may be disposed between the light-shielding layer 36 and the protective layer 33 , and the buffer layer 34 can buffer the stress generated by forming the hole region 300 .
  • a gap may be provided on the side of the buffer layer 34 near the opening area 300 , and the light shielding layer 36 fills the gap, so as to avoid the stress generated by the formation of the opening area 300 on the buffer layer 34. crack.
  • the display substrate in the embodiment of the present disclosure further includes at least one of a polarizer, a touch layer, and a cover disposed on a side of the light-shielding layer 36 away from the base 10 .
  • the technical solution of this embodiment will be further described below through the preparation process of the touch substrate of this embodiment.
  • the "patterning process” mentioned in this embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., which is a mature preparation process in related technologies.
  • the "photolithography process” mentioned in this embodiment includes film coating, mask exposure and development, which is a mature preparation process in the related art.
  • Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition
  • coating can use known coating processes
  • etching can use known methods, which are not specifically limited here.
  • a “thin film” refers to a thin film produced by depositing or coating a certain material on a substrate. If the "thin film” does not require a patterning process or a photolithography process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” still needs a patterning process or a photolithography process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the "layer” after patterning or photolithography includes at least one "pattern”.
  • the display substrate includes a display area, a frame area and an aperture area, the aperture area is located in the display area, and the frame area is located between the display area and the aperture area.
  • the frame area includes a first isolation area and a second isolation area, and the second isolation area is located between the first isolation area and the opening area.
  • Forming an active layer pattern on a substrate includes: first depositing a buffer film on the substrate 10 to form a buffer layer 11 pattern covering the entire substrate 10. Then a layer of active layer thin film is deposited, and the active layer thin film is patterned by a patterning process to form an active layer 12 pattern on the buffer layer 11 in the display area, as shown in FIG. 6 . Wherein, the pattern of the active layer 12 is formed in the display area, and the buffer layer 11 is formed in the frame area and the hole area at this time.
  • the substrate can be a flexible substrate or a rigid substrate, and the flexible substrate can be made of materials such as polyimide PI, polyethylene terephthalate PET or surface-treated polymer soft film.
  • Rigid substrates can be made of materials such as glass or metal foil.
  • the buffer film can be made of silicon nitride SiNx or silicon oxide SiOx, etc., and can be a single layer or a multilayer structure of silicon nitride/silicon oxide.
  • Forming the pattern of the gate electrode and the first signal line group includes: sequentially depositing a first insulating film and a first metal film on the substrate 10 forming the above structure, and patterning the first metal film through a patterning process to form a covering active layer 12 and the first insulating layer 13 of the buffer layer 11, the first gate electrode 14 disposed on the first insulating layer 13, the second gate electrode 15 and the pattern of the first signal line group 301, as shown in FIG. 7 .
  • the first gate electrode 14 and the second gate electrode 15 are formed in the display area
  • the first signal line group 301 is formed in the frame area
  • the buffer layer 11 and the first insulating layer 13 are formed in the opening area at this time.
  • the first gate electrode 14 , the second gate electrode 15 and the first signal line group 301 are arranged in the same layer, made of the same material and formed by the same process.
  • Forming the capacitive electrode and the second signal line group pattern includes: depositing a second insulating film and a second metal film in sequence on the substrate 10 forming the above structure, and patterning the second metal film through a patterning process to form a pattern covering the first grid.
  • the positions of the second gate electrodes 15 correspond to each other, and the capacitor electrode 17 forms a capacitor with the second gate electrode 15 , as shown in FIG. 8 .
  • the capacitive electrode 17 is formed in the display area
  • the second signal line group 302 is formed in the frame area
  • the buffer layer 11 , the first insulating layer 13 and the second insulating layer 16 are formed in the opening area at this time.
  • the capacitive electrode 17 and the second signal line group 302 are arranged in the same layer, made of the same material and formed by the same process.
  • Forming the inorganic insulating layer pattern with the first via holes includes: depositing a third insulating film on the substrate 10 with the above structure, patterning the third insulating film through a patterning process, and forming two first via holes in the display area.
  • the inorganic insulating layer 18 pattern of the via hole 39, the inorganic insulating layer 18, the second insulating layer 16 and the first insulating layer 13 in the two first via holes 39 are etched away, exposing the active layer 12, as shown in Figure 9 shown.
  • two first via holes 39 are formed in the display area, and the buffer layer 11 , the first insulating layer 13 , the second insulating layer 16 and the inorganic insulating layer 18 are formed in the frame area and the opening area at this time.
  • Forming patterns of source electrodes, drain electrodes, and a third signal line group includes: depositing a third metal thin film on the substrate 10 forming the above structure, patterning the third metal thin film through a patterning process, and forming the source electrode 19,
  • the drain electrode 20 and the third signal line group 303 are patterned, and the source electrode 19 and the drain electrode 20 are respectively connected to the active layer 12 through two first via holes 39 , as shown in FIG. 10 .
  • the source electrode 19 and the drain electrode 20 are formed in the display area
  • the third signal line group 303 is formed in the frame area.
  • the buffer layer 11, the first insulating layer 13, the second insulating layer 16 and the inorganic insulating layer are formed in the opening area.
  • the source electrode 19 , the drain electrode 20 and the third signal line group 303 are arranged in the same layer, made of the same material and formed by the same process.
  • the first signal line group 301 , the second signal line group 302 and the third signal line group 303 are the signal line group 3 of the frame area.
  • the vertical projections of at least two of the first signal line group 301, the second signal line group 302 and the third signal line group 303 on the substrate 10 at least partially overlap to reduce the The area occupied by the group 301 , the second signal line group 302 and the third signal line group 303 reduces the area of the frame area.
  • the driving structure layer in the display area, the signal line group 3 and the insulating layer in the frame area, and the insulating layer in the opening area are completed on the substrate 10 .
  • the driving structure layer located in the display area includes an active layer 12 , a first gate electrode 14 , a second gate electrode 15 , a capacitor electrode 17 , a source electrode 19 and a drain electrode 20 .
  • the signal line group 3 located in the frame area includes a first signal line group 301 , a second signal line group 302 and a third signal line group 303 .
  • the insulating layer located in the opening area includes a first insulating layer 13 , a second insulating layer 16 and an inorganic insulating layer 18 .
  • the first insulating layer 13 and the second insulating layer 16 are also called gate insulating layer (GI), and the inorganic insulating layer 18 is also called interlayer insulating layer (ILD), and the inorganic insulating layer 18 is an inorganic insulating layer.
  • GI gate insulating layer
  • ILD interlayer insulating layer
  • Forming the first organic insulating layer pattern includes: coating the first organic thin film on the substrate forming the aforementioned pattern, and exposing and developing the photolithography process through a mask, so that the first organic thin film is formed in the first isolation area of the display area and the frame area.
  • the pattern of the first organic insulating layer 21 , the pattern of the first organic insulating layer 21 covers the source electrode 19 and the drain electrode 20 in the display area, and the pattern of the first organic insulating layer 21 covers the third signal line group 303 in the frame area.
  • the first organic insulating layer 21 is provided with a second via hole and two first grooves 23 arranged at intervals.
  • the first grooves 23 include at least one side wall and a bottom wall.
  • the orthographic projection of the signal line group 3 located in the frame area on the substrate 10 is located between the orthographic projections of the bottom walls of the two first grooves 23 on the substrate 10 .
  • the two first grooves 23 expose the inorganic insulating layer 18 on the frame area.
  • a fourth metal thin film is coated on the first organic insulating layer 21, and the fourth metal thin film is patterned by a patterning process to form a connection electrode 22 in the display area, and the connection electrode 22 is connected to the drain electrode 20 through the second via hole, as shown in the figure 11.
  • the first organic thin film of the second isolation region in the frame region is etched away, exposing the inorganic insulating layer 18 on the second isolation region.
  • Forming a second organic insulating layer pattern includes: coating the second organic thin film on the substrate forming the aforementioned pattern, and exposing and developing the photolithography process through a mask, so that the second organic thin film is formed on the first organic insulating layer 21 and the frame of the display area. Form the pattern of the second organic insulating layer 24 on the first organic insulating layer 21 of the first isolation area in the frame area, and form at least one spacer column 25 arranged at intervals on the inorganic insulating layer 18 of the second isolation area in the frame area.
  • a fourth isolation groove 4 is formed between the isolation columns 25 , and a third via hole 41 is opened in the second organic insulating layer 24 of the display area, and the third via hole 41 exposes the connection electrode 22 .
  • the second organic insulating layer 24 of the first isolation area in the frame area is removed at the two first grooves 23 to form two first isolation grooves 1, both of which expose the inorganic insulating layer 18.
  • Both the first organic insulating layer 21 and the second organic insulating layer 24 are separated by two first isolation grooves 1 .
  • the two first isolation grooves 1 may be a first edge groove 101 and a second edge groove 102 respectively.
  • the vertical projections of the first signal line group 301, the second signal line group 302 and the third signal line group 303 on the substrate 10 are located at the bottom wall of the first edge groove 101 on the substrate 10, and the bottom wall of the second edge groove 102 is on the substrate. Between 10 orthographic projections.
  • the second isolation groove 2 is formed in the second organic insulating layer 24, and the orthographic projection of the second isolation groove 2 on the substrate 10 is located between the orthographic projection of the first edge groove 101 on the substrate 10 and the orthographic projection of the second edge groove 102 on the substrate 10, As shown in Figure 12.
  • Forming second isolation trenches and third isolation trench patterns includes: coating the barrier layer material on the substrate forming the aforementioned pattern, and forming the first barrier layer 37 covering the first isolation region through a photolithography process of mask exposure and development; The second barrier layer 40 covering the second isolation region, the first barrier layer 37 covering the sidewall and the bottom wall of the first isolation groove 1 , and the second barrier layer 40 covering the isolation column 25 .
  • a second isolation trench 2 is formed in the second organic insulating layer 24 on the first isolation region, and the first barrier layer 37 protrudes from the sidewall of the second isolation trench 2 to form a first undercut structure;
  • the third isolation groove 5 is formed in the isolation column 25 on the second isolation region, and the second barrier layer 40 protrudes from the side wall of the third isolation groove 5 to form a second undercut structure; the third isolation groove 5 and the fourth The isolation grooves 4 are alternately arranged along the direction close to the opening area, as shown in FIG. 13 .
  • Forming an anode pattern includes: depositing a transparent conductive film on the substrate forming the aforementioned pattern, patterning the transparent conductive film through a patterning process, forming an anode 27 pattern in the display area, and the anode 27 is connected to the connection electrode 22 through the third via hole, as shown in the figure 14.
  • the anode 27 is only formed in the display area, and the transparent conductive film in the frame area and the opening area is etched away.
  • the transparent conductive film can use indium tin oxide ITO or indium zinc oxide IZO.
  • Forming the pixel definition layer includes: coating a pixel definition material on the substrate forming the aforementioned pattern, making the pixel definition material form a pixel definition layer 30 in the display area, making the pixel definition material a first barrier layer 37 in the first isolation area in the frame area An isolation dam 6 is formed on the top.
  • a pixel opening is provided in the pixel definition layer of the display area, and the pixel opening exposes the anode 27 , as shown in FIG. 15 .
  • Forming a light-emitting layer and a cathode pattern includes: sequentially forming an organic light-emitting material and a cathode metal thin film on the substrate on which the aforementioned pattern is formed, to form the light-emitting layer 28 and the cathode pattern.
  • the light emitting layer 28 is connected to the anode 27 in the pixel opening area defined by the pixel definition layer, and the cathode is arranged on the light emitting layer 28 .
  • the light-emitting layer 28 and the cathode have poor coverage at the undercut structures of the second isolation groove 2 and the third isolation groove 5, and the light-emitting layer and the cathode 28 are disconnected at the second isolation groove 2 and the third isolation groove 5. , so that the light-emitting layer and the cathode 28 are separated between the display area and the aperture area, preventing water and oxygen around the aperture area from entering the display area along the light-emitting layer, and improving the service life of the device, as shown in FIG. 16 .
  • the light emitting layer 28 mainly includes an light emitting layer (EML).
  • the light-emitting layer can include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer arranged in sequence, so as to improve the efficiency of injecting electrons and holes into the light-emitting layer.
  • the cathode can use magnesium Mg, silver One of metal materials such as Ag, aluminum Al, copper Cu, lithium Li, or an alloy of the above metals.
  • Forming an encapsulation structure pattern includes: first depositing a first inorganic thin film on the substrate on which the aforementioned pattern is formed, and the first inorganic thin film covers the display area, the frame area and the opening area to form a pattern of the first inorganic material layer 381 . Subsequently, an organic material layer 383 is formed on the second organic insulating layer 24 of the first isolation area in the display area and the frame area, and the organic material layer 383 is isolated by the isolation dam 6 of the first isolation area.
  • a second inorganic thin film is deposited, and the second inorganic thin film covers the display area, frame area and opening area to form a second inorganic material layer 382 pattern, as shown in FIG. 17 .
  • the first inorganic material layer 381 , the organic material layer 383 and the second inorganic material layer 382 form an encapsulation structure 38 .
  • Forming the protective layer pattern includes: depositing a protective layer material on the substrate on which the aforementioned pattern is formed, at least part of the protective layer material covers the frame area to form a protective layer 33, and the protective layer 33 fills up the second isolation area in the frame area. Subsequently, a buffer layer 34 is formed on the protection layer 33 , and a gap 35 may be provided on the side of the buffer layer 34 near the opening area.
  • the protection layer 33 can fill up the level difference formed by the packaging structure and ensure the flatness of the subsequent formation of the light-shielding layer, as shown in FIG. 18 .
  • the buffer layer 34 may include an inorganic insulating material, such as silicon nitride, silicon oxide, silicon oxynitride, and the like.
  • Forming a light-shielding layer pattern includes: depositing a light-shielding material film on the substrate forming the aforementioned pattern, patterning the light-shielding material film through a patterning process, forming a light-shielding layer 36 pattern on the protective layer 33, and the light-shielding layer 36 filling the gap, as shown in Figure 19 Show.
  • the various structural film layers and substrates in the hole area are etched away by laser and other related processes to form the OLED display substrate with the hole area in the embodiment of the present disclosure, as shown in FIG. 2 .
  • all the structural film layers and substrates in the opening area can be etched away to form through holes, or part of the structural film layers in the open area can be etched away to form blind holes. It is determined according to actual needs.
  • the disclosed embodiments are not specifically limited.
  • An embodiment of the present disclosure also provides a display device, including the display substrate of the foregoing embodiments.
  • the display device can be any product or component with a display function such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, or a product or component with a VR, AR and 3D display function.

Abstract

一种显示基板(700)、显示装置。显示基板(700)包括显示区(100)、位于显示区(100)中的开孔区(300)以及位于显示区(100)与开孔区(300)之间的边框区(200)，边框区(200)至少包括第一隔离区(400)，第一隔离区(400)包括层叠设置的至少一个信号线组(3)以及至少一个有机绝缘层(600)，至少一个有机绝缘层(600)中设置有至少两个第一隔离槽(1)，至少两个第一隔离槽(1)沿着远离开孔区(300)方向间隔设置，信号线组(3)在边框区(200)的正投影位于至少两个第一隔离槽(1)之间间隔在边框区(200)的正投影中。

Description

显示基板、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及显示基板、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
对于智能终端产品，大部分厂商都在追求更高的屏占比，如全面屏和无边框屏，以期给用户带来更炫的视觉冲击。由于智能终端等产品通常需要设置前置摄像头、光线传感器等硬件，因此在OLED显示屏的有效显示区开设开孔区以设置摄像头等硬件的方案，正备受业内的高度关注。
目前，在OLED显示屏的有效显示区开设开孔区方案的难点之一在于封装的有效性。由于开孔区的侧壁会暴露出发光层和阴极，使得大气中的水氧会沿着发光层侵入有效显示区，使得有效显示区的发光层失效，带来显示不良。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示基板，包括显示区、位于所述显示区中的开孔区以及位于所述显示区与开孔区之间的边框区，所述边框区至少包括第一隔离区，所述第一隔离区包括层叠设置的至少一个信号线组以 及至少一个有机绝缘层，所述至少一个有机绝缘层中设置有至少两个第一隔离槽，所述至少两个第一隔离槽将所述至少一个有机绝缘层隔断，所述至少两个第一隔离槽沿着远离所述开孔区方向间隔设置，所述至少一个信号线组在所述边框区的正投影位于所述至少两个第一隔离槽之间间隔在所述边框区的正投影中。
在示例性实施方式中，所述第一隔离区包括层叠设置的至少两个信号线组，所述至少两个信号线组在所述边框区的正投影至少部分交叠。
在示例性实施方式中，至少一个所述第一隔离槽上设置有第一阻挡层。
在示例性实施方式中，所述至少一个有机绝缘层中还设置有至少一个第二隔离槽，所述至少一个第二隔离槽具有底切结构，所述至少一个有机绝缘层上层叠设置有发光层，所述第二隔离槽将所述发光层隔断。
在示例性实施方式中，所述至少一个第二隔离槽位于所述至少两个第一隔离槽之间。
在示例性实施方式中，所述第一隔离区上层叠设置有封装结构和隔离坝，所述封装结构至少包括有机层，所述隔离坝位于所述第一隔离区靠近所述开孔区一侧，所述隔离坝将所述有机层与所述开孔区隔断。
在示例性实施方式中，所述边框区还包括第二隔离区，所述第二隔离区位于所述第一隔离区与所述开孔区之间，所述第二隔离区包括至少两个间隔设置的隔离柱，相邻所述隔离柱之间形成有第三隔离槽，所述第三隔离槽具有底切结构。
在示例性实施方式中，相邻所述隔离柱之间还形成有第四隔离槽，所述第四隔离槽上设置有第二阻挡层。
在示例性实施方式中，所述隔离柱与所述至少一个有机绝缘层同层设置。
在示例性实施方式中，所述第一隔离区上层叠设置有封装结构和隔离坝，所述封装结构至少包括有机层，所述隔离坝位于所述第一隔离区靠近所述开孔区一侧，所述隔离坝将所述有机层与所述第二隔离区隔断，所述第二隔离区上设置有保护层。
在示例性实施方式中，所述保护层远离所述第二隔离区一侧的表面与所 述封装结构远离所述第一隔离区一侧的表面平齐。
在示例性实施方式中，所述保护层上设置有遮光层。
在示例性实施方式中，所述遮光层采用金属层或不透光的黑色无机涂层。
在示例性实施方式中，所述遮光层与所述保护层之间设置有缓冲层。
在示例性实施方式中，所述缓冲层靠近所述开孔区一侧设置有缺口，所述遮光层填充所述缺口中。
第二方面，本公开实施例还提供了一种显示装置，包括前述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
图1为本公开实施例显示基板的结构示意图；
图2为本公开实施例显示基板的剖视图；
图3为本公开实施例显示基板中第一隔离区信号线组的绕线示意图一；
图4为本公开实施例显示基板中第一隔离区信号线组的绕线示意图二；
图5为本公开实施例显示模组的剖视图；
图6为本公开实施例显示基板形成有源层后的示意图；
图7为本公开实施例显示基板形成形成栅电极以及第一栅线后的示意图；
图8为本公开实施例显示基板形成电容电极以及第二栅线后的示意图；
图9为本公开实施例显示基板形成无机绝缘层后的示意图；
图10为本公开实施例显示基板形成源电极、漏电极以及数据线后的示意图；
图11为本公开实施例显示基板形成第一有机绝缘层后的示意图一；
图12为本公开实施例显示基板形成第二有机绝缘层后的示意图；
图13为本公开实施例显示基板形成第二隔离槽、第三隔离槽以及第四隔离槽后的示意图；
图14为本公开实施例显示基板形成阳极后的示意图；
图15为本公开实施例显示基板形成像素定义层后的示意图；
图16为本公开实施例显示基板形成发光层和阴极后的示意图；
图17为本公开实施例显示基板形成封装结构后的示意图；
图18为本公开实施例显示基板形成保护层后的示意图；
图19为本公开实施例显示基板形成遮光层后的示意图；
图20为本公开实施例显示基板中信号线组的放大图；
图21为本公开实施例显示基板形成隔离柱后的放大图；
图22为本公开实施例显示基板形成隔离坝后的示意图；
图23为本公开实施例显示基板形成第一有机绝缘层后的示意图二；
图24为本公开实施例显示基板中隔离柱的放大图。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连 接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
本公开实施例提供了一种显示基板，包括显示区、开孔区以及位于所述显示区与开孔区之间的边框区，所述边框区至少包括第一隔离区，所述第一隔离区包括基底、设置于所述基底上至少一个无机绝缘层、设置于所述至少一个无机绝缘层远离所述基底一侧的至少一个有机绝缘层以及设置于所述至少一个有机绝缘层远离所述基底一侧的封装结构，所述封装结构至少包括一个有机材料层，显示基板包括至少两个第一隔离槽，所述至少两个第一隔离槽贯穿所述至少一个有机绝缘层，所述至少两个第一隔离槽至少包括第一边缘槽和第二边缘槽，其底壁在所述基底的正投影与所述有机材料层在所述基底的正投影交叠的第一隔离槽中，最靠近所述显示区一侧的第一隔离槽为所述第一边缘槽，其底壁在所述基底的正投影与所述有机材料层在所述基底的正投影不交叠的第一隔离槽中，最靠近所述显示区一侧的第一隔离槽为所述第二边缘槽，所述显示基板还包括设置于所述基底上的至少一个信号线组，所述至少一个信号线组在所述基底的正投影位于所述第一边缘槽底壁在所述基底正投影与所述第二边缘槽底壁在所述基底正投影之间。
图1为本公开实施例显示基板的结构示意图，图2为本公开实施例显示基板的剖视图。以图2为图1中A-A向的剖视图为例进行说明。本公开实施例显示基板可以为OLED显示基板或QLED显示基板。以本公开实施例显示基板可以为OLED显示基板为例进行说明书。如图1所示，在平行于显示基板的平面上，显示基板的主体结构包括显示区100、边框区200和开孔区300，边框区200位于显示区100与开孔区300之间。边框区200围绕开孔区300的四周，可以用于阻断从开孔区300入侵到显示区100的水氧路径。开孔区300在显示区100中的位置不限，形状也不做限制，可以为图1中所示的圆形，也可以椭圆形或者方形、菱形等其它多边形。
在平行于显示基板的平面上，显示区100可以包括至少一个栅线和至少一个数据线。栅线可以用于传送栅极电信号，数据线可以用于传送数据电信号。至少一个栅线沿着第一方向(例如水平方向)延伸，且至少一个栅线可以彼此平行。至少一个数据线沿着第二方向(例如垂直方向)延伸，且至少一个数据线可以彼此平行。其中，第一方向与第二方向不同。比如，第一方向与第二方向垂直。栅线和数据线限定至少一个子像素。
在垂直于显示基板的平面上，显示区100可以包括基底、设置在基底上的驱动结构层以及设置在驱动结构层上的发光结构层，驱动结构层主要包括至少一个薄膜晶体管(Thin Film Transistor，TFT)，发光结构层主要包括至少一个阳极、至少一个发光层和至少一个阴极。发光结构层中的阳极与薄膜晶体管中的漏电极连接，数据线与薄膜晶体管中的源电极连接，栅线与薄膜晶体管中的栅极连接。薄膜晶体管可以通过由与其连接的栅线施加的栅极电信号而导通或截止，并可以由与其连接的数据线提供的数据电信号传送到阳极。显示区100的子像素可以根据施加到阳极的数据电信号显示图像。
在一些实施例中，薄膜晶体管中的源极漏极可以依据薄膜晶体管的类型调换，本公开实施例在此不再赘述。
如图1所示，开孔区300包括至少一个通孔或盲孔，通孔的各个结构膜层和基底被去掉，盲孔中的大部分结构膜层被去掉，通孔或盲孔可以用于设置相应的硬件，如摄像头、传感器等硬件。其中，上述结构膜层可以包括驱动结构层中的各膜层以及发光结构层中的各膜层等。
图2中仅以一个子像素为例进行示意。如图2所示，显示区100中子像素的驱动结构层主要包括设置在基底上的缓冲层、设置在缓冲层上的薄膜晶体管。发光结构层主要包括与薄膜晶体管的漏电极连接的阳极、限定像素开口区域的像素界定层、发光层、形成在发光层上的阴极以及封装结构。其中，发光层至少覆盖像素开口区域。例如，发光层覆盖整个像素开口区域或整个子像素。
如图2所示，在平行于显示基板的平面上，本公开实施例显示基板中边框区200至少包括第一隔离区400。在垂直于显示基板的平面上，第一隔离 区400包括基底10、设置于基底10上的至少一个无机绝缘层18、设置于至少一个无机绝缘层18远离基底10一侧的至少一个有机绝缘层600以及设置于至少一个有机绝缘层600远离基底10一侧的至少一个封装结构38，封装结构38至少包括一个有机材料层，信号线组3包括至少一个信号线，至少一个有机绝缘层600中设置有至少两个第一隔离槽1，至少两个第一隔离槽1贯穿至少一个有机绝缘层600，至少两个第一隔离槽1至少包括第一边缘槽101和第二边缘槽102，其底壁在基底10的正投影与有机材料层383在基底10的正投影交叠的第一隔离槽1中，最靠近显示区100一侧的第一隔离槽1为第一边缘槽101；其底壁在基底10的正投影与有机材料层383在基底10的正投影不交叠的第一隔离槽1中，最靠近显示区100一侧的第一隔离槽1为第二边缘槽102，至少一个信号线组3在基底10的正投影位于第一边缘槽101底壁在基底10正投影与第二边缘槽102底壁在基底10正投影之间。
在示例性实施方式中，至少两个第一隔离槽1的底壁位于无机绝缘层18远离基底10一侧的表面上；或者，至少两个第一隔离槽1的底壁位于无机绝缘层18中，即至少两个第一隔离槽1的底壁过刻至无机绝缘层18中。
在示例性实施方式中，本实施例显示基板中除开孔区300以外的区域均设置有基底，且显示基板中的基底均为同层设置，采用相同的材料通过同一制备工艺制备而成。比如，显示区100中的基底与边框区200中的基底10同层设置，采用相同的材料通过同一制备工艺制备而成。
在示例性实施方式中，显示区100中的有机绝缘层与边框区200中的有机绝缘层600同层设置，采用相同的材料通过同一制备工艺制备而成。
在示例性实施方式中，显示区100中的无机绝缘层与边框区200中的无机绝缘层18同层设置，采用相同的材料通过同一制备工艺制备而成。
在示例性实施方式中，第一隔离区400在基底正投影具有两个边缘，两个边缘中靠近显示区100一侧的边缘与第一边缘槽101在基底正投影靠近显示区100一侧的边缘交叠；两个边缘中靠近开孔区300一侧的边缘与第二边缘槽102在基底正投影靠近开孔区300一侧的边缘交叠。
在示例性实施方式中，第一隔离槽1包括至少一个侧壁和底壁。例如， 第一边缘槽101包括两个侧壁以及一个底壁；第二边缘槽102包括两个侧壁以及一个底壁。
本公开实施例显示基板中信号线组3在基底10的正投影位于第一边缘槽101底壁在基底10正投影与第二边缘槽102底壁在基底10正投影之间，避免第一隔离槽1影响信号线组3的走线，从而使信号线组3在第一隔离区400中进行绕线，缩小了边框区200的面积，实现窄边框设计。
本公开实施例显示基板中第一隔离槽1可以为环绕开孔区300的环状结构。第一隔离槽1可以用于将边框区200中的有机绝缘层600隔断，阻断了从开孔区300入侵的水氧通过有机绝缘层600入侵到显示区域的路径。
在示例性实施方式中，有机绝缘层600可以采用有机材料，例如，树脂、聚硅氧烷系材料、亚克力系材料或聚酰亚胺系材料等。
在示例性实施方式中，在垂直于显示基板的平面上，第一隔离区400可以包括至少一个有机绝缘层600，比如，第一隔离区400包括层叠设置的一个、两个、三个或其他数量的有机绝缘层600。第一隔离区400中至少一个有机绝缘层600可以与显示区的有机绝缘层中至少一个同层设置，采用相同材料且通过同一工艺形成。
在示例性实施方式中，在垂直于显示基板的平面上，第一隔离槽1可以贯穿第一隔离区400中所有有机绝缘层600，将第一隔离区400中的有机绝缘层600完全隔断；或者，第一隔离槽1可以贯穿第一隔离区400中一部分有机绝缘层600，将第一隔离区400中部分有机绝缘层600隔断。比如，第一隔离区400包括层叠设置的第一有机绝缘层21和第二有机绝缘层24，第一有机绝缘层21位于第二有机绝缘层24与基底之间。第一隔离槽1贯穿第一有机绝缘层21和第二有机绝缘层24，即第一隔离槽1的深度不小于第一有机绝缘层21和第二有机绝缘层24厚度的总和，如图2所示。
在示例性实施方式中，第一隔离区400可以包括至少一个信号线组3，比如，第一隔离区400包括层叠设置的两个、三个或其他数量的信号线组3。
图3为本公开实施例显示基板中第一隔离区信号线组的绕线示意图一。图3以第一隔离区400包括三个层叠设置的信号线组3为例，说明本公开实 施例中信号线组3的绕线。如图3所示，本公开实施例显示基板为矩形结构，包括相对设置的短边以及相对设置的长边。本公开实施例显示基板中开孔区300的中心位于显示基板短边的中心线上。本公开实施例显示基板第一隔离区400包括三个层叠设置的信号线组3，三个信号线组3分别为依次层叠设第一信号线组301、第二信号线组302和第三信号线组303。第三信号线组303位于信号线组3远离基底10一侧，有机绝缘层600设置于第三信号线组303远离基底10一侧，并将第三信号线组303覆盖。三个信号线组3采用绕线形式在第一隔离区400绕过开孔区300。
在示例性实施方式中，本公开实施例对第一信号线组301、第二信号线组302和第三信号线组303没有限制。比如，第一信号线组301可以为第一栅线，第二信号线组302可以为第二栅线，第三信号线组303可以为第一数据线。
图20为本公开实施例显示基板中信号线组的放大图。在示例性实施方式中，如图20所示，至少一个信号线组3远离基底10一侧设置有阻挡层42，阻挡层42覆盖至少一个信号线组3，以防止至少一个信号线组3被腐蚀。其中，阻挡层42可以采用无机材料。
在示例性实施方式中，阻挡层42可以为连续膜层，阻挡层42覆盖整层信号线组3，如图20所示。或者，阻挡层可以包括至少一个图案化膜层，至少一个图案化膜层覆盖信号线组3中至少一个信号线。
在示例性实施方式中，本公开实施例显示基板中边框区200远离开孔区300一侧边沿到边框区200靠近开孔区300一侧边沿的距离可以小于0.4mm。比如，边框区200远离开孔区300一侧边沿到边框区200靠近开孔区300一侧边沿的距离为0.2-0.3mm。
图4为本公开实施例显示基板中第一隔离区信号线组的绕线示意图二。图4以边框区200包括三个层叠设置的信号线组3为例，说明本公开实施例中信号线组3的绕线。如图4所示，本公开实施例显示基板为矩形结构，包括相对设置的短边以及相对设置的长边。本公开实施例显示基板中开孔区300的中心不位于显示基板短边的中心线上。本公开实施例显示基板第一隔离区400包括三个层叠设置的信号线组3，三个信号线组3分别为依次层叠 设第一信号线组301、第二信号线组302和第三信号线组303。其中，显示区100中子像素采用双边驱动，可以消除开孔区300四周像素由于驱动造成的显示不均现象。
本公开实施例显示基板中信号线组3绕线所占空间小于第一隔离区400，信号线组3的绕线不会增加边框区200空间。另外，本公开实施例显示基板增加像素密度后，信号线组3数量会增加，但是只要信号线组3在边框区200的正投影位于至少两个第一隔离槽1之间间隔在边框区200的正投影中，使信号线组3绕线所占空间小于第一隔离区400，不会额外占用边框区200的空间。
在示例性实施方式中，在垂直于显示基板的平面上，如图2所示，第一隔离区400包括层叠设置的至少两个信号线组3，至少两个信号线组3互相绝缘，至少两个信号线组3在基底10的正投影至少部分交叠，从而减小信号线组3在边框区200绕线所占的空间。其中，信号线组3在基底10的正投影是指信号线组3中位于信号线组3相对两边缘的信号线之间的投影。
在示例性实施方式中，至少两个信号线组3所在的区域在基底10的正投影至少部分交叠，例如，第一隔离区400包括层叠设置的第一信号线组301、第二信号线组302、第三信号线组303，第一信号线组301所在的区域在基底10的正投影与第二信号线组302所在的区域在基底的正投影至少部分交叠；或者，第一信号线组301所在的区域在基底的正投影与第三信号线组303所在的区域在基底10的正投影至少部分交叠；或者，第二信号线组302所在的区域在基底10的正投影与第三信号线组303所在的区域在基底10的正投影至少部分交叠。
在示例性实施方式中，至少两个信号线组3中的信号线在基底10的正投影至少部分交叠。例如，第一隔离区400包括层叠设置的第一信号线组301、第二信号线组302、第三信号线组303，第一信号线组301包括至少一个第一信号线，第二信号线组302包括至少一个第二信号线，第三信号线组303包括至少一个第三信号线。第一信号线组301中至少一个第一信号线在基底10的正投影与第二信号线组302中至少一个第二信号线在基底的正投影至少部分交叠；或者，第一信号线组301中至少一个第一信号线在基底的正投影与 第三信号线组303中至少一个第三信号线在基底10的正投影至少部分交叠；或者，第二信号线组302中至少一个第二信号线在基底10的正投影与第三信号线组303中至少一个第三信号线在基底10的正投影至少部分交叠。
图23为本公开实施例显示基板形成第一有机绝缘层后的示意图二。在示例性实施方式中，如图22所示，本公开实施例显示基板第一隔离区400包括三个层叠设置的信号线组3，三个信号线组3分别为依次层叠设第一信号线组301、第二信号线组302和第三信号线组303。第三信号线组303位于信号线组3远离基底10一侧。在第三信号线组303远离基底10一侧设置有一层有机绝缘层600，有机绝缘层600将第三信号线组303覆盖。有机绝缘层600中设置有至少两个第一隔离槽1以及至少一个第二隔离槽2。第三信号线组303在基底10的正投影不与第一隔离槽1的槽底和第二隔离槽2的槽底交叠。
在示例性实施方式中，第一隔离槽1包括至少一个侧壁以及底壁，第一隔离槽1中的至少一个侧壁以及底壁上设置有第一阻挡层37。第一阻挡层37可以用于阻断从开孔区300入侵的水氧通过有机绝缘层600入侵显示区100。其中，第一阻挡层37可以被称为第一钝化层。
在示例性实施方式中，第一阻挡层37可以采用金属氧化物材料或无机材料。例如，无机材料可以为氮化硅或氧化硅等材料，金属氧化物材料可以为氧化铝、氧化铪、氧化钽等材料。
在示例性实施方式中，在制备第一阻挡层37过程中，先在基底10上形成无机绝缘层18，而后在无机绝缘层18上形成有机绝缘层600，在有机绝缘层600中形成贯穿有机绝缘层600的第一隔离槽1，最后在第一隔离槽1上形成第一阻挡层37，使第一阻挡层37与第一隔离槽1的底壁和至少一个侧壁接触，无机绝缘层18与第一隔离槽1的至少一个侧壁不接触。
在示例性实施方式中，至少一个有机绝缘层600中还设置有至少一个第二隔离槽2，至少一个第二隔离槽2具有第一底切结构。第一隔离区400还包括层叠设置于至少一个有机绝缘层600上的发光层，第二隔离槽2可以将发光层隔断。本公开实施例显示基板在显示区100形成发光层时，利用第二隔离槽2中底切结构覆盖性差，使边框区200的发光层在第二隔离槽2处断 开，可以阻断从开孔区300入侵的水氧通过发光层入侵到显示区域的路径。
在示例性实施方式中，本公开实施例显示基板中第二隔离槽2包括侧边，第一阻挡层37延伸至第二隔离槽2的侧边处，并凸出第二隔离槽2的侧边，形成第一底切结构。本公开实施例在蒸镀形成发光层时，会由于第一底切结构的台阶覆盖性差而断开。断开的发光层会覆盖第二隔离槽2的底壁，阻断了从开孔区300入侵的水氧通过发光层入侵到显示区域的路径，提高显示面板的信赖性。
在示例性实施方式中，第二隔离槽2可以贯穿边框区400中一部分有机绝缘层600。比如，第一隔离区400包括层叠设置的第一有机绝缘层21和第二有机绝缘层24，第一有机绝缘层21位于第二有机绝缘层24与基底10之间。第二隔离槽2贯穿第二有机绝缘层24，延伸至第一有机绝缘层21的表面，即第二隔离槽2的深度等于第二有机绝缘层24的厚度，如图2所示。
在示例性实施方式中，如图2所示，至少一个第二隔离槽2在基底10的正投影位于第一边缘槽101在基底10正投影与第二边缘槽102在基底10正投影之间。第二隔离槽2仅贯穿边框区中一部分有机绝缘层，使第二隔离槽2不会阻挡信号线组3的绕线，进而使至少一个第二隔离槽2在边框区200的正投影与信号线组3在边框区200的正投影至少部分交叠，从而实现窄边框设计。
在示例性实施方式中，至少一个第二隔离槽2在基底10的正投影与封装结构38中有机材料层383在基底10的正投影交叠。
在示例性实施方式中，如图2所示，封装结构38包括层叠设置的第一无机材料层381、第二无机材料层382以及位于第一无机材料层381和第二无机材料层382之间的至少一层有机材料层383。封装结构38可以用于保护发光单元。
在示例性实施方式中，如图2所示，本公开实施例显示基板在发光单元上形成封装结构的过程中，为了防止显示区100中封装结构材料流入开孔区300中。本公开实施例显示基板第一隔离区400上可以设置有隔离坝6，隔离坝6设置于第一隔离区400中的有机绝缘层600远离基底10一侧。隔离坝6 在基底10的正投影位于第一边缘槽101在基底10的正投影与第二边缘槽102在基底10正投影之间。隔离坝6将封装结构38中的有机材料层383与开孔区300隔断，以阻隔有机材料层383流入开孔区300。
在示例性实施方式中，隔离坝6可以与显示区200中的像素定义层同层设置，采用相同材料且通过同一工艺形成。或者，显示区200还包括隔垫层，隔离坝6可以与显示区200中的隔垫层同层设置，采用相同材料且通过同一工艺形成。或者，显示区200还包括隔垫层，隔离坝6包括层叠设置的第一隔离层和第二隔离层，第一隔离层与显示区200中的像素定义层同层设置，采用相同材料且通过同一工艺形成，第二隔离层与显示区200中的隔垫层同层设置，采用相同材料且通过同一工艺形成。
图22为本公开实施例显示基板形成隔离坝后的示意图。在示例性实施方式中，如图22所示，本公开实施例显示基板第一隔离区400上可以设置有至少两个隔离坝6，至少两个隔离坝6设置于第一隔离区400中的有机绝缘层600远离基底10一侧。至少两个隔离坝6可以间隔排布。至少两个隔离坝6在基底10的正投影位于第一边缘槽101在基底10的正投影与第二边缘槽102在基底10正投影之间。至少两个隔离坝6将封装结构38中的有机材料层383与开孔区300隔断，以阻隔有机材料层383流入开孔区300。
在示例性实施方式中，对至少两个隔离坝6之间的高度关系不进行限定，只要至少两个隔离坝6能够阻隔有机材料层383流入开孔区300即可。例如，至少两个隔离坝6之间的高度相等；或者，至少两个隔离坝6中的一个的高度大于至少两个隔离坝6中的另一个的高度。
在示例性实施方式中，边框区200还包括第二隔离区500，第二隔离区500位于第一隔离区400与开孔区300之间。第二隔离区500包括至少两个隔离柱25，相邻隔离柱25之间形成有第三隔离槽5，第三隔离槽5包括侧边，隔离柱25远离基底10一侧设置有第二阻挡层40，第二阻挡层40凸出第三隔离槽5的侧边，形成第二底切结构。本公开实施例在蒸镀形成发光层时，会由于第二底切结构的台阶覆盖性差而断开。断开的发光层会覆盖第三隔离槽5的底壁，阻断了从开孔区300入侵的水氧通过发光层入侵到显示区域的路径，提高显示面板的信赖性。并且，第三隔离槽5能够吸收形成开孔区300 过程中产生的应力，同时可以阻挡开孔区300打孔时产生的裂纹延伸至显示区100，阻断裂纹。其中，第二阻挡层40可以被称为第二钝化层。
在示例性实施方式中，隔离柱25可以与第一隔离区400的有机绝缘层600中的至少一个同层设置，采用相同材料且通过同一工艺形成。比如，第一隔离区400包括层叠设置的第一有机绝缘层21和第二有机绝缘层24，隔离柱25与第二有机绝缘层24同层设置，采用相同材料且通过同一工艺形成，如图2所示。或者，隔离柱25与第一有机绝缘层21同层设置，采用相同材料且通过同一工艺形成。或者，隔离柱25包括层叠设置的第一有机膜层和第二有机膜层，第一有机膜层与第一有机绝缘层21同层设置，采用相同材料且通过同一工艺形成，第二有机膜层与第二有机绝缘层24同层设置，采用相同材料且通过同一工艺形成。
图21为本公开实施例显示基板形成隔离柱后的放大图。在示例性实施方式中，如图21所示，隔离柱25可以与信号线组3同层设置，采用相同材料且通过同一工艺形成。例如，隔离柱25的横截面呈工字型，隔离柱25包括层叠设置的第一金属层、第二金属层以及第三金属层，第一金属层和第三金属层采用金属钛，第二金属层采用金属铝。隔离柱25的横截面呈工字型，由于工字型的隔离柱25覆盖性差，在蒸镀形成发光层时，发光层会在隔离柱25处断开，阻断了从开孔区300入侵的水氧通过发光层入侵到显示区域的路径，提高显示面板的信赖性。
图24为本公开实施例显示基板中隔离柱的放大图。在示例性实施方式中，如图24所示，基底10采用多层柔性基底结构。例如，基底10采用双层柔性基底结构。基底10包括第一柔性基底1001、设置于第一柔性基底1001上的第一隔离层1002、设置于第一隔离层1002远离第一柔性基底1001一侧的第二柔性基底1003以及设置于第二柔性基底1003远离第一柔性基底1001一侧的第二隔离层1004。其中，第一柔性基底1001和第二柔性基底1003可以采用柔性基底材料，比如，聚酰亚胺(PI)。第一隔离层1002和第二隔离层1004可以采用无机绝缘材料。
在示例性实施方式中，如图24所示，隔离柱25可以与第二柔性基底1003和第二隔离层1004同层设置，采用相同材料且通过同一工艺形成。相邻隔离 柱25之间形成有第三隔离槽5，第三隔离槽5包括侧边，第二隔离层1004凸出第三隔离槽5的侧边，形成第二底切结构。本公开实施例在蒸镀形成发光层28时，会由于第二底切结构的台阶覆盖性差而断开。断开的发光层28会覆盖第三隔离槽5的底壁，阻断了从开孔区300入侵的水氧通过发光层28入侵到显示区域的路径，提高显示面板的信赖性。并且，第三隔离槽5能够吸收形成开孔区300过程中产生的应力，同时可以阻挡开孔区300打孔时产生的裂纹延伸至显示区100，阻断裂纹。
在示例性实施方式中，不对第三隔离槽5的深度进行限定，只要第三隔离槽5能够阻断从开孔区300入侵的水氧通过发光层28入侵到显示区域的路径即可。例如，第三隔离槽5的底壁位于第一隔离层1002的表面；或者，第三隔离槽5的底壁位于第二柔性基底1003中，即第三隔离槽5不贯穿第二柔性基底1003。
在示例性实施方式中，如图2所示，相邻隔离柱25之间还可以形成有至少一个第四隔离槽4，第四隔离槽4包括至少一个侧壁以及底壁，第四隔离槽4的至少一个侧壁和至少一个底壁上设置有第二阻挡层40。第二阻挡层40可以用于阻断从开孔区300入侵的水氧通过隔离柱25入侵显示区100。
在示例性实施方式中，第二阻挡层40可以与第一阻挡层37同层设置，采用相同的材料通过同一制备工艺制备而成。
在示例性实施方式中，第二阻挡层40可以采用金属氧化物材料或无机材料。例如，无机材料可以为氮化硅或氧化硅等材料，金属氧化物材料可以为氧化铝、氧化铪、氧化钽等材料。
在示例性实施方式中，第三隔离槽5与第四隔离槽4可以采用多用方式排布。比如，第三隔离槽5与第四隔离槽4沿着靠近开孔区300方向交替排布，如图2所示。或者，第三隔离槽5沿着靠近开孔区300方向连续排布；以及第四隔离槽4沿着靠近开孔区300方向连续排布。
在示例性实施方式中，如图2所示，由于第一无机材料层381和第二无机材料层382覆盖第二隔离区500，第一无机材料层381和第二无机材料层382采用无机材料，应力较大。为缓解第一无机材料层381和第二无机材料 层382的应力，第二隔离区500远离基底10一侧可以设置有保护层33。至少部分保护层33覆盖第二隔离区500上的第一无机材料层381和第二无机材料层382。保护层33能够将第二隔离区500填平，缓解第二隔离区500的应力，提高产品信赖性。
在示例性实施方式中，保护层33可以采用有机材料。例如，树脂。
在示例性实施方式中，如图2所示，保护层33能够将第二隔离区500填平，减小与封装结构38表面断差。例如，第二隔离区500中保护层33远离基底10一侧的表面到基底10靠近封装结构38一侧表面之间的厚度与显示区100中封装结构38远离基底10一侧的表面到基底10靠近封装结构38一侧表面之间的厚度的比值为0.8-1.2。
在示例性实施方式中，保护层33还可以部分位于第一隔离区400，与第一隔离区400中的封装结构38至少部分交叠或者齐平，弥补第一隔离区400边缘处封装结构38减薄。
一般显示基板上设置有盖板。盖板上设置有油墨区，油墨区覆盖显示基板中边框区。由于在盖板上制备形成油墨区的尺寸和位置存在公差；以及玻璃盖板与显示基板贴合的精度均存在公差，导致油墨区的面积大于边框区的面积，从而制约了开孔区窄边框的设计。
在示例性实施方式中，如图2所示，本公开实施例显示基板还可以包括遮光层36，至少部分遮光层36位于边框区200中。
在示例性实施方式中，遮光层36位于边框区200中。
在示例性实施方式中，遮光层36位于保护层33远离基底10一侧。遮光层36覆盖第一隔离区400和第二隔离区500。遮光层36可以遮挡第一隔离区400中信号线组3，防止反光。遮光层36覆盖整个边框区200。其中，遮光层36可以采用金属层或不透光的黑色有机涂层或黑色无机涂层。
图5为本公开实施例显示模组的剖视图。如图5所示，本公开实施例提供一种显示模组，显示模组包括显示基板700以及层叠设置于显示基板700上的盖板800，显示基板700的开孔区中设置有摄像头900，盖板800将摄像头900覆盖。显示模组的边框为b，本公开实施例显示模组中遮光层36设置 在显示基板700上，使遮光层36的设置不受盖板800油墨公差以及贴合公差的影响。显示模组的边框b可以与显示基板700的边框区200相当，使显示模组的边框最小化。示例的，显示模组的边框b可以小于0.5mm。比如，遮光层36的宽度可以为0.3mm，显示模组的边框b为0.3-0.4mm。
在示例性实施方式中，如图2所示，遮光层36与保护层33之间可以设置有缓冲层34，缓冲层34能够缓冲形成开孔区300产生的应力。
在示例性实施方式中，如图2所示，缓冲层34靠近开孔区300一侧可以设置有缺口，遮光层36填充缺口中，以避免形成开孔区300产生的应力对缓冲层34产生裂纹。
在示例性实施方式中，本公开实施例显示基板还包括设置于遮光层36远离基底10一侧的偏光片、触控层以及盖板中的至少一种。
下面通过本实施例触控基板的制备过程进一步说明本实施例的技术方案。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制备工艺。本实施例中所说的“光刻工艺”包括涂覆膜层、掩模曝光和显影，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在衬底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺或光刻工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺或光刻工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺或光刻工艺后的“层”中包含至少一个“图案”。
图6至图19为本实施例显示基板制备过程的示意图。本实施例显示基板包括显示区、边框区和开孔区，开孔区位于显示区内，边框区位于显示区与开孔区之间。边框区包括第一隔离区和第二隔离区，第二隔离区位于第一隔离区与开孔区之间。
本实施例显示基板制备过程包括：
(1)在基底上形成有源层图案。在基底上形成有源层图案包括：先在基 底10上沉积一层缓冲薄膜，形成覆盖整个基底10的缓冲层11图案。随后沉积一层有源层薄膜，通过构图工艺对有源层薄膜进行构图，在显示区形成设置在缓冲层11上的有源层12图案，如图6所示。其中，有源层12图案形成在显示区，此时的边框区和开孔区形成有缓冲层11。基底可以为柔性基底或者刚性基底，柔性基底可以采用聚酰亚胺PI、聚对苯二甲酸乙二酯PET或经表面处理的聚合物软膜等材料。刚性基底可以采用玻璃或金属箔片等材料。缓冲薄膜可以采用氮化硅SiNx或氧化硅SiOx等，可以是单层，也可以是氮化硅/氧化硅的多层结构。
(2)形成栅电极以及第一信号线组图案。形成栅电极以及第一信号线组图案包括：在形成上述结构的基底10上，依次沉积第一绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层12和缓冲层11的第一绝缘层13、设置在第一绝缘层13上的第一栅电极14、第二栅电极15和第一信号线组301图案，如图7所示。其中，第一栅电极14和第二栅电极15形成在显示区，第一信号线组301形成在边框区，此时的开孔区形成有缓冲层11和第一绝缘层13。第一栅电极14、第二栅电极15和第一信号线组301同层设置、采用相同材料且通过同一工艺形成。
(3)形成电容电极以及第二信号线组图案。形成电容电极以及第二信号线组图案包括：在形成上述结构的基底10上，依次沉积第二绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅电极14、第二栅电极15和第一绝缘层13的第二绝缘层16以及设置在第二绝缘层16上的电容电极17图案以及第二信号线组302图案，电容电极17的位置与第二栅电极15的位置相对应，电容电极17与第二栅电极15构成电容，如图8所示。其中，电容电极17形成在显示区，第二信号线组302形成在边框区，此时的开孔区形成有缓冲层11、第一绝缘层13和第二绝缘层16。电容电极17和第二信号线组302同层设置、采用相同材料且通过同一工艺形成。
(4)形成开设有第一过孔的无机绝缘层图案。形成开设有第一过孔的无机绝缘层图案包括：在形成上述结构的基底10上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，在显示区形成开设有两个第一过孔39的无机绝缘层18图案，两个第一过孔39中的无机绝缘层18、第二绝缘层16 和第一绝缘层13被刻蚀掉，暴露出有源层12，如图9所示。其中，两个第一过孔39形成在显示区，此时的边框区和开孔区形成有缓冲层11、第一绝缘层13、第二绝缘层16和无机绝缘层18。
(5)形成源电极、漏电极以及第三信号线组图案。形成源电极、漏电极以及第三信号线组图案包括：在形成上述结构的基底10上，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在显示区形成源电极19、漏电极20和第三信号线组303图案，源电极19和漏电极20分别通过两个第一过孔39与有源层12连接，如图10所示。其中，源电极19和漏电极20形成在显示区，第三信号线组303形成在边框区，此时开孔区形成有缓冲层11、第一绝缘层13、第二绝缘层16和无机绝缘层18。源电极19、漏电极20和第三信号线组303同层设置、采用相同材料且通过同一工艺形成。第一信号线组301、第二信号线组302以及第三信号线组303均为边框区的信号线组3。
在示例性实施方式中，第一信号线组301、第二信号线组302和第三信号线组303中的至少两个在基底10上的垂直投影至少部分重叠，以减小第一信号线组301、第二信号线组302和第三信号线组303占用的面积，从而减小边框区的面积。
通过上述过程，在基底10上完成了位于显示区的驱动结构层，位于边框区的信号线组3和绝缘层，开孔区的绝缘层的制备。其中，位于显示区的驱动结构层包括有源层12、第一栅电极14、第二栅电极15、电容电极17、源电极19和漏电极20。位于边框区的信号线组3包括第一信号线组301、第二信号线组302和第三信号线组303。位于开孔区的绝缘层包括第一绝缘层13、第二绝缘层16和无机绝缘层18。其中，第一绝缘层13和第二绝缘层16也称之为栅绝缘层(GI)，无机绝缘层18也称之为层间绝缘层(ILD)，无机绝缘层18为无机绝缘层。
(6)形成第一有机绝缘层图案。形成第一有机绝缘层图案包括：在形成前述图案的基底上涂覆第一有机薄膜，通过掩膜曝光显影的光刻工艺，使第一有机薄膜在显示区和边框区的第一隔离区形成第一有机绝缘层21图案，第一有机绝缘层21图案在显示区覆盖源电极19和漏电极20，第一有机绝缘层21图案在边框区覆盖第三信号线组303。第一有机绝缘层21 开设有第二过孔和两个间隔设置的第一槽体23，第一槽体23包括至少一个侧壁以及底壁。位于边框区的信号线组3在基底10的正投影位于两个第一槽体23底壁在基底10正投影之间。两个第一槽体23暴露出边框区上的无机绝缘层18。在第一有机绝缘层21上涂覆第四金属薄膜，通过构图工艺对第四金属薄膜进行构图，在显示区形成连接电极22，连接电极22通过第二过孔与漏电极20连接，如图11所示。其中，边框区中第二隔离区的第一有机薄膜被刻蚀掉，暴露出第二隔离区上的无机绝缘层18。
(7)形成第二有机绝缘层图案。形成第二有机绝缘层图案包括：在形成前述图案的基底上涂覆第二有机薄膜，通过掩膜曝光显影的光刻工艺，使第二有机薄膜在显示区的第一有机绝缘层21和边框区中第一隔离区的第一有机绝缘层21上形成第二有机绝缘层24图案，以及在边框区中第二隔离区的无机绝缘层18上形成至少一个间隔设置的隔离柱25，相邻隔离柱25之间形成第四隔离槽4，显示区的第二有机绝缘层24中开设有第三过孔41，第三过孔41暴露出连接电极22。边框区中第一隔离区的第二有机绝缘层24在两个第一槽体23处被去除，形成两个第一隔离槽1，两个第一隔离槽1均暴露出边框区上的无机绝缘层18。第一有机绝缘层21和第二有机绝缘层24均被两个第一隔离槽1隔断。两个第一隔离槽1可以分别为第一边缘槽101和第二边缘槽102。第一信号线组301、第二信号线组302和第三信号线组303在基底10上的垂直投影位于第一边缘槽101底壁在基底10正投影与第二边缘槽102底壁在基底10正投影之间。第二有机绝缘层24中形成第二隔离槽2，第二隔离槽2在基底10的正投影位于第一边缘槽101在基底10正投影与第二边缘槽102在基底10正投影之间，如图12所示。
(8)形成第二隔离槽以及第三隔离槽图案。形成第二隔离槽以及第三隔离槽图案包括：在形成前述图案的基底上，涂覆阻挡层材料，通过掩膜曝光显影的光刻工艺，形成覆盖第一隔离区的第一阻挡层37以及覆盖第二隔离区的第二阻挡层40，第一阻挡层37覆盖第一隔离槽1的侧壁和底壁，第二阻挡层40覆盖隔离柱25。通过刻蚀工艺，在第一隔离区上的第二有机绝缘层24中形成第二隔离槽2，且第一阻挡层37凸出第二隔离槽2的 侧壁，形成第一底切结构；在第二隔离区上的隔离柱25中形成第三隔离槽5，且第二阻挡层40凸出第三隔离槽5的侧壁，形成第二底切结构；第三隔离槽5与第四隔离槽4沿着靠近开孔区的方向交替排布，如图13所示。
(9)形成阳极图案。形成阳极图案包括：在形成前述图案的基底上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在显示区形成阳极27图案，阳极27通过第三过孔与连接电极22连接，如图14所示。其中，阳极27仅形成在显示区域，边框区和开孔区的透明导电薄膜被刻蚀掉。透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。
(10)形成像素定义层。形成像素定义层包括：在形成前述图案的基底上涂覆像素定义材料，使像素定义材料在显示区形成像素定义层30，使像素定义材料在边框区中第一隔离区的第一阻挡层37上形成隔离坝6。显示区的像素定义层中设置有像素开口，像素开口暴露阳极27，如图15所示。
(11)形成发光层和阴极图案。形成发光层和阴极图案包括：在形成前述图案的基底上依次形成有机发光材料及阴极金属薄膜，形成发光层28和阴极图案。在显示区，发光层28与像素定义层限定出的像素开口区域内的阳极27连接，阴极设置在发光层28上。在边框区，发光层28和阴极在第二隔离槽2以及第三隔离槽5的底切结构处覆盖性差，发光层和阴极28在第二隔离槽2以及第三隔离槽5处发生断开，从而将发光层和阴极28在显示区与开孔区之间进行隔断，防止开孔区周围的水氧沿着发光层进入显示区，提高了器件的使用寿命，如图16所示。其中，发光层28主要包括发光层(EML)。实际实施时，发光层可以包括依次设置的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，提高电子和空穴注入发光层的效率，阴极可以采用镁Mg、银Ag、铝Al、铜Cu、锂Li等金属材料的一种，或上述金属的合金。
(12)形成封装结构图案。形成封装结构图案包括：在形成前述图案的基底上先沉积第一无机薄膜，第一无机薄膜覆盖显示区、边框区和开孔区，形成第一无机材料层381图案。随后，在显示区和边框区中第一隔离区的第二有机绝缘层24上形成有机材料层383，有机材料层383被第一隔 离区的隔离坝6隔断。随后，沉积第二无机薄膜，第二无机薄膜覆盖显示区、边框区和开孔区，形成第二无机材料层382图案，如图17所示。其中，第一无机材料层381、有机材料层383和第二无机材料层382形成封装结构38。
(13)形成保护层图案。形成保护层图案包括：在形成前述图案的基底上沉积保护层材料，至少部分保护层材料覆盖边框区，形成保护层33，保护层33将边框区中第二隔离区填平。随后，在保护层33上形成缓冲层34，缓冲层34靠近开孔区一侧可以设置有缺口35。保护层33能够填平封装结构形成的段差，保证后续形成遮光层的平整性，如图18所示。其中，缓冲层34可以包括无机绝缘材料，例如可以包括氮化硅、氧化硅、氮氧化硅等。
(14)形成遮光层图案。形成遮光层图案包括：在形成前述图案的基底上沉积遮光材料薄膜，通过构图工艺对遮光材料薄膜进行构图，在保护层33上形成遮光层36图案，遮光层36将缺口填充，如图19所示。
(15)最后，通过激光等相关工艺将开孔区的各个结构膜层和基底刻蚀掉，形成本公开实施例开设有开孔区的OLED显示基板，如图2所示。实际实施时，可以将开孔区的各个结构膜层和基底全部刻蚀掉，形成通孔，也可以将开孔区的部分结构膜层刻蚀掉，形成盲孔，根据实际需要确定，本公开实施例不做具体限制。
本公开实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，也可以为具有VR、AR和3D显示功能的产品或部件。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (19)

  1. 一种显示基板，包括显示区、开孔区以及位于所述显示区与开孔区之间的边框区，所述边框区至少包括第一隔离区，所述第一隔离区包括基底、设置于所述基底上至少一个无机绝缘层、设置于所述至少一个无机绝缘层远离所述基底一侧的至少一个有机绝缘层以及设置于所述至少一个有机绝缘层远离所述基底一侧的封装结构，所述封装结构至少包括一个有机材料层，显示基板包括至少两个第一隔离槽，所述至少两个第一隔离槽贯穿所述至少一个有机绝缘层，所述至少两个第一隔离槽至少包括第一边缘槽和第二边缘槽，其底壁在所述基底的正投影与所述有机材料层在所述基底的正投影交叠的第一隔离槽中，最靠近所述显示区一侧的第一隔离槽为所述第一边缘槽，其底壁在所述基底的正投影与所述有机材料层在所述基底的正投影不交叠的第一隔离槽中，最靠近所述显示区一侧的第一隔离槽为所述第二边缘槽，所述显示基板还包括设置于所述基底上的至少一个信号线组，所述至少一个信号线组在所述基底的正投影位于所述第一边缘槽底壁在所述基底正投影与所述第二边缘槽底壁在所述基底正投影之间。
  2. 根据权利要求1所述的显示基板，其中，所述第一隔离区包括层叠设置的第一有机绝缘层和第二有机绝缘层，所述第一隔离槽贯穿所述第一有机绝缘层和所述第二有机绝缘层。
  3. 根据权利要求1所述的显示基板，其中，所述第一隔离槽包括至少一个侧壁以及底壁，至少一个所述第一隔离槽的至少一个侧壁和底壁上设置有第一阻挡层。
  4. 根据权利要求1所述的显示基板，其中，所述至少一个有机绝缘层中还设置有至少一个第二隔离槽，所述至少一个第二隔离槽具有第一底切结构，所述第一隔离区还包括设置于至少一个有机绝缘层上的发光层，所述第二隔离槽将所述发光层隔断。
  5. 根据权利要求4所述的显示基板，其中，所述至少一个第二隔离槽在所述基底的正投影与所述有机材料层在所述基底的正投影交叠。
  6. 根据权利要求4所述的显示基板，其中，所述至少一个第二隔离槽在 所述基底的正投影位于所述第一边缘槽在所述基底正投影与所述第二边缘槽在所述基底正投影之间。
  7. 根据权利要求1所述的显示基板，其中，所述第一隔离区还包括至少一个隔离坝，所述至少一个隔离坝设置于所述至少一个有机绝缘层远离所述基底一侧，所述隔离坝在所述基底的正投影位于所述第一边缘槽在所述基底的正投影与所述第二边缘槽在所述基底正投影之间，所述封装结构包括依次层叠设置的第一封装材料层、第二封装材料层和第三封装材料层，所述第一封装材料层和所述第三封装材料层均采用无机材料，所述第二封装材料层包括至少一层有机材料层，所述隔离坝将所述至少一层有机材料层与所述开孔区隔断。
  8. 根据权利要求1所述的显示基板，其中，所述边框区还包括第二隔离区，所述第二隔离区位于所述第一隔离区与所述开孔区之间，所述第二隔离区包括至少两个隔离柱，相邻所述隔离柱之间形成有第三隔离槽，所述第三隔离槽具有第二底切结构。
  9. 根据权利要求8所述的显示基板，其中，相邻所述隔离柱之间还形成有第四隔离槽，所述第四隔离槽包括至少一个侧壁以及底壁，至少一个所述第四隔离槽的至少一个侧壁和至少一个底壁上设置有第二阻挡层。
  10. 根据权利要求8所述的显示基板，其中，所述隔离柱与所述至少一个有机绝缘层同层设置。
  11. 根据权利要求9所述的显示基板，其中，所述第一隔离槽包括至少一个侧壁以及底壁，至少一个所述第一隔离槽的至少一个侧壁和至少一个底壁上设置有第一阻挡层，所述第一阻挡层与所述第二阻挡层同层设置。
  12. 根据权利要求8所述的显示基板，其中，所述封装结构远离所述基底一侧设置有保护层，至少部分所述保护层覆盖所述第二隔离区。
  13. 根据权利要求12所述的显示基板，其中，所述第二隔离区中保护层远离所述基底一侧的表面到所述基底靠近所述封装结构一侧表面之间的厚度与所述显示区中所述封装结构远离所述基底一侧的表面到所述基底靠近所述封装结构一侧表面之间的厚度的比值为0.8-1.2。
  14. 根据权利要求13所述的显示基板，其中，还包括遮光层，所述遮光层位于所述保护层远离所述基底一侧。
  15. 根据权利要求14所述的显示基板，其中，所述遮光层采用金属层或不透光的黑色有机涂层或黑色无机涂层。
  16. 根据权利要求14所述的显示基板，其中，所述遮光层与所述保护层之间设置有缓冲层。
  17. 根据权利要求16所述的显示基板，其中，所述缓冲层靠近所述开孔区一侧设置有缺口，所述遮光层填充所述缺口中。
  18. 根据权利要求1所述的显示基板，其中，所述第一隔离区包括层叠设置的至少两个信号线组，所述至少两个信号线组互相绝缘，所述至少两个信号线组在所述基底的正投影至少部分交叠。
  19. 一种显示装置，包括权利要求1至18任一所述的显示基板。
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Publication number Priority date Publication date Assignee Title
CN114141143B (zh) * 2021-11-24 2023-07-25 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法与移动终端
CN114446190B (zh) * 2022-02-08 2023-07-25 武汉华星光电半导体显示技术有限公司 支撑板及显示装置
CN114899334A (zh) * 2022-03-23 2022-08-12 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN114863814B (zh) * 2022-04-28 2024-04-16 昆山国显光电有限公司 一种显示面板、显示面板的制作方法及显示装置
CN115035793B (zh) * 2022-06-10 2023-10-24 武汉天马微电子有限公司 显示屏、显示装置及显示屏的制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108666347A (zh) * 2018-04-26 2018-10-16 上海天马微电子有限公司 显示面板及其制造方法、显示装置
CN110416435A (zh) * 2019-08-28 2019-11-05 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN110660930A (zh) * 2019-07-29 2020-01-07 云谷（固安）科技有限公司 显示面板及其制备方法和显示装置
CN110660826A (zh) * 2018-06-29 2020-01-07 三星显示有限公司 显示面板和包括显示面板的显示装置
CN111697026A (zh) * 2019-03-15 2020-09-22 三星显示有限公司 显示面板
CN111782080A (zh) * 2020-06-28 2020-10-16 合肥维信诺科技有限公司 显示面板和显示装置
CN211929490U (zh) * 2020-03-31 2020-11-13 京东方科技集团股份有限公司 显示基板及显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108666347A (zh) * 2018-04-26 2018-10-16 上海天马微电子有限公司 显示面板及其制造方法、显示装置
CN110660826A (zh) * 2018-06-29 2020-01-07 三星显示有限公司 显示面板和包括显示面板的显示装置
CN111697026A (zh) * 2019-03-15 2020-09-22 三星显示有限公司 显示面板
CN110660930A (zh) * 2019-07-29 2020-01-07 云谷（固安）科技有限公司 显示面板及其制备方法和显示装置
CN110416435A (zh) * 2019-08-28 2019-11-05 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN211929490U (zh) * 2020-03-31 2020-11-13 京东方科技集团股份有限公司 显示基板及显示面板
CN111782080A (zh) * 2020-06-28 2020-10-16 合肥维信诺科技有限公司 显示面板和显示装置

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