WO2022156155A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2022156155A1
WO2022156155A1 PCT/CN2021/104797 CN2021104797W WO2022156155A1 WO 2022156155 A1 WO2022156155 A1 WO 2022156155A1 CN 2021104797 W CN2021104797 W CN 2021104797W WO 2022156155 A1 WO2022156155 A1 WO 2022156155A1
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WIPO (PCT)
Prior art keywords
shaped member
dielectric layer
opening
wall
pattern
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/104797
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English (en)
French (fr)
Inventor
王蒙蒙
黄信斌
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to US17/648,541 priority Critical patent/US12165919B2/en
Publication of WO2022156155A1 publication Critical patent/WO2022156155A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections

Definitions

  • the embodiments of the present application relate to the technical field of semiconductors, and in particular, to a semiconductor structure and a method for manufacturing the same.
  • a semiconductor structure such as a chip
  • the formed chip usually includes a semiconductor device and an interconnection structure disposed on the semiconductor device.
  • a plurality of chips can be formed on the semiconductor substrate, and these chips are cut from the semiconductor substrate and packaged to form a plurality of independent chips.
  • the stress generated by the dicing tool can cause damage to the edges of the chips, causing the chips to collapse or break, causing the chips to fail and reducing the reliability of the semiconductor structure.
  • water vapor or other gas and liquid easily penetrate from the side, causing erosion and damage to the chip, resulting in chip failure, and further reducing the reliability of the semiconductor structure.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which are used to improve the reliability of the semiconductor structure.
  • the present application provides a method of fabricating a semiconductor structure, comprising: providing a substrate; forming an intermediate layer on the substrate, in which an I-shaped member and a wall-shaped member are formed ; wherein, the top surface of the wall-shaped member is not lower than the top surface of the I-shaped member, and the bottom surface of the wall-shaped member is not higher than the bottom surface of the I-shaped member.
  • the present application also provides a semiconductor structure, comprising a substrate, an intermediate layer on the substrate; an I-shaped member and a wall-shaped member, located in the intermediate layer; wherein, the The top surface of the wall-shaped member is not lower than the top surface of the I-shaped member, and the bottom surface of the wall-shaped member is not higher than the bottom surface of the I-shaped member.
  • the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, wherein the top surface of the wall-shaped member is not lower than the top surface of the I-shaped member, and the bottom surface of the wall-shaped member is not higher than the bottom surface of the I-shaped member; the wall-shaped member It is located on the side of the I-shaped member, and the height of the wall-shaped member is greater than or equal to the height of the I-shaped member, which can reduce or block the transfer of stress from the side to the I-shaped member, or the gas and liquid erode the I-shaped member from the side, thereby avoiding the I-shaped member. failure, thereby improving the reliability of the semiconductor structure.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure in an embodiment of the present application
  • FIG. 2 is a schematic structural diagram after forming a first through hole and a second through hole in an embodiment of the present application
  • Fig. 3 is the flow chart that the upper part and the middle part of the I-shaped member and the wall-shaped member are formed in the same step in the embodiment of the application;
  • FIG. 4 is a schematic structural diagram after forming a first dielectric layer in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram after forming a third opening in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram after the bottom of the I-shaped member is formed in the embodiment of the application.
  • FIG. 7 is a schematic structural diagram after forming a second dielectric layer in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram after forming the first initial opening and the second initial opening in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram after forming the first opening and the second opening in an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of the wall-shaped member and the I-shaped member formed in the embodiment of the application;
  • FIG. 11 is a schematic structural diagram after forming a third dielectric layer in an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of the third through hole and the fourth through hole formed in the embodiment of the present application.
  • FIG. 13 is a schematic structural diagram after forming the third contact structure and the fourth contact structure in the embodiment of the present application.
  • FIG. 14 is a schematic structural diagram after forming a conductive layer in an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of forming a first connection line and a second connection line in an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram after forming a protective layer in an embodiment of the present application.
  • the embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, wherein the height of the wall-shaped member is greater than or equal to the height of the I-shaped member, so that the I-shaped member is located inside the wall-shaped member, thereby reducing or avoiding the expansion of stress from the side to the I-shaped member.
  • the I-shaped member can be eroded by gas and liquid from the side, so as to reduce or avoid the failure of the I-shaped member, thereby improving the reliability of the semiconductor structure.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure in an embodiment of the present application.
  • the manufacturing method specifically includes the following steps:
  • a first contact structure 13 and a second contact structure 14 may be formed in the substrate 10 .
  • the surfaces of the first contact structure 13 and the second contact structure 14 may be provided with a second barrier layer 15 .
  • the side surfaces and the bottom surfaces of the first contact structure 13 and the second contact structure 14 are provided with a second barrier layer 15 for preventing the material of the first contact structure 13 and the second contact structure 14 from diffusing to the substrate In 10, the material of the second barrier layer 15 may be titanium (Ti) or titanium nitride (TiN) or the like.
  • the substrate 10 can be fabricated by the following methods:
  • a silicon wafer is provided, and a dielectric layer is formed on the silicon wafer.
  • the material of the dielectric layer includes silicon dioxide, silicon nitride, silicon oxynitride or polysilicon and other materials required for common semiconductor fabrication processes, or any combination thereof.
  • a second barrier layer 15 and a conductive material are respectively formed in the first through hole 11 and the second through hole 12 to form the first contact structure 13 and the second contact structure 14 as shown in FIG. 3 .
  • an intermediate layer is formed on the substrate, and an I-shaped member and a wall-shaped member are formed in the intermediate layer; wherein, the top surface of the wall-shaped member is not lower than the top surface of the I-shaped member, and the bottom surface of the wall-shaped member is not higher than The bottom surface of the I-shaped member.
  • the intermediate layer 20 may include a first dielectric layer 21 and a second dielectric layer 24
  • the I-shaped member 30 may include an upper portion, a middle portion and a bottom portion
  • the upper portion 33 of the I-shaped member and the middle portion 32 of the I-shaped member are located in the first In the two dielectric layers 24, the bottom 31 of the I-shaped member is located in the first dielectric layer 21, and the wall-shaped member 40 is located in the first dielectric layer and the second dielectric layer.
  • the wall-like member 40 is integrally formed. It will be appreciated that the integrally formed wall member 40 may be completed in one process step. Specifically, openings may be formed in the intermediate layer, and the wall-like members 40 may be formed in the openings through one deposition process or one electroplating process.
  • the material of the wall-shaped member 40 includes conductive materials such as copper, cobalt, and tungsten.
  • the integrally formed wall-shaped member 40 is not prone to interlayer separation, that is, the integrally formed wall-shaped member 40 has a more stable structure, which can avoid separation between parts, so that the wall-shaped member 40 can block gas-liquid or other gas-liquid The capability is improved, which in turn results in improved reliability of the semiconductor structure.
  • the upper portion 33 of the I-shaped member and the middle portion 32 of the I-shaped member are formed in the same step as the wall member 40, that is, the upper portion 33 of the I-shaped member and the middle portion 32 of the I-shaped member are completed in one process step, and It is formed at the same time as the wall-shaped member 40, so that the process steps can be simplified and the process cost can be reduced.
  • the upper portion 33 of the I-shaped member and the middle portion 32 of the I-shaped member and the wall-shaped member 40 are formed in the same step, which specifically includes the following steps:
  • a first dielectric layer 21 is formed on the substrate 10, and the first dielectric layer 21 may be chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) or Physical Vapor Deposition (Physical Vapor Deposition, referred to as PVD) etc. formed by deposition process. As shown in FIG. 4 , the first dielectric layer 21 may cover the first contact structure 13 and the second contact structure 14 .
  • the material of the first dielectric layer 21 includes, but is not limited to, any one or any combination of materials such as silicon oxide, silicon nitride, silicon oxynitride, and Low-K.
  • the bottom 31 of the I-shaped member is formed in the first dielectric layer 21 .
  • the third opening 22 is formed in the first dielectric layer 21, for example, the third opening 22 is formed in the first dielectric layer 21 by photolithography and etching, and the third opening 22 is formed in the first dielectric layer 21 by deposition or electroplating. The process fills the third opening 22 with metallic material to form the bottom 31 of the I-shaped member.
  • the third opening 22 may be formed by dry etching, for example, by plasma etching. As shown in FIG. 5 , the third opening 22 exposes the first contact structure 13 , and the bottom 31 of the I-shaped member is formed in the third opening 22 . As shown in FIG. 6 , the bottom 31 of the I-shaped member is connected to the first contact structure 13 , so that the bottom 31 of the I-shaped member is connected to the first contact structure 13 .
  • the material of the bottom 31 of the I-shaped member may be metal materials such as tungsten, cobalt, aluminum, copper, aluminum alloy, or copper alloy.
  • metal materials such as tungsten, cobalt, aluminum, copper, aluminum alloy, or copper alloy.
  • copper can be formed through an electrochemical plating (ECP) process, so that the copper is filled in the third opening 22 to form the bottom 31 of the I-shaped member.
  • ECP electrochemical plating
  • the surfaces of the first dielectric layer 21 and the bottom portion 31 of the I-shaped member may be planarized.
  • the upper surfaces of the first dielectric layer 21 and the bottom 31 of the I-shaped member are polished by a chemical mechanical polishing process, that is, the upper surface of the structure shown in FIG. 6 is polished to improve its flatness, The quality of the other layers formed on the first dielectric layer 21 and the bottom 31 of the I-shaped member is guaranteed.
  • a second dielectric layer 24 is formed on the first dielectric layer 21 and the bottom 31 of the I-shaped member. 7 , the second dielectric layer 24 may be formed by a deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).
  • the material of the second dielectric layer 24 includes but is not limited to silicon oxide, silicon nitride, and silicon oxynitride. , any one or any combination of materials such as Low-K.
  • the material of the first dielectric layer 21 and the material of the second dielectric layer 22 are the same. Such an arrangement can simplify the subsequent process steps of forming the first opening 27 and the second opening 28, and reduce the manufacturing difficulty and manufacturing cost.
  • a first opening 27 and a second opening 28 are respectively formed in the second dielectric layer 24, wherein the first opening 27 exposes the bottom 31 of the I-shaped member, and the second opening 28 penetrates the second dielectric layer 24 and extend into the first dielectric layer 21, as shown in FIG. 8 .
  • a first photoresist layer with a first pattern and a second pattern can be formed on the second dielectric layer 24; the first initial opening 25 is formed by etching the second dielectric layer 24 with the first pattern and the second pattern, respectively. and the second initial opening 26; wherein, the opening size of the first initial opening 25 may be smaller than the opening size of the second initial opening 26; the first photoresist layer is removed; after the first initial opening 25 and the second initial opening 26 are formed
  • a second photoresist layer with a third pattern is formed on the second dielectric layer 24, the third pattern exposes the first initial opening 25 and part of the second dielectric layer 24, and the fourth pattern exposes the second initial opening 26, that is, the third The opening size of the pattern is larger than the opening size of the first initial opening 25 .
  • a second photoresist layer is formed on the second dielectric layer 24 by a spin coating process, the second photoresist layer fills the first initial opening 25 and the second initial opening 26, and the first initial opening 25 is removed by exposure and development and the photoresist layer in the second initial opening 26 and at the same time, a third pattern and a fourth pattern are respectively formed above the first initial opening 25 and the second initial opening 26, and the opening size of the third pattern is larger than that of the first initial opening 25 and the third pattern exposes the first initial opening 25 and part of the second dielectric layer 24, the fourth pattern exposes the second initial opening 26 and the opening size of the fourth pattern is equal to the opening size of the second initial opening 26; using the third The pattern and the fourth pattern etch the second dielectric layer 24 and the first dielectric layer 21 respectively to form the first opening 27 and the second opening 28.
  • the periphery of the first initial opening 25 can be simultaneously etched by a dry etching process.
  • the second dielectric layer 24 and the first dielectric layer 21 at the bottom of the second initial opening 26 form a first opening 27 and a second opening 28, respectively.
  • the first opening 27 may have a T-shaped structure, the first opening 27 exposes the bottom 31 of the I-shaped member, and the first opening 27 is used to form the middle portion of the I-shaped member in contact with the bottom 31 of the I-shaped member 32 and the upper portion 33 of the I-shaped member; the second opening 28 penetrates the second dielectric layer 24 and the first dielectric layer 21 , and the second opening 28 is used to form the wall-shaped member 40 .
  • the first opening 27 and the second opening 28 are formed by etching at the same time to form the structure shown in FIG. 9 , so as to reduce the manufacturing steps of the semiconductor structure and improve the efficiency.
  • the middle portion 32 of the I-shaped member and the upper portion 33 of the I-shaped member are formed in the first opening 27
  • the wall-shaped member 40 is formed in the second opening 28 .
  • the first opening 27 and the second opening 28 may be filled with conductive material simultaneously by a deposition process or an electroplating process to form the middle portion 32 of the I-shaped member, the upper portion 33 of the I-shaped member and the wall-shaped member 40, respectively. That is, the first opening 27 is filled with conductive material to form the middle portion 32 of the I-shaped member and the upper portion 33 of the I-shaped member, and the second opening 28 is filled with conductive material to form the wall-shaped member 40 .
  • the substrate 10 includes a chip area and a peripheral area, and the I-shaped member 30 and the wall-shaped member 40 are located in the chip area and the peripheral area, respectively.
  • the wall-shaped member 40 may be a part of a guard ring or seal ring of the chip
  • the I-shaped member 30 may be a conductive interconnect structure in the chip area.
  • the width of the upper portion 33 of the I-shaped member is greater than or equal to the width of the bottom 31 of the I-shaped member, the width of the middle portion 32 of the I-shaped member is the smallest, the upper portion 33 of the I-shaped member, the middle portion 32 of the I-shaped member and the I-shaped member have the smallest width.
  • the bottom 31 of the I-shaped member 30 is formed.
  • the middle portion 32 of the I-shaped member is connected with the bottom portion 31 of the I-shaped member.
  • the middle portion 32 of the I-shaped member is in contact with the bottom portion 31 of the I-shaped member, so that the I-shaped member 30 is connected to the first contact structure 13 .
  • the wall-shaped member 40 can be connected with the second contact structure 14, so that the wall-shaped member 40 is connected with the second contact structure 14 to form a tight protection structure.
  • the cross-sectional shape of the wall-shaped member 40 may be rectangular, and the width of the wall-shaped member 40 is greater than the width of the middle portion 32 of the I-shaped member.
  • the manufacturing difficulty of the opening 27 and the second opening 28 improves the manufacturing quality of the first opening 27 and the second opening 28 .
  • the width of the wall-shaped member 40 can be consistent up and down, that is, the wall thickness of the wall-shaped member 40 is the same, and is larger than the width of the middle portion 32 of the I-shaped member, which can further improve the protection performance of the I-shaped member 30 and improve the reliability of the semiconductor structure. .
  • the wall-shaped member 40 surrounds the I-shaped member 30, and the height of the wall-shaped member 40 is greater than or equal to the height of the I-shaped member 30, where the height of the wall-shaped member 40 can be understood as the wall-shaped member 40 along the vertical substrate 10
  • the length in the surface direction; the height of the I-shaped member 30 can be understood as the length of the I-shaped member 30 in the direction perpendicular to the surface of the substrate 10 .
  • the top surface of the wall member 40 may be flush with the top surface of the I-shaped member 30, and the bottom surface of the wall-shaped member 40 is not higher than the bottom surface of the I-shaped member 30, so that the I-shaped member 30 is located in the wall-shaped member 30.
  • the inner side of the member 40 ensures the protection effect of the wall member 40 .
  • the wall member 40 may penetrate through the intermediate layer 20 , and the bottom surface of the wall member 40 may be connected to the second contact structure 14 in the peripheral region, eg, the bottom surface of the wall member 40 is in contact with the top surface of the second contact structure 14 .
  • the bottom surface of the wall-like member 40 completely covers the top surface of the second contact structure 14, ie the orthographic projection of the wall-like member 40 on the substrate 10 covers the orthographic projection of the second contact structure 14 on the substrate 10, so that the wall-like member 40 40 has a larger contact area, which ensures reliable connection between the wall-like member 40 and the second contact structure 14 .
  • the bottom surface of the I-shaped member 30 may be connected to the first contact structure 13 of the chip area, eg, the bottom surface of the I-shaped member 30 is in contact with the top surface of the first contact structure 13 . In this way, conduction between the I-shaped member 30 and the first contact structure 13 can be achieved.
  • the bottom surface of the I-shaped member 30 covers the top surface of the first contact structure 13 , so that the first contact structure 13 and the I-shaped member 30 have a larger contact area and ensure the first contact structure 13 Reliable connection with I-shaped member 30.
  • the width of the middle part 32 of the I-shaped member is the smallest, and the width of the upper part 33 of the I-shaped member is greater than or equal to the width of the bottom 31 of the I-shaped member, so that the upper part 33 of the I-shaped member has a larger contact area, so that when the I-shaped member 30 When other connecting parts are arranged on the upper part, the reliable connection between the I-shaped member and other connecting parts is ensured.
  • the wall-shaped member 40 and the I-shaped member 30 can be made of metal materials.
  • a first barrier layer may be provided, which may be a titanium layer or a titanium nitride (TiN) layer.
  • the second dielectric layer 24 the wall-shaped member 40 and the I-shaped member 30 may be planarized, for example, the upper surface of the structure shown in FIG. 10 may be subjected to a CMP process. Flattening.
  • the method for manufacturing the semiconductor structure before the step of forming the second dielectric layer 24 on the first dielectric layer 21, the method for manufacturing the semiconductor structure further includes: forming a first etch stop layer 23 on the first dielectric layer 21, The etch stop layer 23 covers the bottom 31 of the I-shaped member.
  • the first etch stop layer 23 may be a silicon nitride layer, and the second dielectric layer 24 is formed on the first etch stop layer 23 .
  • the manufacturing method of the semiconductor structure further includes the following steps:
  • a third dielectric layer 50 is formed on the intermediate layer 20 , and a third contact structure 51 and a fourth contact structure 52 are formed in the third dielectric layer 50 penetrating the third dielectric layer 50 , wherein the third contact structure 51 and the I-shaped member are formed
  • the upper part 33 is connected to the fourth contact structure 52
  • the fourth contact structure 52 is connected to the wall member 40
  • the fourth contact structure 52 surrounds the third contact structure 51 .
  • a second etch stop layer 60 is further formed between the intermediate layer 20 and the third dielectric layer 50 .
  • a second etch stop layer 60 is first deposited on the intermediate layer 20, and the second etch stop layer 60 covers the wall-shaped member 40 and the I-shaped member 30; and then the second etch stop layer is formed on the second etch stop layer.
  • a third dielectric layer 50 is formed by depositing on top of 60 . As shown in FIG. 11 , the intermediate layer 20 , the second etch stop layer 60 and the third dielectric layer 50 are arranged from bottom to top.
  • the material of the second etch stop layer 60 may be silicon nitride, and the material of the third dielectric layer 50 may be silicon oxide.
  • the second etch stop layer 60 and the third dielectric layer 50 are etched to form a third through hole 54 extending to the I-shaped member 30 and a fourth through hole 55 extending to the wall-shaped member 40 12 , the I-shaped member 30 is exposed in the third through hole 54 , and the wall-shaped member 40 is exposed in the fourth through hole 55 . That is, the third through holes 54 and the fourth through holes 55 penetrate through the second etch stop layer 60 and the third dielectric layer 50 .
  • a conductive material is deposited in the third through hole 54 and the fourth through hole 55 to form the third contact structure 51 and the fourth contact structure 52 respectively, as shown in FIG. 13 .
  • the third contact structure 51 is connected with the I-shaped member 30
  • the fourth contact structure 52 is connected with the wall-shaped member 40 .
  • the material of the third contact structure 51 and the fourth contact structure 52 can be tungsten or tungsten alloy, and a third barrier layer 53 is also formed on the side surface and the bottom surface of the third contact structure 51 and the fourth contact structure 52 , so as to prevent diffusion into the third dielectric layer 50 .
  • a third barrier layer 53 is first deposited on the inner surfaces of the third through hole 54 and the fourth through hole 55, the third barrier layer 53 formed has a second middle hole, and then a conductive material is deposited in the second middle hole , a third contact structure 51 corresponding to the I-shaped member 30 and a fourth contact structure 52 corresponding to the wall-shaped member 40 are formed.
  • the manufacturing method of the semiconductor structure further includes the following steps:
  • a conductive layer is formed on the third dielectric layer 50 .
  • the conductive layer includes a fourth barrier layer 71 , a metal layer 72 and a fifth barrier layer 73 , and the fourth barrier layer 71 and the metal layer 72 may be sequentially formed on the third dielectric layer 50 by deposition. and the fifth barrier layer 73 .
  • the material of the fourth barrier layer 71 and the fifth barrier layer 73 may be titanium or titanium nitride, and the material of the metal layer 72 may be aluminum or aluminum alloy.
  • the remaining conductive layer corresponding to the third contact structure 51 forms the first connection line 74
  • the remaining conductive layer corresponding to the fourth contact structure 52 forms the second connection line 75, such as As shown in FIG. 15 , there is a space between the first connection line 74 and the second connection line 75 .
  • the first connection 74 is connected to the third contact structure 51, and the second connection 75 is connected to the fourth contact structure 52.
  • the first connection 74 is in contact with the third contact structure 51
  • the second connection 75 is in contact with the third contact structure 51. contact with the fourth contact structure 52 .
  • a protective layer 80 is formed on the third dielectric layer 50 , and the protective layer 80 covers the first wiring 74 and the second wiring 75 , as shown in FIG. 16 .
  • a silicon oxide layer 81 is deposited on the third dielectric layer 50, and the silicon oxide layer 81 covers the first wiring 74 and the second wiring 75; and then a silicon nitride layer 82 is formed on the silicon oxide layer 81 by depositing , the protective layer 80 composed of the silicon oxide layer 81 and the silicon nitride layer 82 is used to prevent the first wiring 74 and the second wiring 75 from being damaged.
  • the semiconductor structure in the embodiment of the present application includes a substrate 10 , an intermediate layer 20 on the substrate 10 , an I-shaped member 30 and a wall member 40 located in the intermediate layer 20 .
  • the top surface of the wall-shaped member 40 is not lower than the top surface of the I-shaped member 30
  • the bottom surface of the wall-shaped member 40 is not higher than the surface of the I-shaped member 30 .
  • the top surface of the wall member 40 is flush with the top surface of the I-shaped member 30 .
  • the upper portion 33 of the I-shaped member and the middle portion 33 of the I-shaped member are integrally formed, and the wall-shaped member 40 is integrally formed.
  • the intermediate layer 20 includes a first dielectric layer 21 and a second dielectric layer 24; the upper part 33 of the I-shaped member and the middle part 32 of the I-shaped member are located in the second dielectric layer 24, and the lower part 31 of the I-shaped member is located in the first dielectric layer 24.
  • the wall-like members 40 are located in the second dielectric layer 24 and the first dielectric layer 21 .
  • the width of the wall member 40 is greater than the width of the middle portion 32 of the I-shaped member.
  • the width of the wall-shaped member 40 is equal to the width of the upper portion 33 of the I-shaped member; the width of the upper portion 33 of the I-shaped member is not less than the width of the bottom portion 31 of the I-shaped member.
  • the upper portion 33 of the I-shaped member and the middle portion 32 of the I-shaped member are formed in the same step as the wall member 40 .
  • the substrate 10 includes a chip area and a peripheral area, and the I-shaped member 30 and the wall-shaped member 40 are located in the chip area and the peripheral area, respectively.
  • the first contact structure 13 is provided in the chip area, and the second contact structure 14 is provided in the peripheral area.
  • the first contact structure 13 and the second contact structure 14 are not communicated with each other, and the second contact structure 14 may surround the first contact structure 13 for a circle to protect the first contact structure 13 .
  • the second contact structure 14 is annular.
  • the second contact structure 14 can be a circular ring, an elliptical ring, a square ring or other polygonal rings.
  • the first contact structure 13 is located in the ring, for example, the first contact structure 13 is located at the center of the ring.
  • the material of the first contact structure 13 and the second contact structure 14 may be tungsten or a tungsten alloy. In the embodiment of the present application, the first contact structure 13 and the second contact structure 14 are both tungsten. In order to prevent the first and second contact structures 13 and 14 from diffusing into the substrate 10 , the side and bottom surfaces of the first and second contact structures 13 and 14 are provided with second barrier layers 15 .
  • the material of the second barrier layer 15 may be titanium or titanium nitride.
  • the I-shaped member 30 may be located on the chip area, and the bottom surface of the I-shaped member 30 is connected with the top surface of the first contact structure 13 to make the I-shaped member 30 conduct with the first contact structure 13 .
  • the material of the I-shaped member 30 may be copper or copper alloy.
  • the I-shaped member 30 includes a bottom, a middle portion and an upper portion, the bottom 31 of the I-shaped member is directly connected with the first contact structure 13, and the middle portion 32 of the I-shaped member is respectively connected with the bottom 31 of the I-shaped member and the upper portion 33 of the I-shaped member.
  • the width of the middle part 32 of the I-shaped member is smaller than the width of the bottom 31 of the I-shaped member and the width of the upper part 33 of the I-shaped member, and the width of the upper part 33 of the I-shaped member is not less than the width of the bottom 31 of the I-shaped member, so that the width of the I-shaped member is
  • the bottom 31 and the upper portion 33 of the I-shaped member have a larger contact area.
  • the upper portion 33 and the middle portion of the I-shaped member may be integrally formed, for example, by a Damascus process.
  • the wall member 40 may be part of a guard ring or seal ring of the chip and located on the peripheral region, and the bottom surface of the wall member 40 is connected to the top surface of the second contact structure 14 so that the wall member 40 is connected to the top surface of the second contact structure 14. 40 is connected to the second contact structure 14 .
  • the wall-shaped member 40 can surround the I-shaped member 30, the top surface of the wall-shaped member 40 is not lower than the top surface of the I-shaped member 30, and the bottom surface of the wall-shaped member 40 is not higher than the bottom surface of the I-shaped member 30.
  • This application implements
  • the bottom surface of the wall member 40 may be flush with the bottom surface of the I-shaped member 30 .
  • the wall-shaped member 40 can surround the I-shaped member 30, and along the direction from the substrate 10 to the intermediate layer 20, the height of the wall-shaped member 40 is greater than or equal to the height of the I-shaped member 30, so that the I-shaped member 30 is located in the wall shape member 40.
  • the cross-sectional shape of the wall member 40 may be rectangular, and the width of the wall member 40 may be greater than the width of the middle portion 32 of the I-shaped member, eg, the width of the wall member 40 is equal to the width of the upper portion 33 of the I-shaped member.
  • the wall-shaped member 40 can be integrally formed to avoid delamination, thereby avoiding interlayer separation of the wall-shaped member 40 , and has a relatively stable structure, which can improve the protection performance of the I-shaped member 30 .
  • the wall-shaped member 40 , the middle portion 32 of the I-shaped member, and the upper portion 33 of the common member are formed at the same time.
  • a third dielectric layer 50 is further formed on the intermediate layer 20 , and a third contact structure 51 and a fourth contact structure 52 are formed in the third dielectric layer 50 .
  • the third contact structure 51 and the fourth contact structure 52 penetrate through the third dielectric layer 50 , and the third contact structure 51 and the fourth contact structure 52 are not conductive with each other.
  • the fourth contact structure 52 may be disposed around the third contact structure 51, the third contact structure 51 is in conduction with the I-shaped member 30, the fourth contact structure 52 is in conduction with the wall member 40, the third contact structure 51 and the fourth contact structure
  • the material of 52 can be tungsten or tungsten alloy.
  • the third barrier layer 53 may be provided outside part of the surfaces of the third contact structure 51 and the fourth contact structure 52 .
  • a second etch stop layer 60 may also be disposed between the second dielectric layer 50 and the intermediate layer 20, and the third contact structure 51, the fourth contact structure 52 and the third barrier layer 53 may penetrate through the second etch stop layer 60, In order to facilitate the connection with the wall member 40 and the I-shaped member 30 .
  • the semiconductor structure further includes a protective layer 80 on the third dielectric layer 50 , the protective layer 80 includes a silicon oxide layer 81 and a silicon nitride layer 82 , wherein the silicon oxide layer 81 is disposed on the third dielectric layer 50 , the silicon nitride layer 82 is disposed on the silicon oxide layer 81 .
  • the silicon oxide layer 81 is provided with a first connection 74 and a first connection 74, the first connection 74 corresponds to the third contact structure 51, the second connection 75 corresponds to the fourth contact structure 52, and the first connection 74 corresponds to the third contact structure 51.
  • the connection line 74 and the second connection line 75 are arranged at intervals.
  • the regions of the protective layer 80 corresponding to the first connection lines 74 and the first connection lines 74 respectively protrude in a direction away from the third dielectric layer 50 .
  • the first wiring 74 and the second wiring 75 each include a fourth barrier layer 71 , a metal layer 72 and a fifth barrier layer 73 .
  • the fourth barrier layer 71 is located on the third dielectric layer 50
  • the metal layer 72 is located on the fourth barrier layer 71
  • the fifth barrier layer 73 is located on the metal layer 72 .
  • the fourth barrier layer 71 is in contact with the third contact structure 51 and the third contact structure 51 , respectively.
  • the material of the metal layer 72 may be aluminum or aluminum alloy, and the material of the fourth barrier layer 71 and the fifth barrier layer 73 may be titanium or titanium nitride.
  • the semiconductor structure in the embodiment of the present application includes a substrate 10 and an intermediate layer 20 located on the substrate 10.
  • the intermediate layer 20 is formed with an I-shaped member 30 and a wall-shaped member 40, and the top surface of the wall-shaped member 40 is not lower than the I-shaped member 40.
  • the top surface of the I-shaped member 30, the bottom surface of the wall-shaped member 40 is not higher than the bottom surface of the I-shaped member 30; the wall-shaped member 40 can reduce or prevent the stress from being transmitted to the I-shaped member 30 from the side, or the gas and liquid are eroded from the side. I-shaped member 30, thereby improving the reliability of the semiconductor structure.
  • references to the terms “one embodiment,” “some embodiments,” “illustrative embodiments,” “examples,” “specific examples,” or “some examples” and the like are meant to incorporate embodiments A particular feature, structure, material, or characteristic described or exemplified is included in at least one embodiment or example of the present application.
  • schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

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Abstract

本申请实施例提供一种半导体结构及其制造方法，该半导体结构的制造方法包括：提供衬底；在衬底上形成中间层，中间层中形成有工形构件和壁状构件；其中，壁状构件的顶表面不低于工形构件的顶表面，壁状构件的底表面不高于工形构件的底表面，通过壁状构件对工形构件进行保护，提高半导体结构的可靠性。

Description

半导体结构及其制造方法
本申请要求于2021年01月19日提交中国专利局、申请号为202110068881.0、申请名称为“半导体结构及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种半导体结构及其制造方法。
背景技术
在半导体制造工艺中，通过光刻、刻蚀、沉积等工艺可以在半导体衬底上形成半导体结构，例如芯片，所形成的芯片通常包括半导体器件以及设置在半导体器件上的互连结构。
半导体衬底上可以形成多个芯片，这些芯片从半导体衬底上切割下来并封装后形成多个独立的芯片。在对这些芯片进行切割的过程中，切割工具产生的应力会对芯片的边缘造成损害，导致芯片发生崩塌或者断裂，使芯片失效，导致半导体结构的可靠性降低。此外，水汽或者其他气液易从侧面渗透，对芯片造成侵蚀、损害，导致芯片失效，进一步降低半导体结构的可靠性。
发明内容
本申请实施例提供一种半导体结构及其制造方法，用于提高半导体结构的可靠性。
根据一些实施例，第一方面，本申请提供一种半导体结构的制造方法，包括：提供衬底；在所述衬底上形成中间层，所述中间层中形成有工形构件和壁状构件；其中，所述壁状构件的顶表面不低于所述工形构件的顶表面，所述壁状构件的底表面不高于所述工形构件的底表面。
根据一些实施例，第二方面，本申请还提供一种半导体结构，包括衬 底，位于所述衬底上的中间层；工形构件和壁状构件，位于所述中间层中；其中，所述壁状构件的顶表面不低于所述工形构件的顶表面，所述壁状构件的底表面不高于所述工形构件的底表面。
本申请实施例提供了一种半导体结构及其制造方法，壁状构件的顶表面不低于工形构件的顶表面，壁状构件的底表面不高于工形构件的底表面；壁状构件位于工形构件的侧面，且壁状构件的高度大于或者等于工形构件的高度，可以减轻或者阻挡应力从侧面传递到工形构件，或者气液从侧面侵蚀工形构件，从而避免工形构件失效，进而提高半导体结构的可靠性。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的半导体结构及其制造方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
图1为本申请实施例中的半导体结构的制造方法的流程图；
图2为本申请实施例中形成第一通孔和第二通孔后的结构示意图；
图3为本申请实施例中的工形构件的上部和中部与壁状构件在同一步骤中形成的流程图；
图4为本申请实施例中形成第一介质层后的结构示意图；
图5为本申请实施例中形成第三开口后的结构示意图；
图6为本申请实施例中形成工形构件的底部后的结构示意图；
图7为本申请实施例中形成第二介质层后的结构示意图；
图8为本申请实施例中形成第一初始开口和第二初始开口后的结构示意图；
图9为本申请实施例中形成第一开口和第二开口后的结构示意图；
图10为本申请实施例中形成壁状构件和工形构件后的结构示意图；
图11为本申请实施例中形成第三介质层后的结构示意图；
图12为本申请实施例中形成第三通孔和第四通孔后的结构示意图；
图13为本申请实施例中形成第三接触结构和第四接触结构后的结构示意图；
图14为本申请实施例中形成导电层后的结构示意图；
图15为本申请实施例中形成第一连线和第二连线后的结构示意图；
图16为本申请实施例中形成保护层后的结构示意图。
具体实施方式
本申请实施例中提供了一种半导体结构及其制造方法，壁状构件的高度大于或者等于工形构件的高度，使工形构件位于壁状构件内部，从而减少或者避免应力从侧面扩展到工形构件，或者气液从侧面侵蚀到工形构件，以减少或者避免工形构件失效，进而提高半导体结构的可靠性。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参照图1，图1为本申请实施例中的半导体结构的制造方法的流程图，该制造方法具体包括以下步骤：
S101、提供衬底。
参照图2和图3，衬底10中可以形成有第一接触结构13以及第二接触结构14。第一接触结构13和第二接触结构14之间具有间隔，第一接触结构13和第二接触结构14可以与有源区连接，即第一接触结构13和第二接触结构14连通有源区，其材质可以均为导电材质，例如金属钨(W)。
需要说明的是，第一接触结构13和第二接触结构14的表面可以设置有第二阻挡层15。示例性的，第一接触结构13和第二接触结构14的侧表面和底表面均设置有第二阻挡层15，用于防止第一接触结构13和第二接触结构14的材质扩散到衬底10中，第二阻挡层15的材质可以为钛(Ti)或者氮化钛(TiN)等。
在一些可能的实施例中，衬底10可以采用如下方法制作：
提供硅晶圆，在硅晶圆上形成介质层，介质层的材料包括二氧化硅、氮化硅、氮氧化硅或多晶硅等常用半导体制作工艺所需材料中的任一种或其任意组合。
然后对介质层进行光刻、刻蚀等工艺，在介质层中形成第一通孔11和第二通孔12，形成图2中所示的具有第一通孔11和第二通孔12的衬底10。
再在第一通孔11和第二通孔12内分别形成第二阻挡层15和导电材料，形成如图3所示的第一接触结构13和第二接触结构14。
S102、在衬底上形成中间层，中间层中形成有工形构件和壁状构件；其中，壁状构件的顶表面不低于工形构件的顶表面，壁状构件的底表面不高于工形构件的底表面。
如图10所示，中间层20可以包括第一介质层21和第二介质层24，工形构件30可以包括上部、中部以及底部，工形构件的上部33和工形构件的中部32位于第二介质层24中，工形构件的底部31位于第一介质层21中，壁状构件40位于第一介质层和第二介质层中。
可选的，壁状构件40一体成型。可以理解的是，一体成型的壁状构件40可以在一步工艺步骤中完成。具体的，可以在中间层中形成开口，通过一次沉积工艺或一次电镀工艺在开口中形成壁状构件40。壁状构件40的材质包括铜、钴、钨等导电材料。一体成型的壁状构件40不易发生层间分离，即一体成型的壁状构件40具有更稳固的结构，可以避免各部分之间产生分离，使得壁状构件40对气液或者其他气液的阻挡能力提高，进而使得半导体结构的可靠性提高。
可选的，工形构件的上部33和工形构件的中部32与壁状构件40在同一步骤中形成，即工形构件的上部33和工形构件的中部32在一步工艺步骤中完成，且与壁状构件40同时形成，如此可以简化工艺步骤，降低工艺成本。
可选的，工形构件的上部33和工形构件的中部32与壁状构件40在同一步骤中形成，具体包括以下步骤：
参照图4至图10，在衬底10上形成第一介质层21，第一介质层21可以采用化学气相沉积(Chemical Vapor Deposition，简称CVD)或者物理气相沉积(Physical Vapor Deposition，简称PVD)等沉积工艺形成。如图4所示，第一介质层21可以覆盖第一接触结构13和第二接触结构14。第一介质层21的材料包括但不限于氧化硅，氮化硅，氮氧化硅，Low-K等材质中的任一种或其任意组合。
形成第一介质层21后，在第一介质层21中形成工形构件的底部31。具体的，如图5和图6所示，在第一介质层21中形成第三开口22，例如通过光刻以及刻蚀工艺在第一介质层21中形成第三开口22，通过沉积或电镀工艺在第三开口22中填充金属材料形成工形构件的底部31。
具体的，第三开口22可以通过干法刻蚀形成，例如，通过等离子体刻蚀形成。如图5所示，第三开口22暴露第一接触结构13，在第三开口22中形成工形构件的底部31。如图6所示，工形构件的底部31与第一接触结构13连接，以使工形构件的底部31与第一接触结构13导通。
工形构件的底部31的材质可以为钨、钴、铝、铜、铝合金或铜合金等金属材料。示例性的，当工形构件的底部31的材质为铜时，可以通过电化学镀(ECP)工艺形成铜，使得铜填充在第三开口22中，以形成工形构件的底部31。
需要说明的是，在形成工形构件的底部31后，可以对第一介质层21以及工形构件的底部31的表面进行平坦化处理。例如，通过化学机械研磨工艺，对第一介质层21以及工形构件的底部31的上表面进行磨平，即对图6中所示的结构的上表面进行磨平，以提高其平整度，保证形成在第一介质层21以及工形构件的底部31上的其他层的质量。
形成工形构件的底部31后，在第一介质层21和工形构件的底部31上形成第二介质层24。参照图7，第二介质层24可以采用化学气相沉积(CVD)或者物理气相沉积(PVD)等沉积工艺形成，第二介质层24的材料包括但不限于氧化硅，氮化硅，氮氧化硅，Low-K等材质中的任一种或其任意组合。
可选的，第一介质层21的材质和第二介质层22的材质相同。如此设置可以简化后续形成第一开口27和第二开口28的工艺步骤，降低制作难度以及制作成本。
形成第二介质层24后，在第二介质层24中分别形成第一开口27和第二开口28，其中，第一开口27暴露工形构件的底部31，第二开口28贯穿第二介质层24并延伸至第一介质层中21，如图8所示。
具体的，可以在第二介质层24上形成具有第一图案和第二图案的第一光刻胶层；利用第一图案和第二图案刻蚀第二介质层24分别形成第一初始开口25和第二初始开口26；其中，第一初始开口25的开口尺寸可以小于 第二初始开口26的开口尺寸；去除第一光刻胶层；在形成有第一初始开口25和第二初始开口26的第二介质层24上形成具有第三图案的第二光刻胶层，第三图案暴露第一初始开口25以及部分第二介质层24，第四图案暴露第二初始开口26，即第三图案的开口尺寸大于第一初始开口25的开口尺寸。具体的，利用旋涂工艺在第二介质层24上形成第二光刻胶层，第二光刻胶层填充第一初始开口25和第二初始开口26，通过曝光显影去除第一初始开口25和第二初始开口26中的光刻胶层以及同时在第一初始开口25和第二初始开口26的上方分别形成第三图案和第四图案，第三图案的开口尺寸大于第一初始开口25的开口尺寸且第三图案暴露第一初始开口25及部分第二介质层24，第四图案暴露第二初始开口26且第四图案的开口尺寸等于第二初始开口26的开口尺寸；利用第三图案和第四图案同时分别刻蚀第二介质层24和第一介质层21形成第一开口27以及第二开口28，具体的，可以利用干法刻蚀工艺同时刻蚀第一初始开口25周边的第二介质层24和第二初始开口26底部的第一介质层21分别形成第一开口27和第二开口28。
如图9所示，第一开口27可以具有T形结构，第一开口27暴露工形构件的底部31，第一开口27用于形成与工形构件的底部31相接触的工形构件的中部32和工形构件的上部33；第二开口28贯穿第二介质层24和第一介质层21，第二开口28用于形成壁状构件40。第一开口27和第二开口28同时通过刻蚀成型，形成图9所示的结构，以减少半导体结构的制造步骤，提高效率。
形成第一开口27和第二开口28后，在第一开口27中形成工形构件的中部32和工形构件的上部33，同时在第二开口28中形成壁状构件40。具体的，可以采用沉积工艺或电镀工艺同时在第一开口27和第二开口28中填充导电材料分别形成工形构件的中部32和工形构件的上部33以及壁状构件40。即在第一开口27中充导电材料形成工形构件的中部32和工形构件的上部33，在第二开口28中填充导电材料形成壁状构件40。
可选的，衬底10包括芯片区和外围区，工形构件30和壁状构件40分别位于芯片区和外围区。具体的，壁状构件40可以为芯片的保护环状壁(guard ring or seal ring)的一部分，工形构件30可以为芯片区中的导电互连结构。具体的，工形构件的上部33的宽度大于或者等于工形构件的底部 31的宽度，工形构件的中部32的宽度最小，工形构件的上部33、工形构件的中部32和工形构件的底部31构成工形构件30。工形构件的中部32与工形构件的底部31相连接，例如，工形构件的中部32与工形构件的底部31接触，从而使得工形构件30与第一接触结构13相导通。
壁状构件40可以与第二接触结构14相连接，以使壁状构件40与第二接触结构14连接，组成严密的保护结构。壁状构件40的截面形状可以为矩形，壁状构件40的宽度大于工形构件的中部32的宽度，例如，壁状构件40的宽度可以等于工形构件的上部33的宽度，可以简化第一开口27和第二开口28的制作难度，提高第一开口27和第二开口28的制作质量。壁状构件40的宽度可以上下一致，即壁状构件40的壁厚一致，且大于工形构件的中部32的宽度，可以进一步提高对工形构件30的保护性能，以提高半导体结构的可靠性。
可选的，壁状构件40环绕工形构件30，壁状构件40的高度大于或者等于工形构件30的高度，此处壁状构件40的高度可以理解为壁状构件40沿垂直衬底10表面方向上的长度；工形构件30的高度可以理解为工形构件30沿垂直衬底10表面方向上的长度。示例性的，壁状构件40的顶表面可以与工形构件30的顶表面齐平，壁状构件40的底表面不高于工形构件30的底表面，以使工形构件30位于壁状构件40的内侧，保证壁状构件40的保护效果。
壁状构件40可以贯穿中间层20，壁状构件40的底表面可以与外围区的第二接触结构14相连，例如，壁状构件40的底表面与第二接触结构14的顶表面相接触。壁状构件40的底表面完全覆盖第二接触结构14的顶表面，即壁状构件40在衬底10上的正投影覆盖第二接触结构14在衬底10上的正投影，使得壁状构件40具有较大的接触面积，保证壁状构件40与第二接触结构14之间的可靠连接。
工形构件30的底表面可以与芯片区的第一接触结构13相连，例如，工形构件30的底表面与第一接触结构13的顶表面相接触。如此设置，工形构件30与第一接触结构13之间可以导通。本申请实施例中，工形构件30的底表面覆盖第一接触结构13的顶表面，以使得第一接触结构13与工形构件30之间具有较大的接触面积，保证第一接触结构13与工形构件30之间的可靠连接。
工形构件的中部32的宽度最小，工形构件的上部33的宽度大于或者等于工形构件的底部31的宽度，使得工形构件的上部33具有较大的接触面积，从而当工形构件30上设置有其他连接件时，保证工形构件与其他连接件之间的可靠连接。
需要说明的是，壁状构件40与工形构件30可以为金属材质，为防止壁状构件40与工形构件30向周围扩散，壁状构件40与工形构件30的侧表面和底表面均可以设置有第一阻挡层，第一阻挡层可以为钛层或者氮化钛(TiN)层。形成壁状构件40和工形构件30后，可以对第二介质层24、壁状构件40和工形构件30进行平坦化处理，例如，对图10所示的结构的上表面通过CMP工艺进行平坦化处理。
本申请实施例中，在第一介质层21上形成第二介质层24的步骤之前，半导体结构的制造方法还包括：在第一介质层21上形成第一刻蚀停止层23，第一刻蚀停止层23覆盖工形构件的底部31。第一刻蚀停止层23可以为氮化硅层，第二介质层24形成在第一刻蚀停止层23上。
本申请实施例中，在形成中间层20之后，半导体结构的制造方法还包括以下步骤：
在中间层20上形成第三介质层50，第三介质层50中形成有贯穿第三介质层50的第三接触结构51和第四接触结构52，其中，第三接触结构51与工形构件的上部33相连，第四接触结构52与壁状构件40相连，第四接触结构52围绕第三接触结构51。
为防止形成第三接触结构51和第四接触结构52时损伤中间层20，中间层20与第三介质层50之间还形成有第二刻蚀停止层60。
在一种可能的示例中，先在中间层20上沉积形成第二刻蚀停止层60，第二刻蚀停止层60覆盖壁状构件40和工形构件30；再在第二刻蚀停止层60上沉积形成第三介质层50，如图11所示，中间层20、第二刻蚀停止层60和第三介质层50由下至上设置。第二刻蚀停止层60的材质可以为氮化硅，第三介质层50的材质可以为氧化硅。
形成第三介质层50之后，刻蚀第二刻蚀停止层60和第三介质层50，形成延伸至工形构件30的第三通孔54和延伸至壁状构件40的第四通孔55，如图12所示，第三通孔54内暴露有工形构件30，第四通孔55内暴露有壁状构件40。即第三通孔54和第四通孔55贯穿第二刻蚀停止层60 和第三介质层50。
形成第三通孔54和第四通孔55后，分别在第三通孔54和第四通孔55内沉积导电材料形成第三接触结构51和第四接触结构52，如图13所示，第三接触结构51与工形构件30相连，第四接触结构52与壁状构件40相连。
参照图13，第三接触结构51和第四接触结构52的材质可以为钨或者钨合金，第三接触结构51和第四接触结构52的侧表面和底表面上还形成有第三阻挡层53，以防止向第三介质层50中扩散。
示例性的，先在第三通孔54和第四通孔55内表面沉积形成第三阻挡层53，形成的第三阻挡层53具有第二中间孔，然后在第二中间孔内沉积导电材料，形成与工形构件30相对应的第三接触结构51，以及与壁状构件40相对应的第四接触结构52。
本申请实施例中，在中间层20上形成第三介质层50之后，半导体结构的制造方法还包括以下步骤：
在第三介质层50上形成导电层。示例性的，如图14所示，导电层包括第四阻挡层71、金属层72和第五阻挡层73，在第三介质层50上可以通过沉积依次形成第四阻挡层71、金属层72和第五阻挡层73。第四阻挡层71和第五阻挡层73的材质可以为钛或者氮化钛，金属层72的材质可以为铝或者铝合金。
然后，去除部分导电层，保留下来的且与第三接触结构51对应的导电层形成第一连线74，保留下来的且与第四接触结构52对应的导电层形成第二连线75，如图15所示，第一连线74和第二连线75之间具有间隔。
其中，第一连线74与第三接触结构51导通，第二连线75与第四接触结构52导通，例如，第一连线74与第三接触结构51接触，第二连线75与第四接触结构52接触。
最后，在第三介质层50上形成保护层80，保护层80覆盖第一连线74和第二连线75，如图16所示。示例性的，先在第三介质层50上沉积形成氧化硅层81，氧化硅层81覆盖第一连线74和第二连线75；再在氧化硅层81上沉积形成氮化硅层82，氧化硅层81和氮化硅层82构成的保护层80用于防止第一连线74和第二连线75受到损伤。
参照图16，本申请实施例中的半导体结构包括衬底10、位于衬底10 上的中间层20、位于中间层20中的工形构件30和壁状构件40。其中，壁状构件40的顶表面不低于工形构件30的顶表面，壁状构件40的底表面不高于工形构件30的表面。
可选的，壁状构件40的顶表面和工形构件30的顶表面齐平。
可选的，工形构件的上部33和工形构件的中部33一体成型，壁状构件40一体成型。
可选的，中间层20包括第一介质层21和第二介质层24；工形构件的上部33和工形构件的中部32位于第二介质层24中，工形构件的下部31位于第一介质层21中，壁状构件40位于第二介质层24和第一介质层21中。
可选的，壁状构件40的宽度大于工形构件的中部32的宽度。
可选的，壁状构件40的宽度等于工形构件的上部33的宽度；工形构件的上部33的宽度不小于工形构件的底部31的宽度。
可选的，工形构件的上部33和工形构件的中部32与壁状构件40在同一步骤中形成。
可选的，衬底10包括芯片区和外围区，工形构件30和壁状构件40分别位于芯片区和外围区。
具体的，芯片区中设置有第一接触结构13，外围区中设置有第二接触结构14。第一接触结构13和第二接触结构14之间互不连通，第二接触结构14可以围绕第一接触结构13一周，用于保护第一接触结构13。可以理解的是，第二接触结构14呈环状，示例性的，第二接触结构14可以圆环、椭圆环、方环或者其他多边形环状。第一接触结构13位于环内，例如，第一接触结构13位于环心位置处。
第一接触结构13和第二接触结构14的材质可以为钨或者钨合金，本申请实施例中，第一接触结构13和第二接触结构14均为钨。为了防止第一接触结构13和第二接触结构14向衬底10中扩散，第一接触结构13和第二接触结构14的侧表面和底表面设置有第二阻挡层15。第二阻挡层15的材质可以为钛或者氮化钛。
工形构件30可以位于芯片区上，工形构件30的底表面与第一接触结构13的顶表面相连，以使工形构件30与第一接触结构13导通。工形构件30的材质可以为铜或者铜合金。
工形构件30包括底部、中部和上部，工形构件的底部31与第一接触结构13直接相连，工形构件的中部32分别与工形构件的底部31和工形构件的上部33相连。工形构件的中部32的宽度小于工形构件的底部31和工形构件的上部33的宽度，工形构件的上部33的宽度不小于工形构件的底部31的宽度，以使得工形构件的底部31和工形构件的上部33具有较大的接触面积。工形构件的上部33和中部可以一体成型，例如，通过大马士革工艺成型。
壁状构件40可以为芯片的保护环状壁(guard ring or seal ring)的一部分且位于外围区上，壁状构件40的底表面与第二接触结构14的顶表面相连，以使壁状构件40与第二接触结构14相连。壁状构件40可以环绕工形构件30，壁状构件40的顶表面不低于工形构件30的顶表面，壁状构件40的底表面不高于工形构件30的底表面，本申请实施例中，壁状构件40的底表面可以与工形构件30的底表面齐平。如此设置，壁状构件40可以环绕工形构件30，且沿衬底10到中间层20的方向，壁状构件40的高度大于或者等于工形构件30的高度，以使工形构件30位于壁状构件40内。
壁状构件40的截面形状可以为矩形，壁状构件40的宽度可以大于工形构件的中部32的宽度，例如壁状构件40的宽度等于工形构件的上部33的宽度。
壁状构件40可以一体成型，避免分层，进而避免壁状构件40出现层间分离，具有较稳固的结构，可以提高对工形构件30的保护性能。本申请实施例中，壁状构件40、工形构件的中部32和共性构件的上部33同时成型。
继续参照图16，中间层20上还形成有第三介质层50，第三介质层50中形成有第三接触结构51和第四接触结构52。第三接触结构51和第四接触结构52贯穿第三介质层50，且第三接触结构51和第四接触结构52互不导通。第四接触结构52可以围绕第三接触结构51设置，第三接触结构51与工形构件30导通，第四接触结构52与壁状构件40导通，第三接触结构51和第四接触结构52的材质可以为钨或者钨合金。
需要说明的是，第三接触结构51和第四接触结构52的部分表面外可以设置第三阻挡层53，第三阻挡层53可以参照第二阻挡层15设置，在此不再赘述。第二介质层50与中间层20之间还可以设置有第二刻蚀停止层 60，第三接触结构51、第四接触结构52和第三阻挡层53可以贯穿第二刻蚀停止层60，以便于与壁状构件40和工形构件30相连。
继续参照图16，半导体结构还包括位于第三介质层50上的保护层80，保护层80包括氧化硅层81和氮化硅层82，其中，氧化硅层81设置在第三介质层50上，氮化硅层82设置在氧化硅层81上。
氧化硅层81中设置有第一连线74和第一连线74，第一连线74与第三接触结构51相对应，第二连线75与第四接触结构52相对应，且第一连线74和第二连线75间隔设置。保护层80中分别对应第一连线74和第一连线74区域向远离第三介质层50的方向凸出。
第一连线74和第二连线75均包括第四阻挡层71、金属层72和第五阻挡层73。其中，第四阻挡层71位于第三介质层50上，金属层72位于第四阻挡层71上，第五阻挡层73位于金属层72。
继续参照图16，第四阻挡层71分别与第三接触结构51和第三接触结构51相接触。金属层72的材质可以为铝或者铝合金，第四阻挡层71和第五阻挡层73的材质可以为钛或者氮化钛。
本申请实施例中的半导体结构，包括衬底10和位于衬底10上的中间层20，中间层20形成有工形构件30和壁状构件40，壁状构件40的顶表面不低于工形构件30的顶表面，壁状构件40的底表面不高于工形构件30的底表面；通过壁状构件40可以减轻或者阻挡应力从侧面传递到工形构件30，或者气液从侧面侵蚀工形构件30，从而提高半导体结构的可靠性。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
本领域技术人员应理解的是，在本申请的揭露中，术语“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系是基于附图所示的方位或位置关系，其仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的系统或元件必须具有特定的方位、以特定的方位构造和操作，因此上述术语不能理解为对本申请的限制。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描 述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (20)

  1. 一种半导体结构的制造方法，包括：
    提供衬底；
    在所述衬底上形成中间层，所述中间层中形成有工形构件和壁状构件；
    其中，所述壁状构件的顶表面不低于所述工形构件的顶表面，所述壁状构件的底表面不高于所述工形构件的底表面。
  2. 根据权利要求1所述的制造方法，其中，所述壁状构件一体成型。
  3. 根据权利要求1所述的制造方法，其中，所述工形构件的上部和中部与所述壁状构件在同一步骤中形成。
  4. 根据权利要求3所述的制造方法，其中，所述工形构件的上部和中部与所述壁状构件在同一步骤中形成，包括：
    在所述衬底上形成第一介质层；
    在所述第一介质层中形成所述工形构件的底部；
    在所述第一介质层和所述工形构件的底部上形成第二介质层；
    在所述第二介质层中分别形成第一开口和第二开口，其中，所述第一开口暴露所述工形构件的底部，所述第二开口贯穿所述第二介质层并延伸至所述第一介质层中；
    在所述第一开口中形成所述工形构件的中部和上部，同时在所述第二开口中形成所述壁状构件。
  5. 根据权利要求4所述的制造方法，其中，所述在所述第二介质层中分别形成第一开口和第二开口的步骤包括：
    在所述第二介质层上形成具有第一图案和第二图案的第一光刻胶层；
    利用所述第一图案和所述第二图案刻蚀所述第二介质层分别形成第一初始开口和第二初始开口；
    在所述第二介质层上形成具有第三图案和第四图案的第二光刻胶层，所述第三图案暴露所述第一初始开口以及部分所述第二介质层，所述第四图案暴露出所述第二初始开口；
    利用所述第三图案刻蚀部分所述第二介质层形成所述第一开口以及利用所述第四图案刻蚀所述第一介质层形成所述第二开口。
  6. 根据权利要求5所述的制造方法，其中，还包括：
    利用所述第三图案刻蚀部分所述第二介质层形成所述第一开口以及利用所述第二初始开口刻蚀所述第一介质层形成所述第二开口在同一步骤中完成。
  7. 根据权利要求5所述的制造方法，其中，还包括：
    填充导电材料于所述第一开口和所述第二开口中分别形成所述工形构件的上部和中部以及所述壁状构件。
  8. 根据权利要求2所述的制造方法，其中，所述工形构件的上部和中部与所述壁状构件在同一步骤中形成。
  9. 根据权利要求8所述的制造方法，其中，所述工形构件的上部和中部与所述壁状构件在同一步骤中形成，包括：
    在所述衬底上形成第一介质层；
    在所述第一介质层中形成所述工形构件的底部；
    在所述第一介质层和所述工形构件的底部上形成第二介质层；
    在所述第二介质层中分别形成第一开口和第二开口，其中，所述第一开口暴露所述工形构件的底部，所述第二开口贯穿所述第二介质层并延伸至所述第一介质层中；
    在所述第一开口中形成所述工形构件的中部和上部，同时在所述第二开口中形成所述壁状构件。
  10. 根据权利要求9所述的制造方法，其中，所述在所述第二介质层中分别形成第一开口和第二开口的步骤包括：
    在所述第二介质层上形成具有第一图案和第二图案的第一光刻胶层；
    利用所述第一图案和所述第二图案刻蚀所述第二介质层分别形成第一初始开口和第二初始开口；
    在所述第二介质层上形成具有第三图案和第四图案的第二光刻胶层，所述第三图案暴露所述第一初始开口以及部分所述第二介质层，所述第四图案暴露出所述第二初始开口；
    利用所述第三图案刻蚀部分所述第二介质层形成所述第一开口以及利用所述第四图案刻蚀所述第一介质层形成所述第二开口。
  11. 根据权利要求10所述的制造方法，其中，还包括：
    利用所述第三图案刻蚀部分所述第二介质层形成所述第一开口以及利用所述第二初始开口刻蚀所述第一介质层形成所述第二开口在同一步骤中 完成。
  12. 根据权利要求10所述的制造方法，其中，还包括：
    填充导电材料于所述第一开口和所述第二开口中分别形成所述工形构件的上部和中部以及所述壁状构件。
  13. 根据权利要求1所述的制造方法，其中，所述衬底包括芯片区和外围区，所述工形构件和所述壁状构件分别位于所述芯片区和所述外围区。
  14. 一种半导体结构，其中，包括：
    衬底；
    位于所述衬底上的中间层；
    工形构件和壁状构件，位于所述中间层中；
    其中，所述壁状构件的顶表面不低于所述工形构件的顶表面，所述壁状构件的底表面不高于所述工形构件的底表面。
  15. 根据权利要求14所述的半导体结构，其中，所述工形构件的上部和中部一体成型，所述壁状构件一体成型。
  16. 根据权利要求15所述的半导体结构，其中，所述中间层包括：第一介质层和第二介质层；
    所述工形构件的上部和中部位于所述第二介质层中，所述工形构件的下部位于所述第一介质层中，所述壁状构件位于所述第二介质层和所述第一介质层中。
  17. 根据权利要求16所述的半导体结构，其中，所述壁状构件的宽度大于所述工形构件的中部的宽度。
  18. 根据权利要求17所述的半导体结构，其中，所述壁状构件的宽度等于所述工形构件的上部的宽度；所述工形构件的上部的宽度不小于所述工形构件的底部的宽度。
  19. 根据权利要求16所述的半导体结构，其中，所述工形构件的上部和中部与所述壁状构件在同一步骤中形成。
  20. 根据权利要求14所述的半导体结构，其中，所述衬底包括芯片区和外围区，所述工形构件和所述壁状构件分别位于所述芯片区和所述外围区。
PCT/CN2021/104797 2021-01-19 2021-07-06 半导体结构及其制造方法 Ceased WO2022156155A1 (zh)

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