WO2022142370A1 - 一种半导体器件 - Google Patents

一种半导体器件 Download PDF

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WO2022142370A1
WO2022142370A1 PCT/CN2021/113009 CN2021113009W WO2022142370A1 WO 2022142370 A1 WO2022142370 A1 WO 2022142370A1 CN 2021113009 W CN2021113009 W CN 2021113009W WO 2022142370 A1 WO2022142370 A1 WO 2022142370A1
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region
substrate
oxide layer
semiconductor device
field oxide
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PCT/CN2021/113009
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English (en)
French (fr)
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王琼
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无锡华润上华科技有限公司
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Priority to US18/260,140 priority Critical patent/US20240055516A1/en
Publication of WO2022142370A1 publication Critical patent/WO2022142370A1/zh

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Definitions

  • the present application relates to the field of semiconductors, in particular to a semiconductor device.
  • STI shallow trench isolation
  • a semiconductor device including:
  • a shallow trench isolation structure disposed in the substrate and in the form of a first annular structure, the region of the substrate surrounded by the shallow trench isolation structure is an active region;
  • a drain doped region having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types, disposed on the upper surface of the central region of the active region;
  • a source doped region having a second conductivity type, is disposed on the upper surface of the active region on both sides of the drain doped region, and is spaced apart from the drain doped region, and the drain
  • the connection direction between the doped region and the source doped region is the first direction, and the direction in the plane where the substrate is located and perpendicular to the first direction is the second direction;
  • a field oxide layer is disposed on the upper surface of the substrate in the active region and has a second annular structure and surrounds the drain doping region, the outer boundary of the field oxide layer and the shallow trench There is a preset spacing between the groove isolation structures, and the preset spacing is greater than 0;
  • a gate poly disposed on the upper surface of the substrate and having a third annular structure and surrounding the field oxide layer, the gate poly being doped from the source in the first direction region extending above the field oxide layer, the gate poly extending from above the shallow trench isolation structure to above the field oxide layer in the second direction, the gate poly A gate oxide layer is also arranged between the extremely polycrystalline and the substrate;
  • drift region having a second conductivity type, disposed in the substrate, surrounding the drain doping region, and spaced apart from the source doping region, the drift region also extending along the second direction to below the shallow trench isolation structure.
  • FIG. 1 shows a schematic top view of the semiconductor device according to an embodiment of the present application and a cross-sectional view along A-A1;
  • FIG. 2 shows a schematic top view of the semiconductor device in another embodiment of the present application.
  • An exemplary LOCOS process compatible structure with the STI process is as follows:
  • the channel and source terminal of the NLDMOS device are centered, the drift region and LOCOS layer are distributed around the outer ring with it as the center, and the drain is distributed as the drift region terminal in the outermost ring; this method can distinguish STI from LOCOS , the disadvantage is that: since the drift region of the device is connected to the outer isolation region, its size needs to be enlarged to meet the withstand voltage of the peripheral PN junction, and eventually the size of the drift region is much larger than the size of the drift region required for the withstand voltage of the device itself, which will bring great Area wasted, reducing product competitiveness.
  • the drift region and drain terminal of the NLDMOS device are centered and distributed in stripes; the channel and source terminals are arranged on both sides of the device; LOCOS is distributed in stripes in the drift region and extends out of the active region, so LOCOS will be in the STI region. overlap.
  • this method avoids the withstand voltage problem of the drift region and the peripheral P-type junction, its disadvantage is that the LOCOS and the STI region partially overlap, resulting in repeated operations such as process etching, exposure, and thermal processes in this region, resulting in device surface defects, The interface state is generated, which destroys the surface morphology, and finally causes the failure of the device reliability assessment and the serious degradation of the device characteristics.
  • the regional interface of LOCOS and STI is directly divided into the periphery of the entire device working area, that is, the isolation of the source, body, drain and other internal regions of the device is completely undertaken by the LOCOS region, and LOCOS is also responsible for the withstand voltage requirements of the device drift region, while
  • the STI part is only on the periphery of the bulk ring of the device, which is used to distinguish the isolation between the device and the device; although this method can clearly distinguish the STI and LOCOS regions, but due to the characteristics of the LOCOS process itself, the internal isolation of the device is caused
  • the size is much larger than that of the STI isolation method, such as the source and body regions, the conventional STI isolation only needs 0.36um, and the LOCOS process needs to be enlarged to at least 0.6 ⁇ 0.8um; in the highly integrated chip circuit design, it will cause the extremely large area. It is a big waste; in addition, since each device needs to consider the isolation interface relationship between LOCOS and STI, it increases the complexity of platform development
  • the present application provides a semiconductor device, as shown in FIG. 1 , the semiconductor device includes:
  • the shallow trench isolation structure 108 is disposed in the substrate 101 and has a first annular structure, and the region of the substrate 101 surrounded by the shallow trench isolation structure 108 is the active region 105 ;
  • the drain doped region 103 has a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types, and are disposed on the upper surface of the central region of the active region 105;
  • the source doped region 102 has the second conductivity type, is disposed on the upper surface of the active region 105 on both sides of the drain doped region, and is spaced apart from the drain doped region 103, so The connection direction of the drain doping region 103 and the source doping region 102 is the first direction, and the direction in the plane where the substrate 101 is located and perpendicular to the first direction is the second direction;
  • a field oxide layer 104 is disposed on the upper surface of the substrate 101 in the active region 105 and has a second annular structure and surrounds the drain doping region 103 .
  • the outer boundary of the field oxide layer 104 There is a predetermined distance between the shallow trench isolation structure 108, and the predetermined distance is greater than 0;
  • the gate polycrystalline 106 is disposed on the upper surface of the substrate 101 and has a third annular structure and surrounds the field oxide layer 104. In the first direction, the gate polycrystalline 106 extends from the Above the source doped region 102 extends to above the field oxide layer 104, and in the second direction the gate poly 106 extends from above the shallow trench isolation structure 108 to the field Above the oxide layer 104, a gate oxide layer is further provided between the gate polycrystalline 106 and the substrate 101;
  • a drift region 107 having a second conductivity type, is disposed in the substrate 101 and surrounds the drain doping region 103, and is spaced apart from the source doping region 102, and the drift region 107 also extends along the The second direction extends below the shallow trench isolation structure 108 .
  • the shallow trench isolation structure is used to define the boundary of the active region, the field oxide layer is formed in the active region, and the shallow trench isolation structure and the field oxide are formed by the setting.
  • the layers are completely spaced from each other.
  • FIG. 1 shows a schematic top view of the semiconductor device according to an embodiment of the present application and a cross-sectional view along A-A1.
  • the substrate 101 is the square area described in FIG. 1 , wherein the substrate 101 can be at least one of the following materials: Silicon, polysilicon, or silicon-on-insulator (SOI).
  • the substrate 101 is silicon.
  • the substrate 101 is a doped substrate 101 having a first conductivity type; for example, a P-type substrate 101 .
  • a shallow trench isolation structure 108 is formed in the semiconductor device, is disposed in the substrate and has a first annular structure, the plane where the substrate is located is a horizontal plane, and the annular structure is a horizontal plane. In projection, the region of the substrate surrounded by the shallow trench isolation structure 108 is the active region 105 .
  • the first annular structure is an octagonal annular structure.
  • the shallow trench isolation structure 108 is located in the substrate 101, and the substrate 101 will be divided into a field region and an active region 105 by the shallow trench isolation structure 108 (STI), wherein
  • the active region 105 refers to the region in the substrate 101 surrounded by the shallow trench isolation structure 108, so the outer boundary of the active region 105 and the inner boundary of the STI structure overlap.
  • the shallow trench isolation structure 108 includes trenches, or may further be filled with isolation oxides in the trenches.
  • the specific structure and preparation method thereof may refer to conventional structures and processes, which will not be repeated here.
  • the extension region of the active region 105 in the second direction B-B1 is the device withstand voltage region; the active region in the first direction A-
  • the region between the drain doping region and the source doping region on A1 is the device working and withstand voltage region.
  • the size of the withstand voltage region of the device and the size of the device operation and withstand voltage region all need to meet the withstand voltage requirements of the semiconductor device of the present application.
  • the first direction A-A1 is the length direction of the conductive channel of the device
  • the second direction B-B1 is the width direction of the conductive channel of the device.
  • the source doped region 102 and the drain doped region 103 are formed in the device working and withstand voltage regions, and the source doped region 102 and the drain doped region 103 are along the first direction A-A1 are set in sequence, as shown in Figure 1.
  • the first direction A-A1 is the length direction of the conductive channel of the device, and along the length direction of the conductive channel of the device, the drain doped region 103, the gate doped region 103 and the gate are sequentially arranged from left to right.
  • a P-type substrate 101 lead-out structure may be further provided outside the source doped region 102 .
  • the method for forming the source doped region 102 and the drain doped region 103 is the method of ion implantation, and details are not described herein again.
  • the drain doping region 103 has a second conductivity type, such as N-type doping, the first conductivity type and the second conductivity type are opposite conductivity types, and are disposed in the active region the upper surface of the central region of the doped source region; the source doped region 102, which has a second conductivity type, such as N-type doping, is disposed on the upper surface of the active region on both sides of the drain doped region , and is spaced apart from the drain doping region.
  • a second conductivity type such as N-type doping
  • the extension regions are provided at the upper and lower ends of the working region, and the extension regions are located on the withstand voltage region of the NLDMOS device.
  • the voltage-resistant structure includes active regions 105 in both the first direction A-A1 (that is, the length direction of the conductive channel) and the second direction B-B1 (that is, the width direction of the conductive communication). Therefore, the withstand voltage dimension in the first direction A-A1 can be applied to the second direction B-B1, which helps to reduce the size of the device in the second direction B-B1.
  • the active region 105 is arranged in an octagonal shape as a whole in the second direction B-B1, and the region where the source doped region 102 is extended is arranged in the first direction A-A1, as shown in FIG. 1 . , wherein the critical dimension of the active region 105 in the second direction B-B1 is larger than the critical dimension of the active region 105 in the first direction A-A1.
  • a field oxide layer 104 is also disposed in the active region 105 and has a second annular structure and surrounds the drain doping region.
  • the outer boundary of the field oxide layer 104 is connected to the shallow trench.
  • the second annular structure is an octagonal annular structure.
  • the field oxide layer 104 is a silicon local oxide field oxide layer 104 (LOCOS).
  • LOCOS silicon local oxide field oxide layer 104
  • the silicon local oxide field oxide layer 104 uses silicon nitride as a mask to selectively oxidize silicon, and also Referred to as the field oxide layer 104 .
  • the field oxide layer 104 is located within the boundary of the active region 105, the boundary of the field oxide layer 104 and the boundary of the active region 105 are set at a certain distance, and the inner boundary of the shallow trench isolation structure 108 is the same as the boundary of the active region 105.
  • the outer boundary of the active region 105 overlaps, and by introducing layers of the active region 105 in the second direction B-B1, the field oxide layer 104 (for example, the LOCOS region) and the STI region in the second direction B-B1 can be connected to each other.
  • Spaced isolation to avoid surface defects, interface state and morphology caused by repeated operations of etching, exposure and other processes in the STI process and the field oxide layer 104 preparation process (LOCOS process), which can further improve the performance and yield of the device.
  • the distance k between the boundary of the active region 105 and the boundary of the field oxide layer 104 should not be too small to ensure that the NLDMOS device is in the second direction B-B1
  • the withstand voltage should not be too large.
  • the distance between the boundary of the active region 105 and the outer boundary of the field oxide layer 104 is 0.5um to 0.8um, that is, In the second direction, the predetermined distance between the outer boundary of the field oxide layer and the shallow trench isolation structure is 0.5um ⁇ 0.8um.
  • the length dimension of the field oxide layer 104 in the first direction A-A1 is smaller than the length dimension of the field oxide layer in the second direction B-B1.
  • a drift region 107 is further included. As shown in FIG. 1 , the drift region 107 is formed in the substrate 101 and has a different doping type from the substrate 101 . The drift region 107 is disposed in the substrate 101 and surrounds the drain doping region 103 and is spaced apart from the source doping region 102 , and the drift region 107 is also along the second direction B -B1 extends below the shallow trench isolation structure.
  • the substrate 101 is P-type doped, and the drift region 107 is N-type doped.
  • the drift region 107 is octagonal, for example, in an embodiment of the present application, the top view of the drift region 107 is an octagonal structure.
  • the LOCOS is formed on the drift region 107, and the outer boundary of the drift region 107 completely surrounds and encloses the outer boundary of the LOCOS.
  • the semiconductor device described herein further includes a gate poly 106 surrounding and surrounding the field oxide layer 104.
  • An N well 110 is further formed in the drift region 107 , and the drain doped region 103 is formed in the N well 110 .
  • the doping depth of the N-well 110 may be greater than the doping depth of the drift region 107 .
  • the gate poly 106 in the first direction, extends from the boundary of the source doped region 102 in the active region 105 of the channel region to the field oxide layer 104 .
  • the gate polycrystalline 106 located on the field oxide layer acts as a field plate structure, which can further improve the withstand voltage of the device; the above arrangement can meet the withstand voltage requirements of high-voltage devices, especially NLDMOS devices with withstand voltage requirements greater than 100V.
  • the gate polycrystalline 106 has a third annular structure, and the third annular structure is an octagonal annular structure.
  • the semiconductor device further includes: an interconnection structure, the interconnection structure may be one of a through hole and a plug.
  • the drain doped region 103, the gate poly 106 and the substrate 101 are electrically connected to connect the source doped region 102, the drain doped region 103, the gate poly 106 and the substrate 101 are led out for packaging.
  • the semiconductor device further includes: further includes a metal field plate 109 , and a schematic top view of the semiconductor device is shown in FIG. 2 .
  • a metal field plate 109 is disposed over the gate polycrystalline 106 and the field oxide layer 104 , and a dielectric layer is provided between the metal field plate 109 and the gate polycrystalline 106 , and the metal field A dielectric layer is also provided between the plate 109 and the field oxide layer 104 .
  • the metal field plate 109 is located above the region where the drift region is located, and its size is larger than that of the gate, which can further improve the withstand voltage of the drift region of the device, and is beneficial to meet the withstand voltage requirements of high-voltage devices, especially NLDMOS devices larger than Withstand voltage requirements above 100V.
  • a field oxide layer is added on the platform based on the STI process, and a new type of high-voltage semiconductor device is proposed; the field oxide layer only exists in the drift region of the high-voltage device, and in the first direction and the second direction, it can be effectively isolated from the STI area, without sacrificing the area of the device and its isolation area, avoiding the repeated etching and exposure of the process due to the overlapping of the field oxide layer and the STI area.
  • the adverse effects of device surface defects, irregular morphology and other problems are examples of device surface defects, irregular morphology and other problems.

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Abstract

本申请提供了一种半导体器件。半导体器件包括：衬底(101)，具有第一导电类型；浅沟槽隔离结构(108)，设置于所述衬底(101)中且呈第一环形结构，所述衬底(101)被所述浅沟槽隔离结构(108)环绕的区域为有源区(105)；漏极掺杂区(103)，具有第二导电类型，设置于所述有源区(105)的中心区域的上表面；源极掺杂区(102)，具有第二导电类型，设置于所述漏极掺杂区(103)的两侧的所述有源区(105)的上表面，且与所述漏极掺杂区(103)间隔设置；场氧化层(104)，设置于所述有源区(105)内的所述衬底(101)的上表面且呈第二环形结构，并环绕所述漏极掺杂区(103)；栅极多晶(106)，设置于所述衬底(101)的上表面且呈第三环形结构，并环绕所述场氧化层(104)；漂移区(107)，具有第二导电类型，设置于所述衬底(101)中并包围所述漏极掺杂区(103)。

Description

一种半导体器件
相关申请的交叉引用
本申请要求于2020年12月31日提交中国专利局、申请号为202011624301.3、发明名称为“一种半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，具体而言涉及一种半导体器件。
背景技术
N型横向双扩散金属氧化物半导体(NLDMOS)器件的设计中，在漂移区区域用STI(浅沟槽隔离，shallow trench isolation)帮助耐压已无法满足要求，主要原因是：高压NLDMOS器件，为了满足高耐压、低导通电阻的特性需求，势必要增加漂移区的掺杂浓度；但STI结构由于其自身形貌特点会在拐角(Corner)处产生较大的电场；在高压应用，特别是耐压需求大于100V的超高压应用领域，该电场会造成器件的提前击穿烧毁以及电学特性的严重退化问题，因而在超高压NLDMOS器件领域具有局限性。
为了解决该问题虽然有一些改进方法，例如将硅局部氧化隔离(Local Oxidation of Silicon)结构取代漂移区的STI结构，辅助器件耐压；该方法虽可有效帮助器件耐压提升，但是如何将LOCOS工艺与STI工艺完美结合，降低工艺兼容给器件带来的不良影响，是目前需要解决的问题。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本申请的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
为了克服目前存在的至少一个问题，本申请第一方面提供了一种半导体器件，包括：
衬底，具有第一导电类型；
浅沟槽隔离结构，设置于所述衬底中且呈第一环形结构，所述衬底被所述浅沟槽隔离结构环绕的区域为有源区；
漏极掺杂区，具有第二导电类型，所述第一导电类型与所述第二导电类型为相反的导 电类型，设置于所述有源区的中心区域的上表面；
源极掺杂区，具有第二导电类型，设置于所述漏极掺杂区的两侧的所述有源区的上表面，且与所述漏极掺杂区间隔设置，所述漏极掺杂区与所述源极掺杂区的连线方向为第一方向，在所述衬底所在平面内且与所述第一方向垂直的方向为第二方向；
场氧化层，设置于所述有源区内的所述衬底的上表面且呈第二环形结构，并环绕所述漏极掺杂区，所述场氧化层的外边界与所述浅沟槽隔离结构之间有预设间距，所述预设间距大于0；
栅极多晶，设置于所述衬底的上表面且呈第三环形结构，并环绕所述场氧化层，在所述第一方向上，所述栅极多晶从所述源极掺杂区的上方延伸至所述场氧化层的上方，在所述第二方向上，所述栅极多晶从所述浅沟槽隔离结构的上方延伸至所述场氧化层的上方，所述栅极多晶与所述衬底间还设有栅氧化层；
漂移区，具有第二导电类型，设置于所述衬底中并包围所述漏极掺杂区，且与所述源极掺杂区间隔设置，所述漂移区还沿所述第二方向延伸至所述浅沟槽隔离结构的下方。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
本申请的下列附图在此作为本申请的一部分用于理解本申请。附图中示出了本申请的实施例及其描述，用来解释本申请的原理。
附图中：
图1示出了本申请一实施例中所述半导体器件的俯视示意图以及沿A-A1的剖视图；
图2示出了本申请另一实施例中所述半导体器件的俯视示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本申请更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本申请可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本申请发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大自始至终相 同附图标记表示相同的元件。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的结构及步骤，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
示例性的LOCOS工艺与STI工艺兼容的结构如下：
NLDMOS器件的沟道及源极引出端居中，漂移区和LOCOS层以其为中心绕环分布于外侧，漏极作为漂移区引出端在最外侧环分布；该方式可将STI与LOCOS区分开来，其缺点在于：由于器件漂移区与外侧隔离区相连，需要扩大其尺寸来满足外围PN结耐压，最终导致漂移区尺寸远大于器件自身耐压所需的漂移区尺寸，会带来极大地面积浪费，降低产品竞争力。
NLDMOS器件的漂移区及漏极端居中，呈条状分布；沟道及源极引出端排布在器件两侧；LOCOS在漂移区内呈条状分布伸出有源区，因此LOCOS会与STI区域交叠。该方式虽然规避了漂移区与外围P型结的耐压问题，但其缺点在于：LOCOS与STI区域部分重叠，导致该区域工艺刻蚀，曝光，热过程等工序重复操作，造成器件表面缺陷、界面态产生，破坏表面形貌，最终造成器件可靠性考核失败，器件特性退化严重。
将LOCOS和STI的区域界面直接划分至整个器件工作区外围，即器件源极，体区，漏极等内部区域的隔离完全由LOCOS区域承担，同时LOCOS还负责器件漂移区的耐压需求，而STI部分只是在器件体区环(Bulk ring)的外围，用于区别器件与器件之间的隔离；该方式虽可将STI和LOCOS区域区分清楚，但由于LOCOS工序自身的特点，导致器件内部隔离尺寸远大于STI隔离方式，比如源极和体区，常规STI隔离只需0.36um，而运用LOCOS工艺至少要放大至0.6～0.8um；在高度集成化的芯片电路设计中，会造成面积的极大浪费；此外，由于每个器件都需要考虑LOCOS和STI的隔离界面关系，增加了平台开发设计的复杂度。
本申请提供了一种半导体器件，如图1所示，所述半导体器件包括：
衬底101，具有第一导电类型；
浅沟槽隔离结构108，设置于所述衬底101中且呈第一环形结构，所述衬底101被所述浅沟槽隔离结构108环绕的区域为有源区105；
漏极掺杂区103，具有第二导电类型，所述第一导电类型与所述第二导电类型为相反的导电类型，设置于所述有源区105的中心区域的上表面；
源极掺杂区102，具有第二导电类型，设置于所述漏极掺杂区的两侧的所述有源区105的上表面，且与所述漏极掺杂区103间隔设置，所述漏极掺杂区103与所述源极掺杂区102的连线方向为第一方向，在所述衬底101所在平面内且与所述第一方向垂直的方向为第二方向；
场氧化层104，设置于所述有源区105内的所述衬底101的上表面且呈第二环形结构，并环绕所述漏极掺杂区103，所述场氧化层104的外边界与所述浅沟槽隔离结构108之间有预设间距，所述预设间距大于0；
栅极多晶106，设置于所述衬底101的上表面且呈第三环形结构，并环绕所述场氧化层104，在所述第一方向上，所述栅极多晶106从所述源极掺杂区102的上方延伸至所述场氧化层104的上方，在所述第二方向上，所述栅极多晶106从所述浅沟槽隔离结构108的上方延伸至所述场氧化层104的上方，所述栅极多晶106与所述衬底101间还设有栅氧化层；
漂移区107，具有第二导电类型，设置于所述衬底101中并包围所述漏极掺杂区103，且与所述源极掺杂区102间隔设置，所述漂移区107还沿所述第二方向延伸至所述浅沟槽隔离结构108的下方。
其中，在本申请中所述浅沟槽隔离结构用于定义有源区的边界，所述场氧化层形成于所述有源区之内，通过所述设置将浅沟槽隔离结构和场氧化层完全相互间隔，通过所述改进在不牺牲器件整体尺寸和高耐压特性需求的同时，有效避免了因为工序叠加刻蚀、曝光带来的器件表面损伤，有利于帮助器件特性退化及可靠性问题的解决。
下面结合附图对本申请的所述半导体器件进行详细的说明。其中图1示出了本申请一实施例中所述半导体器件的俯视示意图以及沿A-A1的剖视图。
如图1所示，其中，在所述半导体器件中所述衬底101为图1中所述的方形区域，其中，所述衬底101可以是以下所提到的材料中的至少一种：硅、多晶硅或者绝缘体上硅(SOI)。
在本申请的一实施例中，所述衬底101为硅。
在本申的一实施例中，所述衬底101为掺杂的衬底101，具有第一导电类型；例如为 P型衬底101。
在所述半导体器件中形成有浅沟槽隔离结构108(STI)，设置于所述衬底中且呈第一环形结构，所述衬底所在平面为水平面，则该环形结构为在水平面上的投影，所述衬底被所述浅沟槽隔离结构108环绕的区域为有源区105。在一示例中，所述第一环形结构为八边形的环形结构。
所述浅沟槽隔离结构108(STI)位于所述衬底101中，并且将通过所述浅沟槽隔离结构108(STI)将所述衬底101划分为场区和有源区105，其中有源区105是指所述衬底101中被所述浅沟槽隔离结构108环绕的区域，因此所述有源区105的外边界与所述STI结构的内边界是重叠的。
其中，所述浅沟槽隔离结构108包括沟槽，或者还可以进一步填充于所述沟槽中的隔离氧化物，其具体结构和制备方法可参照常规的结构和工艺，在此不再赘述。
在本申请中，继续如图1所示，所述有源区105在所述第二方向B-B1上的延伸区域为器件耐压区；所述有源区在所述第一方向A-A1上的所述漏极掺杂区与所述源极掺杂区之间的区域为器件工作及耐压区。器件耐压区的尺寸及器件工作及耐压区的尺寸均需满足本申请半导体器件的耐压需求。其中，第一方向A-A1为器件的导电沟道的长度方向，第二方向B-B1为器件的导电沟道的宽度方向。
其中，在所述器件工作及耐压区中形成有所述源极掺杂区102、漏极掺杂区103，并且所述源极掺杂区102、漏极掺杂区103沿第一方向A-A1依次设置，如图1所示。
在本申请的一实施例中，所述第一方向A-A1为器件的导电沟道的长度方向，沿器件的导电沟道的长度方向从左至右依次设置漏极掺杂区103、栅极多晶106和源极掺杂区102，在所述源极掺杂区102的外侧还可以进一步设置P型衬底101引出结构。
其中，所述源极掺杂区102和漏极掺杂区103的形成方法为离子注入的方法，在此不再赘述。
其中，所述漏极掺杂区103，具有第二导电类型，例如为N型掺杂，所述第一导电类型与所述第二导电类型为相反的导电类型，设置于所述有源区的中心区域的上表面；所述源极掺杂区102，具有第二导电类型，例如为N型掺杂，设置于所述漏极掺杂区的两侧的所述有源区的上表面，且与所述漏极掺杂区间隔设置。
在水平面上，在所述工作区的上下两端设置所述延伸区，并且所述延伸区位于所述NLDMOS器件的耐压区上。在本申请中在第一方向A-A1(即为导电沟道的长度方向)和第二方向B-B1(即为导电沟通的宽度方向)上耐压结构均包含有源区105，其结构一致，因此可以将第一方向A-A1耐压尺寸运用于第二方向B-B1，有助于器件第二方向B-B1尺 寸缩小。
其中，所述有源区105在第二方向B-B1上整体呈八边形设置，并且在第一方向A-A1上设置延伸出来的源极掺杂区102所在区域，如图1所示，其中所述有源区105在第二方向B-B1上的关键尺寸大于所述有源区105在所述第一方向A-A1上的关键尺寸。
在本申请中在所述有源区105内还设置有场氧化层104且呈第二环形结构，并环绕所述漏极掺杂区，所述场氧化层104的外边界与所述浅沟槽隔离结构之间有预设间距，所述预设间距大于0。所述第二环形结构为八边形的环形结构。
在本申请的一实施例中，所述场氧化层104为硅局部氧化场氧化层104(LOCOS)，所述硅局部氧化场氧化层104以氮化硅为掩膜对硅的选择氧化，亦称为场氧化层104。
所述场氧化层104位于有源区105的边界内，所述场氧化层104的边界和所述有源区105的边界设置一定的距离，而所述浅沟槽隔离结构108的内边界与有源区105的外边界重叠，通过在所述第二方向B-B1上引入有源区105层次，可以将第二方向B-B1的场氧化层104(例如LOCOS区域)与STI区域区相互间隔隔离，以避免STI工艺及场氧化层104制备工艺(LOCOS工艺)中刻蚀、曝光等工序重复操作造成的表面缺陷、界面态及形貌等问题，可以进一步提高器件的性能和良率。
在所述第二方向B-B1上，所述有源区105的边界和所述场氧化层104的边界之间的距离k不应过小，以保证NLDMOS器件在第二方向B-B1上的耐压，也不应过大，在本申请的一实施例中，所述有源区105的边界和所述场氧化层104的外边界之间的距离为0.5um～0.8um，也即在第二方向上，所述场氧化层的外边界与所述浅沟槽隔离结构之间的预设间距为0.5um～0.8um。
所述场氧化层104在所述第一方向A-A1上的长度尺寸小于所述场氧化层在所述第二方向B-B1上的长度尺寸。
在本申请中还进一步包括漂移区107，如图1所示，所述漂移区107形成于所述衬底101中，其与所述衬底101具有不同的掺杂类型。所述漂移区107设置于所述衬底101中并包围所述漏极掺杂区103，且与所述源极掺杂区102间隔设置，所述漂移区107还沿所述第二方向B-B1延伸至所述浅沟槽隔离结构的下方。
例如在本申请的一实施例中，所述衬底101为P型掺杂，所述漂移区107为N型掺杂。
其中，所述漂移区107为八边形，例如在本申请的一实施例中，所述漂移区107的俯视图为八边形的结构。所述LOCOS形成于所述漂移区107上，所述漂移区107的外边界完全环绕并包围所述LOCOS的外边界。
在本申请中所述半导体器件还进一步包括栅极多晶106，所述栅极多晶106环绕并包 围住所述场氧化层104。
所述漂移区107内进一步形成有N阱110，所述漏极掺杂区103形成于所述N阱110中。其中，所述N阱110的掺杂深度可以大于所述漂移区107的掺杂深度。
在本申请的一实施例中，在第一方向上，所述栅极多晶106从沟道区域的有源区105内源极掺杂区102边界延伸至场氧化层104上。位于场氧化层上的栅极多晶106作为场板结构，能进一步提升器件耐压；通过所述设置可以满足高压器件耐压需求，特别是耐压需求大于100V以上的NLDMOS器件。所述栅极多晶106呈第三环形结构，所述第三环形结构为八边形的环形结构。
其中，所述第一环形结构在水平面上的几何中心、所述第二环形结构在水平面上的几何中心、所述第三环形结构在水平面上的几何中心及所述漂移区的外轮廓在水平面上的几何中心重合。
进一步，所述半导体器件还包括：互连结构，所述互连结构可以为通孔和插塞中的一种，通过设置所述互连结构进而与所述源极掺杂区102、所述漏极掺杂区103、所述栅极多晶106和所述衬底101形成电连接，以将所述源极掺杂区102、所述漏极掺杂区103、所述栅极多晶106和所述衬底101引出进行封装。
在一个实施例中，半导体器件还包括：还包括金属场板109，半导体器件的俯视示意图如图2所示。金属场板109跨设在所述栅极多晶106和所述场氧化层104的上方，且所述金属场板109与所述栅极多晶106之间设有介质层，所述金属场板109与所述场氧化层104之间也设有介质层。所述金属场板109位于所述漂移区所在区域的上方，其尺寸大于所述栅极，能辅助器件漂移区耐压的进一步提升，利于实现高压器件耐压需求，特别是能够满足NLDMOS器件大于100V以上的耐压需求。
在本申请中通过所述改进，在基于STI工艺的平台上，增加了场氧化层，提出了一种新型高压的半导体器件；该场氧化层只存在于高压器件漂移区内，在第一方向和第二方向，可与STI区域有效的隔离开来，在不牺牲器件及其隔离区面积的情况下，避免了由于场氧化层和STI两个区域相互交叠，导致工艺反复刻蚀、曝光带来的器件表面缺陷，形貌不规则等问题的不良影响。
术语与本申请的技术领域的技术人员通常理解的含义相同。本文中使用的术语只是为了描述具体的实施目的，不是旨在限制本申请。本文中出现的诸如“部”、“件”等术语既可以表示单个的零件，也可以表示多个零件的组合。本文中出现的诸如“安装”、“设置”等术语既可以表示一个部件直接附接至另一个部件，也可以表示一个部件通过中间件附接至另一个部件。本文中在一个实施方式中描述的特征可以单独地或与其他特征结合地 应用于另一个实施方式，除非该特征在该另一个实施方式中不适用或是另有说明。
本申请已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本申请限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本申请并不局限于上述实施例，根据本申请的教导还可以做出更多种的变型和修改，这些变型和修改均落在本申请所要求保护的范围以内。本申请的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

  1. 一种半导体器件，包括：
    衬底，具有第一导电类型；
    浅沟槽隔离结构，设置于所述衬底中且呈第一环形结构，所述衬底被所述浅沟槽隔离结构环绕的区域为有源区；
    漏极掺杂区，具有第二导电类型，所述第一导电类型与所述第二导电类型为相反的导电类型，设置于所述有源区的中心区域的上表面；
    源极掺杂区，具有第二导电类型，设置于所述漏极掺杂区的两侧的所述有源区的上表面，且与所述漏极掺杂区间隔设置，所述漏极掺杂区与所述源极掺杂区的连线方向为第一方向，在所述衬底所在平面内且与所述第一方向垂直的方向为第二方向；
    场氧化层，设置于所述有源区内的所述衬底的上表面且呈第二环形结构，并环绕所述漏极掺杂区，所述场氧化层的外边界与所述浅沟槽隔离结构之间有预设间距，所述预设间距大于0；
    栅极多晶，设置于所述衬底的上表面且呈第三环形结构，并环绕所述场氧化层，在所述第一方向上，所述栅极多晶从所述源极掺杂区的上方延伸至所述场氧化层的上方，在所述第二方向上，所述栅极多晶从所述浅沟槽隔离结构的上方延伸至所述场氧化层的上方，所述栅极多晶与所述衬底间还设有栅氧化层；以及
    漂移区，具有第二导电类型，设置于所述衬底中并包围所述漏极掺杂区，且与所述源极掺杂区间隔设置，所述漂移区还沿所述第二方向延伸至所述浅沟槽隔离结构的下方。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述有源区在所述第二方向上的延伸区域为器件耐压区；所述有源区在所述第一方向上的所述漏极掺杂区与所述源极掺杂区之间的区域为器件工作及耐压区。
  3. 根据权利要求1所述的半导体器件，其特征在于，所述场氧化层在所述第一方向上的长度尺寸小于所述场氧化层在所述第二方向上的长度尺寸。
  4. 根据权利要求1所述的半导体器件，其特征在于，所述栅极多晶在所述第一方向上的长度尺寸小于所述栅极多晶在所述第二方向上的长度尺寸。
  5. 根据权利要求1所述的半导体器件，其特征在于，在所述第二方向上，所述场氧化层的外边界与所述浅沟槽隔离结构之间的预设间距为0.5um～0.8um。
  6. 根据权利要求1所述的半导体器件，其特征在于，所述第二环形结构、所述第三环形结构均为八边形的环形结构。
  7. 根据权利要求1所述的半导体器件，其特征在于，所述漂移区的外轮廓在所述衬底所 在平面内是八边形。
  8. 根据权利要求1所述的半导体器件，其特征在于，所述场氧化层形成于所述漂移区上，所述漂移区的外边界完全环绕并包围所述场氧化层的外边界。
  9. 根据权利要求1所述的半导体器件，其特征在于，在所述衬底所在平面内，所述漏极掺杂区两侧的所述源极掺杂区关于所述漏极掺杂区轴对称。
  10. 根据权利要求1所述的半导体器件，其特征在于，所述衬底所在平面为水平面，所述第一环形结构在水平面上的几何中心、所述第二环形结构在水平面上的几何中心、所述第三环形结构在水平面上的几何中心及所述漂移区的外轮廓在水平面上的几何中心重合。
  11. 根据权利要求1所述的半导体器件，其特征在于，所述场氧化层为硅局部氧化场氧化层。
  12. 根据权利要求1所述的半导体器件，其特征在于，还包括金属场板，所述金属场板跨设在所述栅极多晶和所述场氧化层的上方，且所述金属场板与所述栅极多晶之间，以及所述金属场板与所述场氧化层之间均设有介质层。
  13. 根据权利要求1所述的半导体器件，其特征在于，所述有源区在所述第二方向上的关键尺寸大于所述有源区在所述第一方向上的关键尺寸。
  14. 根据权利要求1所述的半导体器件，其特征在于，所述源极掺杂区的外侧还设置有衬底引出结构，所述衬底引出结构的导电类型与所述衬底的导电类型相同。
  15. 根据权利要求1所述的半导体器件，其特征在于，所述半导体器件为耐压需求大于100V以上的NLDMOS器件。
PCT/CN2021/113009 2020-12-31 2021-08-17 一种半导体器件 WO2022142370A1 (zh)

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