WO2022142334A1 - 存储器及其制备方法 - Google Patents

存储器及其制备方法 Download PDF

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Publication number
WO2022142334A1
WO2022142334A1 PCT/CN2021/109895 CN2021109895W WO2022142334A1 WO 2022142334 A1 WO2022142334 A1 WO 2022142334A1 CN 2021109895 W CN2021109895 W CN 2021109895W WO 2022142334 A1 WO2022142334 A1 WO 2022142334A1
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Prior art keywords
layer
bit line
sacrificial
supplementary
line isolation
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PCT/CN2021/109895
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English (en)
French (fr)
Inventor
卢经文
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长鑫存储技术有限公司
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Priority to US17/665,744 priority Critical patent/US20220216216A1/en
Publication of WO2022142334A1 publication Critical patent/WO2022142334A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a memory and a preparation method thereof.
  • DRAM Dynamic Random Access Memory
  • the dynamic random access memory generally includes a plurality of active regions with a strip structure.
  • the two ends of each active region form a node contact region, and the middle region of each active region forms a bit line contact region.
  • the bit line contact region A gate is set between the contact area and each node, so that two MOSFETs with buried gate structures are formed on each active area (the English name is Metal-Oxide-Semiconductor Field Effect Transistor, and the Chinese name is Metal Oxide Semiconductor Field). effect transistor).
  • the node contact region is connected to the capacitor, and the capacitor and the node contact region are connected through the node contact plunger.
  • a first aspect of the embodiments of the present application provides a method for fabricating a memory, which includes the steps of: providing a substrate on which a plurality of mutually parallel bit line isolation walls are arranged; forming a plurality of sacrificial pillars arranged at intervals therebetween; forming a supplementary layer on the surface of the sacrificial pillars, the supplementary layer covering at least opposite sides between the sacrificial pillars; performing ion implantation on the supplementary layer to make the supplementary layer The ion concentration of the layer decreases from the top to the bottom of the supplementary layer; the supplementary layer is etched so that the thickness of the remaining supplementary layer decreases from the top to the bottom of the remaining supplementary layer; An insulating column is formed between the sacrificial columns, and the side surface of the insulating column is in contact with the bit line isolation wall and the remaining supplementary layer; the sacrificial column and the remaining supplementary layer are removed, so that the insulating column and the The bit
  • a second aspect of the embodiments of the present application provides a memory, which includes a substrate on which a plurality of mutually parallel bit line isolation walls are disposed, and a plurality of spacer rows are disposed between adjacent bit line isolation walls A node contact plug of the cloth, and an insulating column isolating the adjacent node contact plugs, an end of the node contact plug away from the base is equal to or greater than an end of the node contact plug close to the base.
  • a plurality of mutually parallel bit line isolation walls are arranged on a substrate, a plurality of sacrificial columns arranged at intervals are formed between adjacent bit line isolation walls, and a supplementary layer is formed on the surface of the sacrificial columns.
  • the thickness of the remaining supplementary layer decreases from the top to the bottom of the remaining supplementary layer, which makes the adjacent sacrificial columns between the supplementary layers on the adjacent sacrificial columns after the supplementary layer is provided
  • the distance increases gradually from the area away from the base to the area close to the base, and the insulating pillars filled between the supplementary layers on the adjacent sacrificial pillars are in the direction parallel to the bit line isolation wall, and the size of the insulating pillars is from the area away from the base to the area close to the base.
  • the area of the substrate gradually increases, and after the sacrificial pillars and the supplementary layer on the sacrificial pillars are removed, the size of the contact holes formed between the adjacent insulating pillars is larger than the size of the bottom of the hole. In this way, the adjacent insulating pillars have When the node contact plug is formed between them, the material forming the node contact plug can more easily enter the contact hole and fill the entire contact hole, so that the structure of the prepared node contact plug is complete and the performance of the memory is improved.
  • a plurality of node contact plugs arranged at intervals and insulating posts for isolating adjacent node contact plugs are provided between two adjacent bit line isolation walls on the substrate, and the node contact posts The end of the plug away from the base is larger than the end of the node contact plug close to the base.
  • This shape of the node contact plug can make the structure of the node contact plug complete and improve the performance of the memory.
  • the memory and the preparation method thereof provided by the embodiments of the present application can solve the problems.
  • Other technical problems, other technical features included in the technical solution, and the beneficial effects brought about by these technical features will be described in further detail in the specific embodiments.
  • Fig. 1a is the structure reference diagram 1 of the memory in the related art
  • FIG. 1b is a reference to FIG. 2 for the structure of the memory in the related art
  • FIG. 2 is a flowchart of a method for preparing a memory according to the present embodiment
  • 3a is a schematic structural diagram of a substrate after bit line isolation walls are arranged on the substrate according to the present embodiment
  • Figure 3b is a schematic three-dimensional structure diagram of Figure 3a after the disconnection at the AA line position;
  • Fig. 3c is the front view of Fig. 3b;
  • FIG. 3d is a flow chart of the preparation of the bit line isolation wall of the present embodiment
  • FIG. 4a is a first structural schematic diagram after the silicon oxide layer is disposed on the substrate of this embodiment
  • FIG. 4b is a second structural schematic diagram after the silicon oxide layer is disposed on the substrate of this embodiment.
  • FIG. 4c is a third structural schematic diagram after the silicon oxide layer is disposed on the substrate of the present embodiment.
  • FIG. 5 is a schematic structural diagram of the silicon oxide layer on the substrate of the present embodiment after a mask layer is provided;
  • FIG. 6a is a schematic structural diagram 1 of the sacrificial column disposed on the substrate according to the present embodiment
  • FIG. 6b is a second structural schematic diagram of disposing sacrificial pillars on the substrate of the present embodiment
  • Fig. 6c is a sectional view of Fig. 6b at the position of line BB;
  • FIG. 6d is a flow chart 1 of the preparation of the sacrificial column of the present embodiment.
  • FIG. 6e is a second flow chart of the preparation of the sacrificial column of the present embodiment.
  • 6f is a flow chart of the preparation of the silicon oxide layer of the present embodiment.
  • FIG. 7 is a schematic structural diagram of forming a supplementary layer on the sacrificial pillar of FIG. 6c;
  • FIG. 8a is a schematic structural diagram of the photoresist on the supplementary layer in FIG. 7 etched back to 1/3 of the sacrificial column;
  • FIG. 8b is a schematic structural diagram of the supplementary layer in FIG. 8a after the first ion implantation
  • FIG. 8c is a schematic structural diagram of the photoresist on the supplementary layer in FIG. 8b etched back to 2/3 of the sacrificial column;
  • FIG. 8d is a schematic structural diagram of the supplementary layer in FIG. 8c after the second ion implantation
  • FIG. 8e is a schematic structural diagram of the photoresist on the supplementary layer in FIG. 8d after all removal;
  • FIG. 8f is a flow chart of the preparation of ion implantation for the supplementary layer in this embodiment.
  • FIG. 9 is a schematic structural diagram of the supplementary layer in FIG. 8e after selective etching.
  • FIG. 10a is a schematic view of the structure after the silicon nitride layer is formed in the contact hole formed in FIG. 9;
  • FIG. 10b is a schematic view of the structure after etching back part of the silicon nitride in FIG. 10a;
  • FIG. 10c is a flow chart of the preparation of the insulating column in this embodiment.
  • FIG. 11a is a schematic view of the structure after removing the sacrificial pillar and the supplementary layer in FIG. 10b;
  • FIG. 11b is a schematic structural diagram of the insulating column in FIG. 11a after etching
  • FIG. 12 is a structural view after forming a node contact plug between two adjacent insulations in FIG. 11b.
  • 200 bit line isolation wall
  • 201 trench
  • 300 sacrificial column
  • 301 supplementary layer
  • the memory is generally prepared by the following method, and the preparation method includes the following steps: firstly, a plurality of mutually parallel bit line isolation walls are formed on a substrate, and a trench formed between two adjacent bit line isolation walls exposes the substrate Then, a sacrificial column is formed on each node contact area in each trench, and the structure formed in this step is shown in FIG.
  • Two adjacent bit line isolation walls 200 form trenches 201 , and the node contact regions in the substrate 100 are exposed in the trenches 201 ; then, insulation is formed between every two adjacent sacrificial pillars 300 in each trench 201 Then, the sacrificial pillars 300 are removed to form a contact hole exposing a corresponding node contact region in the substrate 100 between every two adjacent insulating pillars in each trench 201, and then a contact hole is formed in each contact hole.
  • the node contact plugs contacted by the node contact regions exposed in the contact holes, each node contact plug is formed with a capacitor in contact with the node contact plug.
  • the step of forming a sacrificial pillar 300 on each node contact region in each trench 201 includes: first, forming a silicon oxide layer 302 in each trench 201, the silicon oxide layer 302 Cover the side surfaces of the bit line isolation walls 200 and the surface away from the substrate 100; then, a mask layer 303 is formed on the silicon oxide layer 302, the mask layer 303 includes a plurality of strip patterns 304 arranged in parallel, and the extension of the strip patterns 304 The direction intersects with the projection of the extension direction of the bit line isolation wall 200 on the substrate.
  • the structure formed in this step is shown in FIG.
  • the inventors of the present application found that, in the memory produced by the above-mentioned memory preparation method, the structure of the node contact plug is not complete, and the reason for this problem is that: When etching the silicon oxide layer 302 between the bit line isolation walls 200 , the etching solution not only removes the silicon oxide layer 302 at the position where the stripe pattern 304 and the bit line isolation walls 200 intersect, but also the etching solution also erodes the trenches.
  • the silicon oxide layer 302 covered by the mask layer 303 in 201 is etched, and the etching rate of the etching solution to the silicon oxide layer 302 covered by the mask layer 303 in the trench 201 is lower than that of the etching solution to the trench 201
  • the etching rate of the silicon oxide layer 302 exposed in the stripe pattern 304 is such that in the sacrificial pillar 300 formed by the silicon oxide layer 302 covered by the mask layer 303 in the trench 201, the cross-sectional dimension of the sacrificial pillar 300 (in vertical The plane of the substrate 100 and parallel to the extending direction of the trench 201 is the cross-section) gradually increases from far from the substrate 100 to close to the substrate 100 , so that the insulating pillars 400 are subsequently formed between every two adjacent sacrificial pillars 300 in the trench 201 .
  • the cross-sectional size of the insulating pillar 400 gradually decreases from far from the substrate 100 to close to the substrate 100 . Therefore, after the subsequent removal of the sacrificial pillars 300 , in the contact holes formed in each trench 201 and between every two adjacent insulating pillars 400 , the aperture size of the contact holes gradually increases from far from the substrate 100 to close to the substrate 100 . , that is, the size of the orifice of the contact hole is smaller than the size of the bottom of the hole, so that when a node contact plug is formed in the contact hole that is in contact with the node contact area in the contact hole, the material forming the node contact plug cannot easily enter the contact hole. In this case, the probability that the material forming the node contact plug cannot fill the entire contact hole increases, which in turn leads to an incomplete or missing structure of the formed node contact plug, and the incomplete structure of the node contact plug will reduce the performance of the memory. .
  • an embodiment of the present application proposes a method for fabricating a memory.
  • a complementary layer is formed on the sacrificial pillar, and the ion concentration of the complementary layer varies from a region far from the substrate to a region close to the substrate.
  • the concentration is gradually reduced, and the supplementary layer is etched, so that the thickness of the supplementary layer gradually decreases from the area far from the substrate to the area close to the substrate, and then the phase in the gap between every two adjacent bit line isolation walls is gradually reduced.
  • the cross-sectional size of the insulating pillars gradually increases from far from the substrate to close to the substrate, so that in the contact holes formed by removing the sacrificial pillars and the supplementary layer, the aperture size of the contact holes varies from far from the substrate to close to the substrate.
  • the base is gradually reduced, that is, the size of the hole of the contact hole is larger than the size of the hole bottom, which makes the material that forms the node contact plug when a node contact plug is formed in the contact hole later in contact with the contact area of the node in the contact hole It is easier to enter into the contact hole, so that the structure of the formed node contact plug is complete without any defect, thereby improving the performance of the memory.
  • This embodiment provides a method for preparing a memory, which is used to prepare a memory, for example, a dynamic random access memory.
  • the preparation method includes the following steps:
  • Step S1 providing a substrate.
  • the structure of the substrate is shown in FIG. 3 a .
  • a plurality of mutually parallel bit line isolation walls 200 are arranged on the substrate 100 , and nodes in the substrate 100 are formed between adjacent bit line isolation walls 200 .
  • the trench 201 of the contact region 101 is shown in FIG. 3 a .
  • Step S2 forming a plurality of sacrificial pillars arranged at intervals between adjacent bit line isolation walls 200 , that is, forming a sacrificial pillar on each node contact region 101 in each trench 201 , this step forms 6a, 6b and 6c, each sacrificial pillar 300 is formed on a corresponding node contact area 101, that is, the sacrificial pillar 300 corresponds to the node contact area 101 one-to-one, and the corresponding node contact area 101 Contact.
  • Step S3 forming a supplementary layer on the surface of each sacrificial pillar 300 , the structure formed in this step is shown in FIG. 7 , the supplementary layer 301 at least covers the opposite sides between the sacrificial pillars 300 , that is, at least a plurality of supplementary layers 301 cover the sacrificial pillars 300 . Sides of the pillars 300 , eg, supplemental layers 301 cover the top and side surfaces of the sacrificial pillars 300 .
  • Step S4 performing ion implantation on the supplementary layer 301, so that the ion concentration of the supplementary layer 301 decreases from the top to the bottom of the supplementary layer 301.
  • the structure formed in this step is shown in FIG. 8e, wherein “+” in FIG. 8e represents The concentration of ions, "+” gradually decreases from the top to the bottom of the supplemental layer 301 shown in Figure 8e.
  • Step S5 Etch the supplementary layer 301 so that the thickness of the remaining supplementary layer 301 decreases from the top to the bottom of the remaining supplementary layer 301, that is, the thickness of the supplementary layer 301 in the area of the remaining supplementary layer 301 close to the substrate 100 is smaller than that of the supplementary layer 301
  • the thickness of the supplementary layer 301 in the region far from the substrate 100 in the layer 301 is shown in FIG. 9 .
  • Step S6 forming an insulating pillar 400 in each trench 201 and between every two adjacent sacrificial pillars 300 , the side surfaces of the insulating pillar 400 and the remaining supplementary layers on the two sacrificial pillars 300 adjacent to the insulating pillar 400 301 is in contact with the bit line isolation wall 200.
  • the structure formed by this step is shown in FIG. 10b.
  • the insulating column 400 and the sacrificial column 300 are spaced apart, and the side surface of the insulating column 400 and the side surface of the sacrificial column 300 are formed by the supplementary layer 301. isolation.
  • Step S7 removing the sacrificial pillar 300 and the remaining supplementary layer 301 to form a contact hole 401 in the trench 201 and between each adjacent insulating pillar 400 in the trench 201 , that is, so that the insulating pillar 400 is connected to the bit
  • the line isolation walls 200 together form a plurality of contact holes 401, and each contact hole 401 exposes a corresponding node contact region 101 in the substrate 100.
  • the structure formed by this step is shown in FIG. 11a.
  • Contact holes 401 are formed between them, a plurality of contact holes 401 can be formed in the same trench 201, and the plurality of contact holes 401 in the same trench 201 are in one-to-one correspondence with the plurality of node contact regions 101 exposed in the trench 201 set up.
  • Step S8 forming a node contact plug 500 in contact with the corresponding node contact region 101 in each contact hole 401 , the structure formed in this step is shown in FIG. 12 , the node contact plug 500 is formed in the contact hole 401 , and Contact with the node contact region 101 exposed in the contact hole 401 ; or, in the same trench 201 , a node contact plug 500 is provided between each adjacent insulating column 400 , that is, the node contact plug 500 It is spaced apart from the insulating column 400 .
  • a capacitor (not shown in the figure) may also be formed on each node contact plug 500 .
  • the capacitor is used to store charges, and the node contact plug 500 is used to electrically connect the node contact region 101 to the capacitor.
  • a plurality of mutually parallel bit line isolation walls 200 are provided on the substrate 100, and a plurality of spaced sacrificial columns 300 are formed between adjacent bit line isolation walls 200, A supplementary layer 301 is formed on the surface of the sacrificial pillar 300.
  • the thickness of the remaining supplementary layer 301 decreases from the top to the bottom of the remaining supplementary layer 301, which makes the adjacent two sacrificial pillars 300 in the
  • the distance between the supplementary layers 301 on adjacent sacrificial pillars 300 gradually increases from the area far from the substrate 100 to the area close to the substrate 100 , and fills the trenches 201 on two adjacent sacrificial pillars 300
  • the insulating pillars 400 between the supplementary layers 301 are in the direction parallel to the bit line isolation wall 200, and the size of the insulating pillars 400 gradually increases from the area far from the substrate 100 to the area close to the substrate 100.
  • the sacrificial pillar 300 and the sacrificial pillar 300 are removed After the supplementary layer 301 on the pillars 300 is applied, the size of the aperture of the contact hole 401 formed between two adjacent insulating pillars 400 in each trench 201 is larger than the size of the hole bottom.
  • the material forming the node contact plug 500 can more easily enter the contact hole 401 and fill the entire contact hole 401 , so that the structure of the formed node contact plug 500 is prepared. Complete, memory performance boost.
  • the size of the orifice of the contact hole 401 formed between the two adjacent insulating pillars 400 in the trench 201 is larger than the size of the bottom of the hole, compared with the related art, the size of the orifice of the contact hole 401 is smaller than that of the bottom of the hole.
  • the material forming the node contact plug 500 fills the contact hole 401 faster, thereby increasing the efficiency of preparing the node contact plug 500 .
  • the substrate 100 can be prepared by the following method:
  • Step S11 providing a substrate 100 , the substrate 100 may be made of materials such as silicon or germanium, and the substrate 100 may be a circular or square plate-like structure. As shown in FIG. 3 a , the substrate 100 is a square plate-like structure.
  • Step S12 forming a plurality of columns of active regions 102 isolated by a first isolation portion (not shown in the figure) in the substrate 100 , and each column of active regions 102 includes a plurality of active regions 102 , as shown in FIG. 3 a .
  • a plurality of active regions 102 are located in the substrate 100 , and a partial region of each active region 102 , such as a middle region, is covered by the bit line isolation wall 200 located above it.
  • the first isolation portion is prepared by, for example, a shallow trench isolation (STI) method, and a material filled with silicon dioxide in the groove formed on the substrate 100 , and the first isolation portion is used to isolate the adjacent active regions 102 . .
  • STI shallow trench isolation
  • Step S13 forming a node contact region 101 , a gate and a bit line contact region 103 on each active region 102 , the structure formed in this step is shown in FIG. 3 a , wherein the gate is located on the node contact on the active region 102 Between the region 101 and the bit line contact region 103, and on the same active region 102, the gate electrode, the bit line contact region 103 and the node contact region 101 form a transistor with a thin film structure.
  • the node contact region 101 and the bit line contact region 103 can be prepared by the following method: First, the substrate 100 made of silicon material can be doped with boron ions, so as to form a P-type semiconductor in the substrate 100. The active region 102 is then implanted with dopant ions such as phosphorus ions into the active region 102 of the P-type semiconductor to form the node contact region 101 and the bit line contact region 103 of the N-type semiconductor within the active region 102 .
  • dopant ions such as phosphorus ions
  • the gate can be prepared by the following method: first, a gate trench is formed in the active region 102, and then a gate oxide layer, a gate isolation layer and a gate metal layer are sequentially deposited in the gate trench, and the gate oxide layer, The gate isolation layer and the gate metal layer constitute the gate.
  • the gate oxide layer is, for example, silicon dioxide
  • the material of the gate isolation layer includes but not limited to metal nitride, such as titanium nitride or tantalum nitride
  • the material of the gate metal layer includes but is not limited to metal or metal alloy , such as tungsten, aluminum, copper and their alloys.
  • the active regions 102 formed in the substrate 100 may be arranged in multiple columns, and each column includes a plurality of active regions 102. Meanwhile, the active regions 102 formed in the substrate 100 may also be arranged in multiple columns. Each row includes a plurality of active regions 102 , that is, the active regions 102 formed in the substrate 100 may be arranged in an array to form multiple rows and multiple columns of active regions 102 .
  • the first isolation portion in the extending direction of the active regions 102 in each row is provided with a conductive portion, and the gates on the active regions 102 in the active regions 102 in each row, and the gates in the active regions 102 in the row in the extending direction
  • the conductive parts provided in the first isolation part may collectively form a word line.
  • Step S14 forming a bit line contact plug 202 on each bit line contact region 103, and each bit line contact plug 202 is in contact with a corresponding bit line contact region 103; and in a plurality of active regions located in the same column In 102, a second isolation portion (not shown in the figure) is formed between the bit line contact regions 103 of every two adjacent active regions 102, and the second isolation portion is used to isolate the two adjacent bit line contact pillars. Plug 202.
  • the structure formed by this step is shown in FIGS. 3b and 3c.
  • the bit line contact plug 202 is electrically connected to the bit line contact region 103, and the bit line contact plug 202 can be made of doped polysilicon or metal.
  • Step S15 forming bit lines 203 on the bit line contact plugs 202 located on the active regions 102 in the same column and on the second isolation portions in the column, so that the bit lines 203 and the Each bit line is in contact with the plunger 202.
  • the structure formed in this step is shown in Figures 3b and 3c.
  • Each bit line 203 is electrically connected to a plurality of bit line contact plungers 202 located in the same row. Materials such as titanium and/or titanium nitride.
  • Step S16 forming bit line isolation walls 200 on each bit line 203 , the bit line isolation walls 200 are formed on the substrate 100 , and the bit line isolation walls 200 are parallel to each other.
  • Each bit line isolation wall 200 covers the surface of the bit line 203 and the side surface of the bit line contact plug 202; a trench 201 is formed between two adjacent bit line isolation walls 200, and each node contact region 10 on the substrate 100 is exposed to the in each groove 201 .
  • the structure formed by this step is shown in Figs. 3b and 3c.
  • Each bit line 203 is electrically connected to a plurality of bit line contact plugs 202 located in the same row.
  • the bit line isolation wall 200 can be made of silicon nitride.
  • the sacrificial column 300 can be prepared by the following method:
  • Step S21 forming a sacrificial layer 302 covering the bit line isolation walls 200 and filling the gaps between the bit line isolation walls 200 , wherein the material of the sacrificial layer 302 can be silicon oxide, for example, the structure formed in this step is shown in FIG. The layers are filled in each trench 201 and cover the surface of each line isolation wall 200 away from the substrate 100 .
  • Step S22 forming a mask layer 303 on the sacrificial layer 302 , the mask layer 303 includes a plurality of strip patterns 304 parallel to each other, and the extending direction of each strip pattern 304 and the extending direction of the bit line isolation wall are projected on the substrate 100
  • the structure formed by this step is shown in FIG. 5 .
  • the mask layer 303 covers the top surface of the sacrificial layer 302 , and a plurality of stripe patterns 304 are arranged on the mask layer 303 , and each stripe pattern 304 corresponds to each groove.
  • the staggered arrangement means that the extending direction of the strip patterns 304 and the extending direction of the grooves 201 are arranged at an angle, and the distances between the strip patterns 304 and the grooves 201 from the substrate 100 are not equal, that is, the strip patterns 304 and
  • the trenches 201 are located on two different layers, or the two layers are disposed in different layers.
  • the mask layer 303 can be prepared from a photoresist material, and the preparation method of forming the stripe pattern 304 on the mask layer 303 can be as follows: a patterned photolithography mask is arranged above the mask layer 303, and a patterned photolithography mask is arranged on the mask layer 303 by exposure, The pattern of the photolithography mask plate is reproduced on the mask layer 303 by developing, so that the stripe pattern 304 is formed on the mask layer 303 .
  • Step S23 etching the sacrificial layer 302 located in the gap between the bit line isolation walls 200 with the mask layer 303 having the stripe pattern 304 , wherein the sacrificial layer 302 corresponding to the intersection area of the stripe pattern 304 and the trench 201 is etched.
  • the etching depth of this area reaches to the substrate 100 to form holes in the intersection area of the stripe pattern 304 and the trench 201; in addition, the sacrificial layer 302 corresponding to the bit line isolation wall 200 is removed, but the bit line isolation wall 200 Not being etched, or in other words, the etching rate of the bit line isolation wall 200 is much lower than that of the sacrificial layer 302 , so that the etching depth of this region reaches the bit line isolation wall 200 .
  • Step S24 removing the mask layer 303 .
  • the method of removing the mask layer 303 may be to perform an exposure treatment first, the mask layer 303 undergoes a photochemical reaction, and then the mask layer 303 is subjected to a development treatment.
  • Step S25 removing the sacrificial layer 302 on the surface of the bit line isolation wall 200 away from the substrate 100 , leaving the sacrificial layer 302 in the trench 201 to form the sacrificial pillar 300 in the trench 201 , an etching method may be used in this step
  • the sacrificial layer 302 on the surface of the bit line isolation wall 200 away from the substrate 100 is removed to form a structure as shown in FIG. 6a, FIG. 6b and FIG.
  • the holes 305 and the sacrificial pillars 300 in one trench 201 are alternately arranged at intervals.
  • the sacrificial column 300 is obtained by etching the sacrificial layer 302 by using the stripe pattern 304 on the mask layer 303 . Therefore, the pattern of the fabricated photolithography mask is simpler, the photolithography mask is easier to prepare, and the stripe pattern 304 on the mask layer 303 is easier to prepare.
  • the sacrificial pillar 300 can be prepared by the following method:
  • Step S21 forming a sacrificial layer 302 covering the bit line isolation walls 200 and filling the gaps between the bit line isolation walls 200 .
  • the sacrificial layer 302 covers the surface of the bit line isolation walls 200 away from the substrate 100 .
  • the structure formed in this step is shown in FIG. 4 a , the sacrificial layer 302 is filled in each trench 201 and covers the surface of each line isolation wall 200 away from the substrate 100 .
  • Step S22 forming a mask layer 303 on the sacrificial layer 302, the material of the sacrificial layer 302 can be silicon oxide, for example, the mask layer 303 includes a plurality of regions corresponding to the trenches 201, and each region includes several openings Displacement arrangement with each node contact region 101 in the corresponding trench 201 , the dislocation arrangement means that the projections of several openings included in each region on the substrate 100 do not coincide with each node contact region 101 in the corresponding trench 201 , and Along the extending direction of the trenches 201 , the projections of the node contact regions 101 and the openings on the substrate 100 in the same trench 201 are alternately arranged.
  • the mask layer 303 can be prepared from a photoresist material, and the preparation method of forming an opening on the mask layer 303 can be as follows: a patterned photolithography mask is arranged above the mask layer 303, and a patterned photolithography mask is arranged on the mask layer 303 by exposure and development. The pattern of the photolithography mask is replicated on the mask layer 303 , so that several openings are formed on the mask layer 303 .
  • Step S23 Etching and removing the sacrificial layer 302 exposed in the opening to form a hole between every two adjacent node contact regions 101 in each trench 201.
  • the sacrificial layer exposed by the opening is 302 is etched away, while the sacrificial layer 302 shielded by the mask layer 303 is hardly etched, so that holes corresponding to the openings one-to-one are formed in the trenches 201 .
  • Step S24 removing the mask layer 303 .
  • the method of removing the mask layer 303 may be to perform an exposure treatment first, the mask layer 303 undergoes a photochemical reaction, and then the mask layer 303 is subjected to a development treatment.
  • Step S25 removing the sacrificial layer 302 on the surface of the bit line isolation wall 200 away from the substrate 100 , leaving the sacrificial layer 302 in the trench 201 to form the sacrificial pillar 300 in the trench 201 , an etching method may be used in this step
  • the sacrificial layer 302 on the surface of the bit line isolation wall 200 away from the substrate 100 is removed to form a structure as shown in FIG. 6a, FIG. 6b and FIG.
  • Each hole 305 in one trench 201 and each sacrificial column 300 are alternately arranged at intervals.
  • the structure of the bit line isolation wall 200 can be kept intact when the sacrificial layer 302 is etched, which is beneficial for the bit line isolation wall 200 to effectively insulate the bit lines 203 and the bit line contact the plunger 202.
  • the sacrificial layer 302 that covers the bit line isolation walls 200 and fills the gaps between the bit line isolation walls 200 can be prepared by the following method, as shown in FIG. 6f :
  • Step S211 using a spin coating method to form a silicon oxide material in the gaps between the bit line isolation walls 200 and on the surface of the bit line isolation walls 200 away from the substrate 100 .
  • the structure formed by this step is shown in FIG. 4b , and the surface of the silicon oxide material away from the substrate 100 is an uneven surface.
  • Step S212 curing the silicon oxide material.
  • the curing treatment can be, for example, an annealing treatment, and the curing treatment of the silicon oxide material can make the silicon oxide material fixed and shaped.
  • Step S213 polishing the cured silicon oxide material to form a sacrificial layer.
  • the polishing treatment may be, for example, mechanochemical polishing. Polishing the silicon oxide material can make the surface of the silicon oxide material away from the substrate 100 smooth, please refer to this Steps to form the structure As shown in FIG. 4a and FIG. 4c, the surface of the silicon oxide material far from the substrate 100 is a flat surface.
  • the supplementary layer 301 may adopt a low pressure chemical vapor deposition method, and polysilicon material is deposited on each sacrificial pillar 300 , the hole 305 and the bit line isolation wall 200 , and the deposited polysilicon material forms the supplementary layer. 301 .
  • the structure formed in this step is shown in FIG. 7 .
  • the supplementary layer 301 covers each of the sacrificial pillars 300 , the holes 305 and the bit line isolation walls 200 .
  • the reaction temperature is between 380°C and 500°C
  • the reaction pressure is between 1 Torr and 3 Torr
  • the reaction gases used are H 3 SiN(C 3 H 7 ) 2 , Si One of 2 H 6 (Chinese name is disilane) and SiH[N(CH 3 ) 2 ] 3 .
  • the thickness D of the formed supplementary layer 301 is between 1/4L-1/3L, wherein L is the minimum distance between the bottom sidewalls of two adjacent sacrificial pillars 300 in the same trench 201, and the minimum distance is the The distance between the side bottoms of two adjacent sacrificial pillars 300 facing each other.
  • the ion implantation of the supplementary layer 301 can be performed by the following method:
  • Step S41 forming a photoresist layer covering the top and side surfaces of the supplementary layer 301 on the supplementary layer 301 .
  • a spin coating method can be used to form a photoresist layer on the supplementary layer 301 .
  • Step S42 at least one etch-back implant process is performed, and each etch-back implant process includes: etch back part of the photoresist layer in the direction from the top to the bottom of the supplementary layer 301 to expose the top and part of the side surface of the supplementary layer 301 ;
  • the direction from the top to the bottom of the supplementary layer 301 is to perform ion implantation into the exposed supplementary layer 301, and the height of the photoresist layer on the side of the supplementary layer 301 before each etchback is greater than that on the side of the supplementary layer 301 after each etchback photoresist layer height.
  • an optical method can be used to first expose and then develop, and then the photoresist layer can be etched back.
  • oxygen plasma can also be used to etch.
  • Performing the etchback implantation process at least once may include multiple etchback implantation processes.
  • performing the etchback implantation process at least once includes performing the etchback implantation process twice, wherein:
  • the photoresist layer on the top of the sacrificial pillar 300 needs to be removed, so that ion implantation can be performed from the top of the supplementary layer 301 into the supplementary layer 301 subsequently.
  • part of the photoresist layer on the side of the sacrificial pillar 300 is also removed, so that the photoresist layer on the side of the sacrificial pillar 300 is also removed.
  • the height of the remaining photoresist layer is 2/3 of the height of the sacrificial pillar 300 (as shown in FIG. 8a ).
  • the depth of the ion implantation in the supplementary layer 301 is 1/3 of the height of the sacrificial pillar 300 (as shown in FIG. 8b ).
  • the photoresist layer of a certain height is removed along the direction from the top to the bottom of the supplementary layer 301 on the basis of the supplementary layer 301 retained during the first photoresist back etch.
  • the height of the photoresist layer on the side of the sacrificial pillar 300 is reduced, so that the supplementary layer 301 on the side of the sacrificial pillar 300 is exposed to a larger area for the second ion implantation.
  • the height of the remaining photoresist layer is 1/3 of the height of the sacrificial pillar 300 (as shown in FIG. 8c ).
  • the depth of the ion implantation supplementary layer 301 is 2/3 of the height of the sacrificial pillar 300 (as shown in FIG. 8d ).
  • the implanted ions may be phosphorus or boron.
  • the depth of the ion implantation in the supplementary layer 301 refers to the farthest distance of the ions from the top of the supplementary layer 301 when ions are implanted into the supplementary layer 301 from the top of the supplementary layer 301 .
  • Implanting phosphorus or boron into the supplementary layer 301 can reduce the rate at which the supplementary layer 301 is etched.
  • Step S43 removing the remaining photoresist layer, which can be removed by oxygen plasma etching, so that the etching process has strong controllability and good consistency.
  • the structure formed by this step is shown in FIG. 8e , the supplementary layer 301 is doped with ions, and the concentration of the ions doped in the supplementary layer 301 gradually increases from the top of the supplementary layer 301 away from the substrate 100 to the bottom of the supplementary layer 301 close to the substrate 100
  • the subsequent supplementary layer 301 is etched, the areas corresponding to different ion concentrations, the supplementary layer 301 is etched at a rate, and the area with a higher ion concentration is etched at a slower rate of the supplementary layer 301 .
  • the etchant used is NH 4 OH solution (named as ammonium hydroxide in Chinese), KOH solution (named as potassium hydroxide in Chinese)
  • NH 4 OH solution named as ammonium hydroxide in Chinese
  • KOH solution named as potassium hydroxide in Chinese
  • FIG. 9 A structure formed after etching the supplementary layer 301 is shown in FIG. 9 , the thickness of the supplementary layer 301 in the area of the etched supplementary layer 301 close to the substrate 100 is smaller than the thickness of the area of the supplementary layer 301 away from the substrate 100 Supplementary layer 301 thickness.
  • the insulating column 400 can be prepared by the following method:
  • Step S61 forming a silicon nitride layer 402 in the gap between the bit line isolation walls 200 and between every two adjacent sacrificial pillars 300 , the silicon nitride layer 402 covers the surface of the bit line isolation walls 200 and the sacrificial pillars 300 The surface of the supplementary layer 301 and the filled holes, the structure formed by this step is shown in FIG. 10a , the silicon nitride layer 402 is filled in each trench 201 and covers the surface of the bit line isolation wall 200 and the supplementary on the sacrificial pillar 300 The surface of layer 301 and fill in the holes.
  • one of the low pressure chemical vapor deposition method and the atomic deposition method may be used to form silicon nitride in the gap between the bit line isolation walls 200 and between every two adjacent sacrificial pillars 300 layer 402 .
  • the reaction gas used is SiH 4 (the Chinese name is silane).
  • the reaction gas used is a mixed gas of N 2 (named as nitrogen in Chinese) and H 2 (named as hydrogen in Chinese), and one of NH 3 (named as ammonia in Chinese).
  • Step S62 etching and removing part of the silicon nitride layer 402 , leaving the silicon nitride layer 402 located between the two adjacent sacrificial pillars 300 , that is, leaving the silicon nitride layer 402 in the hole, the silicon nitride layer 402
  • the insulating pillars 400 are formed. The structure formed in this step is shown in FIG. 10b. Each insulating pillar 400 in the same trench 201 is spaced from each sacrificial pillar 300, and each insulating pillar 400 is close to the sacrificial pillar 400. 300 is separated by a supplementary layer 301 .
  • a structure is formed as shown in FIG. 11a, and the sidewall of the supplementary layer 301 has steps.
  • a step S9 may be added: etching the sidewalls of the insulating pillars 400 , so that the sidewalls of the insulating pillars 400 exposed in the contact holes 401 are A vertical or inclined plane, the structure formed in this step is shown in FIG. 11b, and the sidewall of the formed insulating column 400 is a vertical or inclined plane.
  • the sidewall of the insulating wall 400 is a vertical or inclined plane, that is, the hole wall of the contact hole 401 is a vertical or inclined plane, which is helpful for subsequently filling the contact hole 401 with the material for forming the node contact plug 500 .
  • the dry etching method may be used when etching the sidewalls of the insulating pillars 400 , and the dry etching of the insulating pillars 400 is beneficial to make the sidewalls of the insulating walls 400 be inclined planes.
  • the sidewalls of the insulating pillars 400 are etched by dry etching, and the plasma used is SF 6 (the Chinese name is sulfur hexafluoride), CF 4 (the Chinese name is carbon tetrafluoride), O 2 (the Chinese name is carbon tetrafluoride) At least one of oxygen) and Ar (the Chinese name is argon).
  • an embodiment of the present application further provides a memory, which includes a substrate 100, and a plurality of active regions 102 are formed in the substrate 100, and each active region 102 includes Node contact area 101; a plurality of mutually parallel bit line isolation walls 200 are arranged on the substrate 100, and a plurality of node contact plugs 500 are arranged between two adjacent bit line isolation walls 200 to isolate two adjacent node contact columns For the insulating posts 400 of the plugs 500 , each node contact plug 500 is in contact with the node contact area 101 .
  • the sidewall of the node contact plug 500 in contact with the insulating pillar 400 may be a stepped surface.
  • the sidewall of the node contact plunger 500 in contact with the insulating column 400 may be a flat surface, and the sidewall of the node contact plunger 500 in contact with the insulating column 400 may be a vertical or inclined plane. From the top of the plug 500 to the bottom of the node contact plunger 500 , the sidewall of the node contact plunger 500 in contact with the insulating pillar 400 is inclined in a direction away from the insulating pillar 400 .
  • the active region 102 further includes a bit line contact region 103 , a bit line contact plunger 202 is arranged on the bit line contact region 103 , a bit line 203 is arranged on the bit line contact plunger 202 , and the bit line contacts The plunger 202 and the bit line 203 are located inside the bit line isolation wall 200 .
  • the bit line contact plug 202 is used to electrically connect the bit line contact region 103 and the bit line 203
  • the bit line isolation wall 200 is used to insulate the bit line contact plug 202 and the bit line 203, that is, the bit line isolation
  • the wall 200 can insulate the node contact plug 500 from the bit line contact plug 202 and can insulate the node contact plug 500 from the bit line 203 .
  • a plurality of node contact plugs 500 and insulating posts 400 for isolating two adjacent node contact plugs 500 are disposed between two adjacent bit line isolation walls 200 on the substrate 100 .
  • Each node contact plunger 500 is in contact with the node contact area 101, and the end of the node contact plunger 500 away from the substrate 100 is larger than the end of the node contact plunger 500 close to the substrate 100.
  • the node contact plunger 500 of this shape is prepared by The aperture of the contact hole 301 defined by the two adjacent insulating pillars 400 and the adjacent two bit line isolation walls 200 is equal to or larger than the hole bottom.
  • the sidewalls of the node contact plug 500 in contact with the insulating pillars 400 may be flat because the sidewalls of the insulating pillars 400 are inclined planes during the manufacturing process of the memory, and the inclined walls may be planes so that the node contacts can be formed.
  • the material forming the node contact plug 500 can be further easily entered into the contact hole 301, so that the structure of the node contact plug 500 is complete, and the node contact plug 500 and the node contact area 101 on the substrate 100 are effective. contacts, which in turn improves the performance of the memory.

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Abstract

本申请提供一种存储器及其制备方法，涉及半导体技术领域，该存储器的制备方法包括：提供基底；在相邻的位线隔离墙之间形成多个间隔排布的牺牲柱；在牺牲柱表面形成补充层；对补充层进行离子注入；对补充层进行刻蚀；在相邻的牺牲柱之间形成绝缘柱；去除牺牲柱和剩余补充层；在每个接触孔中形成节点接触柱塞。本申请实施例的存储器的制备方法，形成节点接触柱塞的材料更容易进入到接触孔中，并填充满整个接触孔，进而使得制备形成的节点接触柱塞的结构完整，提升存储器的性能。

Description

存储器及其制备方法
本申请要求于2021年01月04日提交中国专利局、申请号为202110004478.1、申请名称为“存储器及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种存储器及其制备方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
动态随机存储器一般包括多个带状结构的有源区，各有源区的两端形成节点接触区，各有源区的中间区域形成位线接触区，各有源区中，位线接触区和每个节点接触区之间设置一个栅极，如此，在各有源区上形成两个埋栅结构的MOSFET(英文名称为Metal-Oxide-Semiconductor Field Effect Transistor，中文名称为金属氧化物半导体场效应晶体管)。进一步，节点接触区连接电容器，电容器和节点接触区之间通过节点接触柱塞连接。
然而，在节点接触柱塞的制备过程中，形成的节点接触柱塞结构不完整，影响存储器的存储性能。
发明内容
本申请实施例的第一方面提供一种存储器的制备方法，其包括如下步骤：提供基底，所述基底上设置有多个相互平行的位线隔离墙；在相邻的所述位线隔离墙之间形成多个间隔排列的牺牲柱；在所述牺牲柱表面形成补充层，所述补充层至少覆盖所述牺牲柱之间相对的侧面；对所述补充层进行离子注入，使所述补充层的离子浓度从所述补充层的顶部至底部减小；对所述补充层进行刻蚀，使剩余所述补充层的厚度从剩余所述补充层顶部至底部减小； 在相邻的所述牺牲柱之间形成绝缘柱，所述绝缘柱的侧面与所述位线隔离墙以及剩余所述补充层接触；去除所述牺牲柱和剩余所述补充层，使所述绝缘柱与所述位线隔离墙共同围成多个接触孔；在所述接触孔中形成节点接触柱塞。
本申请实施例的第二方面提供一种存储器，其包括基底，所述基底上设置有多个相互平行的位线隔离墙，相邻的所述位线隔离墙之间设置有多个间隔排布的节点接触柱塞，以及隔离相邻的所述节点接触柱塞的绝缘柱，所述节点接触柱塞远离所述基底的一端等于或大于所述节点接触柱塞靠近所述基底的一端。
本申请实施例的存储器的制备方法，基底上设置有多个相互平行的位线隔离墙，相邻的位线隔离墙之间形成多个间隔排布的牺牲柱，牺牲柱的表面形成补充层，对补充层进行离子注入和刻蚀后，剩余补充层的厚度从剩余补充层顶部至底部减小，这使得相邻的牺牲柱在设置补充层之后，相邻牺牲柱上的补充层之间的距离由远离基底区域向靠近基底区域逐渐增大，填充在相邻的牺牲柱上补充层之间的绝缘柱在平行位线隔离墙的方向上，绝缘柱的尺寸由远离基底的区域向靠近基底的区域逐渐增大，之后，在去除牺牲柱和牺牲柱上的补充层后，相邻的绝缘柱之间形成的接触孔的孔口尺寸大于孔底的尺寸，如此，相邻的绝缘柱之间形成节点接触柱塞时，形成节点接触柱塞的材料更容易进入到接触孔中，并填充满整个接触孔，从而使得制备形成的节点接触柱塞的结构完整，存储器的性能提升。
本申请实施例所提供的存储器中，基底上的相邻两个位线隔离墙之间设置多个间隔排布的节点接触柱塞和隔离相邻的节点接触柱塞的绝缘柱，节点接触柱塞远离基底的一端大于节点接触柱塞靠近基底的一端，节点接触柱塞的这种形状能够使得节点接触柱塞的结构完整，存储器的性能得到提升。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的存储器及其制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1a为相关技术中存储器的结构参考图一；
图1b为相关技术中存储器的结构参考图二；
图2为本实施例的存储器的制备方法的流程图；
图3a为本实施例基底上设置位线隔离墙后的结构示意图；
图3b为图3a在AA线位置断开后的立体结构示意图；
图3c为图3b的正视图；
图3d为本实施例的位线隔离墙的制备流程图；
图4a为本实施例的基底上设置氧化硅层后的结构示意图一；
图4b为本实施例的基底上设置氧化硅层后的结构示意图二；
图4c为本实施例的基底上设置氧化硅层后的结构示意图三；
图5为本实施例的基底上的氧化硅层上设置掩膜层后的结构示意图；
图6a为本实施例的基底上设置牺牲柱的结构示意图一；
图6b为本实施例的基底上设置牺牲柱的结构示意图二；
图6c为图6b在BB线位置的断面图；
图6d为本实施例的牺牲柱的制备流程图一；
图6e为本实施例的牺牲柱的制备流程图二；
图6f为本实施例的氧化硅层的制备流程图；
图7为图6c图的牺牲柱上形成补充层的结构示意图；
图8a为图7中补充层上的光刻胶回刻掉牺牲柱的1/3的结构示意图；
图8b为图8a中补充层第一次注入离子后的结构示意图；
图8c为图8b中补充层上的光刻胶回刻掉牺牲柱的2/3的结构示意图；
图8d为图8c中补充层第二次注入离子后的结构示意图；
图8e为图8d中补充层上的光刻胶全部去除后的结构示意图；
图8f为本实施例中对补充层进行离子注入的制备流程图；
图9为对图8e中补充层进行选择性刻蚀后的结构示意图；
图10a为在图9中形成的接触孔中形成氮化硅层后的结构示意图；
图10b为回刻部分图10a中氮化硅后的结构示意图；
图10c为本实施例中绝缘柱的制备流程图；
图11a为去除图10b中牺牲柱和补充层后的结构示意图；
图11b为对图11a中绝缘柱刻蚀后的结构示意图；
图12为在图11b中相邻两个的绝缘之间形成节点接触柱塞后的结构视图。
附图标记：
100：基底；                      101：节点接触区；
102：有源区；                    103：位线接触区；
200：位线隔离墙；                201：沟槽；
202：位线接触柱塞；              203：位线；
300：牺牲柱；                    301：补充层；
302：牺牲层；                    303：掩膜层；
304：条形图案；                  305：孔洞；
306：光刻胶层；                  400：绝缘柱；
401：接触孔；                    402：氮化硅层；
500：节点接触柱塞。
具体实施方式
在相关技术中，存储器一般采用如下方法制备，该制备方法包括如下步骤：先在基底上形成多个相互平行的位线隔离墙，相邻两个位线隔离墙之间形成的沟槽暴露基底上的节点接触区；然后在每个沟槽内的各节点接触区上各形成一个牺牲柱，此步骤形成的结构如图1a所示，基底100上设置有多个位线隔离墙200，每相邻的两个位线隔离墙200形成沟槽201，基底100中的节点接触区暴露在沟槽201中；之后在每个沟槽201内的每相邻两个牺牲柱300之间形成绝缘柱；之后去除牺牲柱300，以在每个沟槽201内的每相邻两个绝缘柱之间形成暴露基底100内对应一个节点接触区的接触孔，再之后在每个接触孔中形成与该接触孔中暴露的节点接触区接触的节点接触柱塞，每个节点接触柱塞上形成有与该节点接触柱塞接触的电容器。
在上述存储器的制备方法中，在每个沟槽201内的各节点接触区上各形 成一个牺牲柱300的步骤包括：首先，在每个沟槽201内形成氧化硅层302，氧化硅层302覆盖各位线隔离墙200的侧面以及远离基底100的表面；然后，在氧化硅层302上形成掩膜层303，掩膜层303包括多个平行设置的条形图案304，条形图案304的延伸方向与位线隔离墙200的延伸方向在基底上的投影相交，此步形成的结构如图1b所示；接下来，以具有条形图案304的掩膜版303刻蚀位于位线隔离墙200之间的氧化硅层302，去除掩膜层303以及去除位线隔离墙200远离基底100表面上的氧化硅层302，保留沟槽201中的氧化硅层302，以形成位于沟槽201内的牺牲柱300。
然而，本申请的发明人发现，采用上述存储器的制备方法制作出的存储器中，节点接触柱塞结构不完整，出现这种问题的原因在于：在以具有条形图案304的掩膜版303刻蚀位线隔离墙200之间的氧化硅层302时，刻蚀液不仅会去除掉条形图案304与位线隔离墙200交错位置处的氧化硅层302，而且刻蚀液也会对沟槽201内被掩膜层303覆盖的氧化硅层302进行刻蚀，且刻蚀液对沟槽201内被掩膜层303覆盖的氧化硅层302的刻蚀速率，小于刻蚀液对沟槽201内暴露在条形图案304内氧化硅层302的刻蚀速率，使得沟槽201内被掩膜层303覆盖的氧化硅层302所形成的牺牲柱300中，牺牲柱300的截面尺寸(以垂直基底100且平行沟槽201延伸方向的平面为截面)从远离基底100到靠近基底100逐渐增大，进而使得后续在沟槽201内每相邻的两个牺牲柱300之间形成的绝缘柱400中，绝缘柱400的截面尺寸从远离基底100到靠近基底100逐渐减小。因此，在后续去除牺牲柱300后，在每个沟槽201内且每相邻两个绝缘柱400之间形成的接触孔中，接触孔的孔径尺寸从远离基底100到靠近基底100逐渐增大，也即，接触孔的孔口尺寸小于孔底的尺寸，使得在接触孔中形成与接触孔中节点接触区接触的节点接触柱塞时，形成节点接触柱塞的材料不容易进入到接触孔中，导致形成节点接触柱塞的材料无法填充满整个接触孔的概率增大，进而导致形成的节点接触柱塞的结构不完整有缺失，而节点接触柱塞的结构不完整会降低存储器的性能。
为此，本申请实施例提出一种存储器的制备方法，在该制备方法中，通过在牺牲柱上形成补充层，该补充层的离子浓度从远离基底的区域到靠近基底的区域补充层的离子浓度逐渐减小，并对该补充层进行刻蚀，使得补充层 的厚度从远离基底的区域到靠近基底的区域逐渐减小，之后在每相邻两个位线隔离墙之间间隙内的相邻两个牺牲柱之间形成的绝缘柱，绝缘柱的截面尺寸从远离基底到靠近基底逐渐增大，使得去除牺牲柱和补充层形成的接触孔中，接触孔的孔径尺寸从远离基底到靠近基底逐渐减小，也即，接触孔的孔口尺寸大于孔底的尺寸，这使得之后在接触孔中形成与接触孔中节点接触区接触的节点接触柱塞时，形成节点接触柱塞的材料更容易进入到接触孔中，从而使得形成的节点接触柱塞的结构完整无缺失，进而提高存储器的性能。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
本实施例提供了一种存储器的制备方法，用于制备存储器，例如用于制备动态随机存储器。请参阅图2，该制备方法包括如下步骤：
步骤S1：提供基底，该基底的结构如图3a所示，基底100上设置有多个相互平行的位线隔离墙200，相邻的位线隔离墙200之间形成暴露出基底100中的节点接触区101的沟槽201。
步骤S2：在相邻的位线隔离墙200之间形成多个间隔排布的牺牲柱，也即，在每个沟槽201内的各节点接触区101上各形成一个牺牲柱，此步骤形成的结构如图6a、图6b和图6c所示，每个牺牲柱300形成在对应的一个节点接触区101上，即牺牲柱300与节点接触区101一一对应，且与对应的节点接触区101接触。
步骤S3：在每个牺牲柱300的表面形成补充层，此步骤形成的结构如图7示，补充层301至少覆盖牺牲柱300之间相对的侧面，也即，补充层301至少多个覆盖牺牲柱300的侧面，例如，补充层301覆盖牺牲柱300的顶面和侧面。
步骤S4：对补充层301进行离子注入，使补充层301的离子浓度从补充层301的顶部至底部减小，此步骤形成的结构如图8e所示，其中，图8e中的“+”代表离子，“+”的浓度从图8e示出的补充层301的顶部到底部逐渐减小。
步骤S5：对补充层301进行刻蚀，使剩余补充层301的厚度从剩余补充层301顶部至底部减小，也即，剩余补充层301中靠近基底100的区域的补充层301的厚度小于补充层301中远离基底100的区域的补充层301的厚度，此步骤形成的结构如图9所示，补充层301的厚度指补充层301在图9示出的X方向的尺寸。
步骤S6：在每个沟槽201内且每相邻的两个牺牲柱300之间形成绝缘柱400，绝缘柱400的侧面与该绝缘柱400相邻的两个牺牲柱300上的剩余补充层301接触，且与位线隔离墙200接触，此步骤形成的结构如图10b所示，绝缘柱400和牺牲柱300间隔设置，绝缘柱400的侧面和牺牲柱300的侧面之间由补充层301隔离。
步骤S7：去除牺牲柱300和剩余补充层301，以在沟槽201内且位于该沟槽201内的每相邻的绝缘柱400之间形成接触孔401，也即，使得绝缘柱400与位线隔离墙200共同围成多个接触孔401，每个接触孔401暴露出基底100中对应的一个节点接触区101，此步骤形成的结构如图11a所示，每相邻的绝缘柱400之间形成接触孔401，在同一沟槽201内可以形成多个接触孔401，且同一沟槽201内的多个接触孔401与暴露在该沟槽201内的多个节点接触区101一一对应设置。
步骤S8：在每个接触孔401中形成与对应的节点接触区101接触的节点接触柱塞500，此步骤形成的结构如图12所示，节点接触柱塞500形成在接触孔401内，并与暴露在该接触孔401内的节点接触区101接触；或者说，在同一沟槽201内，每相邻的绝缘柱400之间设置有节点接触柱塞500，也即，节点接触柱塞500与绝缘柱400间隔设置。
在每个接触孔401中形成与对应的节点接触区101接触的节点接触柱塞500之后，还可以在每个节点接触柱塞500上形成电容器(图中未示出)。其中，电容器用于存储电荷，而节点接触柱塞500用于将节点接触区101与电容器电连接。
在本申请实施例提供的存储器的制备方法中，基底100上设置有多个相互平行的位线隔离墙200，相邻的位线隔离墙200之间形成多个间隔排布的牺牲柱300，牺牲柱300的表面形成补充层301，对补充层301进行离子注入和刻蚀后，剩余补充层301的厚度从剩余补充层301顶部至底部减小，这使 得相邻两个牺牲柱300在设置补充层301后，相邻牺牲柱300上的补充层301之间的距离由远离基底100的区域向靠近基底100的区域逐渐增大，进填充在沟槽201中相邻两个牺牲柱300上补充层301之间的绝缘柱400在平行位线隔离墙200的方向上，绝缘柱400的尺寸由远离基底100的区域向靠近基底100的区域逐渐增大，之后，在去除牺牲柱300和牺牲柱300上的补充层301后，每个沟槽201内相邻两个绝缘柱400之间形成的接触孔401的孔口尺寸大于孔底的尺寸，如此，在沟槽201内每相邻两个绝缘柱400之间形成节点接触柱塞500时，形成节点接触柱塞500的材料更容易进入到接触孔401中，并填充满整个接触孔401，使得制备形成的节点接触柱塞500的结构完整，存储器的性能提升。
此外，由于沟槽201内相邻两个绝缘柱400之间形成的接触孔401的孔口尺寸大于孔底的尺寸，与相关技术中接触孔401的孔口尺寸小于孔底的尺寸相比，形成节点接触柱塞500的材料填充接触孔401的速度更快，从而提高了制备节点接触柱塞500的效率。
在上述存储器的制备方法中，如图3d所示，基底100可以采用如下方法制备：
步骤S11：提供基底100，基底100可以采用硅或锗等材料制备，基底100可以为圆形或方形的板状结构，如图3a所示，基底100为方形板状结构。
步骤S12：在基底100内形成采用第一隔离部(图中未示出)隔离的多列有源区102，每列有源区102包括多个有源区102，如图3a所示，多个有源区102位于基底100中，且每个有源区102的部分区域，如中间区域被位于其上方的位线隔离墙200覆盖。第一隔离部例如是采用浅沟槽隔离结构(STI)法，在形成于基底100上的凹槽内填充二氧化硅的材料制备得到，第一隔离部用于隔离相邻的有源区102。
步骤S13：在每个有源区102上形成节点接触区101、栅极以及位线接触区103，此步骤形成的结构如图3a所示，其中，栅极位于有源区102上的节点接触区101和位线接触区103之间，且同一个有源区102上的栅极、位线接触区103和节点接触区101形成薄膜结构的晶体管。
在上述步骤S13中，节点接触区101和位线接触区103可以采用如下方法制备：首先，可以在由硅材料制备的基底100内掺杂硼离子，以在基底100 内形成P型半导体的有源区102，之后通过向P型半导体的有源区102注入例如磷离子的掺杂离子，形成位于有源区102内的N型半导体的节点接触区101和位线接触区103。
栅极可以采用如下方法制备：首先在有源区102内形成栅极槽，之后在栅极槽内依次沉积栅极氧化物层、栅极隔离层以及栅极金属层，栅极氧化物层、栅极隔离层和栅极金属层构成栅极。其中，栅极氧化物层例如为二氧化硅，栅极隔离层的材料包括但不限于金属氮化物，例如氮化钛或氮化钽，栅极金属层的材料包括但不限于金属或金属合金，例如钨、铝、铜及其合金。
在上述实施例中，形成在基底100内的各有源区102可以排列成多列，每列包括多个有源区102，同时，形成在基底100内的有源区102还可以排列成多行，每行包括多个有源区102，即形成在基底100内的各有源区102可以呈阵列排布，形成多行和多列有源区102。其中，每行有源区102延伸方向上的第一隔离部内设置有导电部，且每行有源区102中各有源区102上的栅极，以及该行有源区102延伸方向上的第一隔离部内设置的各导电部可以共同形成字线。
步骤S14：在每个位线接触区103上形成位线接触柱塞202，每个位线接触柱塞202与对应的一个位线接触区103接触；以及在位于同一列的多个有源区102中，每相邻两个有源区102的位线接触区103之间形成第二隔离部(图中未示出)，第二隔离部用于隔离与其相邻的两个位线接触柱塞202。此步骤形成的结构如图3b和3c所示，位线接触柱塞202与位线接触区103电性连接，位线接触柱塞202可以由掺杂多晶硅、金属制备。
步骤S15：在位于同一列的各有源区102上的位线接触柱塞202上、以及位于该列中各第二隔离部上形成位线203，以使位线203同时与位于同一列的各位线接触柱塞202接触，此步骤形成的结构如图3b和3c所示，每个位线203与位于同一行的多个位线接触柱塞202电性连接，位线203可以由钨、钛和/或氮化钛等材料制备。
步骤S16：在每个位线203上形成位线隔离墙200，这些位线隔离墙200形成在基底100上，且这些位线隔离墙200相互平行。每个位线隔离墙200覆盖位线203的表面和位线接触柱塞202的侧面；相邻两个位线隔离墙200之间形成沟槽201，基底100上的各节点接触区10暴露在各沟槽201内。此 步骤形成的结构如图3b和3c所示，每个位线203与位于同一行的多个位线接触柱塞202电性连接，位线隔离墙200可以由氮化硅制备。
在上述存储器的制备方法中，如图6d所示，牺牲柱300可以采用如下方法制备：
步骤S21：形成覆盖位线隔离墙200并填充位线隔离墙200之间间隙的牺牲层302，其中，牺牲层302的材料例如可以是氧化硅，此步骤形成的结构如图4a所示，牺牲层填充在各沟槽201内，且覆盖在各位线隔离墙200远离基底100的表面。
步骤S22：在牺牲层302上形成掩膜层303，掩膜层303包括互相平行的多个条形图案304，各条形图案304的延伸方向与位线隔离墙的延伸方向在基底100上投影相交，此步骤形成的结构如图5所示，掩膜层303覆盖在牺牲层302的顶面，且掩膜层303上设置有多个条形图案304，各条形图案304与各沟槽201交错设置，其中，交错设置指条形图案304的延伸方向与沟槽201的延伸方向呈夹角设置，条形图案304和沟槽201距离基底100的距离不相等，即条形图案304和沟槽201位于两个不同层上，或者说两者异层设置。
掩膜层303可以由光刻胶材料制备而成，在掩膜层303上形成条形图案304的制备方法可以为：在掩膜层303上方设置图形化的光刻掩膜板，采用曝光、显影的方式在掩膜层303上复制光刻掩膜板的图形，如此，在掩膜层303上形成条形图案304。
步骤S23：以具有条形图案304的掩膜层303刻蚀位于位线隔离墙200之间间隙中的牺牲层302，其中，条形图案304和沟槽201的交叉区域对应的牺牲层302被去除，此区域的刻蚀深度直至基底100，以在条形图案304和沟槽201的交叉区域形成孔洞；此外，与位线隔离墙200对应的牺牲层302被去除，但位线隔离墙200不被刻蚀，或者说位线隔离墙200的被刻蚀速率远小于牺牲层302的被刻蚀速率，使得此区域的刻蚀深度直至位线隔离墙200。
步骤S24：去除掩膜层303，去除掩膜层303的方式可以为先进行曝光处理，掩膜层303发生光致化学反应，之后对掩膜层303进行显影处理。
步骤S25：去除位线隔离墙200远离基底100的表面上的牺牲层302，保留沟槽201中的牺牲层302，以形成位于沟槽201内的牺牲柱300，此步骤中 可以采用刻蚀方式去除位线隔离墙200远离基底100的表面上的牺牲层302，形成的结构如图6a、图6b和图6c所示，各孔洞305和各牺牲柱300位于对应的沟槽201内，且同一个沟槽201内的各孔洞305和各牺牲柱300交替间隔设置。
本实施例中，利用掩膜层303上的条形图案304刻蚀牺牲层302，得到牺牲柱300的方式，条形图案304的开窗面积大于条形图案304和沟槽201的交叉区域，因而，制作的光刻掩膜板的图形更简单，光刻掩膜板更易制备，掩膜层303上的条形图案304更易制备。
在另一些实施方式中，请参阅图6e所示，牺牲柱300可以采用如下方法制备：
步骤S21：形成覆盖位线隔离墙200并填充位线隔离墙200之间间隙的牺牲层302，牺牲层302覆盖各位线隔离墙200远离基底100的表面，此步骤形成的结构如图4a所示，牺牲层302填充在各沟槽201内，且覆盖在各位线隔离墙200远离基底100的表面。
步骤S22：在牺牲层302上形成掩膜层303，牺牲层302的材料例如可以为氧化硅，掩膜层303包括与各沟槽201对应的多个区域，且每个区域包括的数个开口与对应沟槽201内的各节点接触区101错位排布，错位排布指每个区域包括的数个开口在基底100上的投影与对应沟槽201内的各节点接触区101不重合，且沿沟槽201的延伸方向，同一沟槽201内的各节点接触区101与各开口在基底100上的投影交替排布。
掩膜层303可以由光刻胶材料制备而成，在掩膜层303上形成开口的制备方法可以为：在掩膜层303上方设置图形化的光刻掩膜板，采用曝光、显影方式在掩膜层303上复制光刻掩膜板的图形，如此，在掩膜层303上形成数个开口。
步骤S23：刻蚀去除暴露在开口内的牺牲层302，以在每个沟槽201内的每相邻的两个节点接触区101之间形成一个孔洞，此步骤中，开口暴露出的牺牲层302被刻蚀掉，而被掩膜层303遮挡的牺牲层302几乎不会被刻蚀，如此，在沟槽201内形成与开口一一对应的孔洞。
步骤S24：去除掩膜层303，去除掩膜层303的方式可以为先进行曝光处理，掩膜层303发生光致化学反应，之后对掩膜层303进行显影处理。
步骤S25：去除位线隔离墙200远离基底100的表面上的牺牲层302，保留沟槽201中的牺牲层302，以形成位于沟槽201内的牺牲柱300，此步骤中可以采用刻蚀方式去除位线隔离墙200远离基底100的表面上的牺牲层302，形成的结构如图6a、图6b和图6c所示，各孔洞305和各牺牲柱300位于对应的沟槽201内，且同一个沟槽201内的各孔洞305与各牺牲柱300交替间隔设置。
本实施例中，利用掩膜层303上的开口刻蚀牺牲层302时，可以使得位线隔离墙200的在刻蚀牺牲层302时结构保持完整，有利于位线隔离墙200有效绝缘位线203和位线接触柱塞202。
形成覆盖位线隔离墙200并填充位线隔离墙200之间间隙的牺牲层302，可以采用如下方法制备，请参阅图6f所示：
步骤S211：采用旋转涂覆法，在位线隔离墙200之间间隙内以及位线隔离墙200远离基底100的表面形成氧化硅材料，旋转涂覆法是指利用旋转产生的离心力，将溶胶、溶液或悬浊液等均匀平铺到基底100表面的方法，旋转涂覆法可以快速涂覆氧化硅材料。此步骤形成的结构如图4b所示，氧化硅材料远离基底100的表面为凹凸不平的表面。
步骤S212：对氧化硅材料进行固化处理。固化处理例如可以是退火处理，对氧化硅材料进行固化处理可以使得氧化硅材料固定成型。
步骤S213：对固化的氧化硅材料进行抛光处理，以形成牺牲层，抛光处理例如可以是机械化学抛光，对氧化硅材料进行抛光处理，可以使得氧化硅材料远离基底100的表面平整，请参阅此步骤形成的结构图4a和图4c，氧化硅材料远离基底100的表面为平整的表面。
本实施例的存储器的制备方法中，补充层301可以采用低压化学气相沉积法，在每个牺牲柱300上、孔洞305和位线隔离墙200上沉积多晶硅材料，沉积的多晶硅材料即形成补充层301，此步骤形成的结构如图7所示，补充层301覆盖每个牺牲柱300上、孔洞305和位线隔离墙200。
其中，采用低压化学气相沉积法沉积多晶硅材料时，反应温度在380℃-500℃之间，反应气压在1Torr-3Torr之间，使用的反应气体为H 3SiN(C 3H 7) 2、Si 2H 6(中文名为乙硅烷)、SiH[N(CH 3) 2] 3中的一种。形成的补充层301的厚度D在1/4L-1/3L之间，其中，L为同一沟槽201内相邻两个牺牲柱300的底部 侧壁之间的最小距离，该最小距离为相邻两个牺牲柱300彼此朝向对方的侧面底部之间的距离。
本实施例的存储器的制备方法，请参阅图8f所示，对补充层301进行离子注入，可以采用如下方法：
步骤S41：在补充层301上形成覆盖补充层301的顶部和侧面的光刻胶层。此步骤中，可以采用旋转涂覆法，在补充层301上形成光刻胶层。
步骤S42：至少进行一次回刻注入过程，每次回刻注入过程包括：从补充层301的顶部至底部的方向回刻部分光刻胶层，以暴露出补充层301的顶部和部分侧面，以及从补充层301的顶部至底部的方向对暴露出的补充层301内进行离子注入，每次回刻前位于补充层301的侧面上的光刻胶层高度大于每次回刻后位于补充层301的侧面上的光刻胶层高度。其中，对光刻胶层进行回刻的时候，可以采用光学方法先曝光后显影，进而回刻光刻胶层，当然，也可以采用氧等离子体进行刻蚀。
至少进行一次回刻注入过程可以包括多次回刻注入过程，例如，在一些实施方式中，至少进行一次回刻注入过程包括进行两次回刻注入过程，其中：
第一次回刻光刻胶层时，需要去除位于牺牲柱300顶部的光刻胶层，以便后续从补充层301的顶部向补充层301内进行离子注入。在一些实施例中，第一次回刻光刻胶层时，除了去除了位于牺牲柱300顶部的光刻胶层外，还会去除位于牺牲柱300侧面上的部分光刻胶层，使得位于牺牲柱300的侧面的部分补充层301暴露出来，以便于进行第一次离子注入。第一次回刻光刻胶层后，保留的光刻胶层的高度为牺牲柱300的高度的2/3(如图8a所示)，当从补充层301的顶部向补充层301内进行第一次离子注入时，离子注入补充层301内的深度为牺牲柱300高度的1/3(如图8b所示)。
第二次回刻光刻胶层时，在第一次回刻光刻胶层时保留的补充层301基础上，沿从补充层301的顶部至底部的方向，去除一定高度的光刻胶层，使得位于牺牲柱300的侧面上的光刻胶层的高度减小，进而使得位于牺牲柱300的侧面的补充层301暴露出来更大的面积，以便于进行第二次离子注入。第二次回刻光刻胶层后，保留的光刻胶层的高度为牺牲柱300的高度的1/3(如图8c所示)，当从补充层301的顶部向补充层301内进行第二次离子注入时，离子注入补充层301的深度为牺牲柱300高度的2/3(如图8d所示)。
从补充层301的顶部至底部的方向对暴露出的补充层301进行离子注入时，注入离子可以为磷或者硼。离子注入补充层301的深度是指从补充层301的顶部起，向补充层301内注入离子时，离子相对补充层301的顶部的最远距离。在补充层301中注入磷或者硼，可以降低补充层301被刻蚀的速率。
步骤S43：去除剩余光刻胶层，可以采用氧等离子体刻蚀去除，以使刻蚀过程可控性强，一致性好。此步骤形成的结构如图8e所示，补充层301内掺杂有离子，且补充层301中掺杂的离子的浓度从补充层301远离基底100的顶部到补充层301靠近基底100的底部逐渐减小，使得后续补充层301被刻蚀时，不同离子浓度对应的区域，补充层301被刻蚀的速率，且离子浓度越高的区域，补充层301被刻蚀的速率越慢。
本实施例的存储器的制备方法，对补充层301进行选择性刻蚀时，采用的刻蚀液为NH 4OH溶液(中文名为氢氧化铵)、KOH溶液(中文名为氢氧化钾)中的一种，对补充层301刻蚀后形成的结构如图9所示，刻蚀后的补充层301中靠近基底100的区域的补充层301的厚度小于补充层301中远离基底100的区域的补充层301的厚度。
本实施例的存储器的制备方法，请参阅图10c，绝缘柱400可以采用如下方法制备：
步骤S61：在位线隔离墙200之间间隙内且每相邻的两个牺牲柱300之间形成氮化硅层402，氮化硅层402覆盖位线隔离墙200的表面、牺牲柱300上的补充层301的表面以及填充孔洞，此步骤形成的结构如图10a所示，氮化硅层402填充在各沟槽201内，且覆盖位线隔离墙200的表面、牺牲柱300上的补充层301的表面以及填充在孔洞内。
在上述步骤S61中，可以采用低压化学气相沉积法、原子沉积法中的其中一种方式，在位线隔离墙200之间间隙内且每相邻的两个牺牲柱300之间形成氮化硅层402。其中，采用低压化学气相沉积法在位线隔离墙200之间间隙内且每相邻的两个牺牲柱300之间形成氮化硅层402时，使用的反应气体为SiH 4(中文名为硅烷，又叫四氢化硅)、SiH 2Cl 2(中文名为二氯甲硅烷)中的一种，采用原子沉积法在位线隔离墙200之间间隙内且每相邻的两个牺牲柱300之间形成氮化硅层402时，使用的反应气体为N 2(中文名为氮气)和H 2(中文名为氢气)的混合气体、NH 3(中文名为氨气)中的一种。
步骤S62：刻蚀去除部分氮化硅层402，保留位于相邻两个牺牲柱300之间的氮化硅层402，也即，保留孔洞中的氮化硅层402，该氮化硅层402形成绝缘柱400，此步骤形成的结构如图10b所示，在同一沟槽201内的各绝缘柱400与各牺牲柱300间隔设置，且每个绝缘柱400和该绝缘柱400靠近的牺牲柱300之间由补充层301隔开。
本实施例的存储器的制备方法，去除牺牲柱300和剩余补充层301后，形成的结构如图11a所示，补充层301的侧壁具有台阶。本实施例的存储器的制备方法，可以在步骤S7之后，且在步骤S8之前，增加步骤S9：刻蚀绝缘柱400的侧壁，以使暴露在接触孔401中的绝缘柱400的侧壁为竖直或者倾斜的平面，此步骤形成的结构如图11b所示，形成的绝缘柱400的侧壁为竖直或者倾斜的平面。绝缘壁400的侧壁为竖直或者倾斜的平面，也即，接触孔401的孔壁为竖直或者倾斜的平面，有助于后续在接触孔401中填充形成节点接触柱塞500的材料。
其中，刻蚀绝缘柱400的侧壁时可以采用干法刻蚀法，干法刻蚀绝缘柱400有利于使得绝缘壁400的侧壁为倾斜的平面。采用干法刻蚀法刻蚀绝缘柱400的侧壁，采用的等离子体为SF 6(中文名为六氟化硫)、CF 4(中文名为四氟化碳)、O 2(中文名为氧气)、Ar(中文名为氩气)中的至少一种。
请参阅图3a、图6a、图6b以及图12所示，本申请实施例还提供一种存储器，其包括基底100，基底100中形成有多个有源区102，每个有源区102包括节点接触区101；基底100上设置有多个相互平行的位线隔离墙200，相邻两个位线隔离墙200之间设置有多个节点接触柱塞500和隔离相邻两个节点接触柱塞500的绝缘柱400，每个节点接触柱塞500与节点接触区101接触，节点接触柱塞500远离基底100的一端大于节点接触柱塞500靠近基底100的一端。
需要说明的是，在一些实施方式中，节点接触柱塞500与绝缘柱400接触的侧壁可以为台阶面。在另一些实施方式中，节点接触柱塞500与绝缘柱400接触的侧壁可以为平面，节点接触柱塞500与绝缘柱400接触的侧壁可以为竖直或者倾斜的平面，从节点接触柱塞500的顶部到节点接触柱塞500的底部的方向，节点接触柱塞500与绝缘柱400接触的侧壁向背离绝缘柱400的方向倾斜。
本实施例的存储器，有源区102还包括位线接触区103，位线接触区103上设置有位线接触柱塞202，位线接触柱塞202的上设置有位线203，位线接触柱塞202和位线203位于位线隔离墙200内部。其中，位线接触柱塞202用于使得位线接触区103和位线203电性连接，位线隔离墙200用于对位线接触柱塞202和位线203绝缘，也即，位线隔离墙200能够使得节点接触柱塞500和位线接触柱塞202绝缘，以及能够使得节点接触柱塞500和位线203绝缘。
本申请实施例所提供的存储器中，基底100上的相邻两个位线隔离墙200之间设置多个节点接触柱塞500和隔离相邻两个节点接触柱塞500的绝缘柱400，每个节点接触柱塞500与节点接触区101接触，节点接触柱塞500远离基底100的一端大于节点接触柱塞500靠近基底100的一端，这种形状的节点接触柱塞500在制备的时候，由相邻两个绝缘柱400和相邻两个位线隔离墙200限定出的接触孔301的孔口等于或者大于孔底，接触孔301中形成节点接触柱塞500时，形成节点接触柱塞500的材料更容易进入到接触孔301中，得到节点接触柱塞500的结构完整，节点接触柱塞500能够与基底100上的节点接触区101有效接触，进而使得存储器的性能得到提升。此外，节点接触柱塞500与绝缘柱400接触的侧壁可以为平面是由于在存储器的制备过程中，绝缘柱400的侧壁为倾斜的平面造成的，倾斜壁可以为平面可以使得形成节点接触柱塞500时，能够进一步使得形成节点接触柱塞500的材料更容易进入到接触孔301中，得到节点接触柱塞500的结构完整，节点接触柱塞500与基底100上的节点接触区101有效接触，进而使得存储器的性能得到提升。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以 在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (19)

  1. 一种存储器的制备方法，包括如下步骤：
    提供基底，所述基底上设置有多个相互平行的位线隔离墙；
    在相邻的所述位线隔离墙之间形成多个间隔排列的牺牲柱；
    在所述牺牲柱表面形成补充层，所述补充层至少覆盖所述牺牲柱之间相对的侧面；
    对所述补充层进行离子注入，使所述补充层的离子浓度从所述补充层的顶部至底部减小；
    对所述补充层进行刻蚀，使剩余所述补充层的厚度从剩余所述补充层顶部至底部减小；
    在相邻的所述牺牲柱之间形成绝缘柱，所述绝缘柱的侧面与所述位线隔离墙以及剩余所述补充层接触；
    去除所述牺牲柱和剩余所述补充层，使所述绝缘柱与所述位线隔离墙共同围成多个接触孔；
    在所述接触孔中形成节点接触柱塞。
  2. 根据权利要求1所述的存储器的制备方法，其中，对所述补充层进行离子注入的步骤包括：
    在所述补充层上形成覆盖所述补充层的顶部和侧面的光刻胶层；
    至少进行一次回刻注入过程，每次所述回刻注入过程包括：从所述补充层的顶部至底部的方向回刻部分所述光刻胶层，以暴露出所述补充层的顶部和部分侧面，以及从所述补充层的顶部至底部的方向对暴露出的所述补充层进行离子注入，每次回刻前位于所述补充层的侧面上的所述光刻胶层高度大于每次回刻后位于所述补充层的侧面上的所述光刻胶层高度；
    去除剩余所述光刻胶层。
  3. 根据权利要求2所述的存储器的制备方法，其中，至少进行一次所述回刻注入过程包括进行两次所述回刻注入过程，其中，第一次回刻所述光刻胶层后，保留的所述光刻胶层位于所述补充层侧面上的高度为所述牺牲柱的高度的2/3；
    第二次回刻所述光刻胶层后，保留的所述光刻胶层位于所述补充层侧面上的高度为所述牺牲柱的高度的1/3。
  4. 根据权利要求2所述的存储器的制备方法，其中，从所述补充层的顶部至底部的方向对暴露出的所述补充层进行离子注入时，所述离子为磷或者硼。
  5. 根据权利要求2所述的存储器的制备方法，其中，去除剩余所述光刻胶层时采用氧等离子体刻蚀去除。
  6. 根据权利要求1所述的存储器的制备方法，其中，对所述补充层进行刻蚀时，采用的刻蚀液为NH 4OH溶液、KOH溶液中的一种。
  7. 根据权利要求1所述的存储器的制备方法，其中，在去除所述牺牲柱和剩余所述补充层之后，且在所述接触孔中形成所述节点接触柱塞的步骤之前，所述制备方法还包括：
    刻蚀所述绝缘柱的侧壁，以使暴露在所述接触孔中的所述绝缘柱的侧壁为竖直或倾斜的平面。
  8. 根据权利要求7所述的存储器的制备方法，其中，刻蚀所述绝缘柱的侧壁时采用干法刻蚀法。
  9. 根据权利要求8所述的存储器的制备方法，其中，采用干法刻蚀法刻蚀所述绝缘柱的侧壁，采用的等离子体为SF 6、CF 4、O 2、Ar中的一种。
  10. 根据权利要求1所述的存储器的制备方法，其中，所述在相邻的所述位线隔离墙之间形成多个间隔排列的牺牲柱的步骤包括：
    形成覆盖所述位线隔离墙并填充所述位线隔离墙之间间隙的牺牲层；
    在所述牺牲层上形成掩膜层，所述掩膜层包括互相平行的多个条形图案，所述条形图案的延伸方向与所述位线隔离墙的延伸方向在所述基底上的投影相交；
    以具有所述条形图案的所述掩膜层刻蚀位于所述位线隔离墙之间间隙中的所述牺牲层，以在所述位线隔离墙之间形成孔洞，所述孔洞底部暴露出所述基底；
    去除所述掩膜层；
    去除所述位线隔离墙顶部表面的所述牺牲层，保留所述位线隔离墙之间间隙中的剩余所述牺牲层，以形成所述牺牲柱。
  11. 根据权利要求10所述的存储器的制备方法，其中，形成覆盖所述位线隔离墙并填充所述位线隔离墙之间间隙的牺牲层的步骤包括：
    采用旋转涂覆法，在所述位线隔离墙之间间隙内以及所述位线隔离墙远离所述基底的表面形成氧化硅材料；
    对所述氧化硅材料进行固化处理；
    对固化的所述氧化硅材料进行抛光处理，以形成所述牺牲层。
  12. 根据权利要求10所述的存储器的制备方法，其中，在所述牺牲柱表面形成补充层的步骤包括：
    采用低压化学气相沉积法，在所述牺牲柱表面、所述孔洞内和所述位线隔离墙表面沉积多晶硅材料，以形成所述补充层。
  13. 根据权利要求12所述的存储器的制备方法，其中，采用低压化学气相沉积法沉积所述多晶硅材料时，反应温度在380℃-500℃之间，反应气压在1Torr-3Torr之间，使用的反应气体为H 3SiN(C 3H 7) 2、Si 2H 6、SiH[N(CH 3) 2] 3中的一种。
  14. 根据权利要求12所述的存储器的制备方法，其中，所述补充层的厚度D在1/4L-1/3L之间，其中，L为所述位线隔离墙之间间隙内相邻两个所述牺牲柱的底部侧壁之间的最小距离。
  15. 根据权利要求10所述的存储器的制备方法，其中，在相邻的所述牺牲柱之间形成绝缘柱的步骤包括：
    在所述位线隔离墙之间间隙内且每相邻的两个所述牺牲柱之间形成氮化硅层，所述氮化硅层覆盖所述位线隔离墙的表面、所述牺牲柱上的所述补充层的表面以及填充在所述孔洞中；
    刻蚀去除部分所述氮化硅层，保留所述孔洞中的所述氮化硅层，以形成所述绝缘柱。
  16. 根据权利要求15所述的存储器的制备方法，其中，采用低压化学气相沉积法、原子沉积法中的一种方式，在所述位线隔离墙之间间隙内且每相邻的两个所述牺牲柱之间形成氮化硅层。
  17. 根据权利要求16所述的存储器的制备方法，其中，采用低压化学气相沉积法在所述位线隔离墙之间间隙内且每相邻的两个所述牺牲柱之间形成氮化硅层时，使用的反应气体为SiH 4、SiH 2Cl 2中的一种；或者，
    采用原子沉积法在所述位线隔离墙之间间隙内且每相邻的两个所述牺牲柱之间形成氮化硅层时，使用的反应气体为N 2和H 2的混合气体、NH 3中的一 种。
  18. 一种存储器，包括基底，所述基底上设置有多个相互平行的位线隔离墙，相邻的所述位线隔离墙之间设置有多个间隔排布的节点接触柱塞，以及隔离相邻的所述节点接触柱塞的绝缘柱，所述节点接触柱塞远离所述基底的一端等于或大于所述节点接触柱塞靠近所述基底的一端。
  19. 根据权利要求18所述的存储器，其中，所述节点接触柱塞与所述绝缘柱接触的侧壁为竖直或倾斜的平面。
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