WO2022142196A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2022142196A1
WO2022142196A1 PCT/CN2021/102238 CN2021102238W WO2022142196A1 WO 2022142196 A1 WO2022142196 A1 WO 2022142196A1 CN 2021102238 W CN2021102238 W CN 2021102238W WO 2022142196 A1 WO2022142196 A1 WO 2022142196A1
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Prior art keywords
transistor
channel region
substrate
width
semiconductor structure
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PCT/CN2021/102238
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English (en)
French (fr)
Inventor
吴保磊
王晓光
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长鑫存储技术有限公司
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Priority to EP21912952.5A priority Critical patent/EP4191673A4/en
Priority to US17/648,214 priority patent/US11348972B1/en
Publication of WO2022142196A1 publication Critical patent/WO2022142196A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Definitions

  • the embodiments of the present application relate to the technical field of semiconductors, and in particular, to a semiconductor structure and a method for manufacturing the semiconductor structure.
  • Memory is an important part of computer architecture, which has a decisive impact on the speed, integration and power consumption of the computer.
  • the basic unit of the traditional memory usually realizes the read/write function by connecting a memory unit (such as a magnetic memory unit) and a driving transistor in series.
  • a memory unit such as a magnetic memory unit
  • a driving transistor in series.
  • the read/write success rate of the memory based on the magnetic storage unit has different electrical requirements on the transistors, resulting in a low read/write success rate of the magnetic storage unit.
  • the present application provides a semiconductor structure and a method of fabricating the semiconductor structure.
  • a semiconductor structure comprising:
  • a first transistor including a first channel region within the substrate
  • a second transistor including a second channel region within the substrate, the second channel region having a different area from the first channel region, and the first transistor and the second the transistors have a common source or a common drain;
  • a memory cell connected to the common source or the common drain.
  • the area of the second channel region of the second transistor is different from that of the first channel region of the first transistor, which can adapt to different requirements of reading and writing, and improve the success rate of data reading and writing.
  • a method of manufacturing a semiconductor structure comprising:
  • a first transistor including a first channel region within the substrate and a second transistor are formed in the substrate, the second transistor including a second channel within the substrate a channel region, the second channel region has a different area than the first channel region, and the first transistor and the second transistor have a common source or a common drain;
  • a memory cell is formed, the memory cell is connected to the common source or the common drain.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided in an embodiment
  • FIG. 2 is a schematic plan view of a semiconductor structure provided in an embodiment
  • FIG. 3 is a schematic plan view of a semiconductor structure provided in another embodiment
  • FIG. 4 is a flowchart of a method for fabricating a semiconductor structure provided in an embodiment
  • FIG. 5 is a flow diagram of forming a first transistor and a second transistor in a substrate in one embodiment.
  • first doping type becomes the second doping type
  • second doping type can be the first doping type
  • the first doping type and the second doping type are different doping types, for example,
  • the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown may be contemplated due, for example, to manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the invention.
  • a semiconductor structure including a substrate 100 , a first transistor 200 , a second transistor 300 and a memory cell 400 .
  • the substrate 100 may be, but is not limited to, a semiconductor substrate such as a silicon substrate, gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. Both the first transistor 200 and the second transistor 300 are formed in the substrate 100 .
  • the first transistor 200 includes a first channel region 210 and a first terminal 220 .
  • the first channel region 210 is located inside the substrate 100
  • the first end 220 is located on the surface of the substrate 100 .
  • first channel region 210 may be a region where a conductive channel is formed when the first transistor 200 is turned on.
  • the first end 220 may be set as a source electrode, or the first end 220 may also be set as a drain electrode.
  • the second transistor 300 includes a second channel region 310 and a second terminal 320 .
  • the second channel region 310 is located inside the substrate 100
  • the second end 320 is located on the surface of the substrate 100 .
  • the second channel region 310 may be a region where a conductive channel is formed when the second transistor 300 is turned on.
  • the second terminal 320 may be set as a source, or the second terminal 320 may also be set as a drain.
  • the first end 220 of the first crystal 200 and the second end 320 of the second crystal 300 are heavily doped source or drain, both of which can be connected to signal lines, so that data can be read or written.
  • the first transistor 200 and the second transistor 300 have a common terminal 10 , and the common terminal 10 is a common source or a common drain of the first transistor 200 and the second transistor 300 .
  • One end of the memory cell 400 is connected to the common terminal 10, and the other end may be connected to the bit line BL.
  • the memory cell 400 may be connected to the common terminal 10 and the bit line BL respectively through the conductive plug 500 .
  • the memory cell 400 may be any one of a capacitive memory cell, a resistive memory cell, a magnetic memory cell, a phase-change memory cell, and a ferroelectric memory cell.
  • the area of the second channel region 310 of the second transistor 300 is different from that of the first channel region 210 of the first transistor 200 .
  • the first transistor 200 and the second transistor 300 have a common terminal 10, and the common terminal 10 may be a common source or a common drain of the first transistor 200 and the second transistor 300.
  • the common terminal 10 and The surface area of the substrate 100 between the first terminals 220 is the first channel area 210 of the first transistor 200
  • the surface area of the substrate 100 between the common terminal 10 and the second terminal 320 is the first channel area 210 of the second transistor 300 .
  • Two channel regions 310 are two channel regions 310 .
  • the area of the first channel region 210 may be the surface area of the first channel region 210 on the substrate 100; the area of the second channel region 310 may be the surface area of the second channel region 310 on the substrate 100; As shown in FIG. 1 , the first channel region 210 is U-shaped on the substrate 100 , and the area of the first channel region 210 may be the sum of the bottom area of the U-shape and the sidewall area of the U-shape. Similarly, the second channel region 310 is U-shaped on the substrate 100 , and the area of the second channel region 310 may be the sum of the bottom area of the U-shape and the sidewall area of the U-shape.
  • the semiconductor structure in this embodiment can adapt to different requirements of reading and writing, and improves the success rate of data reading and writing.
  • the first channel region 210 has a first width; the second channel region 310 has a second width, wherein the second width is greater than the first width.
  • the first width of the first channel region 210 may be the length of the line intersecting the first channel region 210 and the first end 220
  • the second width of the second channel region 310 may be the length of the second channel The length of the line where the region 310 intersects the second end 320 .
  • the memory cell 400 when it is a magnetic memory cell, it may include a magnetic tunnel junction MTJ.
  • the first transistor 200 with the first channel region 210 having a smaller width can be selected as the transistor for data reading, and the second transistor 300 with the second channel region 310 having a larger width can be used for writing data. transistor.
  • the first transistor 200 when reading data from the storage unit 400 , the first transistor 200 is turned on and the second transistor 300 is turned off; when writing data to the storage unit 400 , the first transistor 200 is turned off and the second transistor 300 is turned on.
  • the second width By setting the second width to be larger than the first width, the driving current of the second transistor 300 is larger than the driving current of the first transistor 200 , thereby satisfying the different requirements of the driving current of the first transistor 200 and the second transistor 300 .
  • the misread rate and the miswrite rate of the data can be reduced at the same time, thereby improving the success rate of reading and writing data.
  • the semiconductor structure may further include a bottom electrode BE and a top electrode TM, and the bottom electrode BE and the top electrode TM are located at the bottom and the top of the magnetic tunnel junction MTJ, respectively.
  • the second width is 2 to 5 times the first width.
  • the driving current of the second transistor can be effectively increased, and the problem that the width is too large and the occupation area is too large and the storage density is reduced can also be avoided.
  • the substrate 100 further includes at least one active region 110 .
  • the active region 110 is formed in the substrate 100 .
  • the first transistor 200 and the second transistor 300 are formed in the active region 110 .
  • One active area 110 corresponds to one memory cell.
  • ion implantation may be performed on the substrate 100 to form a well region of the first conductivity type.
  • the first conductivity type may be P-type or N-type.
  • the first terminal 220 of the first transistor 200 , the second terminal 320 of the second transistor 300 , and the common terminal 10 of the first transistor 200 and the second transistor 300 are N-type.
  • the first conductivity type is N type
  • the first terminal 220 of the first transistor 200 , the second terminal 320 of the second transistor 300 , and the common terminal 10 of the first transistor 200 and the second transistor 300 are P type.
  • a shallow trench isolation structure may also be formed on the substrate 100 , and a plurality of active regions 110 are isolated in the substrate 100 through the shallow trench isolation structure.
  • the first transistor 200 and the second transistor 300 are formed in the active region 110 .
  • the first transistors 200 and the second transistors 300 are distributed on opposite sides of the extending direction of the active region 110 . Also, the first transistor 200 and the second transistor 300 located in the active region 110 have a common terminal 10 .
  • the common terminal 10 can be connected to the memory cell, which can be a source electrode or a drain electrode.
  • the first transistor 200 and the second transistor 300 share the common terminal 10, so that the read and write operations of the memory cells can be effectively controlled, thereby improving the success rate of data read and write.
  • the semiconductor structure further includes a plurality of word lines WL extending along the first direction.
  • the word line WL is used to provide gate voltage signals for the first transistor 200 and the second transistor 300 .
  • the portion of the word line WL corresponding to the active region 110 may serve as the first gate 230 of the first transistor 200 and/or the second gate 330 of the second transistor 300 .
  • the word line WL may be a buried word line, and the two word lines WL pass through the same active region 110; the overlapping portion of the word line WL and the active region 110 may be They are the first gate 230 of the first transistor 200 and/or the second gate 330 of the second transistor 300, respectively.
  • the bottom and sidewalls of the first gate electrode 230 are opposite to the first channel region 210 of the first transistor 200
  • the bottom and sidewalls of the second gate electrode 330 are opposite to the second channel region 320 of the second transistor 300 .
  • the plurality of active regions 110 are arranged in a staggered manner. Moreover, each active region 110 extends along the second direction, and the second direction is inclined by a predetermined angle with respect to the first direction.
  • the preset angle may be between 15° and 30°.
  • the first transistors 200 and the second transistors 300 located in the adjacent active regions 110 are disposed opposite to each other.
  • each active region 110 is arranged in a dislocation array.
  • the arrangement of each active region 110 is more regular, so that the performance of the formed memory is more uniform and stable everywhere, and layout design is facilitated.
  • the first transistors 200 and the second transistors 300 located in the adjacent active regions 110 correspond to the same word line WL.
  • the density of the active regions 110 in the substrate 100 can be further increased, thereby increasing the density of the memory cells.
  • every two active regions 110 constitute an active region pair.
  • the pairs of active regions are arranged in an array.
  • the first transistors 200 of the two active regions 110 in each active region pair are adjacent and oppositely disposed.
  • two first transistors 200 can be arranged side by side in the central portion of each active region pair, so that the substrate space can be effectively saved. Therefore, in a limited substrate space, more active regions can be arranged, thereby increasing the density of memory cells.
  • the semiconductor structure may further include a plurality of word lines WL extending along the first direction. Meanwhile, it may be provided that the word lines WL may include first word lines WL1 and second word lines WL2 alternately arranged in the second direction.
  • the first word line WL1 passes through the first transistors 200 in the active regions in the active region pair in the same column, and the second word line WL2 passes through the second transistors 300 in the active region in the active region pair in the same column.
  • the two first transistors 200 in the same pair of active regions are penetrated by the same first word line WL1.
  • the density of the active regions 110 in the substrate 100 can be further increased, thereby increasing the density of the memory cells.
  • the extending direction of the active region 110 is the second direction.
  • the first direction and the second direction can be set to be perpendicular, thereby facilitating the layout design of the word lines WL.
  • a method for fabricating a semiconductor structure including the following steps:
  • Step S1 providing a substrate 100
  • Step S2 forming a first transistor 200 and a second transistor 300 in the substrate 100 , the first transistor 200 includes a first channel region 210 located in the substrate 100 , and the second transistor 300 includes a second transistor 300 located in the substrate 100
  • the channel region 310, the area of the second channel region 310 is different from that of the first channel region 110, and the first transistor 200 and the second transistor 300 have a common source or a common drain;
  • step S3 a memory cell 400 is formed, and the memory cell 400 is connected to the common source or the common drain.
  • the substrate 100 may be, but not limited to, a semiconductor substrate such as a silicon substrate, gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • a semiconductor substrate such as a silicon substrate, gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • the first transistor 200 includes a first channel region 210 and a first terminal 220 .
  • the first channel region 210 is located inside the substrate 100
  • the first end 220 is located on the surface of the substrate 100 .
  • the first channel region 210 may be a region where a conductive channel is formed when the first transistor 200 is turned on.
  • the first terminal 220 may be a drain or a source.
  • the second transistor 300 includes a second channel region 310 and a second terminal 320 .
  • the second channel region 310 is located inside the substrate 100
  • the second end 320 is located on the surface of the substrate 100 .
  • the second channel region 310 may be a region where a conductive channel is formed when the second transistor 300 is turned on.
  • the second terminal 320 may be set as a source or a drain.
  • the storage unit 400 is a device unit that can implement a storage function.
  • the memory cell 400 may be any one of a capacitive memory cell, a resistive memory cell, a magnetic memory cell, a phase-change memory cell, and a ferroelectric memory cell.
  • the area of the second channel region 310 of the second transistor 300 is different from that of the first channel region 210 of the first transistor 200 .
  • the first transistor 200 and the second transistor 300 have a common terminal 10, and the common terminal 10 may be a common source or a common drain of the first transistor 200 and the second transistor 300.
  • the common terminal 10 and The surface area of the substrate 100 between the first terminals 220 is the first channel area 210 of the first transistor 200
  • the surface area of the substrate 100 between the common terminal 10 and the second terminal 320 is the first channel area 210 of the second transistor 300 .
  • Two channel regions 310 are two channel regions 310 .
  • the area of the first channel region 210 may be the surface area of the first channel region 210 on the substrate 100; the area of the second channel region 310 may be the surface area of the second channel region 310 on the substrate 100; As shown in FIG. 1 , the first channel region 210 is U-shaped on the substrate 100 , and the area of the first channel region 210 may be the sum of the bottom area of the U-shape and the sidewall area of the U-shape. Similarly, the second channel region 310 is U-shaped on the substrate 100 , and the area of the second channel region 310 may be the sum of the bottom area of the U-shape and the sidewall area of the U-shape.
  • the semiconductor structure formed by the method of this embodiment can adapt to different requirements for reading and writing, thereby improving the success rate of data reading and writing.
  • the first channel region 210 has a first width; the second channel region 310 has a second width, wherein the second width is greater than the first width.
  • the first width of the first channel region 210 may be the length of the line intersecting the first channel region 210 and the first end 220
  • the second width of the second channel region 310 may be the length of the second channel The length of the line where the region 310 intersects the second end 320 .
  • the memory cell 400 when it is a magnetic memory cell, it may include a magnetic tunnel junction (MTJ).
  • MTJ magnetic tunnel junction
  • the first transistor 200 with the first channel region 210 having a smaller width can be selected as the transistor for data reading
  • the second transistor 300 with the second channel region 310 having a larger width can be selected as the transistor for data writing transistor.
  • the first transistor 200 when reading data from the storage unit 400 , the first transistor 200 is turned on and the second transistor 300 is turned off; when writing data to the storage unit 400 , the first transistor 200 is turned off and the second transistor 300 is turned on.
  • the second width By setting the second width to be larger than the first width, the driving current of the second transistor 300 is larger than the driving current of the first transistor 200 , thereby satisfying the different requirements of the driving current of the first transistor 200 and the second transistor 300 .
  • the misread rate and the miswrite rate of the data can be reduced at the same time, thereby improving the success rate of reading and writing data.
  • the second width is 2 to 5 times the first width.
  • the driving current of the second transistor can be effectively increased, and the problem that the width is too large and the occupation area is too large and the storage density is reduced can also be avoided.
  • step S2 include:
  • Step S21 forming an active region 110 in the substrate 100, the active region 110 includes a first part and a second part, and the width of the second part is greater than the width of the first part;
  • Step S22 forming a first gate trench 110a and a second gate trench 110b in the first portion and the second portion of the active region 110, respectively, and the active region is divided by the first gate trench 110a and the second gate trench 110b into the first end 220, the second end 320 and the common end 10 between the first end 220 and the second end 320;
  • step S23 the gate material is filled in the first gate trench 110 a and the second gate trench 110 b to form the first gate electrode 230 and the second gate electrode 330 .
  • the first gate 230 is the gate of the first transistor 200
  • the second gate 330 is the gate of the second transistor 300 .
  • the bottom and sidewalls of the first gate electrode 230 are opposite to the first channel region 210 .
  • the bottom and sidewalls of the second gate electrode 330 are opposite to the second channel region 310 .
  • the first transistor 200 includes a first gate 230 , a first channel region 210 , a first terminal 220 and a common terminal 10 .
  • the first terminal 220 and the common terminal 10 are the drain and the source of the first transistor 200 , respectively.
  • the second transistor 300 includes a second gate 330 , a second channel region 310 , a second terminal 320 and a common terminal 10 .
  • the second terminal 320 and the common terminal 10 are the drain and the source of the second transistor 300 , respectively.
  • a second gate dielectric layer 340 eg, an oxide layer
  • the first transistor 200 and the second transistor 300 share the common terminal 10, which can effectively improve the space utilization rate and reduce the size of the device.
  • the common terminal 10 may be a common source or a common drain of the first transistor 200 and the second transistor 300 .
  • the gate (first gate) of the first transistor 200 and the gate (second gate) of the second transistor 300 are both buried gate structures.
  • the present application is not limited to this, and the gates of the first transistor 200 and the second transistor 300 may also be in other forms (eg, planar gates).
  • the method for fabricating the semiconductor structure further includes: forming a plurality of word lines WL extending along the first direction in the substrate 100 .
  • the word line WL may be formed in the first gate trench 110a and the second gate trench 110b.
  • the portion of the word line WL corresponding to the active region 110 may serve as the first gate 230 of the first transistor 200 and/or the second gate 330 of the second transistor 300 .
  • the plurality of active regions 110 are arranged in a staggered manner, the active regions 110 extend along the second direction, and the second direction is inclined at a predetermined angle relative to the first direction.
  • the first transistors located in the adjacent active regions are disposed opposite to the second transistors; along the first direction, the first transistors located in the adjacent active regions The transistor and the second transistor correspond to the same word line.
  • every two active regions 110 constitute an active region pair, the active region pairs are arranged in an array, and the active regions extend along the second direction;
  • the first transistors 200 of the two active regions 110 in each active region pair are adjacent and disposed opposite to each other.
  • the method of fabricating the semiconductor structure further includes forming a plurality of word lines WL extending in the first direction in the substrate.
  • the word lines WL include first word lines WL1 and second word lines WL2 alternately arranged in the second direction.
  • the first word line WL1 runs through the first transistors 200 in the active region in the active region pair located in the same column
  • the second word line runs through the second transistor 300 in the active region in the active region pair located in the same column, and the same has
  • the two first transistors 200 in the pair of source regions are penetrated by the same first word line WL1.
  • the active region extends along a second direction, the first direction being perpendicular to the second direction.

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Abstract

一种半导体结构以及半导体结构的制造方法。半导体结构，包括：衬底；第一晶体管，包括位于衬底内的第一沟道区域；第二晶体管，包括位于衬底内的第二沟道区域，第二沟道区域的面积与第一沟道区域的面积不同，且第一晶体管和第二晶体管具有公共源极或公共漏极；存储单元，与公共源极或公共漏极相连。

Description

半导体结构及其制造方法
相关申请的交叉引用
本申请要求于2020年12月29日提交中国专利局、申请号为2020115980154、发明名称为“半导体结构以及半导体结构的形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及半导体技术领域，特别是涉及一种半导体结构以及半导体结构的制造方法。
背景技术
存储器是计算机体系结构中的重要组成部分，对计算机的速度、集成度和功耗等都有决定性的影响。传统的存储器的基本单元通常通过串联连接的一个存储单元(如磁存储单元)和一个驱动晶体管实现读写功能。但是，基于磁存储单元的存储器的读写成功率对晶体管的电性要求不同，造成磁存储单元的读写成功率较低。
发明内容
根据一些实施例，本申请提供一种半导体结构以及半导体结构的制造方法。
一种半导体结构，包括：
衬底；
第一晶体管，包括位于所述衬底内的第一沟道区域；
第二晶体管，包括位于所述衬底内的第二沟道区域，所述第二沟道区域的面积与所述第一沟道区域的面积不同，且所述第一晶体管和所述第二晶体管具有公共源极或公共漏极；及
存储单元，与所述公共源极或所述公共漏极相连。
上述半导体结构中第二晶体管的第二沟道区域的面积与第一晶体管的第一沟道区域的面积不同，可以适应读取与写入的不同要求，提高了数据读写的成功率。
一种半导体结构的制造方法，包括：
提供衬底；
在所述衬底中形成第一晶体管和第二晶体管，所述第一晶体管包括位于所述衬底内的第一沟道区域，所述第二晶体管包括位于所述衬底内的第二沟道区域，所述第二沟道区域的面积与所述第一沟道区域的面积不同，且所述第一晶体管和所述第二晶体管具有公共源极或公共漏极；及
形成存储单元，所述存储单元与所述公共源极或所述公共漏极相连。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的半导体结构的结构示意图；
图2为一实施例中提供的半导体结构的平面示意图；
图3为另一实施例中提供的半导体结构的平面示意图；
图4为一实施例中提供的半导体结构的制备方法的流程图；
图5为一实施例中在衬底中形成第一晶体管和第二晶体管的流程图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将 第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的 表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本发明的范围。
在一个实施例中，请参阅图1，提供一种半导体结构，包括衬底100、第一晶体管200、第二晶体管300以及存储单元400。
衬底100可以但不限于为硅衬底、氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。第一晶体管200以及第二晶体管300均形成于衬底100中。
第一晶体管200包括第一沟道区域210以及第一端220。第一沟道区域210位于衬底100内部，第一端220位于衬底100表面。
可以理解的是，第一沟道区域210可以为第一晶体管200打开时形成导电沟道的区域。
第一端220可以设置为源极，或者，第一端220也可以设置为漏极。
第二晶体管300包括第二沟道区域310以及第二端320。第二沟道区域310位于衬底100内部，第二端320位于衬底100表面。
同样地，可以理解的是，第二沟道区域310可以为第二晶体管300打开时形成导电沟道的区域。
第二端320可以设置为源极，或者，第二端320也可以设置为漏极。
第一晶体200的第一端220和第二晶体300的第二端320为重掺杂的源极或漏极，二者可以均连接信号线，进而可以进行数据的读取或者写入。
第一晶体管200和第二晶体管300具有公共端10，公共端10为第一晶体管200和第二晶体管300的公共源极或公共漏极。
存储单元400的一端连接公共端10，另一端可以连接位线BL。具体地， 存储单元400可以通过导电插塞500分别与公共端10以及位线BL连接。
作为示例，存储单元400可以为电容存储单元、电阻存储单元、磁存储单元、相变存储单元和铁电存储单元中的任一种。
第二晶体管300的第二沟道区域310的面积与第一晶体管200的第一沟道区域210的面积不同。具体的，如图1所示，第一晶体管200和第二晶体管300具有公共端10，公共端10可以为第一晶体管200和第二晶体管300的公共源极或公共漏极，公共端10和第一端220之间的衬底100的表面区域为第一晶体管200的第一沟道区域210，公共端10和第二端320之间的衬底100的表面区域为第二晶体管300的第二沟道区域310。第一沟道区域210的面积可以为第一沟道区域210在衬底100上的表面积；所述第二沟道区域310的面积可以为第二沟道区域310在衬底100上的表面积；如图1所述，第一沟道区域210在衬底100上为U形，第一沟道区域210的面积可以为所述U形的底部面积和所述U形的侧壁面积之和。同理，第二沟道区域310在衬底100上为U形，第二沟道区域310的面积可以为所述U形的底部面积和所述U形的侧壁面积之和。
因此，本实施例中的半导体结构可以适应读取与写入的不同要求，提高了数据读写的成功率。
在一个实施例中，第一沟道区域210具有第一宽度；第二沟道区域310具有第二宽度，其中，所述第二宽度大于所述第一宽度。如图1所示，第一沟道区域210的第一宽度可以为第一沟道区域210与第一端220相交的线长，第二沟道区域310的第二宽度可以为第二沟道区域310与第二端320相交的线长。
例如，当存储单元400为磁存储单元，其可以包括磁隧道结MTJ。此时， 可以选取具有较小宽度的第一沟道区域210的第一晶体管200作为数据读取用晶体管，而具有较大宽度的第二沟道区域310的第二晶体管300作为数据写入用晶体管。
具体的，当从存储单元400读取数据时，打开第一晶体管200，关闭第二晶体管300；当向存储单元400写入数据时，关闭第一晶体管200，打开第二晶体管300。通过将所述第二宽度设置为大于所述第一宽度，使得第二晶体管300的驱动电流大于第一晶体管200的驱动电流，从而满足第一晶体管200与第二晶体管300驱动电流不同的要求。此时，可以同时降低数据的误读率与误写率，从而提高数据的读写成功率。
进一步的，半导体结构还可以包括底部电极BE和顶部电极TM，底部电极BE和顶部电极TM分别位于磁隧道结MTJ的底部和顶部。
在一个实施例中，所述第二宽度为所述第一宽度的2～5倍。此时，既能有效增加第二晶体管的驱动电流，又能避免宽度过大导致占用面积过大进而降低存储密度的问题。
在一个实施例中，请参阅图2或者图3，衬底100内还包括至少一个有源区110。有源区110形成于衬底100中。第一晶体管200与第二晶体管300形成于有源区110之中。一个有源区110与一个存储单元相对应。
作为示例，具体地，请同时参阅图1，可以对衬底100进行离子注入形成第一导电类型的阱区。第一导电类型可以为P型，也可以为N型。当第一导电类型为P型时，第一晶体管200的第一端220、第二晶体管300的第二端320以及第一晶体管200和第二晶体管300的公共端10为N型。当第一导电类型为N型时，第一晶体管200的第一端220、第二晶体管300的第二端320以及第一晶体管200和第二晶体管300的公共端10为P型。
衬底100上还可以形成浅沟槽隔离结构(STI)，通过浅沟槽隔离结构于衬底100内隔离出多个有源区110。于有源区110中形成第一晶体管200与第二晶体管300。
在本实施例中，第一晶体管200和第二晶体管300分布于有源区110延伸方向的相对两侧。并且，位于有源区110中的第一晶体管200和第二晶体管300具有公共端10。
公共端10可以连接存储单元，其可以为源极，也可以为漏极。
在本实施例中，第一晶体管200与第二晶体管300公用公共端10，进而可以有效控制存储单元的读写操作，从而提高数据的读写成功率。
在一个实施例中，请参阅图2，半导体结构还包括多条沿第一方向延伸的字线WL。字线WL用于为第一晶体管200以及第二晶体管300提供栅压信号。
字线WL对应有源区110的部分可以作为第一晶体管200的第一栅极230和/或第二晶体管300的第二栅极330。具体的，如图1和图2所示，字线WL可以为埋入式字线，两条字线WL穿过同一个有源区110；字线WL和有源区110交叠的部分可以分别为第一晶体管200的第一栅极230和/或第二晶体管300的第二栅极330。第一栅极230的底部和侧壁与第一晶体管200的第一沟道区域210相对，第二栅极330的底部和侧壁与第二晶体管300的第二沟道区域320相对。
在本实施例中，多个有源区110呈错位排布。并且，各个有源区110沿第二方向延伸，而第二方向相对于第一方向倾斜一预设角度。所述预设角度可以为15°～30°之间。
此时，在有限的衬底空间内，可以排布更多个有源区，进而提高存储单 元的密度。
进一步地，在沿第二方向上，位于相邻的有源区110中的第一晶体管200与第二晶体管300相对设置。
此时，各个有源区110呈错位阵列排布。各个有源区110的排布更加规则，从而使得形成的存储器各处性能更加均匀稳定，且便于版图设计。
更进一步地，在沿第一方向上，位于相邻的有源区110中的第一晶体管200与第二晶体管300与同一条字线WL对应。
此时，可以进一步提高衬底100内的有源区110的密度，进而提高存储单元的密度。
在一个实施例中，请参阅图3，多个有源区110中，每两个有源区110构成有源区对。并且，有源区对呈阵列排布。同时，各有源区对中的两个有源区110的第一晶体管200相邻且相对设置。
此时，每个有源区对的中央部位，可以并排设置两个第一晶体管200，从而可以有效节省衬底空间。因此，在有限的衬底空间内，可以排布更多个有源区，进而提高存储单元的密度。
进一步地，半导体结构还可以包括多条沿第一方向延伸的字线WL。同时，可以设置字线WL可以包括沿第二方向交替排列的第一字线WL1和第二字线WL2。
第一字线WL1贯穿位于同一列的有源区对中有源区的第一晶体管200，第二字线WL2贯穿位于同一列的有源区对中有源区的第二晶体管300。
并且，同一有源区对中的两个第一晶体管200被同一第一字线WL1贯穿。此时，可以进一步提高衬底100内的有源区110的密度，进而提高存储单元的密度。
更进一步地，有源区110的延伸方向为第二方向。此时，可以设置第一方向与第二方向垂直，进而便于字线WL的布局设计。
在一个实施例中，请参阅图4，提供一种半导体结构的制造方法，包括如下步骤：
步骤S1，提供衬底100；
步骤S2，在衬底100中形成第一晶体管200和第二晶体管300，第一晶体管200包括位于衬底100内的第一沟道区域210，第二晶体管300包括位于衬底100内的第二沟道区域310，第二沟道区域310的面积与第一沟道区域110的面积不同，且第一晶体管200和第二晶体管300具有公共源极或公共漏极；
步骤S3，形成存储单元400，存储单元400与所述公共源极或公共漏极相连。
其中，衬底100可以但不限于为硅衬底、氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。
第一晶体管200包括第一沟道区域210以及第一端220。第一沟道区域210位于衬底100内部，第一端220位于衬底100表面。
第一沟道区域210可以为第一晶体管200打开时形成导电沟道的区域。第一端220可以为漏极或源极。
第二晶体管300包括第二沟道区域310以及第二端320。第二沟道区域310位于衬底100内部，第二端320位于衬底100表面。
同样地，可以理解的是，第二沟道区域310可以为第二晶体管300打开时形成导电沟道的区域。
第二端320可以设置为源极或漏极。
存储单元400为可以实现存储功能的器件单元。作为示例，存储单元400可以为电容存储单元、电阻存储单元、磁存储单元、相变存储单元和铁电存储单元中的任一种。
第二晶体管300的第二沟道区域310的面积与第一晶体管200的第一沟道区域210的面积不同。
具体的，如图1所示，第一晶体管200和第二晶体管300具有公共端10，公共端10可以为第一晶体管200和第二晶体管300的公共源极或公共漏极，公共端10和第一端220之间的衬底100的表面区域为第一晶体管200的第一沟道区域210，公共端10和第二端320之间的衬底100的表面区域为第二晶体管300的第二沟道区域310。
第一沟道区域210的面积可以为第一沟道区域210在衬底100上的表面积；所述第二沟道区域310的面积可以为第二沟道区域310在衬底100上的表面积；如图1所述，第一沟道区域210在衬底100上为U形，第一沟道区域210的面积可以为所述U形的底部面积和所述U形的侧壁面积之和。同理，第二沟道区域310在衬底100上为U形，第二沟道区域310的面积可以为所述U形的底部面积和所述U形的侧壁面积之和。
因此，本实施例方法形成的半导体结构可以适应不同的读取与写入的不同要求，提高了数据读写的成功率。
在一个实施例中，第一沟道区域210具有第一宽度；第二沟道区域310具有第二宽度，其中，所述第二宽度大于所述第一宽度。
如图1所示，第一沟道区域210的第一宽度可以为第一沟道区域210与第一端220相交的线长，第二沟道区域310的第二宽度可以为第二沟道区域310与第二端320相交的线长。
例如，当存储单元400为磁存储单元，其可以包括磁隧道结(MTJ)。此时，可以选取具有较小宽度的第一沟道区域210的第一晶体管200作为数据读取用晶体管，而具有较大宽度的第二沟道区域310的第二晶体管300作为数据写入用晶体管。
具体的，当从存储单元400读取数据时，打开第一晶体管200，关闭第二晶体管300；当向存储单元400写入数据时，关闭第一晶体管200，打开第二晶体管300。通过将所述第二宽度设置为大于所述第一宽度，使得第二晶体管300的驱动电流大于第一晶体管200的驱动电流，从而满足第一晶体管200与第二晶体管300驱动电流不同的要求。此时，可以同时降低数据的误读率与误写率，从而提高数据的读写成功率。
在一个实施例中，所述第二宽度为所述第一宽度的2～5倍。此时，既能有效增加第二晶体管的驱动电流，又能避免宽度过大导致占用面积过大进而降低存储密度的问题。
在一个实施例中，请参阅图5以及图1，步骤S2的具体步骤包括：
步骤S21，在衬底100中形成有源区110，有源区110包括第一部分和第二部分且第二部分的宽度大于第一部分的宽度；
步骤S22，分别在有源区110的第一部分和第二部分中形成第一栅极槽110a和第二栅极槽110b，有源区被第一栅极槽110a和第二栅极槽110b分割成第一端220、第二端320以及第一端220和第二端320之间的公共端10；
步骤S23，填充栅极材料于第一栅极槽110a和第二栅极槽110b中，形成第一栅极230和第二栅极330。
其中，第一栅极230为第一晶体管200的栅极，第二栅极330为第二晶体管300的栅极。第一栅极230的底部和侧壁与第一沟道区域210相对。第 二栅极330的底部和侧壁与第二沟道区域310相对。
即，第一晶体管200包括第一栅极230、第一沟道区域210、第一端220以及公共端10。第一端220以及公共端10分别为第一晶体管200的漏极和源极。可以理解的是，第一栅极230与第一沟道区域210之间还可以具有第一栅介质层240(如氧化层)。
第二晶体管300包括第二栅极330、第二沟道区域310、第二端320以及公共端10。第二端320以及公共端10分别为第二晶体管300的漏极和源极。可以理解的是，第二栅极330与第二沟道区域230之间具有第二栅介质层340(如氧化层)。
第一晶体管200与第二晶体管300公用公共端10，进而可以有效提高空间利用率，从而降低器件体积。公共端10可以为第一晶体管200和第二晶体管300的公共源极或公共漏极。
在本实施例中，第一晶体管200的栅极(第一栅极)与第二晶体管300的栅极(第二栅极)均为为埋入式栅极结构。
当然，本申请并不以此为限制，第一晶体管200以及第二晶体管300的栅极也可以为其他形式(例如平面栅极)。
在一个实施例中，请参阅图2，半导体结构的制造方法还包括：在衬底100内形成多条沿第一方向延伸的字线WL。
作为示例，字线WL可以形成于第一栅极槽110a和第二栅极槽110b中。字线WL对应有源区110的部分可以作为第一晶体管200的第一栅极230和/或第二晶体管300的第二栅极330。
多个有源区110呈错位排布，有源区110沿第二方向延伸，且第二方向相对于第一方向倾斜一预设角度。
此时，在有限的衬底空间内，可以排布更多个有源区，进而提高存储单元的密度。
在一个实施例中，在沿第二方向上，位于相邻的有源区中的第一晶体管与第二晶体管相对设置；在沿第一方向上，位于相邻的有源区中的第一晶体管与第二晶体管与同一条字线对应。
在一个实施例中，请参阅图3，多个有源区110中，每两个有源区110构成有源区对，有源区对呈阵列排布，有源区沿第二方向延伸；各有源区对中的两个有源区110的第一晶体管200相邻且相对设置。
在一个实施例中，半导体结构的制造方法还包括在衬底内形成多条沿第一方向延伸的字线WL。字线WL包括沿第二方向交替排列的第一字线WL1和第二字线WL2。第一字线WL1贯穿位于同一列的有源区对中有源区的第一晶体管200，第二字线贯穿位于同一列的有源区对中有源区的第二晶体管300，且同一有源区对中的两个第一晶体管200被同一第一字线WL1贯穿。
在一个实施例中，有源区沿第二方向延伸，第一方向与第二方向垂直。
关于半导体结构的制造方法的具体限定可以参见上文中对于半导体结构的限定，在此不再赘述。
在本说明书的描述中，参考术语“一个实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体结构，包括：
    衬底；
    第一晶体管，包括位于所述衬底内的第一沟道区域；
    第二晶体管，包括位于所述衬底内的第二沟道区域，所述第二沟道区域的面积与所述第一沟道区域的面积不同，且所述第一晶体管和所述第二晶体管具有公共源极或公共漏极；及
    存储单元，与所述公共源极或所述公共漏极相连。
  2. 根据权利要求1所述的半导体结构，其中：
    所述存储单元包括电容存储单元、电阻存储单元、磁存储单元、相变存储单元和铁电存储单元中的任一种。
  3. 根据权利要求2所述的半导体结构，其中：
    所述第一沟道区域具有第一宽度；
    所述第二沟道区域具有第二宽度，其中，所述第二宽度大于所述第一宽度；
    所述存储单元为磁存储单元，所述第一晶体管用于从所述磁存储单元读取数据，所述第二晶体管用于向所述磁存储单元写入数据。
  4. 根据权利要求1所述的半导体结构，其中所述衬底内还包括至少一个有源区，所述有源区中具有所述第一晶体管和所述第二晶体管；
    所述第一晶体管和所述第二晶体管分布于所述有源区延伸方向的相对两侧。
  5. 根据权利要求4所述的半导体结构，还包括：
    多条沿第一方向延伸的字线；
    多个所述有源区呈错位排布，所述有源区沿第二方向延伸，且所述第二方向相对于所述第一方向倾斜一预设角度。
  6. 根据权利要求5所述的半导体结构，其中在沿所述第一方向上，位于相邻的所述有源区中的所述第一晶体管与所述第二晶体管与同一条所述字线对应。
  7. 根据权利要求4所述的半导体结构，其中多个所述有源区中，每两个所述有源区构成有源区对，所述有源区对呈阵列排布；各所述有源区对中的两个所述有源区的所述第一晶体管相邻且相对设置。
  8. 根据权利要求7所述的半导体结构，还包括多条沿第一方向延伸的字线；所述字线包括沿第二方向交替排列的第一字线和第二字线；
    所述第一字线贯穿位于同一列的所述有源区对中所述有源区的所述第一晶体管，所述第二字线贯穿位于同一列的所述有源区对中所述有源区的所述第二晶体管，且同一所述有源区对中的两个所述第一晶体管被同一所述第一字线贯穿。
  9. 根据权利要求8所述的半导体结构，其中所述有源区沿第二方向延伸，所述第一方向与所述第二方向垂直。
  10. 根据权利要求3所述的半导体结构，其中所述第二宽度为所述第一宽度的2～5倍。
  11. 一种半导体结构的制造方法，包括：
    提供衬底；
    在所述衬底中形成第一晶体管和第二晶体管，所述第一晶体管包括位于所述衬底内的第一沟道区域，所述第二晶体管包括位于所述衬底内的第二沟道区域，所述第二沟道区域的面积与所述第一沟道区域的面积不同，且所述 第一晶体管和所述第二晶体管具有公共源极或公共漏极；及
    形成存储单元，所述存储单元与所述公共源极或所述公共漏极相连。
  12. 根据权利要求11所述的方法，其中所述存储单元包括电容存储单元、电阻存储单元、磁存储单元、相变存储单元和铁电存储单元中的任一种。
  13. 根据权利要求12所述的方法，其中：
    所述第一沟道区域具有第一宽度；
    所述第二沟道区域具有第二宽度，其中，所述第二宽度大于所述第一宽度；
    所述存储单元为磁存储单元，所述第一晶体管用于从所述磁存储单元读取数据，所述第二晶体管用于向所述磁存储单元写入数据。
  14. 根据权利要求13所述的方法，其中所述在所述衬底中形成第一晶体管和第二晶体管的具体步骤包括：
    在所述衬底中形成有源区，所述有源区包括第一部分和第二部分且所述第二部分的宽度大于所述第一部分的宽度；
    分别在所述有源区的第一部分和第二部分中形成第一栅极槽和第二栅极槽，所述有源区被所述第一栅极槽和所述第二栅极槽分割成第一端、第二端以及所述第一端和所述第二端之间的公共端；
    填充栅极材料于所述第一栅极槽和所述第二栅极槽中，形成第一栅极和第二栅极。
  15. 根据权利要求14所述的方法，其中所述第二宽度为所述第一宽度的2～5倍。
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