WO2022134789A1 - 半导体封装方法及半导体封装结构 - Google Patents

半导体封装方法及半导体封装结构 Download PDF

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Publication number
WO2022134789A1
WO2022134789A1 PCT/CN2021/124847 CN2021124847W WO2022134789A1 WO 2022134789 A1 WO2022134789 A1 WO 2022134789A1 CN 2021124847 W CN2021124847 W CN 2021124847W WO 2022134789 A1 WO2022134789 A1 WO 2022134789A1
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layer
chip
redistribution
dielectric layer
conductive
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PCT/CN2021/124847
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English (en)
French (fr)
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霍炎
涂旭峰
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矽磐微电子(重庆)有限公司
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Priority to US18/013,656 priority Critical patent/US20230170318A1/en
Priority to EP21908790.5A priority patent/EP4266355A4/en
Publication of WO2022134789A1 publication Critical patent/WO2022134789A1/zh

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Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
  • Common semiconductor packaging technology such as chip packaging technology, mainly includes the following process: For the process of the front side of the chip, first mount the front side of the chip on the carrier board, perform thermocompression molding, peel off the carrier board, and then A rewiring layer and a pin layer on the side of the rewiring layer away from the chip are formed on the front side of the chip, and then an insulating layer is formed, the insulating layer covers the rewiring layer, and the surface of the pin layer facing away from the chip is exposed from the insulating layer.
  • the pin layer is formed on the side of the rewiring layer away from the chip, so the area of the rewiring layer is larger, and the rewiring layer is adjacent to the insulating layer.
  • the contact area is large. Due to the large difference in thermal expansion coefficient between the rewiring layer and the insulating layer, the temperature increase of the rewiring layer during the preparation or chip operation will make the stress difference between the rewiring layer and the insulating layer larger, which may make the rewiring layer and the insulating layer.
  • the layers are delaminated or the redistribution layer is warped, which affects the normal operation of the product.
  • Embodiments of the present application provide a semiconductor packaging method and a semiconductor packaging structure.
  • a semiconductor packaging method including:
  • the encapsulation structure includes an encapsulation layer and a chip, the front side of the chip is provided with a plurality of bonding pads, and the encapsulation layer at least covers the side surface of the chip;
  • a redistribution layer is formed on the side of the encapsulation structure close to the front side of the chip, and the redistribution layer leads out the bonding pads of the chip;
  • the dielectric layer covers the redistribution layer, and the dielectric layer is provided with through holes exposing the redistribution layer;
  • a pin layer is formed on the side of the dielectric layer away from the chip, and the pin layer is electrically connected to the redistribution layer through the through hole.
  • a semiconductor packaging structure comprising:
  • An encapsulation structure the encapsulation structure includes an encapsulation layer and a chip, the front side of the chip is provided with a plurality of bonding pads, and the encapsulation layer covers the back and side surfaces of the chip;
  • redistribution layer located on the side of the encapsulation structure close to the front side of the chip, and the redistribution layer leads out the pads of the chip;
  • the pin layer is located on the side of the dielectric layer away from the chip, and the pin layer is electrically connected to the redistribution layer through the through hole.
  • the dielectric layer covers the redistribution layer
  • the pin layer is located on the side of the dielectric layer away from the redistribution layer
  • the pin layer is electrically connected to the rewiring layer through the through holes on the dielectric layer, that is, the pin layer and the rewiring layer are not in direct contact, so that the size of the pin layer is not affected by the size of the rewiring layer, so the rewiring layer can be
  • the size of the wiring layer is set to be smaller, thereby reducing the contact area between the rewiring layer and the adjacent insulating layer such as the dielectric layer, reducing the stress difference between the rewiring layer and the adjacent insulating layer, thereby reducing the rewiring layer and the adjacent insulating layer.
  • the risk of delamination of the insulating layer or warpage of the rewiring layer helps to improve the quality of the product; if the pin layer and the rewiring layer are not in direct contact, the thickness of the pin layer is less affected by the rewiring layer, and the lead
  • the thickness of the pin layer is designed more freely, which helps to increase the thickness of the formed pin layer, thereby increasing the breakdown voltage of the semiconductor package structure, which is helpful for the semiconductor package structure to be applied in a high-voltage environment and expands the application of the semiconductor package structure. scope.
  • FIG. 1 is a flowchart of a semiconductor packaging method provided by an exemplary embodiment of the present application
  • FIG. 2 is a flowchart of forming an encapsulation structure provided by an exemplary embodiment of the present application
  • FIG. 3 is a partial cross-sectional view of a first intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;
  • FIG. 4 is a partial cross-sectional view of a second intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 5 is a partial cross-sectional view of an encapsulation structure provided by an exemplary embodiment of the present application.
  • FIG. 6 is a partial cross-sectional view of a third intermediate structure of a semiconductor package structure provided by another exemplary embodiment of the present application.
  • FIG. 7 is a partial cross-sectional view of a third intermediate structure of a semiconductor package structure provided by another exemplary embodiment of the present application.
  • FIG. 8 is a partial cross-sectional view of a fourth intermediate structure of a semiconductor package structure provided by another exemplary embodiment of the present application.
  • FIG. 9 is a partial cross-sectional view of a fifth intermediate structure of a semiconductor package structure provided by another exemplary embodiment of the present application.
  • FIG. 10 is a partial cross-sectional view of a sixth intermediate structure of a semiconductor package structure provided by another exemplary embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a sixth intermediate structure of a semiconductor package structure provided by another exemplary embodiment of the present application.
  • FIG. 12 is a partial cross-sectional view of a semiconductor package structure provided by an exemplary embodiment of the present application.
  • FIG. 13 is a partial cross-sectional view of a semiconductor package structure and a circuit board provided by an exemplary embodiment of the present application after welding;
  • FIG. 14 is a partial cross-sectional view of a semiconductor package structure provided by another exemplary embodiment of the present application.
  • first, second, third, etc. may be used in this application to describe various information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information without departing from the scope of the present application.
  • word "if” as used herein can be interpreted as "at the time of” or "when” or "in response to determining.”
  • Embodiments of the present application provide a semiconductor packaging method.
  • the semiconductor packaging method includes the following steps 110 to 140 .
  • an encapsulation structure is formed, the encapsulation structure includes an encapsulation layer and a chip, a plurality of bonding pads are disposed on the front side of the chip, and the encapsulation layer at least covers the side surfaces of the chip.
  • a redistribution layer is formed on the side of the encapsulation structure close to the front surface of the chip, and the redistribution layer leads out the bonding pads of the chip.
  • step 130 a dielectric layer is formed, the dielectric layer covering the redistribution layer, and the dielectric layer is provided with through holes exposing the redistribution layer.
  • step 140 a lead layer is formed on the side of the dielectric layer away from the chip, and the lead layer is electrically connected to the redistribution layer through the through hole.
  • the dielectric layer covers the redistribution layer
  • the pin layer is located on the side of the dielectric layer away from the redistribution layer
  • the pin layer is electrically connected to the redistribution layer through the through holes on the dielectric layer. Connection, that is, the pin layer is not in direct contact with the rewiring layer, so that the size of the pin layer is not affected by the size of the rewiring layer, so the size of the rewiring layer can be set smaller, thereby reducing the rewiring layer.
  • the contact area with the adjacent insulating layer such as the dielectric layer reduces the stress difference between the redistribution layer and the adjacent insulating layer, thereby reducing the risk of delamination between the redistribution layer and the adjacent insulating layer or warping of the redistribution layer.
  • the pin layer is not in direct contact with the rewiring layer, the thickness of the pin layer is not affected by the rewiring layer, and the thickness of the pin layer is designed more freely, which helps to increase the formed
  • the thickness of the lead layer increases the breakdown voltage of the semiconductor package structure, which is helpful for the semiconductor package structure to be applied in a high-voltage environment and expands the application range of the semiconductor package structure.
  • an encapsulation structure is formed, the encapsulation structure includes an encapsulation layer and a chip, a plurality of bonding pads are disposed on the front side of the chip, and the encapsulation layer at least covers the side surfaces of the chip.
  • the encapsulation structure may include one or more chips, the encapsulation layer is provided with concave cavities corresponding to the chips one-to-one, and the chips are located in the corresponding concave cavities.
  • the step 110 of forming the encapsulation structure includes the following steps 111 to 113 .
  • step 111 the chip is mounted on the carrier board, and the front side of the chip faces the surface of the carrier board.
  • step 111 the first intermediate structure shown in FIG. 3 can be obtained.
  • a chip 20 is mounted on the carrier board 10 .
  • the number of chips 20 mounted on the carrier board 10 may be multiple.
  • carrier 10 includes a placement area for mounting chips 20 .
  • the shape of the mounting area is designed according to the layout of the chips 20 on the entire carrier board 10 , and the shape of the mounting area may include a circle, a rectangle or other shapes.
  • the carrier board 10 may include one or more placement areas.
  • the shape of the carrier plate 10 may be circular, rectangular or other shapes.
  • the material of the carrier plate 10 may be an iron-nickel constant expansion alloy, or may be stainless steel, polymer, or the like.
  • the chip 20 may be obtained by dicing a silicon wafer.
  • the silicon wafer has an active surface, and the active surface of the silicon wafer is provided with a solder pad.
  • the silicon wafer can be cut by mechanical cutting or laser cutting.
  • grinding equipment may be used to grind the backside of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.
  • the bonding pads 21 of the chip 20 are composed of conductive electrodes drawn from the internal circuit of the chip to the surface of the chip.
  • the front side of the chip 20 may be provided with a plurality of bonding pads 21 .
  • the bonding pads 21 are used to lead out the conductive electrodes of the chip 20 .
  • the semiconductor packaging method before the step 111 of mounting the chip on the carrier board, the semiconductor packaging method further includes: forming a protective layer 22 on the front surface of the chip 20 , and the protective layer 22 is provided with an exposed The opening 23 of the bonding pad 21 is described.
  • the openings 23 may be formed on the protective layer 22 by a laser process.
  • the size of the opening 23 may be smaller than that of the bonding pad 21 , and the opening 23 exposes a part of the surface of the bonding pad 21 away from the carrier board 10 .
  • the material of the protective layer 22 can be plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite material or other materials with similar properties. In some embodiments, organic or inorganic fillers may also be added to the protective layer 22 .
  • the encapsulation material forming the encapsulation layer in this process easily penetrates between the carrier board 10 and the chip 20 .
  • the protective layer 22 can prevent the encapsulation material from infiltrating the surface of the chip 20, and even if the encapsulation material penetrates into the protective layer 22 when the encapsulation layer is formed, it is possible to prevent the encapsulation material from penetrating into the protective layer 22 when the encapsulation layer is formed.
  • the surface of the protective layer 22 may be directly processed by chemical method or grinding method without directly contacting the front side of the chip 20 , thereby avoiding damage to the bonding pads on the front side of the chip 20 .
  • the chip 20 can be mounted on the carrier board 10 through an adhesive layer, and the adhesive layer can be made of an easily peelable material, so that the chip 20 can be peeled off from the carrier board 10 later, for example, the adhesive layer can be A thermal separation material that can lose its viscosity by heating is used.
  • step 112 an encapsulation layer is formed, and the encapsulation layer covers the carrier board and encapsulates the chip.
  • step 112 the second intermediate structure as shown in FIG. 4 can be obtained.
  • the encapsulation layer 30 is formed on the chip 20 and the exposed carrier 10 for encapsulating the chip 20 to reconstruct a flat structure, so that after the carrier 10 is peeled off, the reconstruction can be continued. rewiring and packaging on this flat panel structure.
  • some pre-processing steps such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the chip 20 and the carrier 10, so that the encapsulation layer 30 and the chip 20 and the carrier board 10 can be connected more closely without delamination or cracking.
  • the encapsulation layer 30 may be formed by laminating epoxy resin films, or may be formed by injection molding, compression molding, or transfer molding of epoxy resin compounds.
  • the step 112 of forming the encapsulation layer may include the steps of:
  • an encapsulation structure is formed, the encapsulation structure covers the carrier board, and covers the chip.
  • the thickness of the encapsulation structure is greater than the thickness of the chip 20 , so that the encapsulation structure completely encapsulates the chip 20 .
  • the encapsulation structure may be thinned by a grinding process to reduce the encapsulation structure to a specified thickness.
  • step 113 the carrier plate is removed to obtain the encapsulation structure.
  • the encapsulation structure shown in FIG. 5 can be obtained.
  • the encapsulation layer 30 encapsulates the back and side surfaces of the chip 20 .
  • the encapsulation layer 30 may only encapsulate the side surface of the chip 20 or the like.
  • the carrier 10 may be mechanically peeled directly from the encapsulation layer 30 and the chip 20 .
  • the chip 20 and the carrier 10 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer can also be heated to make the adhesive layer sticky after being heated. lower, and the carrier plate 10 is further peeled off. After the carrier board 10 is peeled off, the bonding pads of each chip 20 are exposed.
  • a redistribution layer is formed on the side of the encapsulation structure close to the front surface of the chip, and the redistribution layer leads out the bonding pads of the chip.
  • the third intermediate structure shown in FIG. 6 can be obtained.
  • the side of the encapsulation structure close to the front side of the chip refers to the side where the front side of the chip is located.
  • the redistribution layer 40 includes a plurality of redistribution structures 41 .
  • Each redistribution structure 41 can be electrically connected to one pad 21 , or can be electrically connected to a plurality of pads 21 .
  • a conductive structure 24 is formed in the opening 23 of the protective layer 22 , the conductive structure 24 is in direct contact with the redistribution structure 41 , and the redistribution structure 41 is electrically connected to the pad 21 through the conductive structure 24 .
  • the conductive structure 24 and the redistribution structure 41 can be formed in the same process step, which helps to simplify the semiconductor packaging process.
  • step 120 may be accomplished by the following steps:
  • a seed layer is formed on the side of the encapsulation structure close to the front side of the chip.
  • the seed layer can cover the front surface of the chip 20 and the inner wall of the opening 23 .
  • a photoresist layer is formed on the side of the seed layer facing away from the chip.
  • the photoresist layer is a patterned film layer.
  • the seed layer is connected to a power source, and electroplating is performed to form a conductive layer on the side of the seed layer facing away from the chip and not shielded by the photoresist layer.
  • the redistribution structure 41 is provided with a hollow portion 411 . In this way, the size of the redistribution structure 41 can be reduced, thereby reducing the contact area between the redistribution structure 41 and the adjacent insulating layer, and further reducing the risk of peeling of the redistribution structure 41 from the adjacent insulating layer.
  • step 130 a dielectric layer is formed, the dielectric layer covers the redistribution layer, and the dielectric layer is provided with through holes exposing the redistribution layer.
  • step 130 may be accomplished by the following process:
  • a dielectric layer is formed on the encapsulation structure, and the dielectric layer covers the redistribution layer 40 and the exposed encapsulation layer 30 .
  • a fourth intermediate structure as shown in FIG. 8 can be obtained.
  • the dielectric layer 50 completely covers the redistribution layer 40 .
  • vias are formed on the dielectric layer exposing the redistribution layer.
  • the dielectric layer 50 is provided with a plurality of through holes 51 .
  • a portion of the dielectric layer 50 corresponding to one redistribution structure 41 in the longitudinal direction may be provided with one through hole 51 or multiple through holes 51 , that is, one redistribution structure 41 may correspond to one through hole 51 or multiple through holes 51 .
  • the size of the through hole 51 is smaller than that of the redistribution structure 41, and the through hole 51 exposes a part of the surface of the redistribution structure 41.
  • the material of the dielectric layer 50 may be plastic film, PI, PBO, organic polymer film, organic polymer composite material, or other materials with similar properties.
  • organic or inorganic fillers may also be added to the dielectric layer 50 .
  • the through hole 51 may be formed on the dielectric layer 50 using a laser process.
  • step 140 a lead layer is formed on the side of the dielectric layer away from the chip, and the lead layer is electrically connected to the redistribution layer through the through hole.
  • the pin layer 60 includes a plurality of conductive bumps 61 arranged at intervals, and the conductive bumps 61 protrude from the dielectric layer 50 .
  • the dielectric layer 50 does not need to be ground;
  • the time of grinding the dielectric layer can be saved, the packaging efficiency can be improved, and the production cost can be reduced; at the same time, the low precision of the grinding process can be avoided.
  • the problem of poor uniformity of the thickness of the dielectric layer can prevent the lead layer from being ground when the dielectric layer is ground, and also avoid the stress on the lead layer from damaging the pads of the chip, which helps to improve the quality of packaged products.
  • a conductive portion 52 is formed in the through hole 51 of the dielectric layer 50 , the conductive portion 52 is in direct contact with the redistribution structure 41 and the conductive bump 61 respectively, and the conductive bump 61 is connected to the redistribution structure through the conductive portion 52 .
  • the conductive bumps 61 and the conductive portions 52 can be formed in the same process step, which helps to simplify the semiconductor packaging process.
  • the lead layer 60 may be formed on the side of the dielectric layer 50 away from the chip 20 by an electroplating process. Since the pin layer 60 is formed on the dielectric layer 50 and is not in direct contact with the redistribution layer 40, a conductive layer with a thicker thickness can be formed on the side of the dielectric layer 50 away from the chip 20 through an electroplating process, so that the conductive layer can be The lead layer 60 with a larger thickness is obtained by etching.
  • the thickness d of the pin layer 60 is greater than 30 ⁇ m. Such arrangement can effectively increase the breakdown voltage of the semiconductor package structure.
  • the conductive portion 52 and the pin layer 60 can be formed at the same time, and this arrangement can also prevent the portion of the conductive portion 52 located at the sidewall of the through hole 51 from being broken due to the small thickness of the conductive portion 52 .
  • the thickness d of the pin layer 60 is, for example, 31 ⁇ m, 33 ⁇ m, 35 ⁇ m, 37 ⁇ m, 40 ⁇ m, and the like.
  • the semiconductor packaging method further includes: forming a heat dissipation layer on the side of the dielectric layer 50 away from the chip 20.
  • each chip 20 may correspond to one heat dissipation layer 80 , and the plurality of conductive bumps 61 of the chip 20 may be located on the peripheral side of the corresponding heat dissipation layer 80 .
  • the heat dissipation layer 80 may be formed in the same process step as the pin layer 60 . This helps to simplify the semiconductor packaging process. At this time, the heat dissipation layer 80 may all protrude from the dielectric layer 50 .
  • the semiconductor packaging method further includes: forming a solder layer, the solder layer covering the conductive bumps The pillars protrude from the surface of the dielectric layer.
  • the conductive bumps 61 of the lead layer 60 are located on the side of the dielectric layer 50 away from the chip 20, the conductive bumps 61 protrude from the dielectric layer 50 as a whole, and the solder has a better climbing ability when the solder layer 70 is formed.
  • the solder layer 70 can completely cover the surface of the conductive bump 61 protruding from the dielectric layer, that is, the solder layer 70 completely covers the sidewall of the conductive bump 61 and the surface away from the chip 20 . In this way, as shown in FIG.
  • the sidewalls of the conductive bumps 61 and the solder layer 70 facing away from the surface of the chip 20 can both be soldered to the circuit board 90 , and the conductive bumps only face away from the chip relative to the conductive bumps.
  • the reliability of the soldering between the conductive bumps 61 and the circuit board 90 of the semiconductor package structure obtained in the embodiment of the present application is higher, and Compared with the solution of forming the solder balls through the reflow process, the embodiment of the present application has a simpler process.
  • the material of the solder layer 70 may be metal tin, gold-tin alloy, or nickel-based alloy and other materials that can realize the soldering function.
  • the solder layer 70 may be formed by a process such as electroplating, electroless plating, or screen printing. In some embodiments, the solder layer 70 may be formed on the surface of the conductive bump 61 by an electroplating process. In this way, the overall thickness of the semiconductor package structure can be more controllable, and at the same time, the thickness uniformity of the semiconductor package structure can be ensured. For board-level packaging, the packaging efficiency can be effectively improved and the cost can be reduced; at the same time, the formed solder layer can be formed. The thickness of 70 is larger, which can improve the reliability of the semiconductor package structure and other post-joint soldering.
  • the heat dissipation layer 80 is located on the side of the dielectric layer 50 away from the chip 20 , and the heat dissipation layer 80 protrudes from the dielectric layer 50 , the climbing ability of the solder is better when the solder layer 70 is formed, so the solder layer 70
  • the sidewalls of the heat dissipation layer 80 and the solder layer 70 facing away from the surface of the chip 20 can both be welded to the circuit board.
  • the reliability of the welding of the heat dissipation layer 80 and the circuit board 90 of the semiconductor package structure obtained in the embodiment of the present application is higher.
  • the tin-plated wire 71 is firstly formed, and the tin-plated wire 71 is electrically connected to each conductive bump 61 and the heat dissipation layer 80 , and then the tin-plated wire 71 is connected to the external
  • the electrical connection of the power source is electroplated to form a solder layer 70 on the sidewalls and the surface facing away from the chip 20 of the conductive bumps 61 and the sidewalls and the surface facing away from the chip 20 of the heat dissipation layer 80 .
  • the size of the through hole 51 is larger, which can prevent the portion of the conductive portion 52 located at the sidewall of the through hole 51 of the dielectric layer 50 from being broken; the solder layer 70 is filled with A depression formed by the conductive portion 52 .
  • the contact area between the solder layer 70 and the conductive bumps 61 of the lead layer 60 is larger, the bonding force is better, and at the same time, sufficient filling space can be provided for the solder layer 70, and the solder layer 70 can be made thicker, which is beneficial to In order to improve the reliability of the soldering between the semiconductor package structure and the circuit board 90 .
  • the ratio of the width D to the depth H of the through hole 51 is greater than or equal to 1/3. In this way, the formed conductive portion 52 is more likely to form a depression at the through hole 51 , which is more helpful to increase the contact area between the conductive bump 61 and the solder layer 70 .
  • the ratio of the width D to the depth H of the through hole 51 is, for example, 1/3, 1/2, 2/3, 3/4, 3/2, and the like.
  • the depth H of the through hole 51 ranges from 60 ⁇ m to 100 ⁇ m, and the thickness S of the portion of the conductive portion 52 located on the bottom wall of the through hole 51 ranges from 10 ⁇ m to 50 ⁇ m. This arrangement further helps to provide enough filling space for the solder layer 70 in the through hole 51, thereby improving the reliability of the soldering between the semiconductor package structure and other structures.
  • the depth H (hereinafter referred to as the depth H) of the through hole 51 is 100 ⁇ m
  • the thickness S of the portion of the conductive portion 52 located on the bottom wall of the through hole 51 (hereinafter referred to as the thickness S) is 40 ⁇ m
  • the width D (hereinafter referred to as width D) of the through hole 51 is 50 ⁇ m; or the depth H is 80 ⁇ m, the thickness S is 35 ⁇ m, and the width D is 40 ⁇ m or 80 ⁇ m; or the depth H is 60 ⁇ m, the thickness S is 25 ⁇ m, and the width D is 30 ⁇ m or 80 ⁇ m etc.
  • Embodiments of the present application also provide a semiconductor packaging structure.
  • the semiconductor package structure includes an encapsulation structure, a redistribution layer 40 , a dielectric layer 50 and a lead layer 60 .
  • the encapsulation structure includes an encapsulation layer 30 and a chip 20 , a plurality of bonding pads 21 are disposed on the front side of the chip 20 , and the encapsulation layer 30 at least covers the side surface of the chip 20 .
  • the redistribution layer 40 is located on the side of the encapsulation structure close to the front surface of the chip 20 , and the redistribution layer 40 leads out the bonding pads 21 of the chip 20 .
  • the side of the encapsulation structure close to the front side of the chip 20 refers to the side where the front side of the chip 20 is located.
  • the dielectric layer 50 covers the redistribution layer 40 , and a through hole 51 exposing a part of the redistribution layer 40 is formed on the dielectric layer 50 .
  • the lead layer 60 is located on the side of the dielectric layer 50 away from the chip 20 , and the lead layer 60 is electrically connected to the redistribution layer 40 through the through hole 51 .
  • the dielectric layer covers the redistribution layer
  • the pin layer is located on the side of the dielectric layer away from the redistribution layer
  • the pin layer is electrically connected to the redistribution layer through the through holes on the dielectric layer. Connection, that is, the pin layer is not in direct contact with the rewiring layer, so that the size of the pin layer is not affected by the rewiring layer, so the area of the rewiring layer can be set smaller, thereby reducing the size of the rewiring layer.
  • the contact area of adjacent insulating layers reduces the stress difference between the redistribution layer and the adjacent insulating layer, thereby reducing the risk of delamination between the redistribution layer and the insulating layer or warping of the redistribution layer, which helps to improve The quality of the product; the pin layer is not in direct contact with the rewiring layer, the thickness of the pin layer is not affected by the rewiring layer, and the thickness design of the pin layer is more free, which helps to increase the thickness of the formed pin layer. , thereby increasing the breakdown voltage of the semiconductor package structure, helping the semiconductor package structure to be applied in a high-voltage environment, and expanding the application range of the semiconductor package structure.
  • a protective layer 22 is formed on the front surface of the chip 20 , and the protective layer 22 is provided with an opening 23 exposing the bonding pad 21 .
  • the size of the opening 23 may be smaller than that of the bonding pad 21 , and the opening 23 exposes a part of the surface of the bonding pad 21 away from the carrier board 10 .
  • the material of the protective layer 22 can be plastic film, PI, PBO, organic polymer film, organic polymer composite material or other materials with similar properties. In some embodiments, organic or inorganic fillers may also be added to the protective layer 22 .
  • High pressure forming is required when forming the encapsulation layer, and the encapsulation material forming the encapsulation layer can easily penetrate between the carrier 10 and the chip 20 during the process.
  • the protective layer 22 can prevent the encapsulation material from penetrating into the surface of the chip 20 , and even if the encapsulation material penetrates into the protective layer 22 when the encapsulation layer 30 is formed, the carrier 10 After being peeled off from the chip 20 , the surface of the protective layer 22 can be directly processed by chemical or grinding methods without directly contacting the front side of the chip 20 , thereby avoiding damage to the bonding pads on the front side of the chip 20 .
  • a conductive structure 24 is formed in the opening 23 of the protective layer 22 , the conductive structure 24 is in direct contact with the redistribution structure 41 , and the redistribution structure 41 is electrically connected to the pad 21 through the conductive structure 24 .
  • the material of the conductive structure 24 and the material of the redistribution structure 41 can be the same, so that the conductive structure 24 and the redistribution structure 41 can be formed in the same process step, which helps to simplify the packaging process for forming the semiconductor package structure.
  • the redistribution layer 40 includes a plurality of spaced redistribution structures 41 .
  • Each redistribution structure 41 can be electrically connected to one pad 21, or can be electrically connected to a plurality of pads 21.
  • the redistribution structure 41 is provided with a hollow portion 411 . In this way, the size of the redistribution structure 41 can be reduced, thereby reducing the contact area between the redistribution structure 41 and the adjacent insulating layer, and further reducing the risk of peeling of the redistribution structure 41 from the adjacent insulating layer.
  • the dielectric layer 50 is provided with a plurality of through holes 51 .
  • a portion of the dielectric layer 50 corresponding to one redistribution structure 41 in the longitudinal direction may be provided with one through hole 51 or multiple through holes 51 , that is, one redistribution structure 41 may correspond to one through hole 51 or multiple through holes 51 .
  • the size of the through hole 51 is smaller than that of the redistribution structure 41 , and the through hole 51 exposes a part of the surface of the redistribution structure 41 .
  • the material of the dielectric layer 50 may be plastic film, PI, PBO, organic polymer film, organic polymer composite material, or other materials with similar properties.
  • organic or inorganic fillers may also be added to the dielectric layer 50 .
  • the pin layer 60 includes a plurality of conductive bumps 61 arranged at intervals, and the conductive bumps 61 protrude from the dielectric layer 50 .
  • the dielectric layer 50 does not need to be ground, which is different from that after the lead layer is formed.
  • the time of grinding the dielectric layer can be saved, the packaging efficiency can be improved, and the production cost can be reduced; at the same time, the low precision of the grinding process can be avoided.
  • the problem of poor uniformity of the thickness of the dielectric layer can prevent the lead layer from being ground when the dielectric layer is ground, and also avoid the stress on the lead layer from damaging the pads of the chip, which helps to improve the quality of packaged products.
  • a conductive portion 52 is formed in the through hole 51 of the dielectric layer 50 , the conductive portion 52 is in direct contact with the redistribution structure 41 and the conductive bump 61 respectively, and the conductive bump 61 is connected to the redistribution structure through the conductive portion 52 .
  • the materials of the conductive bumps 61 and the conductive parts 52 can be the same, so that the conductive bumps 61 and the conductive parts 52 can be formed in the same process step, which helps to simplify the packaging process of the semiconductor package structure.
  • the thickness d of the pin layer 60 is greater than 30 ⁇ m. This arrangement can effectively increase the breakdown voltage of the semiconductor package structure; in some embodiments, the conductive portion 52 and the lead layer 60 can be formed at the same time, and this arrangement can also avoid the portion of the conductive portion 52 located at the sidewall of the through hole 51 fracture occurs. In some embodiments, the thickness of the pin layer 60 is, for example, 31 ⁇ m, 33 ⁇ m, 35 ⁇ m, 37 ⁇ m, 40 ⁇ m, and the like.
  • the semiconductor package structure further includes a heat dissipation layer 80 .
  • the larger area of the heat dissipation layer 80 can make the heat dissipation effect of the semiconductor package structure better.
  • Each chip 20 may correspond to a heat dissipation layer 80, and the plurality of conductive bumps 61 corresponding to the chip 20 may be located on the peripheral side of the corresponding heat dissipation layer 80.
  • the material of the heat dissipation layer 80 and the material of the lead layer 60 can be the same, so the heat dissipation layer 80 and the lead layer 60 can be formed in the same process step, which helps to simplify the packaging process of the semiconductor package structure. At this time, the heat dissipation layer 80 may all protrude from the dielectric layer 50 .
  • the semiconductor package structure further includes a solder layer 70 , and the solder layer 70 covers the conductive bumps 61 and protrudes from the surface of the dielectric layer 50 .
  • the conductive bumps 61 of the lead layer 60 are located on the side of the dielectric layer 50 away from the chip 20, the conductive bumps 61 protrude from the dielectric layer 50 as a whole, and the solder has a better climbing ability when the solder layer 70 is formed.
  • the solder layer 70 can completely cover the surface of the conductive bump 61 protruding from the dielectric layer, that is, the solder layer 70 completely covers the sidewall of the conductive bump 61 and the surface away from the chip 20 . In this way, as shown in FIG.
  • the sidewalls of the conductive bumps 61 and the solder layer 70 facing away from the surface of the chip 20 can both be soldered to the circuit board 90 , and the conductive bumps only face away from the chip relative to the conductive bumps.
  • the surface of the semiconductor package is exposed from the dielectric layer, and the conductive bumps only have a surface facing away from the chip to form a solder layer.
  • the heat dissipation layer 80 is located on the side of the dielectric layer 50 away from the chip, and the heat dissipation layer 80 protrudes from the dielectric layer 50, the climbing ability of the solder is better when the solder layer 70 is formed, so the solder layer 70 wraps
  • the heat-dissipating layer 80 protrudes from the surface of the dielectric layer, that is, the solder layer 70 covers the sidewall of the heat-dissipating layer 80 and the surface facing away from the chip 20 .
  • the semiconductor package structure is soldered to the circuit board 90, the sidewalls of the heat dissipation layer 80 and the solder layer 70 facing away from the surface of the chip 20 can both be welded to the circuit board.
  • the reliability of the welding of the heat dissipation layer 80 and the circuit board 90 of the semiconductor package structure provided by the embodiments of the present application is higher.
  • the material of the solder layer 70 may be metal tin, gold-tin alloy, or nickel-based alloy and other materials that can realize the soldering function.
  • the solder layer 70 may be formed by a process such as electroplating, electroless plating, or screen printing. In some embodiments, the solder layer 70 may be formed on the surface of the conductive bump 61 by an electroplating process. In this way, the overall thickness of the semiconductor package structure can be more controllable, and at the same time, the thickness uniformity of the semiconductor package structure can be ensured. For board-level packaging, the packaging efficiency can be effectively improved and the cost can be reduced; at the same time, the formed solder layer can be formed. The thickness of 70 is larger, which can improve the reliability of the semiconductor package structure and other post-joint soldering.
  • the size of the through hole 51 is relatively large, and a depression is formed at the position of the conductive portion 52 corresponding to the through hole 51 of the dielectric layer 50 ; the solder layer 70 fills the depression.
  • the contact area between the solder layer 70 and the conductive bumps 61 of the lead layer 60 is larger, and the bonding force is better.
  • the solder layer 70 can be made thicker, which helps to improve the soldering between the semiconductor package structure and the circuit board 90 reliability.
  • the ratio of the width D to the depth H of the through hole 51 is greater than or equal to 1/3. In this way, the formed conductive portion 52 is more likely to form a depression at the through hole 51 , which is more helpful to increase the contact area between the conductive bump 61 and the solder layer 70 .
  • the ratio of the width D to the depth H of the through hole 51 is, for example, 1/3, 1/2, 2/3, 3/4, 3/2, and the like.
  • the depth H of the through hole 51 ranges from 60 ⁇ m to 100 ⁇ m, and the thickness S of the portion of the conductive portion 52 located on the bottom wall of the through hole 51 ranges from 10 ⁇ m to 50 ⁇ m. This arrangement further helps to provide enough filling space for the solder layer 70 in the through hole 51, thereby improving the reliability of the soldering between the semiconductor package structure and other structures.
  • the depth H (hereinafter referred to as the depth H) of the through hole 51 is 100 ⁇ m
  • the thickness S of the portion of the conductive portion 52 located on the bottom wall of the through hole 51 (hereinafter referred to as the thickness S) is 40 ⁇ m
  • the width D (hereinafter referred to as width D) of the through hole 51 is 50 ⁇ m; or the depth H is 80 ⁇ m, the thickness S is 35 ⁇ m, and the width D is 40 ⁇ m or 80 ⁇ m; or the depth H is 60 ⁇ m, the thickness S is 25 ⁇ m, and the width D is 30 ⁇ m or 80 ⁇ m etc.

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Abstract

本申请提供一种半导体封装方法及半导体封装结构。所述半导体封装方法包括：形成包封结构，所述包封结构包括包封层及芯片，所述芯片的正面设有多个焊垫，所述包封层至少覆盖所述芯片的侧面；在所述包封结构靠近所述芯片正面的一侧形成再布线层，所述再布线层将所述芯片的焊垫引出；形成介电层，所述介电层覆盖所述再布线层，且所述介电层上设有暴露所述再布线层的通孔；在所述介电层背离所述芯片的一侧形成引脚层，所述引脚层通过所述通孔与所述再布线层电连接。

Description

半导体封装方法及半导体封装结构 技术领域
本申请涉及半导体技术领域，特别涉及一种半导体封装方法及半导体封装结构。
背景技术
常见的半导体封装技术，比如芯片封装技术主要包含下述工艺过程：对于芯片正面进行工艺处理过程而言，首先将芯片的正面贴装在载板上，进行热压塑封，将载板剥离，然后在芯片的正面形成再布线层及位于再布线层背离芯片一侧的引脚层，之后形成绝缘层，绝缘层覆盖再布线层，且引脚层背离芯片的表面从绝缘层露出。
上述的芯片封装技术，由于引脚层形成在再布线层背离芯片的一侧，再布线层的面积大于引脚层的面积，因此再布线层的面积较大，再布线层与邻接的绝缘层接触面积较大。由于再布线层与绝缘层的热膨胀系数差别较大，在制备或芯片工作过程中再布线层的温度升高会使得再布线层与绝缘层的应力差较大，可能会使得再布线层与绝缘层发生分层或再布线层发生翘曲，影响产品的正常工作。
发明内容
本申请实施例提供了一种半导体封装方法及半导体封装结构。
根据本申请实施例的第一方面，提供了一种半导体封装方法，包括：
形成包封结构，所述包封结构包括包封层及芯片，所述芯片的正面设有多个焊垫，所述包封层至少覆盖所述芯片的侧面；
在所述包封结构靠近所述芯片正面的一侧形成再布线层，所述再布线层将所述芯片的焊垫引出；
形成介电层，所述介电层覆盖所述再布线层，且所述介电层上设有暴露所述再布线层的通孔；
在所述介电层背离所述芯片的一侧形成引脚层，所述引脚层通过所述通孔与所述再布线层电连接。
根据本申请实施例的第二方面，提供了一种半导体封装结构，所述半导体封装结构包括：
包封结构，所述包封结构包括包封层及芯片，所述芯片的正面设有多个焊垫，所述 包封层包覆所述芯片的背面及侧面；
再布线层，位于所述包封结构靠近所述芯片正面的一侧，所述再布线层将所述芯片的焊垫引出；
介电层，覆盖所述再布线层，所述介电层上设有暴露所述再布线层的通孔；
引脚层，位于所述介电层背离所述芯片的一侧，所述引脚层通过所述通孔与所述再布线层电连接。
本申请实施例所达到的主要技术效果是：根据本申请实施例提供的半导体封装方法及半导体封装结构，介电层覆盖再布线层，引脚层位于介电层背离再布线层的一侧，引脚层通过介电层上的通孔与再布线层电连接，也即引脚层与再布线层不直接接触，使得引脚层的尺寸不受再布线层尺寸的影响，因此可将再布线层的尺寸设置得较小一些，从而减小再布线层与相邻绝缘层例如介电层的接触面积，降低再布线层与相邻绝缘层的应力差，进而降低再布线层与相邻绝缘层发生分层或再布线层发生翘曲的风险，有助于提升产品的质量；引脚层与再布线层不直接接触，则引脚层的厚度受再布线层的影响较小，引脚层的厚度设计更加自由，有助于增大形成的引脚层的厚度，进而增大半导体封装结构的击穿电压，有助于半导体封装结构应用在高压环境中，扩大半导体封装结构的应用范围。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
图1是本申请一示例性实施例提供的半导体封装方法的流程图；
图2是本申请一示例性实施例提供的形成包封结构的流程图；
图3是本申请一示例性实施例提供的半导体封装结构的第一中间结构的局部剖视图；
图4是本申请一示例性实施例提供的半导体封装结构的第二中间结构的局部剖视图；
图5是本申请一示例性实施例提供的包封结构的局部剖视图；
图6是本申请另一示例性实施例提供的半导体封装结构的第三中间结构的局部剖视图；
图7是本申请另一示例性实施例提供的半导体封装结构的第三中间结构的局部剖视图；
图8是本申请另一示例性实施例提供的半导体封装结构的第四中间结构的局部剖视图；
图9是本申请另一示例性实施例提供的半导体封装结构的第五中间结构的局部剖视图；
图10是本申请另一示例性实施例提供的半导体封装结构的第六中间结构的局部剖视图；
图11是本申请另一示例性实施例提供的半导体封装结构的第六中间结构的结构示意图；
图12是本申请一示例性实施例提供的半导体封装结构的局部剖视图；
图13是本申请一示例性实施例提供的半导体封装结构与电路板焊接后的局部剖视图；
图14本申请另一示例性实施例提供的半导体封装结构的局部剖视图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施例并不代表与本申请相一致的所有实施例。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
下面结合附图，对本申请的一些实施例作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
本申请实施例提供了一种半导体封装方法。参见图1，所述半导体封装方法包括如下步骤110至步骤140。
在步骤110中，形成包封结构，所述包封结构包括包封层及芯片，所述芯片的正面设有多个焊垫，所述包封层至少覆盖所述芯片的侧面。
在步骤120中，在所述包封结构靠近所述芯片正面的一侧形成再布线层，所述再布线层将所述芯片的焊垫引出。
在步骤130中，形成介电层，所述介电层覆盖所述再布线层，且所述介电层设有暴露所述再布线层的通孔。
在步骤140中，在所述介电层背离所述芯片的一侧形成引脚层，所述引脚层通过所述通孔与所述再布线层电连接。
根据本申请实施例提供的半导体封装方法，介电层覆盖再布线层，引脚层位于介电层背离再布线层的一侧，引脚层通过介电层上的通孔与再布线层电连接，也即引脚层与再布线层不直接接触，使得引脚层的尺寸不受再布线层尺寸的影响，因此可将再布线层的尺寸设置得较小一些，从而减小再布线层与相邻绝缘层例如介电层的接触面积，降低再布线层与相邻绝缘层的应力差，进而降低再布线层与相邻绝缘层发生分层或再布线层发生翘曲的风险，有助于提升产品的质量；引脚层与再布线层不直接接触，则引脚层的厚度不受再布线层的影响较小，引脚层的厚度设计更加自由，有助于增大形成的引脚层的厚度，进而增大半导体封装结构的击穿电压，有助于半导体封装结构应用在高压环境中，扩大半导体封装结构的应用范围。
下面将对本申请实施例提供的半导体封装方法的各个步骤进行详细介绍。
在步骤110中，形成包封结构，所述包封结构包括包封层及芯片，所述芯片的正面设有多个焊垫，所述包封层至少覆盖所述芯片的侧面。
在一个实施例中，包封结构可包括一个或多个芯片，包封层上设有与芯片可一一对应的内凹的腔体，芯片位于对应的内凹的腔体内。
在一个实施例中，参见图2，所述形成包封结构的步骤110包括如下步骤111至步骤113。
在步骤111中，将所述芯片贴装于载板上，所述芯片的正面朝向所述载板的表面。
通过步骤111可得到如图3所示的第一中间结构。图3所示的实施例中，载板10上贴装有一个芯片20。在其他实施例中，载板10上贴装的芯片20的数量可为多个。
在一个实施例中，载板10包括用于贴装芯片20的贴装区。贴装区的形状是根据芯片20在整片载板10上的布局进行设计的，贴装区的形状可包括圆形、矩形或其他形状。载板10可包括一个或多个贴装区。
在一个实施例中，载板10的形状可为圆形、矩形或其他形状。载板10的材料可以是铁镍定膨胀合金，也可以是不锈钢、聚合物等。
在一个实施例中，芯片20可通过对硅片进行切割得到。硅片具有活性面，硅片的活性面设有焊垫。可采用机械切割的方式或者激光切割的方式切割硅片。可选的，在对硅片进行切割之前，可采用研磨设备对硅片与活性面相对的背面进行研磨，以使硅片的厚度为指定厚度。
芯片20的焊垫21是由芯片内部电路引出至芯片表面的导电电极构成。芯片20的正面可设有多个焊垫21。焊垫21用于将芯片20的导电电极引出。
在一个实施例中，在将所述芯片贴装于载板上的步骤111之前，所述半导体封装方法还包括：在所述芯片20的正面形成保护层22，保护层22上设有暴露所述焊垫21的开孔23。
在一些实施例中，可通过镭射工艺在保护层22上形成开孔23。开孔23的尺寸可小于焊垫21的尺寸，开孔23暴露焊垫21背离载板10的部分表面。
保护层22的材料可以为塑封膜、PI(聚酰亚胺)、PBO(聚苯并恶唑)、有机聚合物膜、有机聚合物复合材料或者其他具有类似特性的材料。在一些实施例中，保护层22中还可以加入有机或无机的填料。
在后续形成包封层的步骤112中，由于包封层在成型时需要高压成型，在此过程中形成包封层的包封材料容易渗透到载板10与芯片20之间。通过在芯片20的正面形成一层保护层22，保护层22能够防止包封材料渗透到芯片20表面，而且即使在形成包封层时包封材料有渗入到保护层22，在载板10与芯片20剥离之后，还可以通过化学方式或者研磨方式直接处理保护层22的表面，而不会直接接触到芯片20的正面，进而可避免破坏芯片20正面的焊垫。
在一个实施例中，芯片20可通过粘接层贴装于载板10，且粘接层可采用易剥离的材料，以便在后续将芯片20与载板10剥离开来，例如粘接层可采用通过加热能够使其失去粘性的热分离材料。
在步骤112中，形成包封层，所述包封层覆盖在所述载板上，包封住所述芯片。
通过步骤112可得到如图4所示的第二中间结构。
参见图4，包封层30形成在芯片20与露出的载板10上，用于将芯片20包封住，以重新构造一平板结构，以便在将载板10剥离后，能够继续在重新构造的该平板结构上进行再布线和封装。
在一个实施例中，在形成包封层30之前，可以执行一些前处理步骤，例如化学清洗、等离子清洗等步骤，以将芯片20与载板10表面的杂质去除，以便包封层30与芯片20及载板10之间能够连接的更加密切，不会出现分层或开裂的现象。
在一个实施例中，包封层30可采用层压环氧树脂膜的方式形成，也可以通过对环氧树脂化合物进行注塑成型、压模成型或传递成型等方式形成。
在一个实施例中，形成包封层的步骤112可包括如下步骤：
首先，形成包封结构，所述包封结构覆盖在所述载板上，包覆所述芯片。在该步骤中，包封结构的厚度大于芯片20的厚度，从而包封结构将芯片20完全包封住。
之后，对所述包封结构背离所述载板的一侧进行减薄处理，得到所述包封层。在该步骤中，可通过研磨工艺对包封结构进行减薄处理，使包封结构减薄至指定的厚度。
在步骤113中，去除所述载板，得到所述包封结构。
通过步骤113可得到如图5所示的包封结构。附图5所示的实施例中包封层30包覆芯片20的背面及侧面。在其他实施例中，包封层30可仅包覆芯片20的侧面等。
在一个实施例中，可直接机械的从包封层30及芯片20上剥离载板10。在另一个实施例中，芯片20与载板10与之间通过粘接层粘接，且粘接层的材料为热分离材料时，还可以通过加热的方式，使得粘接层遇热后粘性降低，进而将载板10剥离。载板10剥离后，各个芯片20的焊垫暴露出来。
在步骤120中，在所述包封结构靠近所述芯片正面的一侧形成再布线层，所述再布线层将所述芯片的焊垫引出。
通过步骤120可得到如图6所示的第三中间结构。包封结构靠近芯片正面的一侧指 的是芯片的正面所在的一侧。参见图6，再布线层40包括多个再布线结构41。每一再布线结构41可与一个焊垫21电连接，也可与多个焊垫21电连接。
在一个实施例中，保护层22的开孔23中形成有导电结构24，导电结构24与再布线结构41直接接触，再布线结构41通过导电结构24与焊垫21电连接。导电结构24与再布线结构41可在同一工艺步骤中形成，如此有助于简化半导体封装工艺。
在一个实施例中，步骤120可通过如下步骤完成：
首先，在所述包封结构靠近所述芯片正面的一侧形成种子层。种子层可覆盖芯片20的正面且将开孔23的内壁覆盖。
随后，在种子层背离芯片的一侧形成光阻层。光阻层为图形化的膜层。
随后，将种子层连接至电源，进行电镀，以在所述种子层背离所述芯片的一侧且未被所述光阻层遮挡的区域形成导电层。
随后，去除光阻层。
随后，对种子层进行图形化处理，将种子层未被导电层遮挡的区域刻蚀掉，未被刻蚀掉的种子层与导电层形成再布线层。
在一个实施例中，参见图7，所述再布线结构41设置有镂空部411。如此，可减小再布线结构41的尺寸，进而减小再布线结构41与相邻绝缘层的接触面积，进一步降低再布线结构41与相邻绝缘层剥离的风险。
在步骤130中，形成介电层，所述介电层覆盖所述再布线层，且所述介电层上设有暴露所述再布线层的通孔。
在一个实施例中，步骤130可通过如下过程完成：
首先，在包封结构上形成介电层，介电层包覆再布线层40及露出的包封层30。
通过该步骤可得到如图8所示的第四中间结构。参见图8，介电层50将再布线层40全部包覆。
随后，在介电层上形成暴露再布线层的通孔。
通过该步骤可得到如图9所示的第五中间结构。参见图9，介电层50上设有多个通孔51。介电层50与一个再布线结构41在纵向上对应的部分可设有一个通孔51或多个通孔51，也即一个再布线结构41可对应一个通孔51或多个通孔51。通孔51的尺寸小 于再布线结构41的尺寸，通孔51暴露再布线结构41的部分表面。
在一个实施例中，介电层50的材料可以是塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其他具有类似特性的材料。在一些实施例中，介电层50中还可以加入有机或无机的填料。
在一个实施例中，可采用镭射工艺在介电层50上形成通孔51。
在步骤140中，在所述介电层背离所述芯片的一侧形成引脚层，所述引脚层通过所述通孔与所述再布线层电连接。
通过步骤140可得到如图10所示的第六中间结构。参见图10，引脚层60包括多个间隔排布的导电凸柱61，导电凸柱61凸出于所述介电层50。
由于引脚层60位于介电层50背离芯片20的一侧，导电凸柱61凸出于所述介电层50，则不需要对介电层50进行研磨；相对于在形成引脚层之后形成介电层，通过研磨介电层使引脚层露出的方案来说，可节省对介电层进行研磨处理的时间，提升封装效率，降低生产成本；同时可避免研磨工艺的精度较低导致介电层厚度均匀性较差的问题，且可避免研磨介电层时研磨到引脚层，还可避免对引脚层的应力损伤芯片的焊垫，有助于提升封装产品的质量。
在一个实施例中，介电层50的通孔51中形成有导电部52，导电部52分别与再布线结构41及导电凸柱61直接接触，导电凸柱61通过导电部52与再布线结构41电连接。导电凸柱61与导电部52可在同一工艺步骤中形成，如此有助于简化半导体封装工艺。
在一个实施例中，可采用电镀工艺在介电层50背离芯片20的一侧形成引脚层60。由于引脚层60形成于介电层50上，不与再布线层40直接接触，通过电镀工艺可在介电层50背离芯片20的一侧形成厚度较大的导电层，从而对导电层进行刻蚀得到厚度较大的引脚层60。
在一个实施例中，所述引脚层60的厚度d大于30μm。如此设置，可有效提升半导体封装结构的击穿电压。在一些实施例中，导电部52与引脚层60可以同时形成，如此设置也可避免因导电部52的厚度较小而导致导电部52位于通孔51的侧壁处的部分发生断裂。在一些实施例中，引脚层60的厚度d例如为31μm、33μm、35μm、37μm、40μm等。
在一个实施例中，所述半导体封装方法还包括：在介电层50背离芯片20的一侧形 成散热层。
参见图11，散热层80的面积较大，可使得半导体封装结构的散热效果较好。每一芯片20可对应一个散热层80，芯片20的多个导电凸柱61可位于其对应的散热层80周侧。
在一个实施例中，散热层80可与引脚层60在同一工艺步骤中形成。如此有助于简化半导体封装工艺。此时，散热层80可全部凸出于介电层50。
在一个实施例中，在所述介电层背离所述芯片的一侧形成引脚层的步骤140之后，所述半导体封装方法还包括：形成焊料层，所述焊料层包覆所述导电凸柱凸出于所述介电层的表面。
通过该步骤可得到如图12所示的半导体封装结构。
由于引脚层60的导电凸柱61位于介电层50背离芯片20的一侧，导电凸柱61整体凸出于介电层50，在形成焊料层70时焊料的爬升能力较好，形成的焊料层70可将导电凸柱61凸出于介电层的表面全部包覆，也即焊料层70将导电凸柱61的侧壁及背离芯片20的表面全部包覆。如此，如图13所示，半导体封装结构与电路板90焊接时，导电凸柱61的侧壁及背离芯片20表面的焊料层70可均与电路板90焊接，相对于导电凸柱仅背离芯片的表面从介电层露出，导电凸柱只有背离芯片的表面形成焊料层的方案来说，本申请实施例得到的半导体封装结构的导电凸柱61与电路板90焊接的可靠性更高，且本申请实施例相对于通过回流焊工艺形成锡球的方案来说，工艺更简单。
在一些实施例中，焊料层70的材料可以是金属锡、金锡合金或者镍基合金等可实现焊接功能的材料。
在一些实施例中，焊料层70可采用电镀、化学镀或者网板印刷等工艺来形成。在一些实施例中，可采用电镀工艺在导电凸柱61表面形成焊料层70。如此可使得半导体封装结构整体的厚度更加可控，同时可保证半导体封装结构的厚度均一性，对于板级封装来说，可有效提升封装效率，有助于降低成本；同时可使得形成的焊料层70的厚度较大，可提升半导体封装结构与其他节后焊接的可靠性。
在一个实施例中，由于散热层80位于介电层50背离芯片20的一侧，散热层80凸出于介电层50，在形成焊料层70时焊料的爬升能力较好，则焊料层70包覆散热层80凸出于介电层的表面，也即焊料层70将散热层80的侧壁及背离芯片20的表面包覆。半导体封装结构与电路板90焊接时，散热层80的侧壁及背离芯片20表面的焊料层70 可均与电路板焊接，相对于散热层仅背离芯片的表面从介电层露出，焊料层仅形成于散热层背离芯片的表面的方案来说，本申请实施例得到的半导体封装结构的散热层80与电路板90焊接的可靠性更高。
在一个实施例中，再次参见图11，在形成焊料层70时，首先形成镀锡线71，镀锡线71与各个导电凸柱61及散热层80电连接，随后将镀锡线71与外部电源电连接进行电镀，以在导电凸柱61的侧壁与背离芯片20的表面、以及散热层80的侧壁与背离芯片20的表面形成焊料层70。
在一个实施例中，参见图14，通孔51的尺寸较大，可避免所述导电部52位于所述介电层50的通孔51侧壁处的部分发生断裂；所述焊料层70填充导电部52形成的凹陷。如此，焊料层70与引脚层60的导电凸柱61的接触面积更大，结合力更好，同时能为焊料层70提供足够的填充空间，可将焊料层70做得更厚，有助于提升半导体封装结构与电路板90焊接的可靠性。
在一些实施例中，所述通孔51的宽度D与深度H的比值大于或等于1/3。如此设置，形成的导电部52更易于在通孔51处形成凹陷，更有助于提升导电凸柱61与焊料层70的接触面积。通孔51的宽度D与深度H的比值例如为1/3、1/2、2/3、3/4、3/2等。
在一个实施例中，所述通孔51的深度H范围为60μm至100μm，所述导电部52位于所述通孔51底壁的部分的厚度S的范围为10μm至50μm。如此设置，更有助于在通孔51内为焊料层70提供足够的填充空间，从而提升半导体封装结构与其他结构焊接的可靠性。在一些实施例中，所述通孔51的深度H(以下简称深度H)为100μm，所述导电部52位于所述通孔51底壁的部分的厚度S(以下简称厚度S)为40μm，通孔51的宽度D(以下简称宽度D)为50μm；或者，深度H为80μm，厚度S为35μm，宽度D为40μm或80μm；或者，深度H为60μm，厚度S为25μm,宽度D为30μm或80μm等。
本申请实施例还提供了一种半导体封装结构。参见图12与图14，所述半导体封装结构包括包封结构、再布线层40、介电层50与引脚层60。
所述包封结构包括包封层30及芯片20，所述芯片20的正面设有多个焊垫21，所述包封层30至少覆盖所述芯片20的侧面。所述再布线层40位于所述包封结构靠近所述芯片20正面的一侧，所述再布线层40将所述芯片20的焊垫21引出。其中包封结 构靠近芯片20正面的一侧指的是芯片20的正面所在的一侧。所述介电层50覆盖所述再布线层40，所述介电层50上设有暴露部分所述再布线层40的通孔51。所述引脚层60位于所述介电层50背离所述芯片20的一侧，所述引脚层60通过所述通孔51与所述再布线层40电连接。
根据本申请实施例提供的半导体封装结构，介电层覆盖再布线层，引脚层位于介电层背离再布线层的一侧，引脚层通过介电层上的通孔与再布线层电连接，也即引脚层与再布线层不直接接触，使得引脚层的大小不受再布线层的影响，因此可将再布线层的面积设置得较小一些，从而减小再布线层与相邻绝缘层例如介电层的接触面积，降低再布线层与相邻绝缘层的应力差，进而降低再布线层与绝缘层发生分层或再布线层发生翘曲的风险，有助于提升产品的质量；引脚层与再布线层不直接接触，则引脚层的厚度不受再布线层的影响，引脚层的厚度设计更加自由，有助于增大形成的引脚层的厚度，进而增大半导体封装结构的击穿电压，有助于半导体封装结构应用在高压环境中，扩大半导体封装结构的应用范围。
在一个实施例中，芯片20的正面形成有保护层22，保护层22上设有暴露所述焊垫21的开孔23。开孔23的尺寸可小于焊垫21的尺寸，开孔23暴露焊垫21背离载板10的部分表面。
保护层22的材料可以为塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其他具有类似特性的材料。在一些实施例中，保护层22中还可以加入有机或无机的填料。
在形成包封层时需要高压成型，在此过程中形成包封层的包封材料容易渗透到载板10与芯片20之间。通过在芯片20的正面形成一层保护层22，保护层22能够防止包封材料渗透到芯片20表面，而且即使在形成包封层30时包封材料有渗入到保护层22，在载板10与芯片20剥离之后，还可以通过化学方式或者研磨方式直接处理保护层22的表面，而不会直接接触到芯片20的正面，进而可避免破坏芯片20正面的焊垫。
在一个实施例中，保护层22的开孔23中形成有导电结构24，导电结构24与再布线结构41直接接触，再布线结构41通过导电结构24与焊垫21电连接。导电结构24的材料与再布线结构41的材料可相同，从而导电结构24与再布线结构41可在同一工艺步骤中形成，如此有助于简化形成半导体封装结构的封装工艺。
在一个实施例中，再布线层40包括多个间隔排布的再布线结构41。每一再布线 结构41可与一个焊垫21电连接，也可与多个焊垫21电连接。
在一个实施例中，参见图7，所述再布线结构41设置有镂空部411。如此，可减小再布线结构41的尺寸，进而减小再布线结构41与相邻绝缘层的接触面积，进一步降低再布线结构41与相邻绝缘层剥离的风险。
在一个实施例中，介电层50上设有多个通孔51。介电层50与一个再布线结构41在纵向上对应的部分可设有一个通孔51或多个通孔51，也即一个再布线结构41可对应一个通孔51或多个通孔51。通孔51的尺寸小于再布线结构41的尺寸，通孔51暴露再布线结构41的部分表面。
在一个实施例中，介电层50的材料可以是塑封膜、PI、PBO、有机聚合物膜、有机聚合物复合材料或者其他具有类似特性的材料。在一些实施例中，介电层50中还可以加入有机或无机的填料。
在一个实施例中，引脚层60包括多个间隔排布的导电凸柱61，导电凸柱61凸出于所述介电层50。
由于引脚层60位于介电层50背离芯片20的一侧，导电凸柱61凸出于所述介电层50，则不需要对介电层50进行研磨，相对于在形成引脚层之后形成介电层，通过研磨介电层使引脚层露出的方案来说，可节省对介电层进行研磨处理的时间，提升封装效率，降低生产成本；同时可避免研磨工艺的精度较低导致介电层厚度均匀性较差的问题，且可避免研磨介电层时研磨到引脚层，还可避免对引脚层的应力损伤芯片的焊垫，有助于提升封装产品的质量。
在一个实施例中，介电层50的通孔51中形成有导电部52，导电部52分别与再布线结构41及导电凸柱61直接接触，导电凸柱61通过导电部52与再布线结构41电连接。导电凸柱61的材料与导电部52的材料可相同，从而导电凸柱61与导电部52可在同一工艺步骤中形成，如此有助于简化半导体封装结构的封装工艺。
在一个实施例中，所述引脚层60的厚度d大于30μm。如此设置，可有效提升半导体封装结构的击穿电压；在一些实施例中，导电部52与引脚层60可以同时形成，如此设置也可避免导电部52位于通孔51的侧壁处的部分发生断裂。在一些实施例中，引脚层60的厚度例如为31μm、33μm、35μm、37μm、40μm等。
在一个实施例中，参见图11，所述半导体封装结构还包括散热层80。散热层80的面积较大，可使得半导体封装结构的散热效果较好。每一芯片20可对应一个散热层 80，芯片20对应的多个导电凸柱61可位于其对应的散热层80周侧。
在一个实施例中，散热层80的材料与引脚层60的材料可相同，因而散热层80与引脚层60可在同一工艺步骤中形成，有助于简化半导体封装结构的封装工艺。此时，散热层80可全部凸出于介电层50。
在一个实施例中，所述半导体封装结构还包括焊料层70，所述焊料层70包覆所述导电凸柱61凸出于所述介电层50的表面。
由于引脚层60的导电凸柱61位于介电层50背离芯片20的一侧，导电凸柱61整体凸出于介电层50，在形成焊料层70时焊料的爬升能力较好，形成的焊料层70可将导电凸柱61凸出于介电层的表面全部包覆，也即焊料层70将导电凸柱61的侧壁及背离芯片20的表面全部包覆。如此，如图13所示，半导体封装结构与电路板90焊接时，导电凸柱61的侧壁及背离芯片20表面的焊料层70可均与电路板90焊接，相对于导电凸柱仅背离芯片的表面从介电层露出，导电凸柱只有背离芯片的表面形成焊料层的方案来说，本申请实施例提供的半导体封装结构的导电凸柱61与电路板90焊接的可靠性更高。
在一个实施例中，由于散热层80位于介电层50背离芯片的一侧，散热层80凸出于介电层50，在形成焊料层70时焊料的爬升能力较好，则焊料层70包覆散热层80凸出于介电层的表面，也即焊料层70将散热层80的侧壁及背离芯片20的表面包覆。半导体封装结构与电路板90焊接时，散热层80的侧壁及背离芯片20表面的焊料层70可均与电路板焊接，相对于散热层仅背离芯片的表面从介电层露出，焊料层仅形成于散热层背离芯片的表面的方案来说，本申请实施例提供的半导体封装结构的散热层80与电路板90焊接的可靠性更高。
在一些实施例中，焊料层70的材料可以是金属锡、金锡合金或者镍基合金等可实现焊接功能的材料。
在一些实施例中，焊料层70可采用电镀、化学镀或者网板印刷等工艺来形成。在一些实施例中，可采用电镀工艺在导电凸柱61表面形成焊料层70。如此可使得半导体封装结构整体的厚度更加可控，同时可保证半导体封装结构的厚度均一性，对于板级封装来说，可有效提升封装效率，有助于降低成本；同时可使得形成的焊料层70的厚度较大，可提升半导体封装结构与其他节后焊接的可靠性。
在一个实施例中，参见图14，通孔51的尺寸较大，导电部52与所述介电层50 的通孔51对应的位置处形成凹陷；所述焊料层70填充所述凹陷。如此，焊料层70与引脚层60的导电凸柱61的接触面积更大，结合力更好，同时也可将焊料层70做得更厚，有助于提升半导体封装结构与电路板90焊接的可靠性。
在一些实施例中，所述通孔51的宽度D与深度H的比值大于或等于1/3。如此设置，形成的导电部52更易于在通孔51处形成凹陷，更有助于提升导电凸柱61与焊料层70的接触面积。通孔51的宽度D与深度H的比值例如为1/3、1/2、2/3、3/4、3/2等。
在一个实施例中，所述通孔51的深度H范围为60μm至100μm，所述导电部52位于所述通孔51底壁的部分的厚度S的范围为10μm至50μm。如此设置，更有助于在通孔51内为焊料层70提供足够的填充空间，从而提升半导体封装结构与其他结构焊接的可靠性。在一些实施例中，所述通孔51的深度H(以下简称深度H)为100μm，所述导电部52位于所述通孔51底壁的部分的厚度S(以下简称厚度S)为40μm，通孔51的宽度D(以下简称宽度D)为50μm；或者，深度H为80μm，厚度S为35μm，宽度D为40μm或80μm；或者，深度H为60μm，厚度S为25μm,宽度D为30μm或80μm等。
本申请实施例提供的半导体封装方法与半导体封装结构属于同一发明构思，相关细节及有益效果的描述可互相参见，不再进行赘述。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构， 并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (17)

  1. 一种半导体封装方法，包括：
    形成包封结构，所述包封结构包括包封层及芯片，所述芯片的正面设有多个焊垫，所述包封层至少覆盖所述芯片的侧面；
    在所述包封结构靠近所述芯片正面的一侧形成再布线层，所述再布线层将所述芯片的焊垫引出；
    形成介电层，所述介电层覆盖所述再布线层，且所述介电层上设有暴露所述再布线层的通孔；
    在所述介电层背离所述芯片的一侧形成引脚层，所述引脚层通过所述通孔与所述再布线层电连接。
  2. 根据权利要求1所述的半导体封装方法，其特征在于，所述引脚层包括多个间隔排布的导电凸柱，所述导电凸柱凸出于所述介电层；在所述介电层背离所述芯片的一侧形成所述引脚层之后，所述半导体封装方法还包括：
    形成焊料层，所述焊料层包覆所述导电凸柱凸出于所述介电层的表面。
  3. 根据权利要求1所述的半导体封装方法，其特征在于，所述引脚层包括多个间隔排布的导电凸柱，所述导电凸柱凸出于所述介电层；所述通孔内设有导电部，所述引脚层通过所述导电部与所述再布线层电连接，所述导电部与所述通孔对应的位置处形成凹陷；在所述介电层背离所述芯片的一侧形成所述引脚层之后，所述半导体封装方法还包括：
    形成焊料层，所述焊料层包覆所述导电凸柱凸出于所述介电层的表面，且所述焊料层填充所述凹陷。
  4. 根据权利要求3所述的半导体封装方法，其特征在于，所述通孔的宽度与深度的比值大于或等于1/3。
  5. 根据权利要求4所述的半导体封装方法，其特征在于，所述通孔的深度范围为60μm至100μm；所述导电部位于所述通孔底壁的部分的厚度范围为10μm至50μm。
  6. 根据权利要求1所述的半导体封装方法，其特征在于，所述引脚层的厚度大于30μm。
  7. 根据权利要求1所述的半导体封装方法，其特征在于，所述半导体封装方法还包括：在所述介电层背离所述芯片的一侧形成散热层；
    在所述介电层背离所述芯片的一侧形成所述散热层之后，所述半导体封装方法还包括：形成焊料层，所述焊料层包覆所述散热层露出于所述介电层的表面。
  8. 根据权利要求1所述的半导体封装方法，其特征在于，所述再布线层包括多个间隔设置的再布线结构，所述再布线结构设置有镂空部。
  9. 一种半导体封装结构，包括：
    包封结构，所述包封结构包括包封层及芯片，所述芯片的正面设有多个焊垫，所述包封层包覆所述芯片的背面及侧面；
    再布线层，位于所述包封结构靠近所述芯片正面的一侧，所述再布线层将所述芯片的焊垫引出；
    介电层，覆盖所述再布线层，所述介电层上设有暴露所述再布线层的通孔；
    引脚层，位于所述介电层背离所述芯片的一侧，所述引脚层通过所述通孔与所述再布线层电连接。
  10. 根据权利要求9所述的半导体封装结构，其特征在于，所述引脚层包括多个间隔排布的导电凸柱，所述导电凸柱凸出于所述介电层；所述半导体封装结构还包括焊料层，所述焊料层包覆所述导电凸柱凸出于所述介电层的表面。
  11. 根据权利要求9所述的半导体封装结构，其特征在于，所述引脚层包括多个间隔排布的导电凸柱，所述导电凸柱凸出于所述介电层；所述通孔内设有导电部，所述引脚层通过所述导电部与所述再布线层电连接，所述导电部与所述通孔对应的位置处形成凹陷；所述半导体封装结构还包括焊料层，所述焊料层包覆所述导电凸柱凸出于所述介电层的表面，且所述焊料层填充所述凹陷。
  12. 根据权利要求11所述的半导体封装结构，其特征在于，所述通孔的宽度与深度的比值大于或等于1/3。
  13. 根据权利要求12所述的半导体封装结构，其特征在于，所述通孔的深度范围为60μm至100μm；所述导电部位于所述通孔底壁的部分的厚度范围为10μm至50μm。
  14. 根据权利要求9所述的半导体封装结构，其特征在于，所述引脚层的厚度大于30μm。
  15. 根据权利要求9所述的半导体封装结构，其特征在于，所述再布线层包括多个间隔设置的再布线结构，所述再布线结构设有镂空部。
  16. 根据权利要求15所述的半导体封装结构，还包括：
    形成于所述芯片的正面的保护层，其中，所述保护层包括暴露所述多个焊垫的开孔；
    形成于所述保护层的开孔内的导电结构，其中，所述再布线结构通过所述导电结构与所述焊垫电连接。
  17. 根据权利要求16所述的半导体封装结构，还包括：
    位于所述介电层背离所述芯片的一侧的散热层，其中，所述引脚层包括多个间隔排布的导电凸柱，所述多个间隔排布的导电凸柱位于所述散热层的周侧。
PCT/CN2021/124847 2020-12-21 2021-10-20 半导体封装方法及半导体封装结构 WO2022134789A1 (zh)

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