WO2022133792A1 - 显示面板及其制造方法、显示装置 - Google Patents

显示面板及其制造方法、显示装置 Download PDF

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Publication number
WO2022133792A1
WO2022133792A1 PCT/CN2020/138584 CN2020138584W WO2022133792A1 WO 2022133792 A1 WO2022133792 A1 WO 2022133792A1 CN 2020138584 W CN2020138584 W CN 2020138584W WO 2022133792 A1 WO2022133792 A1 WO 2022133792A1
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WIPO (PCT)
Prior art keywords
layer
base substrate
cofferdam
display panel
resistor
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PCT/CN2020/138584
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English (en)
French (fr)
Inventor
陈登云
刘浩
张慧娟
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080003600.7A priority Critical patent/CN114981764A/zh
Priority to PCT/CN2020/138584 priority patent/WO2022133792A1/zh
Priority to US17/599,628 priority patent/US20220399419A1/en
Publication of WO2022133792A1 publication Critical patent/WO2022133792A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • OLED organic light emitting diode
  • a display panel comprising: a base substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels located in the display area, among the plurality of sub-pixels At least one sub-pixel of the pixel includes a driving transistor, and the driving transistor includes a multi-layer conductive layer; a first bank surrounding the display area, located in the peripheral area; a second bank surrounding the display area, located in the The peripheral area is located on the side of the first bank away from the display area; the encapsulation layer is located at the side of the plurality of sub-pixels, the first bank and the second bank away from the base substrate one side, wherein the orthographic projections of the plurality of sub-pixels, the first dam and the second dam on the base substrate are located between the orthographic projections of the encapsulation layer on the base substrate and at least one pressure sensor on at least one of a first side of the second cofferdam close to the first cofferdam and
  • the driving transistor includes: an active layer and a gate, located on one side of the base substrate; a first insulating layer, located between the active layer and the gate; a second insulating layer an insulating layer, located on a side of the active layer, the gate electrode and the first insulating layer away from the base substrate; a third insulating layer, located at a side of the second insulating layer away from the base substrate one side; and a first electrode and a second electrode, located on the side of the third insulating layer away from the base substrate, and electrically connected to the active layer, wherein the multi-layer conductive layer includes the gate electrode, the first electrode and the second electrode, the at least one resistor, the first electrode and the second electrode are located on the same layer.
  • the at least one sub-pixel further includes a storage capacitor
  • the storage capacitor includes: a first electrode plate located on the same layer as the gate electrode; and a second electrode plate located on the second insulating layer and the third insulating layer.
  • the at least one resistor includes a first resistor electrically connected between the first input terminal and the first output terminal, a second resistor electrically connected between the first output terminal and the second input terminal, and a second resistor electrically connected between the first output terminal and the second input terminal.
  • the display panel further includes a first signal output line electrically connected to the first output end and a second signal output line electrically connected to the second output end, the first signal output line and the second signal output line The signal output line is located on the same layer as one of the first electrode plate and the second electrode plate.
  • the first signal output line and the second signal output line are located on the same layer as the second electrode plate.
  • the display panel further includes: a first signal input line electrically connected to the first input end; and a second signal input line electrically connected to the second input end, the first signal input line
  • the signal input line and the second signal input line are located on the same layer as the other of the first electrode plate and the second electrode plate.
  • the first resistance and the third resistance are arranged symmetrically with respect to the first line, and the second resistance and the fourth resistance are arranged symmetrically with respect to the second line.
  • the first line and the second line are perpendicular.
  • the first resistance is located on one side of the first line, and the second resistance, the third resistance and the fourth resistance are located on the other side of the first line.
  • the display panel further includes: a crack arrester located on a side of the encapsulation layer away from the display area, wherein the at least one pressure sensor is located on the crack arrester close to the display area side.
  • the at least one pressure sensor includes a first pressure sensor located between the second dam and the first dam, wherein the first pressure sensor is on the substrate
  • the orthographic projection on the substrate is within the orthographic projection of the encapsulation layer on the base substrate.
  • the at least one pressure sensor includes: a second pressure sensor located between the second dam and the crack stop, wherein the second pressure sensor is on the base substrate The orthographic projection of is within the orthographic projection of the encapsulation layer on the base substrate.
  • the at least one pressure sensor includes a third pressure sensor located between the encapsulation layer and the crack arrester.
  • the display panel further includes: a buffer layer located between the base substrate and the first insulating layer, wherein: the first insulating layer, the second insulating layer, the The third insulating layer and the buffer layer extend from the display area to the peripheral area, and the crack stopper penetrates the third insulating layer, the second insulating layer, the first insulating layer and all the the buffer layer.
  • the at least one sub-pixel further comprises: a planarization layer located on a side of the first electrode, the second electrode and the third insulating layer away from the base substrate; an anode, a side of the planarization layer away from the base substrate, and electrically connected to one of the first electrode and the second electrode; a pixel defining layer, located at a distance from the anode and the planarization layer one side of the base substrate, and has a first opening, the orthographic projection of the first opening on the base substrate at least partially overlaps the orthographic projection of the anode on the base substrate; function a layer at least partially located in the first opening and located on the side of the anode away from the base substrate; and a cathode located at least partially in the first opening and located away from the functional layer side of the base substrate.
  • the display panel further includes a power bus located in the peripheral region, electrically connected to the cathode, and located on the same layer as the first electrode and the second electrode.
  • the planarization layer has a second opening
  • the pixel defining layer further has a third opening
  • the orthographic projections of the second opening and the third opening on the base substrate are located at the the peripheral region
  • the display panel further includes an electrical connection part located at least partially in the second opening, on the same layer as the anode, and in contact with the power bus; and the cathode partially located on the in the third opening and in contact with the electrical connection part.
  • the display panel further includes: a plurality of initialization lines located in the display area, electrically connected to the plurality of sub-pixels, and configured to provide initialization signals to the plurality of sub-pixels; and an initialization bus line , located in the peripheral region, located between the planarization layer and the base substrate, electrically connected to the plurality of initialization lines, and located in the same layer as the first electrode and the second electrode.
  • the first dam includes: a first layer on the same layer as the planarization layer; and a second layer on a side of the first layer away from the base substrate, and on the same layer as the pixel defining layer.
  • the second cofferdam includes: a third layer, located on the same layer as the planarization layer; a fourth layer, located on a side of the third layer away from the base substrate, and the same as the the pixel defining layer is located on the same layer; and the fifth layer is located on the side of the fourth layer away from the base substrate and is located on the same layer as the support layer, wherein the support layer is located in the display area, and is located on the side of the pixel defining layer away from the base substrate.
  • a display device comprising: the display panel according to any one of the above embodiments.
  • a method for manufacturing a display panel including: providing a base substrate, the base substrate including a display area and a peripheral area surrounding the display area; forming a plurality of sub-pixels, a first a cofferdam, a second cofferdam and at least one pressure sensor, wherein: the plurality of sub-pixels are located in the display area, and at least one sub-pixel in the plurality of sub-pixels includes a drive transistor, and the drive transistor includes a multi-layer conductive layer, The first cofferdam and the second cofferdam are located in the peripheral area and surround the display area, the second cofferdam is located on a side of the first cofferdam away from the display area, and the The at least one pressure sensor is located on at least one of a first side of the second cofferdam close to the first cofferdam and a second side away from the first cofferdam, wherein the at least one pressure sensor is At least one resistor in each of the pressure sensors is located on
  • FIG. 1 is a schematic structural diagram illustrating a display panel according to an embodiment of the present disclosure
  • 2A is a schematic cross-sectional view illustrating a sub-pixel in a display panel according to an embodiment of the present disclosure
  • 2B is a schematic cross-sectional view illustrating a display panel according to an embodiment of the present disclosure
  • FIG. 3 is a schematic circuit diagram illustrating a pressure sensor according to an embodiment of the present disclosure
  • 4A is a schematic cross-sectional view illustrating wiring of a pressure sensor according to one embodiment of the present disclosure
  • 4B is a schematic cross-sectional view illustrating wiring of a pressure sensor according to another embodiment of the present disclosure.
  • 5A and 5B are schematic layout diagrams illustrating a pressure sensor according to some embodiments of the present disclosure.
  • FIG. 6 is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure.
  • first,” “second,” and similar words do not denote any order, quantity, or importance, but are merely used to distinguish the different parts.
  • “Comprising” or “comprising” and similar words mean that the element preceding the word covers the elements listed after the word, and does not exclude the possibility that other elements are also covered.
  • “Up”, “down”, etc. are only used to indicate the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • a specific component when a specific component is described as being between a first component and a second component, there may or may not be an intervening component between the specific component and the first component or the second component.
  • the specific component When it is described that a specific component is electrically connected to other components, the specific component may be directly electrically connected to the other components without intervening components, or may not be directly electrically connected to the other components but have intervening components.
  • FIG. 1 is a schematic structural diagram illustrating a display panel according to an embodiment of the present disclosure.
  • the display panel includes a base substrate 11 and a plurality of sub-pixels 12 .
  • the base substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area.
  • the base substrate 11 includes a first base substrate layer, a second base substrate layer, a first barrier layer, and a second barrier layer.
  • the first barrier layer is located between the first substrate substrate layer and the second substrate substrate layer
  • the second substrate substrate layer is located between the first barrier layer and the second barrier layer.
  • the material of at least one of the first base substrate layer and the second base substrate layer may include a flexible material such as polyimide (PI).
  • the material of at least one of the first barrier layer and the second barrier layer may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • a plurality of sub-pixels 12 are located in the display area 111 .
  • the plurality of sub-pixels 12 may include red sub-pixels, green sub-pixels, blue sub-pixels, or the like.
  • Each sub-pixel 12 includes a pixel circuit.
  • a pixel circuit may include 6 transistors and 1 capacitor (6T1C); as another example, a pixel circuit may include 7 transistors and 1 capacitor (7T1C).
  • the display panel further includes a plurality of data lines DL.
  • the plurality of data lines DL are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12 located in the display area 111 .
  • the plurality of data lines DL are configured to provide data signals to the plurality of sub-pixels 12. For example, each data line 13 is electrically connected to a column of sub-pixels 12 .
  • the display panel further includes a plurality of gate lines GL.
  • the plurality of gate lines GL are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12 .
  • the plurality of gate lines GL are configured to supply gate signals to the plurality of sub-pixels 12 .
  • each gate line GL is electrically connected to a row of sub-pixels 12 .
  • the display panel further includes a plurality of light emission control lines GCL.
  • the plurality of light emission control lines GCL are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12 .
  • the plurality of light emission control lines GCL are configured to provide light emission control signals to the plurality of sub-pixels 12 .
  • each light emission control line 15 is electrically connected to a row of sub-pixels 12 .
  • the display panel further includes a plurality of power lines PL.
  • a plurality of power supply lines PL are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12 .
  • the plurality of power supply lines 16 are configured to provide power supply signals to the plurality of sub-pixels 12 .
  • the display panel further includes a plurality of initialization lines IL.
  • a plurality of initialization lines IL are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12 .
  • the plurality of initialization lines IL are configured to provide initialization signals to the plurality of sub-pixels 12 .
  • FIG. 2A is a schematic cross-sectional view illustrating a sub-pixel in a display panel according to an embodiment of the present disclosure.
  • FIG. 2B is a schematic cross-sectional view illustrating a display panel according to an embodiment of the present disclosure.
  • the structure of a display panel according to some embodiments of the present disclosure will be described below with reference to FIGS. 2A and 2B .
  • the sub-pixel 12 includes a drive transistor 121 .
  • the driving transistor 121 includes multiple conductive layers.
  • the drive transistor 121 may be a top-gate transistor; as other implementations, the drive transistor 121 may be a bottom-gate transistor.
  • FIG. 2A shows the case where the driving transistor 121 is a top-gate transistor.
  • the display panel in addition to the base substrate 11 and a plurality of sub-pixels 12 , the display panel further includes a first bank 13 , a second bank 14 , an encapsulation layer 15 and at least one pressure sensor 16 .
  • the pressure sensor 16 may act as a volume key or an on key.
  • Both the first cofferdam 13 and the second cofferdam 14 surround the display area 111 and are located in the peripheral area 112 .
  • the second cofferdam 14 is located on the side of the first cofferdam 13 away from the display area 111 .
  • the first cofferdam 13 and the second cofferdam 14 may block water and oxygen from entering the sub-pixels 12 .
  • the encapsulation layer 15 is located on a side of the plurality of sub-pixels 12 , the first bank 13 and the second bank 14 away from the base substrate 11 .
  • the orthographic projections of the plurality of sub-pixels 12 , the first bank 13 and the second bank 14 on the base substrate 11 are located within the orthographic projection of the encapsulation layer 15 on the base substrate 11 .
  • the encapsulation layer 15 may comprise a thin film encapsulation layer.
  • the encapsulation layer 15 may include a first inorganic layer 151 , a second inorganic layer 152 , and an organic layer 153 between the first inorganic layer 151 and the second inorganic layer 152 .
  • the display panel may further include a third bank 22 located between the second bank 14 and the display area 111 . The third bank 22 is used to block the flow of the organic layer 153 .
  • At least one pressure sensor 16 is located on at least one of a first side of the second cofferdam 14 close to the first cofferdam 13 and a second side away from the first cofferdam 13 .
  • the at least one pressure sensor 16 is located on the first side of the second cofferdam 14 close to the first cofferdam 13 ; for another example, the at least one pressure sensor 16 is located on the second cofferdam 14 away from the first cofferdam 13 .
  • Two sides; for another example, one or more pressure sensors 16 of the at least one pressure sensor 16 are located on the first side of the second cofferdam 14 close to the first cofferdam 13, and one or more of the at least one pressure sensor 16 The pressure sensor 16 is located on the second side of the second cofferdam 14 away from the first cofferdam 13 .
  • At least one resistor R in each pressure sensor 16 is located on the same layer as one of the multiple conductive layers in the drive transistor 121 .
  • the at least one resistor R of the pressure sensor 16 includes four resistors.
  • the multiple components are located in the same layer means that the multiple components are formed by performing a patterning process on the same material layer. Therefore, the materials of these multiple parts are the same, and the thicknesses are basically the same.
  • At least one pressure sensor 16 is located on at least one of the first side of the second cofferdam 14 close to the first cofferdam 13 and the second side away from the first cofferdam 13 , and each pressure sensor 16 At least one resistor R of , is located on the same layer as one of the multi-layer conductive layers in the driving transistor 121 . Under such a structure, the pressure sensor 16 can be formed in the process of forming the sub-pixels 12, without adding additional interactive keys, which is beneficial to reduce the thickness of the display panel.
  • the pressure sensor 16 can make full use of the space of the peripheral area 112 without additionally increasing the size of the peripheral area 112. Therefore, some embodiments of the present disclosure can reduce the thickness of the display panel while realizing a narrow frame.
  • driving transistor 121 Some specific implementations of the driving transistor 121 are described below with reference to FIG. 2A .
  • the driving transistor 121 includes an active layer 1211 , a gate electrode 1212 , a first insulating layer 1213 , a second insulating layer 1214 , a third insulating layer 1215 , a first electrode 1216 and a second electrode 1217 .
  • the multi-layer conductive layers in the driving transistor 121 include a gate electrode 1212 , a first electrode 1216 and a second electrode 1217 .
  • the active layer 1211 and the gate electrode 1212 are located on one side of the base substrate 11 .
  • the gate 1212 is located on the side of the active layer 1211 away from the base substrate 11 .
  • the material of the active layer 1211 may include polysilicon.
  • the material of the gate 1212 may include Mo.
  • the first insulating layer 1213 is located between the active layer 1211 and the gate electrode 1212 .
  • the second insulating layer 1214 is located on the side of the active layer 1211 , the gate electrode 1212 and the first insulating layer 1213 away from the base substrate 11 .
  • the third insulating layer 1215 is located on the side of the second insulating layer 1214 away from the base substrate 11.
  • the material of at least one of the first insulating layer 1213 , the second insulating layer 1214 , and the third insulating layer 1215 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the first electrode 1216 and the second electrode 1217 are located on the side of the third insulating layer 1215 away from the base substrate 11 and are electrically connected to the active layer 1211 .
  • the first electrode 1216 is a drain electrode
  • the second electrode 1217 is a source electrode.
  • the first electrode 1216 and the second electrode 1217 are electrically connected to the active layer 1211 through vias penetrating the third insulating layer 1215, the second insulating layer 1214 and the first insulating layer 1213, respectively.
  • the first electrode 1216 and the second electrode 1217 may include a stack of Ti/Al/Ti.
  • At least one resistor R of pressure sensor 16 and gate 1212 are located on the same layer.
  • the at least one resistor R of the pressure sensor 16, the first electrode 1216 and the second electrode 1217 are located on the same layer.
  • the resistor R includes a stack of Ti/Al/Ti. In this way, the pressure sensor 16 is more sensitive to the resistance change after being subjected to external pressure.
  • the pixel circuit in sub-pixel 12 includes 7 transistors and 1 capacitor.
  • the sub-pixel 12 further includes a first switching transistor, a second switching transistor, and a third switching transistor.
  • the first electrode of the first switching transistor is electrically connected to one of the plurality of data lines DL
  • the second electrode of the first switching transistor is electrically connected to the second electrode 1217 (eg, the source) of the driving transistor 121
  • the first switching transistor The gate of the is electrically connected to a first gate line GL among the plurality of gate lines GL.
  • the first electrode of the second switching transistor is electrically connected to one power supply line PL among the plurality of power supply lines PL
  • the second electrode of the second switching transistor is electrically connected to the second electrode 1217 (eg, the source) of the driving transistor 122
  • the second switching transistor The gate of the transistor is electrically connected to one light emitting control line GCL among the plurality of light emitting control lines GCL.
  • the first electrode of the third switching transistor is electrically connected to the first electrode 1216 (eg, the drain) of the driving transistor 121
  • the second electrode of the third switching transistor is electrically connected to the anode 124
  • the gate of the third switching transistor is electrically connected to a plurality of One of the light emission control lines GCL.
  • the sub-pixel 12 further includes a planarization layer 123 , an anode 124 , a pixel defining layer 125 , a functional layer 126 and a cathode 127 .
  • the planarization layer 123 is located on the side of the first electrode 1216 , the second electrode 1217 and the third insulating layer 1215 away from the base substrate 11 .
  • the material of the planarization layer 123 may include organic insulating materials such as PI and resin materials.
  • the anode 124 is located on the side of the planarization layer 123 away from the base substrate 11 , and is electrically connected to one of the first electrode 1216 and the second electrode 1217 .
  • the anode 124 is electrically connected to the first electrode 1216 via vias through the planarization layer 123 .
  • the material of the anode 124 may include indium tin oxide (ITO) or the like.
  • the pixel defining layer 125 is located on the side of the anode 124 and the planarization layer 123 away from the base substrate 11 .
  • the pixel defining layer 125 has a first opening V1.
  • the orthographic projection of the first opening V1 on the base substrate 11 at least partially overlaps the orthographic projection of the anode 124 on the base substrate 11 .
  • the first opening V1 exposes at least a portion of the anode 124 .
  • the material of the pixel defining layer 125 may include organic insulating materials such as PI and resin materials.
  • the functional layer 126 is at least partially located in the first opening V1 and is located on the side of the anode 124 away from the base substrate 11 .
  • the functional layer 126 includes at least a light-emitting layer, such as an organic light-emitting layer.
  • functional layer 126 may also include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.
  • the cathode 127 is at least partially located in the first opening V1 and located on the side of the functional layer 126 away from the base substrate 11 .
  • the cathode 127 may extend from the display area 111 to the peripheral area 112 .
  • the display panel further includes a power bus 18 electrically connected to the cathode 127 .
  • the power bus 18 is located in the peripheral region 112 and is located on the same layer as the first electrode 1216 and the second electrode 1217 .
  • a power supply signal may be applied to the cathode via power bus 18 .
  • the planarization layer 123 has a second opening V2, and the pixel defining layer 125 also has a third opening V3.
  • the orthographic projections of the second opening V2 and the third opening V3 on the base substrate 11 are located in the peripheral region 112 .
  • the second opening V2 and the third opening V3 may be holes or grooves.
  • the second opening V2 and the third opening V3 may be grooves disposed around the display area 111 .
  • the display panel also includes electrical connections 19 .
  • the electrical connection portion 19 is located at least partially in the second opening V2 and is in contact with the power line bus 18 .
  • the cathode 127 is partially located in the third opening V3 and is in contact with the electrical connection 19 .
  • the electrical connection portion 19 is located on the same layer as the anode 124 .
  • the cathode 127 is electrically connected to the power bus 18 via the electrical connection portion 19 located on the same layer as the anode 124 .
  • the display panel further includes an initialization bus 21 located in the peripheral area 112 and electrically connected to the plurality of initialization lines 20 located in the display area 111 .
  • An initialization signal may be provided to a plurality of initialization lines 20 via an initialization bus 21 .
  • the initialization bus 21 is located between the planarization layer 123 and the base substrate 11 , and is located on the same layer as the first electrode 1216 and the second electrode 1217 .
  • the initialization bus 21 is located between the power line 13 and the display area 111 .
  • the display panel further includes a driving circuit 22 .
  • the drive circuit 22 is located between the power supply bus 18 and the initialization bus 21 , and between the planarization layer 123 and the base substrate 11 .
  • the driver circuit 22 may include a gate driver circuit and a lighting control driver circuit.
  • the gate driving circuit includes a plurality of gate driving units electrically connected to the plurality of gate lines GL, eg, a plurality of first shift registers in cascade.
  • the light emission control driving circuit includes a plurality of light emission control driving units electrically connected to the plurality of light emission control lines GCL, eg, a plurality of second shift registers in cascade.
  • first cofferdam 13 and the second cofferdam 14 are described below.
  • the first dam 13 includes a first layer 131 and a second layer 132 on a side of the first layer away from the base substrate 11 .
  • the first layer 131 and the planarization layer 123 are located in the same layer, and the second layer 132 and the pixel defining layer 125 are located in the same layer.
  • the orthographic projection of the first bank 13 on the base substrate 11 partially overlaps the orthographic projection of the power bus 18 on the base substrate 11 .
  • the second dam 14 includes a third layer 141 , a fourth layer 142 located on a side of the third layer 141 away from the base substrate 11 , and a fourth layer 142 located away from the base substrate 11 .
  • the fifth layer 143 on the side.
  • the third layer 141 is located on the same layer as the planarization layer 123
  • the fourth layer 142 is located on the same layer as the pixel defining layer 125
  • the fifth layer 143 is located on the same layer as the support layer 24 (see FIG. 2A ) located in the display area 111 .
  • the support layer 24 is located on the side of the pixel defining layer 125 away from the base substrate 11 .
  • the material of the support layer 24 may include organic insulating materials such as PI and resin materials.
  • the display panel further includes a crack stopper 17 for preventing cracks in the process of cutting the display panel from extending to the display area 111 .
  • the crack arrester 17 is located on the side of the encapsulation layer 15 away from the display area 111
  • the pressure sensor 16 in the display panel is located on the side of the crack arrester 17 close to the display area 111 .
  • the orthographic projection of the first cofferdam 13 on the base substrate 11 is close to the boundary of the second cofferdam 14 and the orthographic projection of the second cofferdam 14 on the base substrate 11 is close to the boundary of the first cofferdam 13 .
  • the distance between the boundaries is the first distance
  • the orthographic projection of the second bank 14 on the base substrate 11 is far away from the boundary between the boundary of the first bank 13 and the boundary of the orthographic projection of the encapsulation layer 15 on the base substrate 11 .
  • the distance is the second distance
  • the distance between the boundary of the orthographic projection of the encapsulation layer 15 on the base substrate 11 and the boundary of the orthographic projection of the crack arrester 17 on the base substrate 11 close to the display area 111 is the third distance.
  • the first distance and the second distance are greater than the third distance.
  • the first distance and the second distance are greater than 50 microns, such as 80 microns, 90 microns, 100 microns, 110 microns, 130 microns, 150 microns, and the like.
  • the third distance is 30 to 70 microns, such as 40 microns, 50 microns, 60 microns, and the like. It should be understood that those skilled in the art can adjust the first distance, the second distance and the third distance according to the size of the frame of the display panel. In addition, it should also be understood that the distance between two boundaries can be understood as the minimum distance from each point on one boundary to each point on the other boundary.
  • the display panel further includes a buffer layer 23 between the base substrate 11 and the first insulating layer 1213.
  • the material of the buffer layer 23 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the first insulating layer 1213 , the second insulating layer 1214 and the third insulating layer 1215 extend from the display area 111 to the peripheral area 112 , and the crack stopper 17 penetrates the third insulating layer 1215 , the second insulating layer 1214 and the first insulating layer 1213 and buffer layer 18.
  • the display panel has one or more trenches penetrating the third insulating layer 1215, the second insulating layer 1214, the first insulating layer 1213 and the buffer layer 18, by filling the one or more trenches with a material, such as an organic material , one or more crack arresters 17 may be formed.
  • crack arrester 17 includes multiple layers of material, which may be on the same layer as one or more of planarization layer 123 , pixel definition layer 125 , and support layer 24 .
  • the crack arrester 17 includes two material layers, and the two material layers are located on the same layer as the planarization layer 123 and the pixel defining layer 125 respectively.
  • the at least one pressure sensor 16 of the display panel includes the first pressure sensor 16 .
  • the first pressure sensor 16 is located between the second cofferdam 14 and the first cofferdam 13
  • the orthographic projection of the first pressure sensor 16 on the base substrate 11 is located at the orthographic projection of the encapsulation layer 15 on the base substrate 11 within the projection.
  • the first pressure sensor 161 is covered by the encapsulation layer 15 ; on the other hand, the second cofferdam 14 can block the adverse effects of water and oxygen on the first pressure sensor 161 . In this way, the reliability of the first pressure sensor 161 can be improved.
  • the at least one pressure sensor 16 of the display panel includes a second pressure sensor 16 .
  • the second pressure sensor 162 is located between the second dam 14 and the crack arrester 17 , and the orthographic projection of the second pressure sensor 162 on the base substrate 11 is located at the orthographic projection of the encapsulation layer 15 on the base substrate 11 within. In this way, the second pressure sensor 162 is covered by the encapsulation layer 15 , which can reduce the adverse effects of water and oxygen on the second pressure sensor 162 .
  • the at least one pressure sensor 16 of the display panel includes a third pressure sensor 163 located between the encapsulation layer 15 and the crack arrester 17 .
  • FIG. 3 is a schematic circuit diagram illustrating a pressure sensor according to one embodiment of the present disclosure.
  • the at least one resistor R of the display panel includes a first resistor R1 , a second resistor R2 , a third resistor R3 and a fourth resistor R4 .
  • the first resistor R1 is electrically connected between the first input terminal IN1 and the first output terminal OUT1
  • the second resistor R2 is electrically connected between the first output terminal OUT1 and the second input terminal IN2
  • the third resistor R3 is electrically connected between the first output terminal OUT1 and the second input terminal IN2.
  • the fourth resistor R4 is electrically connected between the second output terminal OUT2 and the first input terminal IN1.
  • the resistance values of the first resistor R1 , the second resistor R2 , the third resistor R3 and the fourth resistor R4 are the same when the pressure is not applied. It should be understood that the same here is the same within the semiconductor process variation.
  • the working principle of the pressure sensor 16 is described below by taking the example that the first resistor R1 is subjected to the external pressure, and the other three resistors are not subjected to the external pressure.
  • the input voltage Vin is applied between the first input terminal IN1 and the second input terminal IN2. Under the condition that they are not subject to external pressure, the resistance values of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are the same, and the output voltage between the first output terminal OUT1 and the second output terminal OUT2 Vout is 0; when the first resistor R1 is subjected to external pressure, and the other three resistors are not subjected to external pressure, the resistance value of the first resistor R1 changes, and the resistance values of the other three resistors do not change. Therefore, Vout does not change. is 0. Therefore, whether or not the external pressure is applied to the first resistor R1 of the pressure sensor 16 can be identified according to the value of Vout.
  • the embodiment of the present disclosure also provides the following wiring methods.
  • 4A is a schematic cross-sectional view illustrating wiring of a pressure sensor according to one embodiment of the present disclosure.
  • the display panel further includes a first signal output line SG1 electrically connected to the first output end OUT1 and a second signal output line SG2 electrically connected to the second output end OUT2.
  • the electrical connection manner of the first output terminal OUT1 and the first signal output wire SG1 and the electrical connection manner of the second output terminal OUT2 and the second signal output wire SG2 are similar.
  • the signal line shown in FIG. 4A is the first output terminal OUT1
  • the signal line shown in FIG. 4 is the second signal output line SG2.
  • the first signal output line SG1 and the second signal output line SG2 may be located at the same layer as a certain layer in the sub-pixels 12 . The following description will be made with reference to FIG. 2A and FIG. 4A .
  • the sub-pixel 12 further includes a storage capacitor 122 .
  • the storage capacitor 122 includes a first electrode plate 1221 located on the same layer as the gate electrode 1212 , and a second electrode plate 1222 located between the second insulating layer 1214 and the third insulating layer 1215 . It should be understood that the storage capacitor 122 further includes a second insulating layer 1214 located between the first electrode plate 1221 and the second electrode plate 1222 .
  • the first signal output line SG1 and the second signal output line SG2 are located on the same layer as one of the first electrode plate 1221 and the second electrode plate 1222 .
  • the first signal output line SG1 and the second signal output line SG2 are located on the same layer as the first electrode plate 1221 .
  • the first output terminal OUT1 may be electrically connected to the first signal output line SG1 through one or more vias penetrating the third insulating layer 1215 and the second insulating layer 1214
  • the second output terminal OUT2 may be electrically connected to the first signal output line SG1 through the third insulating layer 1215 and the second insulating layer 1214.
  • One or more vias of the three insulating layers 1215 and the second insulating layer 1214 are electrically connected to the second signal output line SG2.
  • the first signal output line SG1 and the second signal output line SG2 are located on the same layer as the second electrode plate 1222 .
  • the first output terminal OUT1 may be electrically connected to the first signal output line SG1 through one or more via holes penetrating the third insulating layer 1215
  • the second output terminal OUT2 may be electrically connected to the first signal output line SG1 through one or more via holes penetrating the third insulating layer 1215 . or a plurality of via holes are electrically connected to the second signal output line SG2.
  • 4B is a schematic cross-sectional view illustrating wiring of a pressure sensor according to another embodiment of the present disclosure.
  • the display panel further includes a first signal input line SI1 electrically connected to the first input/output terminal IN1 and a second signal input line SI2 electrically connected to the second input terminal IN2.
  • the electrical connection manner of the first input terminal IN1 and the first signal input line SI1 and the electrical connection manner of the second input terminal IN2 and the second signal input line SI2 are similar.
  • the signal line shown in FIG. 4B is the first signal input terminal SI1; in the case where the input terminal shown in FIG. 4B is the second input terminal IN2 , the signal line shown in FIG. 4B is the second signal input line SI2.
  • the first signal output line SG1 and the second signal output line SG2 are located on the same layer as one of the first electrode plate 1221 and the second electrode plate 1222
  • the first signal input line SI1 and the second signal input line SI2 are It is located on the same layer as the other of the first electrode plate 1221 and the second electrode plate 1222 .
  • the two signal output lines SG1 and SG2 are located on different layers from the two signal input lines SI1 and SI2.
  • the first signal input line SI1 and the second signal input line SI2 are located on the same layer as the first electrode plate 1221 .
  • the first input terminal IN1 may be electrically connected to the first signal input line SI1 through one or more vias penetrating the third insulating layer 1215 and the second insulating layer 1214
  • the second input terminal IN2 may be electrically connected to the first signal input line SI1 through the third insulating layer 1214.
  • 1215 and one or more vias of the second insulating layer 1214 are electrically connected to the second signal input line IG2.
  • 5A and 5B are schematic layout diagrams illustrating a pressure sensor according to some embodiments of the present disclosure.
  • the first resistor R1 and the third resistor R3 are arranged symmetrically with respect to the first line L1
  • the second resistor R2 and the fourth resistor R4 are arranged symmetrically with respect to the second line L2 .
  • the first line L1 and the second line L2 are perpendicular.
  • the first resistor R1 is located on one side of the first line L1
  • the second resistor R2 , the third resistor R3 and the fourth resistor R4 are located on the other side of the first line L1 . In this way, it is easier to arrange the four resistors such that the first resistor R1 is subjected to external pressure, while the other three resistors are not subject to external pressure.
  • FIGS. 5A and 5B schematically illustrate the positions of the first input terminal IN1 , the second input terminal IN2 , the first output terminal OUT1 and the second output terminal OUT2 .
  • FIG. 6 is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure
  • a base substrate is provided, and the base substrate includes a display area and a peripheral area surrounding the display area;
  • a plurality of sub-pixels, a first dam, a second dam, and at least one pressure sensor are formed.
  • the first dam, the second dam and the pressure sensor may be formed simultaneously.
  • a plurality of sub-pixels are located in the display area, and at least one sub-pixel of the plurality of sub-pixels includes a driving transistor, and the driving transistor includes a multi-layer conductive layer.
  • the first cofferdam and the second cofferdam are located in the peripheral area and surround the display area, and the second cofferdam is located on the side of the first cofferdam away from the display area.
  • At least one pressure sensor is located on at least one of a first side of the second cofferdam close to the first cofferdam and a second side remote from the first cofferdam. At least one resistor in each of the at least one pressure sensor is located on the same layer as one of the multiple conductive layers.
  • an encapsulation layer is formed on a side of the plurality of sub-pixels, the first bank and the second bank away from the base substrate.
  • the orthographic projections of the plurality of sub-pixels, the first bank and the second bank on the base substrate are located within the orthographic projection of the encapsulation layer on the base substrate.
  • At least one pressure sensor is located on at least one of the first side of the second cofferdam close to the first cofferdam and the second side away from the first cofferdam, and at least one resistance R in each pressure sensor On the same layer as one of the multi-layer conductive layers in the drive transistor.
  • the pressure sensor can be formed in the process of forming the sub-pixels, and there is no need to add additional interactive keys, which is beneficial to reduce the thickness of the display panel.
  • the present disclosure also provides a display device, which may include the display panel of any one of the above embodiments.
  • the display device may be, for example, a mobile terminal, a television, a monitor, a notebook computer, a digital photo frame, a navigator, an electronic paper, or any other product or component with a display function.
  • the display device is a mobile terminal.
  • external pressure can be applied to the first resistor R1 in the pressure sensor 16 of the display panel, while external pressure cannot be applied to the other three resistors, so that the pressure sensor 16 The output voltage Vout changes.

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Abstract

本公开提供一种显示面板及其制造方法、显示装置，显示面板包括：衬底基板，包括显示区和围绕显示区的周边区；多个子像素，位于显示区，多个子像素中的至少一个子像素包括驱动晶体管，驱动晶体管包括多层导电层；围绕显示区的第一围堰，位于周边区；围绕显示区的第二围堰，位于周边区，且位于第一围堰远离显示区的一侧；封装层，位于多个子像素、第一围堰和第二围堰远离衬底基板的一侧，多个子像素、第一围堰和第二围堰在衬底基板上的正投影位于封装层在衬底基板上的正投影之内；至少一个压力传感器，位于第二围堰靠近第一围堰的第一侧和远离第一围堰的第二侧中的至少一侧，每个压力传感器中的至少一个电阻与多层导电层中的一层位于同一层。

Description

显示面板及其制造方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制造方法、显示装置。
背景技术
随着显示技术的发展，有机发光二极管(OLED)显示面板的应用越来越普遍。相关技术中，为了实现人机交互，需要额外设置交互按键，例如音量键、开机键等。
发明内容
根据本公开实施例的一方面，提供一种显示面板，包括：衬底基板，包括显示区和围绕所述显示区的周边区；多个子像素，位于所述显示区，所述多个子像素中的至少一个子像素包括驱动晶体管，所述驱动晶体管包括多层导电层；围绕所述显示区的第一围堰，位于所述周边区；围绕所述显示区的第二围堰，位于所述周边区，并且位于所述第一围堰远离所述显示区的一侧；封装层，位于所述多个子像素、所述第一围堰和所述第二围堰远离所述衬底基板的一侧，其中，所述多个子像素、所述第一围堰和所述第二围堰在所述衬底基板上的正投影位于所述封装层在所述衬底基板上的正投影之内；和至少一个压力传感器，位于所述第二围堰靠近所述第一围堰的第一侧和远离所述第一围堰的第二侧中的至少一侧，其中，所述至少一个压力传感器中的每个压力传感器中的至少一个电阻与所述多层导电层中的一层位于同一层。
在一些实施例中，所述驱动晶体管包括：有源层和栅极，位于所述衬底基板的一侧；第一绝缘层，位于所述有源层和所述栅极之间；第二绝缘层，位于所述有源层、所述栅极和所述第一绝缘层远离所述衬底基板的一侧；第三绝缘层，位于所述第二绝缘层远离所述衬底基板的一侧；和第一电极和第二电极，位于所述第三绝缘层远离所述衬底基板一侧，并且电连接至所述有源层，其中，所述多层导电层包括所述栅极、所述第一电极和所述第二电极，所述至少一个电阻、所述第一电极和所述第二电极位于同一层。
在一些实施例中，所述至少一个子像素还包括存储电容，所述存储电容包括：第一电极板，与所述栅极位于同一层；和第二电极板，位于所述第二绝缘层和所述第三绝缘层之间。所述至少一个电阻包括电连接在第一输入端和第一输出端之间的第一电 阻、电连接在所述第一输出端和第二输入端之间的第二电阻、电连接在所述第二输入端和第二输出端之间的第三电阻、以及电连接在所述第二输出端和所述第一输入端之间的第四电阻，所述第一电阻、所述第二电阻、所述第三电阻和所述第四电阻在不受压力的情况下的电阻值相同。所述显示面板还包括与所述第一输出端电连接的第一信号输出线和与所述第二输出端电连接的第二信号输出线，所述第一信号输出线和所述第二信号输出线与所述第一电极板和所述第二电极板中的一个位于同一层。
在一些实施例中，所述第一信号输出线和所述第二信号输出线与所述第二电极板位于同一层。
在一些实施例中，所述显示面板还包括：与所述第一输入端电连接的第一信号输入线；和与所述第二输入端电连接的第二信号输入线，所述第一信号输入线和所述第二信号输入线与所述第一电极板和所述第二电极板中的另一个位于同一层。
在一些实施例中，所述第一电阻和所述第三电阻相对于第一线对称设置，所述第二电阻和所述第四电阻相对于第二线对称设置。
在一些实施例中，所述第一线和所述第二线垂直。
在一些实施例中，所述第一电阻位于所述第一线的一侧，所述第二电阻、所述第三电阻和所述第四电阻位于所述第一线的另一侧。
在一些实施例中，所述显示面板还包括：止裂件，位于所述封装层远离所述显示区的一侧，其中，所述至少一个压力传感器位于所述止裂件靠近所述显示区的一侧。
在一些实施例中，所述至少一个压力传感包括：第一压力传感器，位于所述第二围堰与所述第一围堰之间，其中，所述第一压力传感器在所述衬底基板上的正投影位于所述封装层在所述衬底基板上的正投影之内。
在一些实施例中，所述至少一个压力传感器包括：第二压力传感器，位于所述第二围堰与所述止裂件之间，其中，所述第二压力传感器在所述衬底基板上的正投影位于所述封装层在所述衬底基板上的正投影之内。
在一些实施例中，所述至少一个压力传感器包括：第三压力传感器，位于所述封装层与所述止裂件之间。
在一些实施例中，所述显示面板还包括：缓冲层，位于所述衬底基板与所述第一绝缘层之间，其中：所述第一绝缘层、所述第二绝缘层、所述第三绝缘层和所述缓冲层从所述显示区延伸到所述周边区，并且所述止裂件贯穿所述第三绝缘层、所述第二绝缘层、所述第一绝缘层和所述缓冲层。
在一些实施例中，所述至少一个子像素还包括：平坦化层，位于所述第一电极、所述第二电极和所述第三绝缘层远离所述衬底基板的一侧；阳极，位于所述平坦化层远离所述衬底基板的一侧，并且电连接至所述第一电极和所述第二电极中的一个；像素界定层，位于所述阳极和所述平坦化层远离所述衬底基板的一侧，并且具有第一开口，所述第一开口在所述衬底基板上的正投影与所述阳极在所述衬底基板上的正投影至少部分交叠；功能层，至少部分地位于所述第一开口中，并且位于所述阳极远离所述衬底基板一侧；和阴极，至少部分地位于所述第一开口中，并且位于所述功能层远离所述衬底基板一侧。所述显示面板还包括电源总线，位于所述周边区，电连接至所述阴极，并且与所述第一电极和所述第二电极位于同一层。
在一些实施例中，所述平坦化层具有第二开口，所述像素界定层还具有第三开口，所述第二开口和所述第三开口在所述衬底基板上的正投影位于所述周边区；所述显示面板还包括电连接部，至少部分地位于所述第二开口中，与所述阳极位于同一层，并且与所述电源总线接触；以及所述阴极部分地位于所述第三开口中，并且与所述电连接部接触。
在一些实施例中，所述显示面板还包括：多条初始化线，位于所述显示区，电连接至所述多个子像素，并且被配置为向所述多个子像素提供初始化信号；和初始化总线，位于所述周边区，位于所述平坦化层和所述衬底基板之间，电连接至所述多条初始化线，并且与所述第一电极和所述第二电极位于同一层。
在一些实施例中，所述第一围堰包括：第一层，与所述平坦化层位于同一层；和第二层，位于所述第一层远离所述衬底基板的一侧，并且与所述像素界定层位于同一层。
在一些实施例中，所述第二围堰包括：第三层，与所述平坦化层位于同一层；第四层，位于所述第三层远离所述衬底基板的一侧，并且与所述像素界定层位于同一层；和第五层，位于所述第四层远离所述衬底基板的一侧，并且与支撑层位于同一层，其中，所述支撑层位于所述显示区，并且位于所述像素界定层远离所述衬底基板的一侧。
根据本公开实施例的另一方面，提供一种显示装置，包括：上述任意一个实施例所述的显示面板。
根据本公开实施例的又一方面，提供一种显示面板的制造方法，包括：提供衬底基板，所述衬底基板包括显示区和围绕所述显示区的周边区；形成多个子像素、第一围堰、第二围堰和至少一个压力传感器，其中:所述多个子像素位于所述显示区，多个 子像素中的至少一个子像素包括驱动晶体管，所述驱动晶体管包括多层导电层，所述第一围堰和所述第二围堰位于所述周边区、且围绕所述显示区，所述第二围堰位于所述第一围堰远离所述显示区的一侧，以及所述至少一个压力传感器位于所述第二围堰靠近所述第一围堰的第一侧和远离所述第一围堰的第二侧中的至少一侧，其中，所述至少一个压力传感器中的每个压力传感器中的至少一个电阻与所述多层导电层中的一层位于同一层；以及形成位于所述多个子像素、所述第一围堰和所述第二围堰远离所述衬底基板的一侧的封装层，其中，所述多个子像素、所述第一围堰和所述第二围堰在所述衬底基板上的正投影位于所述封装层在所述衬底基板上的正投影之内。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是示出根据本公开一个实施例的显示面板的结构示意图；
图2A是示出根据本公开一个实施例的显示面板中的子像素的截面示意图；
图2B是示出根据本公开一个实施例的显示面板的截面示意图；
图3是示出根据本公开一个实施例的压力传感器的电路示意图；
图4A是示出根据本公开一个实施例的压力传感器的布线的截面示意图；
图4B是示出根据本公开另一个实施例的压力传感器的布线的截面示意图；
图5A和图5B是示出根据本公开一些实施例的压力传感器的布局示意图；
图6是示出根据本公开一个实施例的显示面板的制造方法的流程示意图。
应当明白，附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值 应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件电连接其它部件时，该特定部件可以与所述其它部件直接电连接而不具有居间部件，也可以不与所述其它部件直接电连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
图1是示出根据本公开一个实施例的显示面板的结构示意图。
如图1所示，显示面板包括衬底基板11和多个子像素12。
衬底基板11包括显示区111和围绕显示区的周边区112。在一些实施例中，衬底基板11包括第一衬底基板层、第二衬底基板层、第一阻挡层和第二阻挡层。第一阻挡层位于第一衬底基板层和第二衬底基板层之间，第二衬底基板层位于第一阻挡层和第二阻挡层之间。例如，第一衬底基板层和第二衬底基板层中的至少一个的材料可以包括聚酰亚胺(PI)等柔性材料。例如，第一阻挡层和第二阻挡层的至少一个的材料可以包括硅的氧化物、硅的氮化物、硅的氮氧化物等无机绝缘材料。
多个子像素12位于显示区111。例如，多个子像素12可以包括红色子像素、绿色子像素或蓝色子像素等。每个子像素12包括像素电路。例如，像素电路可以包括6个晶体管和1个电容器(6T1C)；又例如，像素电路可以包括7个晶体管和1个电容器(7T1C)。
在一些实施例中，参见图1，显示面板还包括多条数据线DL。多条数据线DL位于显示区111，并且电连接至位于显示区111的多个子像素12。多条数据线DL被配 置为向多个子像素12提供数据信号。例如，每条数据线13电连接至一列子像素12。
在一些实施例中，参见图1，显示面板还包括多条栅极线GL。多条栅极线GL位于显示区111，并且电连接至多个子像素12。多条栅极线GL被配置为向多个子像素12提供栅极信号。例如，每条栅极线GL电连接至一行子像素12。
在一些实施例中，参见图1，显示面板还包括多条发光控制线GCL。多条发光控制线GCL位于显示区111，并且电连接至多个子像素12。多条发光控制线GCL被配置为向多个子像素12提供发光控制信号。例如，每条发光控制线15电连接至一行子像素12。
在一些实施例中，参见图1，显示面板还包括多条电源线PL。多条电源线PL位于显示区111，并且电连接至多个子像素12。多条电源线16被配置为向多个子像素12提供电源信号。
在一些实施例中，参见图1，显示面板还包括多条初始化线IL。多条初始化线IL位于显示区111，并且电连接至多个子像素12。多条初始化线IL被配置为向多个子像素12提供初始化信号。
图2A是示出根据本公开一个实施例的显示面板中的子像素的截面示意图。图2B是示出根据本公开一个实施例的显示面板的截面示意图。下面结合图2A和图2B对根据本公开一些实施例的显示面板的结构进行介绍。
如图2A所示，子像素12包括驱动晶体管121。这里，驱动晶体管121包括多层导电层。作为一些实现方式，驱动晶体管121可以是顶栅极晶体管；作为另一些实现方式，驱动晶体管121可以是底栅极晶体管。图2A示出的是驱动晶体管121为顶栅极晶体管的情况。
如图2B所示，显示面板除了包括衬底基板11、多个子像素12外，还包括第一围堰13、第二围堰14、封装层15和至少一个压力传感器16。例如，压力传感器16可以作为音量键或开启键。
第一围堰13和第二围堰14均围绕显示区111，并且均位于周边区112。第二围堰14位于第一围堰13远离显示区111的一侧。这里，第一围堰13和第二围堰14可以阻挡水和氧气进入子像素12。
封装层15位于多个子像素12、第一围堰13和第二围堰14远离衬底基板11的一侧。这里，多个子像素12、第一围堰13和第二围堰14在衬底基板11上的正投影位于封装层15在衬底基板11上的正投影之内。例如，封装层15可以包括薄膜封装层。 在一些实施例中，封装层15可以包括第一无机层151、第二无机层152、以及位于第一无机层151和第二无机层152之间的有机层153。在一些实施例中，显示面板还可以包括位于第二围堰14与显示区111之间的第三围堰22。第三围堰22用于阻挡有机层153的流动。
至少一个压力传感器16位于第二围堰14靠近第一围堰13的第一侧和远离第一围堰13的第二侧中的至少一侧。例如，该至少一个压力传感器16均位于第二围堰14靠近第一围堰13的第一侧；又例如，该至少一个压力传感器16均位于第二围堰14远离第一围堰13的第二侧；再例如，该至少一个压力传感器16中的一个或多个压力传感器16位于第二围堰14靠近第一围堰13的第一侧，该至少一个压力传感器16中的一个或多个压力传感器16位于第二围堰14远离第一围堰13的第二侧。
每个压力传感器16中的至少一个电阻R与驱动晶体管121中的多层导电层中的一层位于同一层。例如，压力传感器16的至少一个电阻R包括四个电阻。
需要说明的是，在本公开实施例中，多个部件位于同一层是指多个部件是通过对同一材料层进行构图工艺而形成的。故，这多个部件的材料相同，厚度也基本相同。
上述实施例中，至少一个压力传感器16位于第二围堰14靠近第一围堰13的第一侧和远离第一围堰13的第二侧中的至少一侧，并且每个压力传感器16中的至少一个电阻R与驱动晶体管121中的多层导电层中的一层位于同一层。这样的结构下，压力传感器16可以在形成子像素12的过程中形成，无需额外增加交互按键，有利于减小显示面板的厚度。
另外，压力传感器16可以充分利用周边区112的空间，无需额外增大周边区112的尺寸，故，本公开的一些实施例可以在实现窄边框的情况下，减小显示面板的厚度。
下面结合图2A介绍驱动晶体管121的一些具体实现方式。
参见图2A，驱动晶体管121包括有源层1211、栅极1212、第一绝缘层1213，第二绝缘层1214、第三绝缘层1215、第一电极1216和第二电极1217。驱动晶体管121中的多层导电层包括栅极1212、第一电极1216和第二电极1217。
有源层1211和栅极1212位于衬底基板11的一侧。例如，栅极1212位于有源层1211远离衬底基板11的一侧。例如，有源层1211的材料可以包括多晶硅。例如，栅极1212的材料可以包括Mo。
第一绝缘层1213位于有源层1211和栅极1212之间。第二绝缘层1214位于有源层1211、栅极1212和第一绝缘层1213远离衬底基板11的一侧。第三绝缘层1215位 于第二绝缘层1214远离衬底基板11的一侧。例如，第一绝缘层1213、第二绝缘层1214和第三绝缘层1215中的至少一个的材料可以包括硅的氧化物、硅的氮化物、硅的氮氧化物等无机绝缘材料。
第一电极1216和第二电极1217位于第三绝缘层1215远离衬底基板11一侧，并且电连接至有源层1211。在一些实施例中，第一电极1216为漏极，第二电极1217为源极。例如，第一电极1216和第二电极1217分别通过贯穿第三绝缘层1215、第二绝缘层1214和第一绝缘层1213的过孔电连接至有源层1211。例如，第一电极1216和第二电极1217可以包括Ti/Al/Ti的叠层。
作为一些实现方式，压力传感器16的至少一个电阻R和栅极1212位于同一层。
作为另一些实现方式，压力传感器16的至少一个电阻R、第一电极1216和第二电极1217位于同一层。例如，电阻R包括Ti/Al/Ti的叠层。这样的方式下，压力传感器16受外界压力后的电阻变化更为敏感。
在一些实施例中，子像素12中的像素电路包括7个晶体管和1个电容器。例如，除了驱动晶体管121外，子像素12还包括第一开关晶体管、第二开关晶体管和第三开关晶体管。第一开关晶体管的第一电极电连接至多条数据线DL中的一条数据线，第一开关晶体管的第二电极电连接至驱动晶体管121的第二电极1217(例如源极)，第一开关晶体管的栅极电连接至多条栅极线GL中的一条第一栅极线GL。第二开关晶体管的第一电极电连接至多条电源线PL中的一条电源线PL，第二开关晶体管的第二电极电连接至驱动晶体管122的第二电极1217(例如源极)，第二开关晶体管的栅极电连接至多条发光控制线GCL中的一条发光控制线GCL。第三开关晶体管的第一电极电连接至驱动晶体管121的第一电极1216(例如漏极)，第三开关晶体管的第二电极电连接至阳极124，第三开关晶体管的栅极电连接至多条发光控制线GCL中的一条发光控制线GCL。
在一些实施例中，参见图2A，子像素12还包括平坦化层123、阳极124、像素界定层125、功能层126和阴极127。
平坦化层123位于第一电极1216、第二电极1217和第三绝缘层1215远离衬底基板11的一侧。例如，平坦化层123的材料可以包括PI、树脂材料等有机绝缘材料。
阳极124位于平坦化层123远离衬底基板11的一侧，并且电连接至第一电极1216和第二电极1217中的一个。例如，阳极124经由贯穿平坦化层123过孔电连接至第一电极1216。例如，阳极124的材料可以包括氧化铟锡(ITO)等。
像素界定层125位于阳极124和平坦化层123远离衬底基板11的一侧。像素界定层125具有第一开口V1。这里，第一开口V1在衬底基板11上的正投影与阳极124在衬底基板11上的正投影至少部分交叠。换言之，第一开口V1使得阳极124的至少一部分露出。例如，像素界定层125的材料可以包括PI、树脂材料等有机绝缘材料。
功能层126至少部分地位于第一开口V1中，并且位于阳极124远离衬底基板11一侧。这里，功能层126至少包括发光层，例如有机发光层。在某些实施例中，功能层126还可以包括电子传输层、电子注入层、空穴传输层和空穴注入层中的一层或多层。
阴极127至少部分地位于第一开口V1中，并且位于功能层126远离衬底基板11一侧。例如，阴极127可以从显示区111延伸到周边区112。
在一些实施例中，参见图2B，显示面板还包括电连接至阴极127的电源总线18。这里，电源总线18位于周边区112，并且与第一电极1216和第二电极1217位于同一层。例如，可以经由电源总线18向阴极施加电源信号。
下面介绍根据本公开一些实现方式的阴极127与电源总线18的电连接方式。
参见图2B，平坦化层123具有第二开口V2，像素界定层125还具有第三开口V3。这里，第二开口V2和第三开口V3在衬底基板11上的正投影位于周边区112。例如，第二开口V2和第三开口V3可以是孔或槽。在一些实施例中，第二开口V2和第三开口V3可以是围绕显示区111设置的槽。
显示面板还包括电连接部19。电连接部19至少部分地位于第二开口V2中，并且与电源线总线18接触。阴极127部分地位于第三开口V3中，并且与电连接部19接触。另外，电连接部19与阳极124位于同一层。
这样的方式下，阴极127经由与阳极124位于同一层的电连接部19与电源总线18电连接。
在一些实施例中，显示面板还包括位于周边区112，并且电连接至位于显示区111的多条初始化线20的初始化总线21。经由初始化总线21可以向多条初始化线20提供初始化信号。初始化总线21位于平坦化层123和衬底基板11之间，并且与第一电极1216和第二电极1217位于同一层。例如，初始化总线21位于电源线13和显示区111之间。
在一些实施例中，显示面板还包括驱动电路22。驱动电路22位于电源总线18与初始化总线21之间，并且位于平坦化层123和衬底基板11之间。在一些实施例中， 驱动电路22可以包括栅极驱动电路和发光控制驱动电路。栅极驱动电路包括电连接至多条栅极线GL的多个栅极驱动单元，例如，级联的多个第一移位寄存器。发光控制驱动电路包括电连接至多条发光控制线GCL的多个发光控制驱动单元，例如，级联的多个第二移位寄存器。
下面介绍第一围堰13和第二围堰14的一些具体实现方式。
在一些实现方式中，参见图2B，第一围堰13包括第一层131和位于第一层远离衬底基板11的一侧的第二层132。第一层131与平坦化层123位于同一层，第二层132与像素界定层125位于同一层。例如，第一围堰13在衬底基板11上的正投影与电源总线18在衬底基板11上的正投影部分交叠。
在一些实现方式中，参见图2B，第二围堰14包括第三层141、位于第三层141远离衬底基板11的一侧的第四层142和位于第四层142远离衬底基板11的一侧的第五层143。第三层141与平坦化层123位于同一层，第四层142与像素界定层125位于同一层，第五层143与位于显示区111的支撑层24(参见图2A)位于同一层。这里，支撑层24位于像素界定层125远离衬底基板11的一侧。例如，支撑层24的材料可以包括PI、树脂材料等有机绝缘材料。
在一些实施例中，参见图2B，显示面板还包括止裂件17，用于阻挡切割显示面板过程中的裂纹向显示区111扩展。这里，止裂件17位于封装层15远离显示区111的一侧，显示面板中的压力传感器16位于止裂件17靠近显示区111的一侧。
在一些实施例中，第一围堰13在衬底基板11上的正投影靠近第二围堰14的边界与第二围堰14在衬底基板11上的正投影靠近第一围堰13的边界之间的距离为第一距离，第二围堰14在衬底基板11上的正投影远离第一围堰13的边界与封装层15在衬底基板11上的正投影的边界之间的距离为第二距离，封装层15在衬底基板11上的正投影的边界与止裂件17在衬底基板11上的正投影靠近显示区111的边界之间的距离为第三距离。这里，第一距离和第二距离大于第三距离。例如，第一距离和第二距离大于50微米，例如可以是80微米、90微米、100微米、110微米、130微米，150微米等。例如，第三距离为30至70微米，例如40微米、50微米、60微米等。应理解，本领域技术人员可以根据显示面板的边框的尺寸对第一距离、第二距离和第三距离进行调整。另外，还应理解，两个边界之间的距离可以理解为一个边界上的各点到另一边界上各点的最小距离。
在一些实施例中，参见图2A和图2B，显示面板还包括位于衬底基板11与第一 绝缘层1213之间的缓冲层23。例如，缓冲层23的材料可以包括硅的氧化物、硅的氮化物、硅的氮氧化物等无机绝缘材料。这里，第一绝缘层1213、第二绝缘层1214和第三绝缘层1215从显示区111延伸到周边区112，止裂件17贯穿第三绝缘层1215、第二绝缘层1214、第一绝缘层1213和缓冲层18。
例如，显示面板具有贯穿第三绝缘层1215、第二绝缘层1214、第一绝缘层1213和缓冲层18的一个或多个沟槽，通过在一个或多个沟槽中填充材料，例如有机材料，可以形成一个或多个止裂件17。在一些实施例中，止裂件17包括多个材料层，多个材料层可以与平坦化层123、像素界定层125和支撑层24中的一层或多层位于同一层。例如，止裂件17包括2个材料层，2个材料层分别与平坦化层123和像素界定层125位于同一层。
下面介绍显示面板中的压力传感器16的设置位置的一些实现方式。
在一些实施例中，参见图2B，显示面板的至少一个压力传感16包括第一压力传感器16。这里，第一压力传感器16位于第二围堰14与第一围堰13之间，并且，第一压力传感器16在衬底基板11上的正投影位于封装层15在衬底基板11上的正投影之内。这样的方式下，一方面，第一压力传感器161被封装层15覆盖；另一方面，第二围堰14可以阻挡水和氧气对第一压力传感器161的不利影响。如此，可以提高第一压力传感器161的可靠性。
在另一些实施例中，参见图2B，显示面板的至少一个压力传感16包括第二压力传感器16。这里，第二压力传感器162位于第二围堰14与止裂件17之间，并且，第二压力传感器162在衬底基板11上的正投影位于封装层15在衬底基板11上的正投影之内。这样的方式下，第二压力传感器162被封装层15覆盖，可以减小水和氧气对第二压力传感器162的不利影响。
在又一些实施例中，参见图2B，显示面板的至少一个压力传感16包括位于封装层15与止裂件17之间的第三压力传感器163。
图3是示出根据本公开一个实施例的压力传感器的电路示意图。
如图3所示，显示面板的至少一个电阻R包括第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4。
第一电阻R1电连接在第一输入端IN1和第一输出端OUT1之间，第二电阻R2电连接在第一输出端OUT1和第二输入端IN2之间、第三电阻R3电连接在第二输入端IN2和第二输出端OUT2之间，第四电阻R4电连接在第二输出端OUT2和第一输 入端IN1之间。这里，第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4在不受压力的情况下的电阻值相同。应理解，这里的相同是在半导体工艺偏差范围内的相同。
下面以第一电阻R1受外界压力，而其他三个电阻不受外界压力为例说明压力传感器16的工作原理。
第一输入端IN1和第二输入端IN2之间施加有输入电压Vin。在均不受外界压力的情况下，第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4的电阻值相同，第一输出端OUT1和第二输出端OUT2之间的输出电压Vout为0；在第一电阻R1受外界压力，而其他三个电阻不受外界压力的情况下，第一电阻R1的电阻值变化，其他三个电阻的电阻值不发生变化，故，Vout不为0。因此，根据Vout的值可以识别是否有外界压力施加到压力传感器16的第一电阻R1。
针对压力传感器16的信号输入和信号输出，本公开实施例还提供了如下布线方式。
图4A是示出根据本公开一个实施例的压力传感器的布线的截面示意图。
如图4A所示，显示面板还包括与第一输出端OUT1电连接的第一信号输出线SG1和与第二输出端OUT2电连接的第二信号输出线SG2。需要说明的是，第一输出端OUT1和第一信号输出线SG1的电连接方式以及第二输出端OUT2和第二信号输出线SG2的电连接方式类似。在图4A示出的输出端是第一输出端OUT1的情况下，图4示出的信号线为第一信号输出线SG1；在图4示出的输出端是第二输出端OUT2的情况下，图4示出的信号线为第二信号输出线SG2。
第一信号输出线SG1和第二信号输出线SG2可以与子像素12中的某一层位于同一层。下面结合图2A和图4A进行说明。
参见图2A，子像素12还包括存储电容122。存储电容122包括与栅极1212位于同一层的第一电极板1221、以及位于第二绝缘层1214和第三绝缘层1215之间的第二电极板1222。应理解，存储电容122还包括位于第一电极板1221和第二电极板1222之间的第二绝缘层1214。
在一些实施例中，第一信号输出线SG1和第二信号输出线SG2与第一电极板1221和第二电极板1222中的一个位于同一层。
例如，第一信号输出线SG1和第二信号输出线SG2与第一电极板1221位于同一层。这种情况下，第一输出端OUT1可以通过贯穿第三绝缘层1215和第二绝缘层1214 的一个或多个过孔与第一信号输出线SG1电连接，第二输出端OUT2可以通过贯穿第三绝缘层1215和第二绝缘层1214的一个或多个过孔与第二信号输出线SG2电连接。
又例如，参见图4A，第一信号输出线SG1和第二信号输出线SG2与第二电极板1222位于同一层。这种情况下，第一输出端OUT1可以通过贯穿第三绝缘层1215的一个或多个过孔与第一信号输出线SG1电连接，第二输出端OUT2可以通过贯穿第三绝缘层1215的一个或多个过孔与第二信号输出线SG2电连接。
图4B是示出根据本公开另一个实施例的压力传感器的布线的截面示意图。
如图4B所示，显示面板还包括与第入输出端IN1电连接的第一信号输入线SI1和与第二输入端IN2电连接的第二信号输入线SI2。需要说明的是，第一输入端IN1和第一信号输入线SI1的电连接方式以及第二输入端IN2和第二信号输入线SI2的电连接方式类似。在图4B示出的输入端是第一输入端IN1的情况下，图4B示出的信号线为第一信号输入线SI1；在图4B示出的输入端是第二输入端IN2的情况下，图4B示出的信号线为第二信号输入线SI2。
在第一信号输出线SG1和第二信号输出线SG2与第一电极板1221和第二电极板1222中的一个位于同一层的情况下，第一信号输入线SI1和第二信号输入线SI2与与第一电极板1221和第二电极板1222中的另一个位于同一层。换言之，两个信号输出线SG1和SG2与两个信号输入线SI1和SI2位于不同层。
例如，参见图4B，第一信号输入线SI1和第二信号输入线SI2与第一电极板1221位于同一层。例如，第一输入端IN1可以通过贯穿第三绝缘层1215和第二绝缘层1214的一个或多个过孔与第一信号输入线SI1电连接，第二输入端IN2可以通过贯穿第三绝缘层1215和第二绝缘层1214的一个或多个过孔与第二信号输入线IG2电连接。
这样的方式下，可以减小两个信号输出线SG1和SG2与两个信号输入线SI1和SI2之间的信号干扰。
图5A和图5B是示出根据本公开一些实施例的压力传感器的布局示意图。
在图5A和图5B中，第一电阻R1和第三电阻R3相对于第一线L1对称设置，第二电阻R2和第四电阻R4相对于第二线L2对称设置。例如，第一线L1和第二线L2垂直。
在一些实施例中，参见图5B，第一电阻R1位于第一线L1的一侧，第二电阻R2、第三电阻R3和第四电阻R4位于第一线L1的另一侧。这样的方式下，更容易将四个电阻布置为使得第一电阻R1受外界压力，而其他三个电阻不受外界压力。
另外，图5A和图5B示意性地示出了第一输入端IN1、第二输入端IN2、第一输出端OUT1和第二输出端OUT2的位置。
图6是示出根据本公开一个实施例的显示面板的制造方法的流程示意图；
在步骤602，提供衬底基板，衬底基板包括显示区和围绕显示区的周边区；
在步骤604，形成多个子像素、第一围堰、第二围堰和至少一个压力传感器。例如，在形成子像素的过程中，可以同时形成第一围堰、第二围堰和压力传感器。
多个子像素位于显示区，多个子像素中的至少一个子像素包括驱动晶体管，驱动晶体管包括多层导电层。
第一围堰和第二围堰位于周边区、且围绕显示区，第二围堰位于第一围堰远离显示区的一侧。
至少一个压力传感器位于第二围堰靠近第一围堰的第一侧和远离第一围堰的第二侧中的至少一侧。至少一个压力传感器中的每个压力传感器中的至少一个电阻与多层导电层中的一层位于同一层。
在步骤606，形成位于多个子像素、第一围堰和第二围堰远离衬底基板的一侧的封装层。
这里，多个子像素、第一围堰和第二围堰在衬底基板上的正投影位于封装层在衬底基板上的正投影之内。
上述实施例中，至少一个压力传感器位于第二围堰靠近第一围堰的第一侧和远离第一围堰的第二侧中的至少一侧，并且每个压力传感器中的至少一个电阻R与驱动晶体管中的多层导电层中的一层位于同一层。这样的结构下，压力传感器可以在形成子像素的过程中形成，无需额外增加交互按键，有利于减小显示面板的厚度。
本公开还提供了一种显示装置，显示装置可以包括上述任意一个实施例的显示面板。在一些实施例中，显示装置例如可以是移动终端、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
例如，显示装置是移动终端。在一些实施例中，通过设计移动终端侧面的边框，可以使得显示面板的压力传感器16中的第一电阻R1能够被施加外界压力，而其他三个电阻不能被施加外界压力，如此使得压力传感器16的输出电压Vout发生变化。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (20)

  1. 一种显示面板，包括：
    衬底基板，包括显示区和围绕所述显示区的周边区；
    多个子像素，位于所述显示区，所述多个子像素中的至少一个子像素包括驱动晶体管，所述驱动晶体管包括多层导电层；
    围绕所述显示区的第一围堰，位于所述周边区；
    围绕所述显示区的第二围堰，位于所述周边区，并且位于所述第一围堰远离所述显示区的一侧；
    封装层，位于所述多个子像素、所述第一围堰和所述第二围堰远离所述衬底基板的一侧，其中，所述多个子像素、所述第一围堰和所述第二围堰在所述衬底基板上的正投影位于所述封装层在所述衬底基板上的正投影之内；和
    至少一个压力传感器，位于所述第二围堰靠近所述第一围堰的第一侧和远离所述第一围堰的第二侧中的至少一侧，其中，所述至少一个压力传感器中的每个压力传感器中的至少一个电阻与所述多层导电层中的一层位于同一层。
  2. 根据权利要求1所述的显示面板，其中，所述驱动晶体管包括：
    有源层和栅极，位于所述衬底基板的一侧；
    第一绝缘层，位于所述有源层和所述栅极之间；
    第二绝缘层，位于所述有源层、所述栅极和所述第一绝缘层远离所述衬底基板的一侧；
    第三绝缘层，位于所述第二绝缘层远离所述衬底基板的一侧；和
    第一电极和第二电极，位于所述第三绝缘层远离所述衬底基板一侧，并且电连接至所述有源层，
    其中，所述多层导电层包括所述栅极、所述第一电极和所述第二电极，所述至少一个电阻、所述第一电极和所述第二电极位于同一层。
  3. 根据权利要求2所述的显示面板，其中：
    所述至少一个子像素还包括存储电容，所述存储电容包括：
    第一电极板，与所述栅极位于同一层，和
    第二电极板，位于所述第二绝缘层和所述第三绝缘层之间；
    所述至少一个电阻包括电连接在第一输入端和第一输出端之间的第一电阻、电连接在所述第一输出端和第二输入端之间的第二电阻、电连接在所述第二输入端和第二输出端之间的第三电阻、以及电连接在所述第二输出端和所述第一输入端之间的第四电阻，所述第一电阻、所述第二电阻、所述第三电阻和所述第四电阻在不受压力的情况下的电阻值相同；以及
    所述显示面板还包括与所述第一输出端电连接的第一信号输出线和与所述第二输出端电连接的第二信号输出线，所述第一信号输出线和所述第二信号输出线与所述第一电极板和所述第二电极板中的一个位于同一层。
  4. 根据权利要求3所述的显示面板，其中，所述第一信号输出线和所述第二信号输出线与所述第二电极板位于同一层。
  5. 根据权利要求3所述的显示面板，还包括：
    与所述第一输入端电连接的第一信号输入线；和
    与所述第二输入端电连接的第二信号输入线，所述第一信号输入线和所述第二信号输入线与所述第一电极板和所述第二电极板中的另一个位于同一层。
  6. 根据权利要求5所述的显示面板，其中，所述第一电阻和所述第三电阻相对于第一线对称设置，所述第二电阻和所述第四电阻相对于第二线对称设置。
  7. 根据权利要求6所述的显示面板，其中，所述第一线和所述第二线垂直。
  8. 根据权利要求7所述的显示面板，其中，所述第一电阻位于所述第一线的一侧，所述第二电阻、所述第三电阻和所述第四电阻位于所述第一线的另一侧。
  9. 根据权利要求1-8任意一项所述的显示面板，还包括：
    止裂件，位于所述封装层远离所述显示区的一侧，其中，所述至少一个压力传感器位于所述止裂件靠近所述显示区的一侧。
  10. 根据权利要求9所述的显示面板，其中，所述至少一个压力传感包括：
    第一压力传感器，位于所述第二围堰与所述第一围堰之间，其中，所述第一压力传感器在所述衬底基板上的正投影位于所述封装层在所述衬底基板上的正投影之内。
  11. 根据权利要求9所述的显示面板，其中，所述至少一个压力传感器包括：
    第二压力传感器，位于所述第二围堰与所述止裂件之间，其中，所述第二压力传感器在所述衬底基板上的正投影位于所述封装层在所述衬底基板上的正投影之内。
  12. 根据权利要求9所述的显示面板，其中，所述至少一个压力传感器包括：
    第三压力传感器，位于所述封装层与所述止裂件之间。
  13. 根据权利要求9-12任意一项所述的显示面板，还包括：缓冲层，位于所述衬底基板与所述第一绝缘层之间，其中：
    所述第一绝缘层、所述第二绝缘层、所述第三绝缘层和所述缓冲层从所述显示区延伸到所述周边区，并且
    所述止裂件贯穿所述第三绝缘层、所述第二绝缘层、所述第一绝缘层和所述缓冲层。
  14. 根据权利要求2所述的显示面板，其中：
    所述至少一个子像素还包括：
    平坦化层，位于所述第一电极、所述第二电极和所述第三绝缘层远离所述衬底基板的一侧，
    阳极，位于所述平坦化层远离所述衬底基板的一侧，并且电连接至所述第一电极和所述第二电极中的一个，
    像素界定层，位于所述阳极和所述平坦化层远离所述衬底基板的一侧，并且具有第一开口，所述第一开口在所述衬底基板上的正投影与所述阳极在所述衬底基板上的正投影至少部分交叠，
    功能层，至少部分地位于所述第一开口中，并且位于所述阳极远离所述衬底基板一侧，和
    阴极，至少部分地位于所述第一开口中，并且位于所述功能层远离所述衬 底基板一侧；以及
    所述显示面板还包括电源总线，位于所述周边区，电连接至所述阴极，并且与所述第一电极和所述第二电极位于同一层。
  15. 根据权利要求14所述的显示面板，其中：
    所述平坦化层具有第二开口，所述像素界定层还具有第三开口，所述第二开口和所述第三开口在所述衬底基板上的正投影位于所述周边区；
    所述显示面板还包括电连接部，至少部分地位于所述第二开口中，与所述阳极位于同一层，并且与所述电源总线接触；以及
    所述阴极部分地位于所述第三开口中，并且与所述电连接部接触。
  16. 根据权利要求14所述的显示面板，还包括：
    多条初始化线，位于所述显示区，电连接至所述多个子像素，并且被配置为向所述多个子像素提供初始化信号；和
    初始化总线，位于所述周边区，位于所述平坦化层和所述衬底基板之间，电连接至所述多条初始化线，并且与所述第一电极和所述第二电极位于同一层。
  17. 根据权利要求14-16任意一项所述的显示面板，其中，所述第一围堰包括：
    第一层，与所述平坦化层位于同一层；和
    第二层，位于所述第一层远离所述衬底基板的一侧，并且与所述像素界定层位于同一层。
  18. 根据权利要求14-17任意一项所述的显示面板，其中，所述第二围堰包括：
    第三层，与所述平坦化层位于同一层；
    第四层，位于所述第三层远离所述衬底基板的一侧，并且与所述像素界定层位于同一层；和
    第五层，位于所述第四层远离所述衬底基板的一侧，并且与支撑层位于同一层，其中，所述支撑层位于所述显示区，并且位于所述像素界定层远离所述衬底基板的一侧。
  19. 一种显示装置，包括：如权利要求1-18任意一项所述的显示面板。
  20. 一种显示面板的制造方法，包括：
    提供衬底基板，所述衬底基板包括显示区和围绕所述显示区的周边区；
    形成多个子像素、第一围堰、第二围堰和至少一个压力传感器，其中:
    所述多个子像素位于所述显示区，多个子像素中的至少一个子像素包括驱动晶体管，所述驱动晶体管包括多层导电层，
    所述第一围堰和所述第二围堰位于所述周边区、且围绕所述显示区，所述第二围堰位于所述第一围堰远离所述显示区的一侧，以及
    所述至少一个压力传感器位于所述第二围堰靠近所述第一围堰的第一侧和远离所述第一围堰的第二侧中的至少一侧，其中，所述至少一个压力传感器中的每个压力传感器中的至少一个电阻与所述多层导电层中的一层位于同一层；
    以及
    形成位于所述多个子像素、所述第一围堰和所述第二围堰远离所述衬底基板的一侧的封装层，其中，所述多个子像素、所述第一围堰和所述第二围堰在所述衬底基板上的正投影位于所述封装层在所述衬底基板上的正投影之内。
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