WO2022116347A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2022116347A1
WO2022116347A1 PCT/CN2020/141417 CN2020141417W WO2022116347A1 WO 2022116347 A1 WO2022116347 A1 WO 2022116347A1 CN 2020141417 W CN2020141417 W CN 2020141417W WO 2022116347 A1 WO2022116347 A1 WO 2022116347A1
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WIPO (PCT)
Prior art keywords
thin film
node
film transistor
electrically connected
pixel circuit
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Application number
PCT/CN2020/141417
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English (en)
French (fr)
Inventor
韩志斌
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2022116347A1 publication Critical patent/WO2022116347A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • Embodiments of the present invention relate to the field of display technology, and in particular, to a pixel circuit, a driving method thereof, and a display panel.
  • the light-emitting mode can be divided into two schemes: top emission and bottom emission.
  • the AMOLED display panel using the top emission scheme needs to let the light emitted by the organic light-emitting diode (Organic Light-Emitting Diode, OLED) pass through the cathode, so the thickness of the cathode needs to be thin to ensure the light transmittance, but Doing so will make the sheet resistance of the cathode larger, and the larger sheet resistance will cause the voltage drops of the cathodes in different pixel circuits to be unequal.
  • OLED Organic Light-Emitting Diode
  • the voltage drop of the cathode will be conducted to the source of the driving transistor through the OLED after the OLED is turned on, and coupled to the gate of the driving transistor under the action of the storage capacitor, because the brightness of the OLED is mainly affected by the driving transistor. Due to the influence of the voltage Vgs between the gate and the source, when the next frame of signal is written, if the gate and source of the drive transistor cannot be reset normally (among them, the reset ability of the source is weaker, and it is difficult to reset within the specified time). reset), it will affect the brightness of the OLED in the pixel circuit. In addition, since the voltage drops of the cathodes of different pixel circuits are not equal, the brightness of the OLEDs in different pixel circuits is different, which ultimately affects the display uniformity of the AMOLED display panel.
  • the charging time of the pixel is further shortened, and the reset time of the driving transistor is also shortened.
  • the source of the driving transistor cannot be reset within the specified time.
  • the impact on the display uniformity of the AMOLED display panel is accentuated.
  • Embodiments of the present invention provide a pixel circuit, a driving method thereof, and a display panel, so as to solve the problem of poor display uniformity of the existing AMOLED display panel.
  • an embodiment of the present invention provides a pixel circuit, where the pixel circuit includes:
  • a driving unit, a pull-down unit and a light-emitting unit wherein,
  • the control terminal of the driving unit is electrically connected to the first node, the first terminal of the driving unit is connected to the working voltage, and the second terminal of the driving terminal unit is electrically connected to the second node;
  • the control end of the pull-down unit is connected to the pull-down control signal, the first end of the pull-down unit is electrically connected to the second node, and the second end of the pull-down unit is electrically connected to the common ground voltage; the pull-down unit uses connecting the second node to the common ground voltage when the pixel circuit is reset, so as to pull down the potential of the second node;
  • the first end of the light-emitting unit is electrically connected to the second node, and the second end of the light-emitting unit is electrically connected to the common ground voltage.
  • the pixel circuit further includes a writing unit, a control terminal of the writing unit is connected to a first control signal, a first terminal of the writing unit is electrically connected to a data line, and the writing unit is The second end of the unit is electrically connected to the first node.
  • the pixel circuit further includes a sensing unit, a control terminal of the sensing unit is connected to a second control signal, and a first terminal of the sensing unit is electrically connected to the second node, so The second end of the sensing unit is electrically connected to the sensing line.
  • the pixel circuit further includes a storage unit, a first terminal of the storage unit is electrically connected to the first node, and a second terminal of the storage unit is electrically connected to the second node.
  • the driving unit includes a first thin film transistor
  • the writing unit includes a second thin film transistor
  • the sensing unit includes a third thin film transistor
  • the pull-down unit includes a fourth thin film transistor
  • the The storage unit includes a storage capacitor
  • the light-emitting unit includes an organic light-emitting diode
  • the gate of the first thin film transistor is electrically connected to the first node, the source of the first thin film transistor is connected to the working voltage, and the drain of the first thin film transistor is electrically connected to the second node node;
  • the gate of the second thin film transistor is connected to the first control signal, the source of the second thin film transistor is electrically connected to the data line, and the drain of the second thin film transistor is electrically connected to the first control signal node;
  • the gate of the third thin film transistor is connected to the second control signal, the source of the third thin film transistor is electrically connected to the second node, and the drain of the third thin film transistor is electrically connected to the second node sensing line;
  • the gate of the fourth thin film transistor is connected to the pull-down control signal, the source of the fourth thin film transistor is electrically connected to the second node, and the drain of the fourth thin film transistor is electrically connected to the common ground voltage;
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the second node;
  • the first terminal of the organic light emitting diode is electrically connected to the second node, and the second terminal of the organic light emitting diode is electrically connected to the common ground voltage.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are N-type thin film transistors.
  • the pixel circuit includes a reset phase in which the first control signal and the second control signal provide a low level and the pull-down control signal provides a high level.
  • the pixel circuit further includes a write phase in which the first control signal and the second control signal provide a high level and the pull-down control signal provides a low level flat.
  • the pixel circuit further includes a light-emitting phase in which the first control signal, the second control signal, and the pull-down control signal provide a low level.
  • an embodiment of the present invention provides a method for driving a pixel circuit, which is used to drive the pixel circuit described in the first aspect.
  • the method for driving a pixel circuit includes a reset phase, and in the reset phase:
  • the first control signal and the second control signal provide a low level, and the pull-down control signal provides a high level, so that the first thin film transistor, the second thin film transistor, and the third thin film transistor off, the fourth thin film transistor is on.
  • the driving method of the pixel circuit further includes a writing stage, in which:
  • the first control signal and the second control signal provide a high level, and the pull-down control signal provides a low level, so that the first thin film transistor, the second thin film transistor and the third thin film transistor On, the fourth thin film transistor is off.
  • the driving method of the pixel circuit further includes a light-emitting stage, in which:
  • the first control signal, the second control signal and the pull-down control signal provide a low level to turn on the first thin film transistor, the second thin film transistor, the third thin film transistor and the The fourth thin film transistor is turned off.
  • the duration of the reset phase is adjusted according to the size of the fourth thin film transistor and the target potential of the second node.
  • the duration of the reset phase is positively related to the potential difference between the initial potential of the second node and the target potential obtained by reset.
  • the size of the fourth thin film transistor is negatively correlated with the time period during which the second node is reset from the initial potential to the target potential.
  • an embodiment of the present invention provides a display panel, the display panel includes a pixel circuit, and the pixel circuit includes:
  • a driving unit, a pull-down unit and a light-emitting unit wherein,
  • the control terminal of the driving unit is electrically connected to the first node, the first terminal of the driving unit is connected to the working voltage, and the second terminal of the driving terminal unit is electrically connected to the second node;
  • the control end of the pull-down unit is connected to the pull-down control signal, the first end of the pull-down unit is electrically connected to the second node, and the second end of the pull-down unit is electrically connected to the common ground voltage; the pull-down unit uses connecting the second node to the common ground voltage when the pixel circuit is reset, so as to pull down the potential of the second node;
  • the first end of the light-emitting unit is electrically connected to the second node, and the second end of the light-emitting unit is electrically connected to the common ground voltage.
  • the pixel circuit further includes a writing unit, a control terminal of the writing unit is connected to a first control signal, a first terminal of the writing unit is electrically connected to a data line, and the writing unit is The second end of the unit is electrically connected to the first node.
  • the pixel circuit further includes a sensing unit, a control terminal of the sensing unit is connected to a second control signal, and a first terminal of the sensing unit is electrically connected to the second node, so The second end of the sensing unit is electrically connected to the sensing line.
  • the pixel circuit further includes a storage unit, a first terminal of the storage unit is electrically connected to the first node, and a second terminal of the storage unit is electrically connected to the second node.
  • the driving unit includes a first thin film transistor
  • the writing unit includes a second thin film transistor
  • the sensing unit includes a third thin film transistor
  • the pull-down unit includes a fourth thin film transistor
  • the The storage unit includes a storage capacitor
  • the light-emitting unit includes an organic light-emitting diode
  • the gate of the first thin film transistor is electrically connected to the first node, the source of the first thin film transistor is connected to the working voltage, and the drain of the first thin film transistor is electrically connected to the second node node;
  • the gate of the second thin film transistor is connected to the first control signal, the source of the second thin film transistor is electrically connected to the data line, and the drain of the second thin film transistor is electrically connected to the first control signal node;
  • the gate of the third thin film transistor is connected to the second control signal, the source of the third thin film transistor is electrically connected to the second node, and the drain of the third thin film transistor is electrically connected to the second node sensing line;
  • the gate of the fourth thin film transistor is connected to the pull-down control signal, the source of the fourth thin film transistor is electrically connected to the second node, and the drain of the fourth thin film transistor is electrically connected to the common ground voltage;
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to the second node;
  • the first terminal of the organic light emitting diode is electrically connected to the second node, and the second terminal of the organic light emitting diode is electrically connected to the common ground voltage.
  • the potential of the second node is pulled down by the pull-down unit during reset, which improves the reset capability of the second node, so that the second node can drop to the target potential in a shorter period of time, avoiding This avoids the influence on the voltage Vgs between the first node and the second node of the driving unit due to the fact that the second node cannot drop to the target potential within a specified period of time.
  • the pixel circuit is applied to an AMOLED display panel, since the second node of each pixel circuit can be reset to the same target potential, the Vgs of each pixel circuit are equal, and the current flowing through the light-emitting unit of each pixel circuit is equal to If they are equal, the light-emitting luminances of the light-emitting units of each pixel circuit are all equal, thereby improving the display uniformity of the AMOLED display panel.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a pixel circuit provided by an embodiment of the present invention.
  • FIG. 3 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of signal simulation results of different pixel circuits.
  • FIG. 5 is a graph showing the variation trend of display non-uniformity with cathode voltage drop of a display panel including different pixel circuits.
  • FIG. 6 is a flowchart of a method for driving a pixel circuit according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. As shown in FIG. 1 , the pixel circuit includes:
  • a driving unit 101 a pull-down unit 102 and a light-emitting unit 103 . in:
  • the control terminal of the driving unit 101 is electrically connected to the first node G, the first terminal of the driving unit 101 is connected to the working voltage V DD , and the second terminal of the driving unit 101 is electrically connected to the second node S.
  • the control end of the pull-down unit 102 is connected to the pull-down control signal RD_V SS , the first end of the pull-down unit 102 is electrically connected to the second node S, and the second end of the pull-down unit 102 is electrically connected to the common ground voltage V SS .
  • the pull-down unit 102 is used to connect the second node S to the common ground voltage V SS when the pixel circuit is reset, so as to pull down the potential of the second node S.
  • the first terminal of the light-emitting unit 103 is electrically connected to the second node S, and the second terminal of the light-emitting unit 103 is electrically connected to the common ground voltage V SS .
  • the potential of the second node S is pulled down by the pull-down unit 102 during reset, so that the reset capability of the second node S is improved, so that the second node S can be reset in a shorter period of time.
  • Lowering to the target potential avoids the influence on the voltage Vgs between the first node G and the second node S of the driving unit 101 due to the failure of the second node S to drop to the target potential within a specified period of time.
  • the pixel circuit is applied to an AMOLED display panel, since the second node S of each pixel circuit can be reset to the same target potential, the Vgs of each pixel circuit are equal, and the Vgs flowing through the light emitting unit 103 of each pixel circuit are equal. The currents are equal, and the light-emitting luminances of the light-emitting units 103 of each pixel circuit are equal, thereby improving the display uniformity of the AMOLED display panel.
  • the pixel circuit further includes a writing unit 104 , the control terminal of the writing unit 104 is connected to the first control signal WR, and the first terminal of the writing unit 104 is electrically connected to the data line Date , the second terminal of the writing unit 104 is electrically connected to the first node G.
  • the data line Date is used to output a data signal
  • the writing unit 104 is used to control the first node G to access the data signal.
  • the pixel circuit further includes a sensing unit 105 , the control terminal of the sensing unit 105 is connected to the second control signal RD, and the first terminal of the sensing unit 105 is electrically connected to the second node S, the second end of the sensing unit is electrically connected to the sensing line Monitor.
  • the sensing line Monitor is used to output an initialization signal
  • the sensing unit 105 is used to control the second node S to access the initialization signal.
  • the pixel circuit further includes a storage unit 106 , the first terminal of the storage unit 106 is electrically connected to the first node G, and the second terminal of the storage unit 106 is electrically connected to the second node S.
  • FIG. 2 is a circuit diagram of the pixel circuit provided by the embodiment of the present invention.
  • the driving unit 101 includes a first thin film transistor T1, and writes
  • the unit 104 includes a second thin film transistor T2
  • the sensing unit 105 includes a third thin film transistor T3
  • the pull-down unit 102 includes a fourth thin film transistor T4
  • the storage unit 106 includes a storage capacitor Cst
  • the light emitting unit 103 includes an organic light emitting diode OLED.
  • the gate of the first thin film transistor T1 is electrically connected to the first node G, the source of the first thin film transistor T1 is connected to the working voltage VDD, and the drain of the first thin film transistor T1 is electrically connected to the second node S; the second thin film transistor T1 is electrically connected to the second node S;
  • the gate of T2 is connected to the first control signal WR, the source of the second thin film transistor T2 is electrically connected to the data line Date, the drain of the second thin film transistor T2 is electrically connected to the first node G; the gate of the third thin film transistor T3
  • the pole is connected to the second control signal RD, the source of the third thin film transistor T3 is electrically connected to the second node S, the drain of the third thin film transistor T3 is electrically connected to the sensing line Monitor; the gate of the fourth thin film transistor T4 is connected to the second node S.
  • the pull-down control signal RD_V SS is input, the source of the fourth thin film transistor T4 is electrically connected to the second node S, and the drain of the fourth thin film transistor T4 is electrically connected to the common ground voltage V SS .
  • the first terminal of the storage capacitor Cst is electrically connected to the first node G, and the second terminal of the storage capacitor Cst is electrically connected to the second node S; the first terminal of the organic light emitting diode OLED is electrically connected to the second node S, and the organic light emitting diode OLED is electrically connected to the second node S.
  • the second end of the is electrically connected to the common ground voltage Vss.
  • the thin film transistor in the embodiment of the present invention includes a gate electrode, a source electrode and a drain electrode. Since the source electrode and the drain electrode of the thin film transistor are symmetrical, the source electrode and the drain electrode thereof can be interchanged.
  • the control terminal is the gate, and the first terminal and the second terminal are the source and the drain, respectively. It should be noted that, in other embodiments, the first end and the second end are the drain electrode and the source electrode, respectively.
  • the thin film transistors in the embodiments of the present invention may include P-type and/or N-type transistors, wherein the P-type thin-film transistor is turned on when the gate is at a low potential, and is turned off when the gate is at a high potential; Turns on when the gate is high and turns off when the gate is low.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are N-type thin film transistors.
  • FIG. 3 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention.
  • the first control signal WR, the second control signal RD and the pull-down control signal RD_Vss act together in the reset phase t1 of the pixel circuit, write In the stage t2 and the light-emitting stage t3, the working process of the pixel circuit will be described in detail below:
  • the first control signal WR and the second control signal RD provide a low level
  • the pull-down control signal RD_V SS provides a high level.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 is turned off, and the fourth thin film transistor T4 is turned on. Since the fourth thin film transistor T4 is turned on, the second node S can be connected to the common ground voltage, thereby pulling down the potential of the second node S, and reducing the potential of the second node S from the initial potential to the target potential.
  • the duration of the reset phase t1 can be adjusted according to the size of the fourth thin film transistor T4 and the target potential of the second node S.
  • the duration of the reset phase is positively related to the potential difference between the initial potential of the second node and the target potential obtained by reset, that is, for the fourth thin film of the same size
  • the longer the duration of the reset phase t1 the lower the target potential obtained by the reset of the potential of the second node S from the initial potential.
  • the size of the fourth thin film transistors is negatively correlated with the time period during which the second node is reset from the initial potential to the target potential, that is, for the fourth thin film transistors T4 of different sizes , the larger the size of the fourth thin film transistor T4, the shorter the time period for the potential of the second node S to be reset from the initial potential to the target potential.
  • the organic light emitting diode OLED is in a non-light-emitting state, so this time is equivalent to performing black insertion processing on the display screen, which can improve or even eliminate the dynamic afterimage of the display screen.
  • the first control signal WR and the second control signal RD provide a high level
  • the pull-down control signal RD_V SS provides a low level.
  • the first thin film transistor T1, the second thin film transistor T2 and the third thin film The transistor T3 is turned on, and the fourth thin film transistor T4 is turned off.
  • the gate of the first thin film transistor T1 is connected to the data signal provided by the data line Date
  • the source of the first thin film transistor T1 is connected to the initialization signal provided by the sensing line Monitor.
  • the first control signal WR, the second control signal RD and the pull-down control signal RD_V SS provide a low level
  • the first thin film transistor T1 is turned on
  • the second thin film transistor T2 the third thin film transistor T3 and the fourth thin film transistor T4 is closed.
  • the first thin film transistor T1 drives the organic light emitting diode OLED to emit light.
  • the fourth thin film transistor T4 is turned on, so that the second node S is connected to the common ground voltage, the potential of the second node S is pulled down, and the second node is raised.
  • the reset capability of S enables the second node S to drop to the target potential in a shorter period of time, avoiding the first thin film transistor T1 due to the fact that the second node S cannot drop to the target potential within a specified period of time. Influence of the voltage Vgs between the node G and the second node S.
  • the pixel circuit is applied to an AMOLED display panel, since the second node S of each pixel circuit can be reset to the same target potential, the Vgs of each pixel circuit are equal, and the organic light emitting diode OLED flowing through each pixel circuit The currents of the OLEDs are equal, and the luminous brightness of the organic light emitting diodes OLED in each pixel circuit is equal, thereby improving the display uniformity of the AMOLED display panel.
  • the embodiment of the present invention removes the fourth thin film transistor T4 in the pixel circuit (referred to as a 4T1C pixel circuit) in the embodiment of the present invention to obtain a 3T1C pixel circuit.
  • the 3T1C pixel circuit and the 4T1C pixel circuit in the embodiment of the present invention are simulated respectively, and the signal simulation results of the two pixel circuits are obtained as shown in FIG. 4 .
  • Figure 4 is a schematic diagram of the signal simulation results of different pixel circuits, wherein, part (a) in Figure 4 is the signal simulation results of the 3T1C pixel circuit, from top to bottom, the first control signal WR, the second control signal RD and the The potential waveform of the second node S, part (b) in FIG.
  • 4 is the signal simulation result of the 4T1C pixel circuit in the embodiment of the present invention, from top to bottom are the first control signal WR, the second control signal RD, the pull-down For the potential waveforms of the control signal RD_V SS and the second node S, the abscissa of each signal above is time, and the unit is seconds, and the ordinate of each signal is voltage, and the unit is volts.
  • the second node S can only be reset to 2.2V (the target potential is 1.2V), while the 4T1C pixel circuit in the embodiment of the present invention can be reset to the second node S after the reset phase. Reset to 1.1V, and then write the target potential 1.2V. Therefore, through the simulation test, it can be verified that the 4T1C pixel circuit in the embodiment of the present invention has a strong reset capability.
  • the embodiment of the present invention simulates a display panel including the above-mentioned 3T1C pixel circuit and a display panel including the 4T1C pixel circuit in the embodiment of the present invention under the condition of different cathode voltage drops, and obtains two The display non-uniformity of each display panel under different cathode voltage drops is shown in FIG. 5 .
  • 5 is a graph showing the variation trend of display non-uniformity with cathode voltage drop of a display panel including different pixel circuits, wherein the abscissa is the cathode voltage drop, in volts, the ordinate is the non-uniformity, and the dotted line represents pixels including 3T1C
  • the abscissa is the cathode voltage drop, in volts
  • the ordinate is the non-uniformity
  • the dotted line represents pixels including 3T1C
  • the solid line represents the variation trend of the display non-uniformity with the cathode voltage drop of the display panel including the 4T1C pixel circuit in the embodiment of the present invention.
  • the display panel including the 4T1C pixel circuit in the embodiment of the present invention is very effective in resisting the influence of the cathode voltage drop, and even when the cathode voltage drop reaches 3V, the display screen of the display panel can still remain within 20%. inhomogeneity.
  • An embodiment of the present invention further provides a method for driving a pixel circuit, the driving method is used to drive the pixel circuit described in any of the above embodiments. Repeat.
  • the driving method includes at least a reset phase t1.
  • the pixel circuit is in the reset phase t1, that is, reset, the second node S is connected to the common ground voltage RD_Vss through the pull-down unit 102 to pull down the potential of the second node S.
  • the potential of the second node S is pulled down by the pull-down unit 102 during reset, which improves the reset capability of the second node S, so that the second node S can be operated in a shorter time.
  • the voltage Vgs between the first node G and the second node S of the driving unit 101 is prevented from being affected by the failure of the second node S to drop to the target potential within the specified time period. If the pixel circuit is applied to an AMOLED display panel, since the second node S of each pixel circuit can be reset to the same target potential, the Vgs of each pixel circuit are equal, and the Vgs flowing through the light emitting unit 103 of each pixel circuit are equal. The currents are equal, and the light-emitting luminances of the light-emitting units 103 of each pixel circuit are equal, thereby improving the display uniformity of the AMOLED display panel.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are N-type thin film transistors as an example to describe the driving method of the pixel circuit.
  • illustrate. 6 is a flowchart of a method for driving a pixel circuit according to an embodiment of the present invention. As shown in FIG. 6 , the method for driving a pixel circuit includes a reset phase t1, and in the reset phase t1:
  • the first control signal WR and the second control signal RD provide a low level, and the pull-down control signal RD_V SS provides a high level.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are turned off, and the fourth The thin film transistor T4 is turned on. Since the fourth thin film transistor T4 is turned on, the second node S can be connected to the common ground voltage, thereby pulling down the potential of the second node S, and reducing the potential of the second node S from the initial potential to the target potential.
  • the duration of the reset phase t1 can be adjusted according to the size of the fourth thin film transistor T4 and the target potential of the second node S.
  • the longer the duration of the reset phase t1 is, the lower the target potential obtained by the reset of the potential of the second node S from the initial potential is lower; for the fourth thin film transistor T4 of different sizes, the first The larger the size of the four thin film transistor T4, the shorter the time period for the potential of the second node S to be reset from the initial potential to the target potential.
  • the organic light emitting diode OLED is in a non-light-emitting state, so this time is equivalent to performing black insertion processing on the display screen, which can improve or even eliminate the dynamic afterimage of the display screen.
  • the driving method of the pixel circuit further includes a writing stage t2, and in the writing stage t2:
  • the first control signal WR and the second control signal RD provide a high level, and the pull-down control signal RD_V SS provides a low level.
  • the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the fourth The thin film transistor T4 is turned off.
  • the gate of the first thin film transistor T1 is connected to the data signal provided by the data line Date, and the source of the first thin film transistor T1 is connected to the initialization signal provided by the sensing line Monitor.
  • the driving method of the pixel circuit further includes a light-emitting stage t3, and in the light-emitting stage t3:
  • the first control signal WR, the second control signal RD and the pull-down control signal RD_V SS provide a low level, the first thin film transistor T1 is turned on, and the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are turned off.
  • the first thin film transistor T1 drives the organic light emitting diode OLED to emit light.
  • the fourth thin film transistor T4 is turned on, so that the second node S is connected to the common ground voltage, the potential of the second node S is pulled down, and the voltage of the second node S is increased.
  • the reset capability of the second node S enables the second node S to drop to the target potential in a shorter period of time, and avoids the impact on the first thin film transistor T1 due to the fact that the second node S cannot drop to the target potential within a specified period of time
  • the pixel circuit is applied to an AMOLED display panel, since the second node S of each pixel circuit can be reset to the same target potential, the Vgs of each pixel circuit are equal, and the organic light emitting diode OLED flowing through each pixel circuit The currents of the OLEDs are equal, and the luminous brightness of the organic light emitting diodes OLED in each pixel circuit is equal, thereby improving the display uniformity of the AMOLED display panel.
  • the duration of the reset phase t1 can be adjusted according to the size of the fourth thin film transistor T4 and the target potential of the second node S.
  • the duration of the reset phase is positively related to the potential difference between the initial potential of the second node and the target potential obtained by reset, that is, for the fourth thin film of the same size
  • the longer the duration of the reset phase t1 the lower the target potential obtained by the reset of the potential of the second node S from the initial potential.
  • the size of the fourth thin film transistors is negatively correlated with the time period during which the second node is reset from the initial potential to the target potential, that is, for the fourth thin film transistors T4 of different sizes , the larger the size of the fourth thin film transistor T4, the shorter the time period for the potential of the second node S to be reset from the initial potential to the target potential.
  • An embodiment of the present invention further provides a display panel, which includes the above-mentioned pixel circuit.
  • the display panel is preferably an AMOLED display panel.
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention. As shown in FIG. 1 , the pixel circuit includes:
  • a driving unit 101 a pull-down unit 102 and a light-emitting unit 103 . in:
  • the control terminal of the driving unit 101 is electrically connected to the first node G, the first terminal of the driving unit 101 is connected to the working voltage V DD , and the second terminal of the driving unit 101 is electrically connected to the second node S.
  • the control end of the pull-down unit 102 is connected to the pull-down control signal RD_V SS , the first end of the pull-down unit 102 is electrically connected to the second node S, and the second end of the pull-down unit 102 is electrically connected to the common ground voltage V SS .
  • the pull-down unit 102 is used to connect the second node S to the common ground voltage V SS when the pixel circuit is reset, so as to pull down the potential of the second node S.
  • the first terminal of the light-emitting unit 103 is electrically connected to the second node S, and the second terminal of the light-emitting unit 103 is electrically connected to the common ground voltage V SS .
  • An embodiment of the present invention provides a pixel circuit included in a display panel, during reset, the potential of the second node S is pulled down by the pull-down unit 102, which improves the reset capability of the second node S, so that the second node S can be used in a shorter time
  • the voltage Vgs between the first node G and the second node S of the driving unit 101 is prevented from being affected by the failure of the second node S to drop to the target potential within the specified time period. Since the second node S of each pixel circuit in the display panel can be reset to the same target potential, the Vgs of each pixel circuit are equal, and the currents flowing through the light emitting units 103 of each pixel circuit are equal, and each pixel circuit has the same Vgs. The light-emitting luminances of the light-emitting units 103 are equal, thereby improving the display uniformity of the display panel.
  • the pixel circuit further includes a writing unit 104 , the control terminal of the writing unit 104 is connected to the first control signal WR, and the first terminal of the writing unit 104 is electrically connected to the data line Date , the second terminal of the writing unit 104 is electrically connected to the first node G.
  • the data line Date is used to output a data signal
  • the writing unit 104 is used to control the first node G to access the data signal.
  • the pixel circuit further includes a sensing unit 105 , the control terminal of the sensing unit 105 is connected to the second control signal RD, and the first terminal of the sensing unit 105 is electrically connected to the second node S, the second end of the sensing unit is electrically connected to the sensing line Monitor.
  • the sensing line Monitor is used to output an initialization signal
  • the sensing unit 105 is used to control the second node S to access the initialization signal.
  • the pixel circuit further includes a storage unit 106 , the first terminal of the storage unit 106 is electrically connected to the first node G, and the second terminal of the storage unit 106 is electrically connected to the second node S.
  • FIG. 2 is a circuit diagram of the pixel circuit provided by the embodiment of the present invention.
  • the driving unit 101 includes a first thin film transistor T1, and writes
  • the unit 104 includes a second thin film transistor T2
  • the sensing unit 105 includes a third thin film transistor T3
  • the pull-down unit 102 includes a fourth thin film transistor T4
  • the storage unit 106 includes a storage capacitor Cst
  • the light emitting unit 103 includes an organic light emitting diode OLED.
  • the gate of the first thin film transistor T1 is electrically connected to the first node G, the source of the first thin film transistor T1 is connected to the working voltage VDD, and the drain of the first thin film transistor T1 is electrically connected to the second node S; the second thin film transistor T1 is electrically connected to the second node S;
  • the gate of T2 is connected to the first control signal WR, the source of the second thin film transistor T2 is electrically connected to the data line Date, the drain of the second thin film transistor T2 is electrically connected to the first node G; the gate of the third thin film transistor T3
  • the pole is connected to the second control signal RD, the source of the third thin film transistor T3 is electrically connected to the second node S, the drain of the third thin film transistor T3 is electrically connected to the sensing line Monitor; the gate of the fourth thin film transistor T4 is connected to the second node S.
  • the pull-down control signal RD_V SS is input, the source of the fourth thin film transistor T4 is electrically connected to the second node S, and the drain of the fourth thin film transistor T4 is electrically connected to the common ground voltage V SS .
  • the first terminal of the storage capacitor Cst is electrically connected to the first node G, and the second terminal of the storage capacitor Cst is electrically connected to the second node S; the first terminal of the organic light emitting diode OLED is electrically connected to the second node S, and the organic light emitting diode OLED is electrically connected to the second node S.
  • the second end of the is electrically connected to the common ground voltage Vss.
  • the thin film transistor in the embodiment of the present invention includes a gate electrode, a source electrode and a drain electrode. Since the source electrode and the drain electrode of the thin film transistor are symmetrical, the source electrode and the drain electrode thereof can be interchanged.
  • the control terminal is the gate, and the first terminal and the second terminal are the source and the drain, respectively. It should be noted that, in other embodiments, the first end and the second end are the drain electrode and the source electrode, respectively.
  • the thin film transistors in the embodiments of the present invention may include P-type and/or N-type transistors, wherein the P-type thin-film transistor is turned on when the gate is at a low potential, and is turned off when the gate is at a high potential; Turns on when the gate is high and turns off when the gate is low.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are N-type thin film transistors.
  • FIG. 3 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention.
  • the first control signal WR, the second control signal RD and the pull-down control signal RD_Vss act together in the reset phase t1 of the pixel circuit, write In the stage t2 and the light-emitting stage t3, the working process of the pixel circuit will be described in detail below:
  • the first control signal WR and the second control signal RD provide a low level
  • the pull-down control signal RD_V SS provides a high level.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 is turned off, and the fourth thin film transistor T4 is turned on. Since the fourth thin film transistor T4 is turned on, the second node S can be connected to the common ground voltage, thereby pulling down the potential of the second node S, and reducing the potential of the second node S from the initial potential to the target potential.
  • the duration of the reset phase t1 can be adjusted according to the size of the fourth thin film transistor T4 and the target potential of the second node S.
  • the duration of the reset phase is positively related to the potential difference between the initial potential of the second node and the target potential obtained by reset, that is, for the fourth thin film of the same size
  • the longer the duration of the reset phase t1 the lower the target potential obtained by the reset of the potential of the second node S from the initial potential.
  • the size of the fourth thin film transistors is negatively correlated with the time period during which the second node is reset from the initial potential to the target potential, that is, for the fourth thin film transistors T4 of different sizes , the larger the size of the fourth thin film transistor T4, the shorter the time period for the potential of the second node S to be reset from the initial potential to the target potential.
  • the organic light emitting diode OLED is in a non-light-emitting state, so this time is equivalent to performing black insertion processing on the display screen, which can improve or even eliminate the dynamic afterimage of the display screen.
  • the first control signal WR and the second control signal RD provide a high level
  • the pull-down control signal RD_V SS provides a low level.
  • the first thin film transistor T1, the second thin film transistor T2 and the third thin film The transistor T3 is turned on, and the fourth thin film transistor T4 is turned off.
  • the gate of the first thin film transistor T1 is connected to the data signal provided by the data line Date
  • the source of the first thin film transistor T1 is connected to the initialization signal provided by the sensing line Monitor.
  • the first control signal WR, the second control signal RD and the pull-down control signal RD_V SS provide a low level
  • the first thin film transistor T1 is turned on
  • the second thin film transistor T2 the third thin film transistor T3 and the fourth thin film transistor T4 is closed.
  • the first thin film transistor T1 drives the organic light emitting diode OLED to emit light.
  • the fourth thin film transistor T4 is turned on, so that the second node S is connected to the common ground voltage, and the potential of the second node S is pulled down,
  • the reset capability of the second node S is improved, so that the second node S can drop to the target potential in a shorter period of time, avoiding the impact on the first film due to the fact that the second node S cannot drop to the target potential within a specified period of time. Influence of the voltage Vgs between the first node G and the second node S of the transistor T1.
  • the Vgs of each pixel circuit is equal, the current flowing through the organic light emitting diode OLED of each pixel circuit is equal, and each pixel The light-emitting luminances of the organic light-emitting diodes OLED of the circuit are all equal, thereby improving the display uniformity of the display panel.

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Abstract

本发明实施例提供一种像素电路及其驱动方法、显示面板，在进行复位时通过下拉单元拉低第二节点的电位，提升了第二节点的复位能力，从而使第二节点能够在更短的时间段内降至目标电位，避免了由于第二节点无法在规定的时间段内降至目标电位对驱动单元的第一节点与第二节点之间电压的影响，提高了显示面板的显示均一性。

Description

像素电路及其驱动方法、显示面板 技术领域
本发明实施例涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示面板。
 背景技术
在大尺寸有源矩阵有机发光二极管（Active-Matrix Organic Light-Emitting Diode，AMOLED）显示面板中，发光模式可分为顶发射和底发射两种方案。其中，采用顶发射方案的AMOLED显示面板需要让有机发光二极管（Organic Light-Emitting Diode，OLED）发出的光穿过阴极，因此阴极的厚度需要做得很薄，以保证光的透过率，但这样做会使得阴极的面电阻变得较大，而较大的面电阻会使不同的像素电路中的阴极的电压降不相等。
对于每一像素电路，阴极的电压降会在OLED导通后通过OLED传导至驱动晶体管的源极，且在存储电容的作用下耦合到驱动晶体管的栅极，由于OLED的亮度主要受驱动晶体管的栅极与源极之间的电压Vgs的影响，因此在下一帧信号写入时，若驱动晶体管的栅极与源极无法正常复位（其中，源极的复位能力更弱，难以在规定时间内复位），则会影响该像素电路中的OLED的亮度。并且，由于不同的像素电路的阴极的电压降不相等，因此不同的像素电路中的OLED的亮度各不相同，最终影响AMOLED显示面板显示的均一性。
特别地，随着AMOLED显示面板的分辨率和刷新率的进一步提高，像素的充电时间进一步缩短，驱动晶体管的复位时间也随之缩短，导致驱动晶体管的源极无法在规定时间内复位，从而进一步加重了对AMOLED显示面板显示均一性的影响。
 技术问题
本发明实施例提供一种像素电路及其驱动方法、显示面板，用以解决现有的AMOLED显示面板显示均一性差的问题。
 技术解决方案
第一方面，本发明实施例提供一种像素电路，所述像素电路包括：
驱动单元、下拉单元和发光单元；其中，
所述驱动单元的控制端电性连接第一节点，所述驱动单元的第一端接入工作电压，所述驱动端单元的第二端电性连接第二节点；
所述下拉单元的控制端接入下拉控制信号，所述下拉单元的第一端电性连接所述第二节点，所述下拉单元的第二端电性连接公共接地电压；所述下拉单元用于在所述像素电路进行复位时使所述第二节点接入所述公共接地电压，以拉低所述第二节点的电位；
所述发光单元的第一端电性连接所述第二节点，所述发光单元的第二端电性连接所述公共接地电压。
在一些实施例中，所述像素电路还包括写入单元，所述写入单元的控制端接入第一控制信号，所述写入单元的第一端电性连接数据线，所述写入单元的第二端电性连接所述第一节点。
在一些实施例中，所述像素电路还包括感测单元，所述感测单元的控制端接入第二控制信号，所述感测单元的第一端电性连接所述第二节点，所述感测单元的第二端电性连接感测线。
在一些实施例中，所述像素电路还包括存储单元，所述存储单元的第一端电性连接所述第一节点，所述存储单元的第二端电性连接所述第二节点。
在一些实施例中，所述驱动单元包括第一薄膜晶体管，所述写入单元包括第二薄膜晶体管，所述感测单元包括第三薄膜晶体管，所述下拉单元包括第四薄膜晶体管，所述存储单元包括存储电容，所述发光单元包括有机发光二极管；其中，
所述第一薄膜晶体管的栅极电性连接所述第一节点，所述第一薄膜晶体管的源极接入所述工作电压，所述第一薄膜晶体管的漏极电性连接所述第二节点；
所述第二薄膜晶体管的栅极接入所述第一控制信号，所述第二薄膜晶体管的源极电性连接所述数据线，所第二薄膜晶体管的漏极电性连接所述第一节点；
所述第三薄膜晶体管的栅极接入所述第二控制信号，所述第三薄膜晶体管的源极电性连接所述第二节点，所述第三薄膜晶体管的漏极电性连接所述感测线；
所述第四薄膜晶体管的栅极接入所述下拉控制信号，所述第四薄膜晶体管的源极电性连接所述第二节点，所述第四薄膜晶体管的漏极电性连接所述公共接地电压；
所述存储电容的第一端电性连接所述第一节点，所述存储电容的第二端电性连接所述第二节点；
所述有机发光二极管的第一端电性连接所述第二节点，所述有机发光二极管的第二端电性连接所述公共接地电压。
在一些实施例中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管和所述第四薄膜晶体管为N型薄膜晶体管。
在一些实施例中，所述像素电路包括复位阶段，在所述复位阶段中，所述第一控制信号和所述第二控制信号提供低电平，所述下拉控制信号提供高电平。
在一些实施例中，所述像素电路还包括写入阶段，在所述写入阶段中，所述第一控制信号和所述第二控制信号提供高电平，所述下拉控制信号提供低电平。
在一些实施例中，所述像素电路还包括发光阶段，在所述发光阶段中，所述第一控制信号、所述第二控制信号和所述下拉控制信号提供低电平。
第二方面，本发明实施例提供一种像素电路的驱动方法，用于驱动第一方面所述的像素电路，所述像素电路的驱动方法包括复位阶段，在所述复位阶段中：
所述第一控制信号和所述第二控制信号提供低电平，所述下拉控制信号提供高电平，以使所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管关闭，所述第四薄膜晶体管打开。
在一些实施例中，所述像素电路的驱动方法还包括写入阶段，在所述写入阶段中：
所述第一控制信号和所述第二控制信号提供高电平，所述下拉控制信号提供低电平，以使所述第一薄膜晶体管、所述第二薄膜晶体管和所述第三薄膜晶体管打开，所述第四薄膜晶体管关闭。
在一些实施例中，所述像素电路的驱动方法还包括发光阶段，在所述发光阶段中：
所述第一控制信号、所述第二控制信号和所述下拉控制信号提供低电平，以使所述第一薄膜晶体管打开，所述第二薄膜晶体管、所述第三薄膜晶体管和所述第四薄膜晶体管关闭。
在一些实施例中，复位阶段的时长根据所述第四薄膜晶体管的尺寸和所述第二节点的目标电位进行调整。
在一些实施例中，对于同一尺寸的所述第四薄膜晶体管，所述复位阶段的时长与所述第二节点的初始电位与复位得到的所述目标电位之间电位差正相关。
在一些实施例中，对于不同尺寸的所述第四薄膜晶体管，所述第四薄膜晶体管的尺寸与所述第二节点由初始电位复位到所述目标电位的时长负相关。
第三方面，本发明实施例提供一种显示面板，所述显示面板包括像素电路，所述像素电路包括：
驱动单元、下拉单元和发光单元；其中，
所述驱动单元的控制端电性连接第一节点，所述驱动单元的第一端接入工作电压，所述驱动端单元的第二端电性连接第二节点；
所述下拉单元的控制端接入下拉控制信号，所述下拉单元的第一端电性连接所述第二节点，所述下拉单元的第二端电性连接公共接地电压；所述下拉单元用于在所述像素电路进行复位时使所述第二节点接入所述公共接地电压，以拉低所述第二节点的电位；
所述发光单元的第一端电性连接所述第二节点，所述发光单元的第二端电性连接所述公共接地电压。
在一些实施例中，所述像素电路还包括写入单元，所述写入单元的控制端接入第一控制信号，所述写入单元的第一端电性连接数据线，所述写入单元的第二端电性连接所述第一节点。
在一些实施例中，所述像素电路还包括感测单元，所述感测单元的控制端接入第二控制信号，所述感测单元的第一端电性连接所述第二节点，所述感测单元的第二端电性连接感测线。
在一些实施例中，所述像素电路还包括存储单元，所述存储单元的第一端电性连接所述第一节点，所述存储单元的第二端电性连接所述第二节点。
在一些实施例中，所述驱动单元包括第一薄膜晶体管，所述写入单元包括第二薄膜晶体管，所述感测单元包括第三薄膜晶体管，所述下拉单元包括第四薄膜晶体管，所述存储单元包括存储电容，所述发光单元包括有机发光二极管；其中，
所述第一薄膜晶体管的栅极电性连接所述第一节点，所述第一薄膜晶体管的源极接入所述工作电压，所述第一薄膜晶体管的漏极电性连接所述第二节点；
所述第二薄膜晶体管的栅极接入所述第一控制信号，所述第二薄膜晶体管的源极电性连接所述数据线，所第二薄膜晶体管的漏极电性连接所述第一节点；
所述第三薄膜晶体管的栅极接入所述第二控制信号，所述第三薄膜晶体管的源极电性连接所述第二节点，所述第三薄膜晶体管的漏极电性连接所述感测线；
所述第四薄膜晶体管的栅极接入所述下拉控制信号，所述第四薄膜晶体管的源极电性连接所述第二节点，所述第四薄膜晶体管的漏极电性连接所述公共接地电压；
所述存储电容的第一端电性连接所述第一节点，所述存储电容的第二端电性连接所述第二节点；
所述有机发光二极管的第一端电性连接所述第二节点，所述有机发光二极管的第二端电性连接所述公共接地电压。
 有益效果
本发明提供的像素电路，在进行复位时通过下拉单元拉低第二节点的电位，提升了第二节点的复位能力，从而使第二节点能够在更短的时间段内降至目标电位，避免了由于第二节点无法在规定的时间段内降至目标电位对驱动单元的第一节点与第二节点之间电压Vgs的影响。若将该像素电路应用于AMOLED显示面板，由于每一像素电路的第二节点均能复位为同一目标电位，因此每一像素电路的Vgs均相等，流经每一像素电路的发光单元的电流均相等，每一像素电路的发光单元的发光亮度均相等，从而提高了AMOLED显示面板的显示均一性。
 附图说明
图1为本发明实施例提供的像素电路的结构示意图。
图2为本发明实施例提供的像素电路的电路图。
图3为本发明实施例提供的像素电路的驱动时序图。
图4为不同的像素电路的信号仿真结果示意图。
图5为包含不同的像素电路的显示面板的显示不均一性随阴极电压降的变化趋势图。
图6为本发明实施例提供的像素电路的驱动方法的流程图。
 本发明的实施方式
为使本发明的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
图1为本发明实施例提供的像素电路的结构示意图，如图1所示，该像素电路包括：
驱动单元101、下拉单元102和发光单元103。其中：
驱动单元101的控制端电性连接第一节点G，驱动单元101的第一端接入工作电压V DD，驱动单元101的第二端电性连接第二节点S。
下拉单元102的控制端接入下拉控制信号RD_V SS，下拉单元102的第一端电性连接第二节点S，下拉单元102的第二端电性连接公共接地电压V SS。其中，下拉单元102用于在像素电路进行复位时使第二节点S接入公共接地电压V SS，以拉低第二节点S的电位。
发光单元103的第一端电性连接第二节点S，发光单元103的第二端电性连接公共接地电压V SS。
本发明实施例提供的像素电路，在进行复位时通过下拉单元102拉低第二节点S的电位，提升了第二节点S的复位能力，从而使第二节点S能够在更短的时间段内降至目标电位，避免了由于第二节点S无法在规定的时间段内降至目标电位对驱动单元101的第一节点G与第二节点S之间电压Vgs的影响。若将该像素电路应用于AMOLED显示面板，由于每一像素电路的第二节点S均能复位为同一目标电位，因此每一像素电路的Vgs均相等，流经每一像素电路的发光单元103的电流均相等，每一像素电路的发光单元103的发光亮度均相等，从而提高了AMOLED显示面板的显示均一性。
基于上述实施例，如图1所示，该像素电路还包括写入单元104，写入单元104的控制端接入第一控制信号WR，写入单元104的第一端电性连接数据线Date，写入单元104的第二端电性连接第一节点G。
具体地，在像素电路进行写入时，数据线Date用于输出数据信号，写入单元104用于控制第一节点G接入该数据信号。
基于上述实施例，如图1所示，该像素电路还包括感测单元105，感测单元105的控制端接入第二控制信号RD，感测单元105的第一端电性连接第二节点S，感测单元的第二端电性连接感测线Monitor。
具体地，在像素电路进行写入时，感测线Monitor用于输出初始化信号，感测单元105用于控制第二节点S接入初始化信号。
基于上述实施例，如图1所示，该像素电路还包括存储单元106，存储单元106的第一端电性连接第一节点G，存储单元106的第二端电性连接第二节点S。
基于上述实施例，本发明实施例对像素电路的具体结构进行说明，图2为本发明实施例提供的像素电路的电路图，如图2所示，驱动单元101包括第一薄膜晶体管T1，写入单元104包括第二薄膜晶体管T2，感测单元105包括第三薄膜晶体管T3，下拉单元102包括第四薄膜晶体管T4，存储单元106包括存储电容Cst，发光单元103包括有机发光二极管OLED。其中：
第一薄膜晶体管T1的栅极电性连接第一节点G，第一薄膜晶体管T1的源极接入工作电压VDD，第一薄膜晶体管T1的漏极电性连接第二节点S；第二薄膜晶体管T2的栅极接入第一控制信号WR，第二薄膜晶体管T2的源极电性连接数据线Date，第二薄膜晶体管T2的漏极电性连接第一节点G；第三薄膜晶体管T3的栅极接入第二控制信号RD，第三薄膜晶体管T3的源极电性连接第二节点S，第三薄膜晶体管T3的漏极电性连接感测线Monitor；第四薄膜晶体管T4的栅极接入下拉控制信号RD_V SS，第四薄膜晶体管T4的源极电性连接第二节点S，第四薄膜晶体管T4的漏极电性连接公共接地电压V SS。存储电容Cst的第一端电性连接第一节点G，存储电容Cst的第二端电性连接第二节点S；有机发光二极管OLED的第一端电性连接第二节点S，有机发光二极管OLED的第二端电性连接公共接地电压Vss。
需要说明的是，本发明实施例中的薄膜晶体管包括栅极、源极和漏极，由于薄膜晶体管的源极和漏极是对称的，因此其源极和漏极是可以互换的。对于上述的每一薄膜晶体管，其控制端为栅极，其第一端和第二端分别为源极和漏极。需要说明的是，在其他实施例中，第一端和第二端分别为漏极和源极。
此外，本发明实施例中的薄膜晶体管可以包括P型和/或N型晶体管两种，其中，P型薄膜晶体管在栅极为低电位时打开，在栅极为高电位时关闭；N型薄膜晶体管在栅极为高电位时打开，在栅极为低电位时关闭。
基于上述实施例，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4为N型薄膜晶体管。
基于上述实施例，以第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4为N型薄膜晶体管为例对该像素电路的驱动时序进行说明。图3为本发明实施例提供的像素电路的驱动时序图，如图3所示，第一控制信号WR、第二控制信号RD和下拉控制信号RD_Vss共同作用于像素电路的复位阶段t1、写入阶段t2和发光阶段t3，以下对该像素电路的工作过程进行详细说明：
在复位阶段t1，第一控制信号WR和第二控制信号RD提供低电平，下拉控制信号RD_V SS提供高电平，此时，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3关闭，第四薄膜晶体管T4打开。由于第四薄膜晶体管T4打开，因此可以使第二节点S接入公共接地电压，从而拉低第二节点S的电位，使第二节点S的电位由初始电位降至目标电位。
需要说明的是，在本发明实施例中，复位阶段t1的时长可以根据第四薄膜晶体管T4的尺寸和第二节点S的目标电位来调整。对于同一尺寸的所述第四薄膜晶体管，所述复位阶段的时长与所述第二节点的初始电位与复位得到的所述目标电位之间电位差正相关，即，对于同一尺寸的第四薄膜晶体管T4，复位阶段t1的时长越长，则第二节点S的电位由初始电位所复位得到的目标电位越低。对于不同尺寸的所述第四薄膜晶体管，所述第四薄膜晶体管的尺寸与所述第二节点由初始电位复位到所述目标电位的时长负相关，即，对于不同尺寸的第四薄膜晶体管T4，第四薄膜晶体管T4的尺寸越大，则第二节点S的电位由初始电位复位到目标电位的时长越短。
可以理解地，由于在复位阶段t1中，有机发光二极管OLED处于非发光状态，因此此时相当于对显示画面进行了插黑处理，能够改善甚至消除显示画面的动态残像。
在写入阶段t2，第一控制信号WR和第二控制信号RD提供高电平，下拉控制信号RD_V SS提供低电平，此时，第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3打开，第四薄膜晶体管T4关闭。第一薄膜晶体管T1的栅极接入数据线Date提供的数据信号，第一薄膜晶体管T1的源极接入感测线Monitor提供的初始化信号。
在发光阶段t3，第一控制信号WR、第二控制信号RD和下拉控制信号RD_V SS提供低电平，第一薄膜晶体管T1打开，第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4关闭。第一薄膜晶体管T1驱动有机发光二极管OLED发光。
本发明实施例提供的像素电路，在复位阶段t1中通过使第四薄膜晶体管T4打开，从而使第二节点S接入公共接地电压，拉低了第二节点S的电位，提升了第二节点S的复位能力，使第二节点S能够在更短的时间段内降至目标电位，避免了由于第二节点S无法在规定的时间段内降至目标电位对第一薄膜晶体管T1的第一节点G与第二节点S之间电压Vgs的影响。若将该像素电路应用于AMOLED显示面板，由于每一像素电路的第二节点S均能复位为同一目标电位，因此每一像素电路的Vgs均相等，流经每一像素电路的有机发光二极管OLED的电流均相等，每一像素电路的有机发光二极管OLED的发光亮度均相等，从而提高了AMOLED显示面板的显示均一性。
作为一个优选的实施例，本发明实施例去除本发明实施例中的像素电路（为了便于描述，将其称为4T1C像素电路）中的第四薄膜晶体管T4，得到3T1C像素电路。分别对该3T1C像素电路和本发明实施例中的4T1C像素电路进行仿真，得到两个像素电路的信号仿真结果如图4所示。图4为不同的像素电路的信号仿真结果示意图，其中，图4中的（a）部分为3T1C像素电路的信号仿真结果，从上到下依次为第一控制信号WR、第二控制信号RD和第二节点S的电位波形，图4中的（b）部分为本发明实施例中的4T1C像素电路的信号仿真结果，从上到下依次为第一控制信号WR、第二控制信号RD、下拉控制信号RD_V SS和第二节点S的电位波形，上述每个信号的横坐标均为时间，单位为秒，每个信号的纵坐标均为电压，单位为伏特。显而易见的是，3T1C像素电路经过复位阶段后，第二节点S只能复位到2.2V（目标电位为1.2V），而本发明实施例中的4T1C像素电路经过复位阶段后，第二节点可以被复位到1.1V，后续将写入目标电位1.2V。因此，通过该仿真试验可以验证本发明实施例中的4T1C像素电路具有较强的复位能力。
作为一个优选的实施例，本发明实施例在不同的阴极电压降的情况下分别对包含上述的3T1C像素电路的显示面板和包含本发明实施例中的4T1C像素电路的显示面板进行仿真，得到两个显示面板在不同的阴极电压降下的显示不均一性情况如图5所示。图5为包含不同的像素电路的显示面板的显示不均一性随阴极电压降的变化趋势图，其中，横坐标为阴极电压降，单位为伏特，纵坐标为不均一性，虚线代表包含3T1C像素电路的显示面板的显示不均一性随阴极电压降的变化趋势，实线代表包含本发明实施例中的4T1C像素电路的显示面板的显示不均一性随阴极电压降的变化趋势。显而易见的是，包含本发明实施例中的4T1C像素电路的显示面板在抗阴极电压降影响上十分有效，即使在阴极电压降达到3V的情况下，显示面板的显示画面仍可保持20%以内的不均一性。
本发明实施例还提供一种像素电路的驱动方法，该驱动方法用于驱动上述任一实施例中所述的像素电路，由于上述实施例已对像素电路进行了详细说明，因此此处不再赘述。该驱动方法至少包括复位阶段t1，在该像素电路处于复位阶段t1也即进行复位时，通过下拉单元102使第二节点S接入公共接地电压RD_Vss，以拉低第二节点S的电位。
本发明实施例提供的像素电路的驱动方法，在进行复位时通过下拉单元102拉低第二节点S的电位，提升了第二节点S的复位能力，从而使第二节点S能够在更短的时间段内降至目标电位，避免了由于第二节点S无法在规定的时间段内降至目标电位对驱动单元101的第一节点G与第二节点S之间电压Vgs的影响。若将该像素电路应用于AMOLED显示面板，由于每一像素电路的第二节点S均能复位为同一目标电位，因此每一像素电路的Vgs均相等，流经每一像素电路的发光单元103的电流均相等，每一像素电路的发光单元103的发光亮度均相等，从而提高了AMOLED显示面板的显示均一性。
作为一个优选的实施例，本发明实施例以第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4为N型薄膜晶体管为例对该像素电路的驱动方法进行说明。图6为本发明实施例提供的像素电路的驱动方法的流程图，如图6所示，像素电路的驱动方法包括复位阶段t1，在复位阶段t1中：
第一控制信号WR和第二控制信号RD提供低电平，下拉控制信号RD_V SS提供高电平，此时，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3关闭，第四薄膜晶体管T4打开。由于第四薄膜晶体管T4打开，因此可以使第二节点S接入公共接地电压，从而拉低第二节点S的电位，使第二节点S的电位由初始电位降至目标电位。
需要说明的是，在本发明实施例中，复位阶段t1的时长可以根据第四薄膜晶体管T4的尺寸和第二节点S的目标电位来调整。通常，对于同一尺寸的第四薄膜晶体管T4，复位阶段t1的时长越长，则第二节点S的电位由初始电位所复位得到的目标电位越低；对于不同尺寸的第四薄膜晶体管T4，第四薄膜晶体管T4的尺寸越大，则第二节点S的电位由初始电位复位到目标电位的时长越短。
可以理解地，由于在复位阶段t1中，有机发光二极管OLED处于非发光状态，因此此时相当于对显示画面进行了插黑处理，能够改善甚至消除显示画面的动态残像。
基于上述实施例，如图6所示，像素电路的驱动方法还包括写入阶段t2，在写入阶段t2中：
第一控制信号WR和第二控制信号RD提供高电平，下拉控制信号RD_V SS提供低电平，此时，第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3打开，第四薄膜晶体管T4关闭。第一薄膜晶体管T1的栅极接入数据线Date提供的数据信号，第一薄膜晶体管T1的源极接入感测线Monitor提供的初始化信号。
基于上述实施例，如图6所示，像素电路的驱动方法还包括发光阶段t3，在发光阶段t3中：
第一控制信号WR、第二控制信号RD和下拉控制信号RD_V SS提供低电平，第一薄膜晶体管T1打开，第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4关闭。第一薄膜晶体管T1驱动有机发光二极管OLED发光。
本发明实施例提供的像素电路的驱动方法，在复位阶段t1中通过使第四薄膜晶体管T4打开，从而使第二节点S接入公共接地电压，拉低了第二节点S的电位，提升了第二节点S的复位能力，使第二节点S能够在更短的时间段内降至目标电位，避免了由于第二节点S无法在规定的时间段内降至目标电位对第一薄膜晶体管T1的第一节点G与第二节点S之间电压Vgs的影响。若将该像素电路应用于AMOLED显示面板，由于每一像素电路的第二节点S均能复位为同一目标电位，因此每一像素电路的Vgs均相等，流经每一像素电路的有机发光二极管OLED的电流均相等，每一像素电路的有机发光二极管OLED的发光亮度均相等，从而提高了AMOLED显示面板的显示均一性。
基于上述实施例，复位阶段t1的时长可以根据第四薄膜晶体管T4的尺寸和第二节点S的目标电位来调整。对于同一尺寸的所述第四薄膜晶体管，所述复位阶段的时长与所述第二节点的初始电位与复位得到的所述目标电位之间电位差正相关，即，对于同一尺寸的第四薄膜晶体管T4，复位阶段t1的时长越长，则第二节点S的电位由初始电位所复位得到的目标电位越低。对于不同尺寸的所述第四薄膜晶体管，所述第四薄膜晶体管的尺寸与所述第二节点由初始电位复位到所述目标电位的时长负相关，即，对于不同尺寸的第四薄膜晶体管T4，第四薄膜晶体管T4的尺寸越大，则第二节点S的电位由初始电位复位到目标电位的时长越短。
本发明实施例还提供一种显示面板，该显示面板包括上述的像素电路。
具体地，显示面板优选为AMOLED显示面板。
图1为本发明实施例提供的像素电路的结构示意图，如图1所示，该像素电路包括：
驱动单元101、下拉单元102和发光单元103。其中：
驱动单元101的控制端电性连接第一节点G，驱动单元101的第一端接入工作电压V DD，驱动单元101的第二端电性连接第二节点S。
下拉单元102的控制端接入下拉控制信号RD_V SS，下拉单元102的第一端电性连接第二节点S，下拉单元102的第二端电性连接公共接地电压V SS。其中，下拉单元102用于在像素电路进行复位时使第二节点S接入公共接地电压V SS，以拉低第二节点S的电位。
发光单元103的第一端电性连接第二节点S，发光单元103的第二端电性连接公共接地电压V SS。
本发明实施例提供显示面板所包含的像素电路，在进行复位时通过下拉单元102拉低第二节点S的电位，提升了第二节点S的复位能力，从而使第二节点S能够在更短的时间段内降至目标电位，避免了由于第二节点S无法在规定的时间段内降至目标电位对驱动单元101的第一节点G与第二节点S之间电压Vgs的影响。由于显示面板中每一像素电路的第二节点S均能复位为同一目标电位，因此每一像素电路的Vgs均相等，流经每一像素电路的发光单元103的电流均相等，每一像素电路的发光单元103的发光亮度均相等，从而提高了显示面板的显示均一性。
基于上述实施例，如图1所示，该像素电路还包括写入单元104，写入单元104的控制端接入第一控制信号WR，写入单元104的第一端电性连接数据线Date，写入单元104的第二端电性连接第一节点G。
具体地，在像素电路进行写入时，数据线Date用于输出数据信号，写入单元104用于控制第一节点G接入该数据信号。
基于上述实施例，如图1所示，该像素电路还包括感测单元105，感测单元105的控制端接入第二控制信号RD，感测单元105的第一端电性连接第二节点S，感测单元的第二端电性连接感测线Monitor。
具体地，在像素电路进行写入时，感测线Monitor用于输出初始化信号，感测单元105用于控制第二节点S接入初始化信号。
基于上述实施例，如图1所示，该像素电路还包括存储单元106，存储单元106的第一端电性连接第一节点G，存储单元106的第二端电性连接第二节点S。
基于上述实施例，本发明实施例对像素电路的具体结构进行说明，图2为本发明实施例提供的像素电路的电路图，如图2所示，驱动单元101包括第一薄膜晶体管T1，写入单元104包括第二薄膜晶体管T2，感测单元105包括第三薄膜晶体管T3，下拉单元102包括第四薄膜晶体管T4，存储单元106包括存储电容Cst，发光单元103包括有机发光二极管OLED。其中：
第一薄膜晶体管T1的栅极电性连接第一节点G，第一薄膜晶体管T1的源极接入工作电压VDD，第一薄膜晶体管T1的漏极电性连接第二节点S；第二薄膜晶体管T2的栅极接入第一控制信号WR，第二薄膜晶体管T2的源极电性连接数据线Date，第二薄膜晶体管T2的漏极电性连接第一节点G；第三薄膜晶体管T3的栅极接入第二控制信号RD，第三薄膜晶体管T3的源极电性连接第二节点S，第三薄膜晶体管T3的漏极电性连接感测线Monitor；第四薄膜晶体管T4的栅极接入下拉控制信号RD_V SS，第四薄膜晶体管T4的源极电性连接第二节点S，第四薄膜晶体管T4的漏极电性连接公共接地电压V SS。存储电容Cst的第一端电性连接第一节点G，存储电容Cst的第二端电性连接第二节点S；有机发光二极管OLED的第一端电性连接第二节点S，有机发光二极管OLED的第二端电性连接公共接地电压Vss。
需要说明的是，本发明实施例中的薄膜晶体管包括栅极、源极和漏极，由于薄膜晶体管的源极和漏极是对称的，因此其源极和漏极是可以互换的。对于上述的每一薄膜晶体管，其控制端为栅极，其第一端和第二端分别为源极和漏极。需要说明的是，在其他实施例中，第一端和第二端分别为漏极和源极。
此外，本发明实施例中的薄膜晶体管可以包括P型和/或N型晶体管两种，其中，P型薄膜晶体管在栅极为低电位时打开，在栅极为高电位时关闭；N型薄膜晶体管在栅极为高电位时打开，在栅极为低电位时关闭。
基于上述实施例，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4为N型薄膜晶体管。
基于上述实施例，以第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4为N型薄膜晶体管为例对该像素电路的驱动时序进行说明。图3为本发明实施例提供的像素电路的驱动时序图，如图3所示，第一控制信号WR、第二控制信号RD和下拉控制信号RD_Vss共同作用于像素电路的复位阶段t1、写入阶段t2和发光阶段t3，以下对该像素电路的工作过程进行详细说明：
在复位阶段t1，第一控制信号WR和第二控制信号RD提供低电平，下拉控制信号RD_V SS提供高电平，此时，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3关闭，第四薄膜晶体管T4打开。由于第四薄膜晶体管T4打开，因此可以使第二节点S接入公共接地电压，从而拉低第二节点S的电位，使第二节点S的电位由初始电位降至目标电位。
需要说明的是，在本发明实施例中，复位阶段t1的时长可以根据第四薄膜晶体管T4的尺寸和第二节点S的目标电位来调整。对于同一尺寸的所述第四薄膜晶体管，所述复位阶段的时长与所述第二节点的初始电位与复位得到的所述目标电位之间电位差正相关，即，对于同一尺寸的第四薄膜晶体管T4，复位阶段t1的时长越长，则第二节点S的电位由初始电位所复位得到的目标电位越低。对于不同尺寸的所述第四薄膜晶体管，所述第四薄膜晶体管的尺寸与所述第二节点由初始电位复位到所述目标电位的时长负相关，即，对于不同尺寸的第四薄膜晶体管T4，第四薄膜晶体管T4的尺寸越大，则第二节点S的电位由初始电位复位到目标电位的时长越短。
可以理解地，由于在复位阶段t1中，有机发光二极管OLED处于非发光状态，因此此时相当于对显示画面进行了插黑处理，能够改善甚至消除显示画面的动态残像。
在写入阶段t2，第一控制信号WR和第二控制信号RD提供高电平，下拉控制信号RD_V SS提供低电平，此时，第一薄膜晶体管T1、第二薄膜晶体管T2和第三薄膜晶体管T3打开，第四薄膜晶体管T4关闭。第一薄膜晶体管T1的栅极接入数据线Date提供的数据信号，第一薄膜晶体管T1的源极接入感测线Monitor提供的初始化信号。
在发光阶段t3，第一控制信号WR、第二控制信号RD和下拉控制信号RD_V SS提供低电平，第一薄膜晶体管T1打开，第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4关闭。第一薄膜晶体管T1驱动有机发光二极管OLED发光。
本发明实施例提供的显示面板所包含的像素电路，在复位阶段t1中通过使第四薄膜晶体管T4打开，从而使第二节点S接入公共接地电压，拉低了第二节点S的电位，提升了第二节点S的复位能力，使第二节点S能够在更短的时间段内降至目标电位，避免了由于第二节点S无法在规定的时间段内降至目标电位对第一薄膜晶体管T1的第一节点G与第二节点S之间电压Vgs的影响。由于显示面板中每一像素电路的第二节点S均能复位为同一目标电位，因此每一像素电路的Vgs均相等，流经每一像素电路的有机发光二极管OLED的电流均相等，每一像素电路的有机发光二极管OLED的发光亮度均相等，从而提高了显示面板的显示均一性。
可以理解的是，对本领域普通技术人员来说，可以根据本发明的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本发明所附的权利要求的保护范围。

Claims (20)

  1. 一种像素电路，其中，所述像素电路包括：
    驱动单元、下拉单元和发光单元；其中，
    所述驱动单元的控制端电性连接第一节点，所述驱动单元的第一端接入工作电压，所述驱动端单元的第二端电性连接第二节点；
    所述下拉单元的控制端接入下拉控制信号，所述下拉单元的第一端电性连接所述第二节点，所述下拉单元的第二端电性连接公共接地电压；所述下拉单元用于在所述像素电路进行复位时使所述第二节点接入所述公共接地电压，以拉低所述第二节点的电位；
    所述发光单元的第一端电性连接所述第二节点，所述发光单元的第二端电性连接所述公共接地电压。
  2. 如权利要求1所述的像素电路，其中，所述像素电路还包括写入单元，所述写入单元的控制端接入第一控制信号，所述写入单元的第一端电性连接数据线，所述写入单元的第二端电性连接所述第一节点。
  3. 如权利要求2所述的像素电路，其中，所述像素电路还包括感测单元，所述感测单元的控制端接入第二控制信号，所述感测单元的第一端电性连接所述第二节点，所述感测单元的第二端电性连接感测线。
  4. 如权利要求3所述的像素电路，其中，所述像素电路还包括存储单元，所述存储单元的第一端电性连接所述第一节点，所述存储单元的第二端电性连接所述第二节点。
  5. 如权利要求4所述的像素电路，其中，所述驱动单元包括第一薄膜晶体管，所述写入单元包括第二薄膜晶体管，所述感测单元包括第三薄膜晶体管，所述下拉单元包括第四薄膜晶体管，所述存储单元包括存储电容，所述发光单元包括有机发光二极管；其中，
    所述第一薄膜晶体管的栅极电性连接所述第一节点，所述第一薄膜晶体管的源极接入所述工作电压，所述第一薄膜晶体管的漏极电性连接所述第二节点；
    所述第二薄膜晶体管的栅极接入所述第一控制信号，所述第二薄膜晶体管的源极电性连接所述数据线，所第二薄膜晶体管的漏极电性连接所述第一节点；
    所述第三薄膜晶体管的栅极接入所述第二控制信号，所述第三薄膜晶体管的源极电性连接所述第二节点，所述第三薄膜晶体管的漏极电性连接所述感测线；
    所述第四薄膜晶体管的栅极接入所述下拉控制信号，所述第四薄膜晶体管的源极电性连接所述第二节点，所述第四薄膜晶体管的漏极电性连接所述公共接地电压；
    所述存储电容的第一端电性连接所述第一节点，所述存储电容的第二端电性连接所述第二节点；
    所述有机发光二极管的第一端电性连接所述第二节点，所述有机发光二极管的第二端电性连接所述公共接地电压。
  6. 如权利要求5所述的像素电路，其中，所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管和所述第四薄膜晶体管为N型薄膜晶体管。
  7. 如权利要求6所述的像素电路，其中，所述像素电路包括复位阶段，在所述复位阶段中，所述第一控制信号和所述第二控制信号提供低电平，所述下拉控制信号提供高电平。
  8. 如权利要求7所述的像素电路，其中，所述像素电路还包括写入阶段，在所述写入阶段中，所述第一控制信号和所述第二控制信号提供高电平，所述下拉控制信号提供低电平。
  9. 如权利要求8所述的像素电路，其中，所述像素电路还包括发光阶段，在所述发光阶段中，所述第一控制信号、所述第二控制信号和所述下拉控制信号提供低电平。
  10. 一种像素电路的驱动方法，用于驱动权利要求6所述的像素电路，其中，所述像素电路的驱动方法包括复位阶段，在所述复位阶段中：
    所述第一控制信号和所述第二控制信号提供低电平，所述下拉控制信号提供高电平，以使所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管关闭，所述第四薄膜晶体管打开。
  11. 根据权利要求10所述的像素电路的驱动方法，其中，所述像素电路的驱动方法还包括写入阶段，在所述写入阶段中：
    所述第一控制信号和所述第二控制信号提供高电平，所述下拉控制信号提供低电平，以使所述第一薄膜晶体管、所述第二薄膜晶体管和所述第三薄膜晶体管打开，所述第四薄膜晶体管关闭。
  12. 根据权利要求11所述的像素电路的驱动方法，其中，所述像素电路的驱动方法还包括发光阶段，在所述发光阶段中：
    所述第一控制信号、所述第二控制信号和所述下拉控制信号提供低电平，以使所述第一薄膜晶体管打开，所述第二薄膜晶体管、所述第三薄膜晶体管和所述第四薄膜晶体管关闭。
  13. 根据权利要求10所述的像素电路的驱动方法，其中，复位阶段的时长根据所述第四薄膜晶体管的尺寸和所述第二节点的目标电位进行调整。
  14. 根据权利要求13所述的像素电路的驱动方法，其中，对于同一尺寸的所述第四薄膜晶体管，所述复位阶段的时长与所述第二节点的初始电位与复位得到的所述目标电位之间电位差正相关。
  15. 根据权利要求13所述的像素电路的驱动方法，其中，对于不同尺寸的所述第四薄膜晶体管，所述第四薄膜晶体管的尺寸与所述第二节点由初始电位复位到所述目标电位的时长负相关。
  16. 一种显示面板，其中，所述显示面板包括像素电路，所述像素电路包括：
    驱动单元、下拉单元和发光单元；其中，
    所述驱动单元的控制端电性连接第一节点，所述驱动单元的第一端接入工作电压，所述驱动端单元的第二端电性连接第二节点；
    所述下拉单元的控制端接入下拉控制信号，所述下拉单元的第一端电性连接所述第二节点，所述下拉单元的第二端电性连接公共接地电压；所述下拉单元用于在所述像素电路进行复位时使所述第二节点接入所述公共接地电压，以拉低所述第二节点的电位；
    所述发光单元的第一端电性连接所述第二节点，所述发光单元的第二端电性连接所述公共接地电压。
  17. 根据权利要求16所述的显示面板，其中，所述像素电路还包括写入单元，所述写入单元的控制端接入第一控制信号，所述写入单元的第一端电性连接数据线，所述写入单元的第二端电性连接所述第一节点。
  18. 根据权利要求17所述的显示面板，其中，所述像素电路还包括感测单元，所述感测单元的控制端接入第二控制信号，所述感测单元的第一端电性连接所述第二节点，所述感测单元的第二端电性连接感测线。
  19. 根据权利要求18所述的显示面板，其中，所述像素电路还包括存储单元，所述存储单元的第一端电性连接所述第一节点，所述存储单元的第二端电性连接所述第二节点。
  20. 根据权利要求19所述的显示面板，其中，所述驱动单元包括第一薄膜晶体管，所述写入单元包括第二薄膜晶体管，所述感测单元包括第三薄膜晶体管，所述下拉单元包括第四薄膜晶体管，所述存储单元包括存储电容，所述发光单元包括有机发光二极管；其中，
    所述第一薄膜晶体管的栅极电性连接所述第一节点，所述第一薄膜晶体管的源极接入所述工作电压，所述第一薄膜晶体管的漏极电性连接所述第二节点；
    所述第二薄膜晶体管的栅极接入所述第一控制信号，所述第二薄膜晶体管的源极电性连接所述数据线，所第二薄膜晶体管的漏极电性连接所述第一节点；
    所述第三薄膜晶体管的栅极接入所述第二控制信号，所述第三薄膜晶体管的源极电性连接所述第二节点，所述第三薄膜晶体管的漏极电性连接所述感测线；
    所述第四薄膜晶体管的栅极接入所述下拉控制信号，所述第四薄膜晶体管的源极电性连接所述第二节点，所述第四薄膜晶体管的漏极电性连接所述公共接地电压；
    所述存储电容的第一端电性连接所述第一节点，所述存储电容的第二端电性连接所述第二节点；
    所述有机发光二极管的第一端电性连接所述第二节点，所述有机发光二极管的第二端电性连接所述公共接地电压。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104424893A (zh) * 2013-08-30 2015-03-18 乐金显示有限公司 有机发光显示设备
CN105913802A (zh) * 2016-06-30 2016-08-31 上海天马有机发光显示技术有限公司 一种有机电致发光二极管显示面板及其驱动方法
CN106910463A (zh) * 2017-04-28 2017-06-30 深圳市华星光电技术有限公司 一种amoled驱动电路及显示装置
CN110235193A (zh) * 2019-04-30 2019-09-13 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置及其驱动方法
CN110517641A (zh) * 2019-08-30 2019-11-29 京东方科技集团股份有限公司 像素电路、参数检测方法、显示面板和显示装置
CN111179851A (zh) * 2020-02-25 2020-05-19 合肥鑫晟光电科技有限公司 像素电路及其驱动方法、和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106782310B (zh) * 2017-03-01 2019-09-03 上海天马有机发光显示技术有限公司 一种像素电路、驱动方法、显示面板以及显示装置
CN108877669A (zh) * 2017-05-16 2018-11-23 京东方科技集团股份有限公司 一种像素电路、驱动方法及显示装置
CN108564920B (zh) * 2018-04-26 2019-11-05 上海天马有机发光显示技术有限公司 一种像素电路及显示装置
CN108877611B (zh) * 2018-07-16 2019-12-17 深圳市华星光电半导体显示技术有限公司 像素驱动电路感测方法及像素驱动电路
CN110444163B (zh) * 2019-08-15 2021-05-04 京东方科技集团股份有限公司 像素电路、显示面板和显示设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104424893A (zh) * 2013-08-30 2015-03-18 乐金显示有限公司 有机发光显示设备
CN105913802A (zh) * 2016-06-30 2016-08-31 上海天马有机发光显示技术有限公司 一种有机电致发光二极管显示面板及其驱动方法
CN106910463A (zh) * 2017-04-28 2017-06-30 深圳市华星光电技术有限公司 一种amoled驱动电路及显示装置
CN110235193A (zh) * 2019-04-30 2019-09-13 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置及其驱动方法
CN110517641A (zh) * 2019-08-30 2019-11-29 京东方科技集团股份有限公司 像素电路、参数检测方法、显示面板和显示装置
CN111179851A (zh) * 2020-02-25 2020-05-19 合肥鑫晟光电科技有限公司 像素电路及其驱动方法、和显示装置

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