WO2022111360A1 - 芯片供电电路与电子设备 - Google Patents

芯片供电电路与电子设备 Download PDF

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Publication number
WO2022111360A1
WO2022111360A1 PCT/CN2021/131287 CN2021131287W WO2022111360A1 WO 2022111360 A1 WO2022111360 A1 WO 2022111360A1 CN 2021131287 W CN2021131287 W CN 2021131287W WO 2022111360 A1 WO2022111360 A1 WO 2022111360A1
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Prior art keywords
power supply
chip
circuit
voltage
domain
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PCT/CN2021/131287
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English (en)
French (fr)
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王利军
吴飞
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北京比特大陆科技有限公司
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Application filed by 北京比特大陆科技有限公司 filed Critical 北京比特大陆科技有限公司
Priority to EP21896861.8A priority Critical patent/EP4254132A4/en
Publication of WO2022111360A1 publication Critical patent/WO2022111360A1/zh
Priority to US18/201,746 priority patent/US20230297150A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

  • the present application relates to the technical field of power supply, and in particular, to a chip power supply circuit and an electronic device.
  • the power consumption of data-generating devices that require a huge computational workload is quite high, and their power supply technology needs to be improved.
  • the power supply mode of chips in series can be adopted on the printed circuit board, and a multi-level series voltage domain is formed between the power input terminal and the ground port.
  • the number of stages formed by the chip is particularly large, since the auxiliary power supply port of each stage of the chip needs to consume current, and the top-level chip needs a higher voltage, the current of the lower-level chip will gradually increase and each stage will be The voltages of different chips are inconsistent, and the performance of chips at different levels is different, which reduces the working performance of the data generating device.
  • the present application provides a chip power supply circuit and electronic equipment, which can improve the balance of chips at all levels and optimize working performance.
  • the present application provides a chip power supply circuit, and the method includes:
  • the at least two chip domains are connected in sequence, and in two adjacent chip domains, the ground port of the chip domain of the upper level is connected to the main power supply port of the chip domain of the next level;
  • At least one voltage conversion circuit in two adjacent chip domains, the ground port of the chip domain of the previous stage is connected to the auxiliary power supply port of the chip domain of the next stage through one of the voltage conversion circuits, and the voltage conversion circuit uses for outputting the target voltage to the auxiliary power supply port.
  • each of the chip domains includes a first number of chips, and the first number is at least one;
  • the ground ports of the chips in the chip domain of the previous level are respectively connected to the main power supply ports of the chips in the chip domain of the next level one by one;
  • the ground ports of the chips in the chip domain of the previous stage are all connected to the input end of the voltage conversion circuit, and the auxiliary power supply ports of the chips in the chip domain of the next stage are all connected to the input end of the voltage conversion circuit.
  • the output terminal of the voltage conversion circuit is connected.
  • the main power supply ports of the chips in the uppermost chip domain are all connected to the power supply, and the ground ports of the chips in the lowermost chip domain are all grounded.
  • the auxiliary power supply port includes a first power supply pin and a second power supply pin, and the voltage conversion circuit is configured to output a first voltage to the first power supply pin and output a second voltage to the the second power supply pin.
  • the voltage conversion circuit includes a first transformer circuit and a second transformer circuit
  • the input end of the first transformer circuit is connected to the ground port of the chip domain of the upper stage, and the output end of the first transformer circuit is connected to the first power supply pin, and is the first The power supply pin provides the first voltage;
  • the input end of the second transformer circuit is connected to the output end of the first transformer circuit, and the output end of the second transformer circuit is connected to the second power supply pin of the chip domain of the next stage, and provide a second voltage to the second power supply pin.
  • the first transformer circuit is a boost circuit
  • the second transformer circuit is a buck circuit
  • the first power supply pin is an I/O unit
  • the second power supply pin is a PLL unit.
  • the first voltage is greater than the second voltage.
  • the present application provides an electronic device including the chip power supply circuit according to any of the above embodiments.
  • the electronic device is a data generating device.
  • the present application discloses a chip power supply circuit and an electronic device
  • the chip power supply circuit includes: at least two chip domains, the at least two chip domains are connected in sequence, and in the two adjacent chip domains, the chip of the upper level is The ground port of the domain is connected to the main power supply port of the chip domain of the next stage; at least one voltage conversion circuit, in two adjacent chip domains, the ground port of the chip domain of the previous stage passes through one of the voltage conversion circuits and the The auxiliary power supply port of the next-level chip domain is connected, and the voltage conversion circuit is used for outputting the target voltage to the auxiliary power supply port.
  • the auxiliary power supply port of each chip domain can obtain power from the power supply domain where the chip domain itself is located, which can improve the performance of each chip domain.
  • the voltage balance is optimized, and the working performance and computing performance of the chip domain are optimized.
  • FIG. 1 is a schematic block diagram of a chip power supply circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic block diagram of another chip power supply circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic block diagram of another chip power supply circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic block diagram of another chip power supply circuit according to an embodiment of the present application.
  • FIG. 1 is a schematic block diagram of a chip power supply circuit provided by an embodiment of the present application. As shown in FIG. 1 , the chip power supply circuit includes at least two chip domains 10 and at least one voltage conversion circuit 20 .
  • At least two chip domains 10 are connected in sequence.
  • the ground port 11 of the chip domain 10 of the upper level is connected to the main power supply port 12 of the chip domain 10 of the next level;
  • the ground port 11 of the chip domain 10 of the previous stage is connected to the auxiliary power supply port 13 of the chip domain 10 of the next stage through a voltage conversion circuit 20, and the voltage conversion circuit 20 is used to output the target voltage to the auxiliary power supply port. 13.
  • each chip domain is provided with a ground port, a main power supply port and an auxiliary power supply port.
  • the main power supply port is used to provide the main power for the chip domain.
  • the main power supply port is generally connected to the power supply, and the function of the auxiliary power supply port is related to the The chip domain provides auxiliary power.
  • Multiple chip domains are connected in sequence, the main power supply port of the top-level chip domain is connected to the power supply, the ground port of the upper-level chip domain and the main power supply port of the next-level chip domain, so that the upper-level chip is The chip domain of the next level provides the main power, the ground port of the chip domain of the lowest level is grounded, and the multiple chip domains form a series power supply.
  • Power can be taken from inside the chip domain to provide power to the auxiliary power supply port, and the voltage on the series power supply circuit is converted into the target voltage required by the auxiliary power supply port through the voltage conversion circuit.
  • the ground port of the chip domain of the previous stage is connected to the auxiliary power supply port of the chip domain of the next stage through a voltage conversion circuit, so that the auxiliary power supply port of the chip domain of the next stage is directly
  • the power is obtained from the power domain where the chip domain itself is located, so that the balance of the series-supplied power domain can be increased, and at the same time, when the printed circuit board is laid out, the wiring, the area and the cost can be reduced.
  • the chip power supply circuit includes a plurality of chip domains 10 , and a voltage conversion circuit 20 is set in every two adjacent chip domains 10 . Therefore, the number of the voltage conversion circuits 20 corresponds to the number of the chip domains 10 .
  • the number of conversion circuits 20 may be the number of chip domains 10 minus one.
  • the auxiliary power supply port of each chip domain can obtain power from the power supply domain where the chip domain itself is located, which can improve the performance of each chip domain.
  • the voltage balance is optimized, and the working performance and computing performance of the chip domain are optimized.
  • each of the chip domains 10 includes a first number of chips, and the first number is at least one; in two adjacent chip domains 10 , the ground ports 11 of the chips in the chip domain 10 of the upper level are respectively and The main power supply ports 12 of the chips in the chip domain 10 of the next level are connected one by one; in two adjacent chip domains 10 , the ground ports 11 of the chips in the chip domain 10 of the previous level are all connected to the voltage conversion circuit 20 The input terminal of the voltage conversion circuit 20 is connected, and the auxiliary power supply port 13 of the chip in the next-level chip domain 10 is connected to the output terminal of the voltage conversion circuit 20 .
  • each chip domain includes the first number of chips, so when the series power supply connection is performed, the chips in the upper-level chip domain can be connected to the chips in the next-level chip domain one by one, and the chip power supply circuit including a first number of chip series circuits.
  • Each chip is provided with a ground port, a main power supply port and an auxiliary power supply port, and each chip domain also includes a first number of ground ports, a first number of main power supply ports and a first number of auxiliary power supply ports.
  • the ground ports 11 of each chip in the chip domain 10 of the upper stage are respectively connected to the main power supply ports 12 of the chips in the chip domain 10 of the next stage one by one.
  • the ground ports 11 of the chips in the chip domain 10 of the previous stage are connected to the input end of the voltage conversion circuit 20 , and the auxiliary power supply of the chips in the chip domain 10 of the next stage is connected
  • the ports 13 are all connected to the output terminals of the voltage conversion circuit 20 .
  • the voltage conversion circuit obtains electrical energy from the chip domain of the upper stage, and converts it into a target voltage, so as to provide the target voltage for the auxiliary power supply ports of all chips in the chip domain of the next stage.
  • the main power supply ports of the chips in the uppermost chip domain are all connected to the power supply, and the ground ports of the chips in the lowermost chip domain are all grounded.
  • each chip domain multiple chips in each chip domain are connected in parallel, the main power supply ports of all chips in the uppermost chip domain are connected to the power supply, and the power supply provides the main power for the series circuit of the first number of chips, and the most The ground ports of all chips in the subordinate chip domain are grounded.
  • the auxiliary power supply port 13 includes a first power supply pin 131 and a second power supply pin 132 , the voltage conversion circuit 20 is configured to output the first voltage to the first power supply pin 131 , and The second voltage is output to the second power supply pin 132 .
  • Each chip is provided with a first power supply pin and a second power supply pin.
  • the first power supply pin and the second power supply pin need to obtain auxiliary power of different voltages and supply power to the chip with different voltages.
  • the voltage conversion circuit can output the first voltage to provide the first voltage to the first power supply pin of the chip.
  • the voltage conversion circuit can also output the second voltage to provide the second voltage to the second power supply pin of the chip.
  • the voltage conversion circuit 20 includes a first transformer circuit 21 and a second transformer circuit 22 ; the input terminal of the first transformer circuit 21 and the ground of the chip domain 10 of the previous stage The port 11 is connected, the output end of the first transformer circuit 21 is connected to the first power supply pin 131, and provides the first voltage for the first power supply pin 131; the input end of the second transformer circuit 22 is connected to the first transformer circuit 21 is connected to the output end, and the output end of the second transformer circuit 22 is connected to the second power supply pin 132 of the chip domain 10 of the next stage, and provides the second power supply pin 132 with a second voltage.
  • the voltage provided by the power supply that is, the voltage on the main power supply port of the chip domain, is different from the voltage values of the first voltage and the second voltage. Therefore, two transformer circuits can be used to convert the voltage on the main power supply port. Converted to a first voltage and a second voltage.
  • the first transformer circuit may be a boost circuit
  • the second transformer circuit may be a step-down circuit.
  • the voltage provided by the power supply is generally lower than the first voltage, and the second voltage is lower than the first voltage. Therefore, the voltage on the main power supply port can be boosted through the first transformer circuit to obtain the first voltage.
  • the output end of the transformer circuit is connected to the first power supply pin to provide the first voltage to the first power supply pin of the chip, and the input end of the second transformer circuit is connected to the output end of the first transformer circuit, so that the second The transformer circuit can step down the first voltage to the second voltage, and provide the second voltage for the second power supply pin of the chip.
  • the first transformer circuit is a boost circuit
  • the second transformer circuit is a buck circuit.
  • the boost circuit is a switching DC boost circuit, which can make the output voltage higher than the input voltage.
  • a buck circuit is a step-down circuit. Through the combination of the boost circuit and the buck circuit, it is possible to output two voltages and supply power to the first power supply pin and the second power supply pin of the chip.
  • the first power supply pin is an I/O unit
  • the second power supply pin is a PLL unit.
  • the voltage requirement of the I/O (Input/Output, input/output) unit is the first voltage, optionally, the first voltage may be 1.8 volts, and the voltage requirement of the PLL (PhaseLockedLoop, phase locked loop) unit is the second voltage voltage, optionally, the second voltage is 0.8 volts.
  • An embodiment of the present application further provides an electronic device, where the electronic device includes the chip power supply circuit according to any of the foregoing embodiments.
  • the electronic device may include a plurality of chip power supply circuits.
  • the electronic device is a data generating device.

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  • General Engineering & Computer Science (AREA)
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Abstract

一种芯片供电电路与电子设备，涉及电源供电技术领域，所述芯片供电电路包括：至少两个芯片域（10），所述至少两个芯片域（10）依次连接，两个相邻的芯片域（10）中，上一级的芯片域的接地端口（11）和下一级的芯片域的主供电端口（12）连接；至少一个电压转换电路（20），在两个相邻的芯片域（10）中，上一级的芯片域的接地端口（11）通过一个所述电压转换电路（20）和下一级芯片域的辅供电端口（13）连接，所述电压转换电路（20）用于输出目标电压给所述辅供电端口（13）。可以提高各级芯片的平衡性，优化工作性能。

Description

芯片供电电路与电子设备
本申请要求于2020年11月25日提交中国专利局、申请号为202011346368.5、发明名称为“芯片供电电路与电子设备”的中国优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电源供电技术领域，尤其涉及一种芯片供电电路与电子设备。
背景技术
需要进行巨大的运算工作量的数据生成设备的功耗相当高，需要改进其供电技术。为了最大化电源的转换效率，可以在印刷电路板上采取芯片串联的供电方式，在电源输入端和接地端口之间形成多级串联的电压域。但是当芯片形成的级数特别多的时候，由于每一级芯片的辅供电端口都需要消耗电流，且最上级的芯片需要更高的电压，如此会使下级的芯片电流逐渐增加且每一级的芯片的电压不一致，不同级的芯片性能出现差异，降低数据生成设备的工作性能。
发明内容
本申请提供了一种芯片供电电路与电子设备，可以提高各级芯片的平衡性，优化工作性能。
第一方面，本申请提供了一种芯片供电电路，所述方法包括：
至少两个芯片域，所述至少两个芯片域依次连接，两个相邻的芯片域中，上一级的芯片域的接地端口和下一级的芯片域的主供电端口连接；
至少一个电压转换电路，在两个相邻的芯片域中，上一级的芯片域的接地端口通过一个所述电压转换电路和下一级芯片域的辅供电 端口连接，所述电压转换电路用于输出目标电压给所述辅供电端口。
在一个实施例中，所述芯片域均包括第一数量的芯片，所述第一数量为至少一个；
两个相邻的芯片域中，上一级的芯片域中的芯片的接地端口分别和下一级的芯片域中的芯片的主供电端口一一连接；
在两个相邻的芯片域中，上一级的芯片域中的芯片的接地端口均与所述电压转换电路的输入端连接，以及下一级芯片域中的芯片的辅供电端口均与所述电压转换电路的输出端连接。
在一个实施例中，最上级的芯片域中的芯片的主供电端口均与供电电源连接，最下级的芯片域中的芯片的接地端口均接地。
在一个实施例中，所述辅供电端口包括第一供电管脚和第二供电管脚，所述电压转换电路用于输出第一电压给所述第一供电管脚，以及输出第二电压给所述第二供电管脚。
在一个实施例中，所述电压转换电路包括第一变压电路和第二变压电路；
所述第一变压电路的输入端和所述上一级的芯片域的接地端口连接，所述第一变压电路的输出端和所述第一供电管脚连接，并为所述第一供电管脚提供第一电压；
所述第二变压电路的输入端和所述第一变压电路的输出端连接，所述第二变压电路的输出端和所述下一级的芯片域的第二供电管脚连接，并为所述第二供电管脚提供第二电压。
在一个实施例中，所述第一变压电路为boost电路，所述第二变压电路为buck电路。
在一个实施例中，所述第一供电管脚为I/O单元，所述第二供电管脚为PLL单元。
在一个实施例中，所述第一电压大于所述第二电压。
第二方面，本申请提供了一种电子设备，所述电子设备包括如上述任一实施例的芯片供电电路。
在一个实施例中，所述电子设备为数据生成设备。
本申请公开了一种芯片供电电路与电子设备，所述芯片供电电路 包括：至少两个芯片域，所述至少两个芯片域依次连接，两个相邻的芯片域中，上一级的芯片域的接地端口和下一级的芯片域的主供电端口连接；至少一个电压转换电路，在两个相邻的芯片域中，上一级的芯片域的接地端口通过一个所述电压转换电路和下一级芯片域的辅供电端口连接，所述电压转换电路用于输出目标电压给所述辅供电端口。本申请实施例提供的芯片供电电路通过在两个相邻的芯片域中设置电压转换电路，可以使每个芯片域的辅供电端口从芯片域自身所在的电源域获取电能，可以提高各个芯片域的电压的平衡性，优化芯片域的工作性能和算力性能。
附图说明
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种芯片供电电路的模块示意图；
图2为本申请实施例提供的另一种芯片供电电路的模块示意图；
图3为本申请实施例提供的另一种芯片供电电路的模块示意图；
图4为本申请实施例提供的另一种芯片供电电路的模块示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解，在此本申请说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本申请。如在本申请说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
还应当进一步理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
图1为本申请实施例提供的一种芯片供电电路的模块示意图，如图1所示，芯片供电电路包括至少两个芯片域10和至少一个电压转换电路20。
至少两个芯片域10依次连接，两个相邻的芯片域10中，上一级的芯片域10的接地端口11和下一级的芯片域10的主供电端口12连接；在两个相邻的芯片域10中，上一级的芯片域10的接地端口11通过一个电压转换电路20和下一级芯片域10的辅供电端口13连接，电压转换电路20用于输出目标电压给辅供电端口13。
其中，每个芯片域均设置有接地端口、主供电端口和辅供电端口，主供电端口用于为芯片域提供主要的电能，主供电端口一般是和供电电源连接，辅供电端口哟功能与为芯片域提供辅助的电能。多个芯片域依次连接，最上级的芯片域的主供电端口和供电电源连接，上一级的芯片域的接地端口和下一级的芯片域的主供电端口，以使上一级的芯片为下一级的芯片域提供主要的电能，最下级的芯片域的接地端口接地，多个芯片域形成串联供电。
可以从芯片域内部进行取电以为辅供电端口提供电能，通过电压转换电路将串联供电电路上的电压转换为辅供电端口所需要的目标电压。通过在两个相邻的芯片域中，将上一级的芯片域的接地端口通过一个电压转换电路和下一级芯片域的辅供电端口连接，使下一级的芯片域的辅供电端口直接从该芯片域自身所在的电源域获取电能，如此可以增加串联供电的电源域的平衡性，同时在印刷电路板布局时，可以减少走线、减小面积以及降低成本。
如图2所示，芯片供电电路包括多个芯片域10，每两个相邻的芯片域10中设置一个电压转换电路20，因此电压转换电路20的数量跟芯片域10的数量相对应，电压转换电路20的数量可以是芯片域10的数量减一。
本申请实施例提供的芯片供电电路通过在两个相邻的芯片域中 设置电压转换电路，可以使每个芯片域的辅供电端口从芯片域自身所在的电源域获取电能，可以提高各个芯片域的电压的平衡性，优化芯片域的工作性能和算力性能。
在一个实施例中，芯片域10均包括第一数量的芯片，第一数量为至少一个；两个相邻的芯片域10中，上一级的芯片域10中的芯片的接地端口11分别和下一级的芯片域10中的芯片的主供电端口12一一连接；在两个相邻的芯片域10中，上一级的芯片域10中的芯片的接地端口11均与电压转换电路20的输入端连接，以及下一级芯片域10中的芯片的辅供电端口13均与电压转换电路20的输出端连接。
其中，每个芯片域都包括第一数量的芯片，因此在进行串联供电连接时，上一级的芯片域中的芯片均可以一一与下一级的芯片域中的芯片连接，芯片供电电路中包括第一数量的芯片串联电路。每个芯片设置有接地端口、主供电端口和辅供电端口，每个芯片域中也包括第一数量的接地端口、第一数量的主供电端口和第一数量的辅供电端口。
如图3所示，上一级的芯片域10中的每个芯片的接地端口11分别和下一级的芯片域10中的芯片的主供电端口12一一连接。在每两个相邻的芯片域10中，上一级的芯片域10中的芯片的接地端口11均与电压转换电路20的输入端连接，以及下一级芯片域10中的芯片的辅供电端口13均与电压转换电路20的输出端连接。电压转换电路从上一级的芯片域中获得电能，并转换为目标电压，为下一级的芯片域中的所有芯片的辅供电端口提供目标电压。
在一个实施例中，最上级的芯片域中的芯片的主供电端口均与供电电源连接，最下级的芯片域中的芯片的接地端口均接地。
其中，每个芯片域中的多个芯片之间并联，最上级的芯片域中的所有芯片的主供电端口均与供电电源连接，供电电源为第一数量的芯片串联电路提供主要的电能，最下级的芯片域中的所有芯片的接地端口均接地。
在一个实施例中，如图4所示，辅供电端口13包括第一供电管脚131和第二供电管脚132，电压转换电路20用于输出第一电压给第一供电管脚131，以及输出第二电压给第二供电管脚132。
每个芯片上均设置有第一供电管脚和第二供电管脚，第一供电管脚和第二供电管脚需要获取不同电压的辅助电能，并为芯片内部进行不同电压的供电。
电压转换电路可以输出第一电压，以向芯片的第一供电管脚提供第一电压。电压转换电路还可以输出第二电压，向芯片的第二供电管脚提供第二电压。
在一个实施例中，如图4所示，电压转换电路20包括第一变压电路21和第二变压电路22；第一变压电路21的输入端和上一级的芯片域10的接地端口11连接，第一变压电路21的输出端和第一供电管脚131连接，并为第一供电管脚131提供第一电压；第二变压电路22的输入端和第一变压电路21的输出端连接，第二变压电路22的输出端和下一级的芯片域10的第二供电管脚132连接，并为第二供电管脚132提供第二电压。
其中，供电电源提供的电压，即芯片域的主供电端口上的电压，和第一电压以及第二电压的电压值均不相同，因此可以采用两个变压电路实现将主供电端口上的电压转换为第一电压和第二电压。
可选地，第一变压电路可以是升压电路，第二变压电路可以是降压电路。供电电源提供的电压一般是低于第一电压，第二电压低于第一电压，因此可以先将主供电端口上的电压通过第一变压电路升进行升压，得到第一电压，第一变压电路的输出端和第一供电管脚连接，以为芯片的第一供电管脚提供第一电压，同时第二变压电路的输入端和第一变压电路的输出端连接，以便第二变压电路可以将第一电压降压为第二电压，并为芯片的第二供电管脚提供第二电压。在一个实施例中，第一变压电路为boost电路，第二变压电路为buck电路。
其中，boost电路是一种开关直流升压电路，它可以使输出电压比输入电压高。buck电路是一种降压电路。通过boost电路和buck电路的组合，可以实现输出两种电压，并为芯片的第一供电管脚和第二供电管脚进行供电。
在一个实施例中，第一供电管脚为I/O单元，第二供电管脚为PLL单元。
其中，I/O(Input/Output,输入/输出)单元的电压需求为第一电压，可选地，第一电压可以是1.8伏，PLL(PhaseLockedLoop,锁相环)单元的电压需求为第二电压，可选地，第二电压为0.8伏。
本申请实施例还提供一种电子设备，所述电子设备包括如上述任一实施例的芯片供电电路。其中，电子设备中可以是包括多个芯片供电电路。
在一个实施例中，所述电子设备为数据生成设备。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种芯片供电电路，其特征在于，包括：
    至少两个芯片域，所述至少两个芯片域依次连接，两个相邻的芯片域中，上一级的芯片域的接地端口和下一级的芯片域的主供电端口连接；
    至少一个电压转换电路，在两个相邻的芯片域中，上一级的芯片域的接地端口通过一个所述电压转换电路和下一级芯片域的辅供电端口连接，所述电压转换电路用于输出目标电压给所述辅供电端口。
  2. 根据权利要求1所述的芯片供电电路，其特征在于，所述芯片域均包括第一数量的芯片，所述第一数量为至少一个；
    两个相邻的芯片域中，上一级的芯片域中的芯片的接地端口分别和下一级的芯片域中的芯片的主供电端口一一连接；
    在两个相邻的芯片域中，上一级的芯片域中的芯片的接地端口均与所述电压转换电路的输入端连接，以及下一级芯片域中的芯片的辅供电端口均与所述电压转换电路的输出端连接。
  3. 根据权利要求2所述的芯片供电电路，其特征在于，最上级的芯片域中的芯片的主供电端口均与供电电源连接，最下级的芯片域中的芯片的接地端口均接地。
  4. 根据权利要求1所述的芯片供电电路，其特征在于，所述辅供电端口包括第一供电管脚和第二供电管脚，所述电压转换电路用于输出第一电压给所述第一供电管脚，以及输出第二电压给所述第二供电管脚。
  5. 根据权利要求4所述的芯片供电电路，其特征在于，所述电压转换电路包括第一变压电路和第二变压电路；
    所述第一变压电路的输入端和所述上一级的芯片域的接地端口连接，所述第一变压电路的输出端和所述第一供电管脚连接，并为所述第一供电管脚提供第一电压；
    所述第二变压电路的输入端和所述第一变压电路的输出端连接，所述第二变压电路的输出端和所述下一级的芯片域的第二供电管脚 连接，并为所述第二供电管脚提供第二电压。
  6. 根据权利要求5所述的芯片供电电路，其特征在于，所述第一变压电路为boost电路，所述第二变压电路为buck电路。
  7. 根据权利要求4所述的芯片供电电路，其特征在于，所述第一供电管脚为I/O单元，所述第二供电管脚为PLL单元。
  8. 根据权利要求4至7任一项所述的芯片供电电路，其特征在于，所述第一电压大于所述第二电压。
  9. 一种电子设备，其特征在于，所述电子设备包括如权利要求1至8任一项所述的芯片供电电路。
  10. 根据权利要求9所述的电子设备，其特征在于，所述电子设备为数据生成设备。
PCT/CN2021/131287 2020-11-25 2021-11-17 芯片供电电路与电子设备 WO2022111360A1 (zh)

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