WO2019119965A1 - 串联供电电路、系统和方法 - Google Patents

串联供电电路、系统和方法 Download PDF

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Publication number
WO2019119965A1
WO2019119965A1 PCT/CN2018/112023 CN2018112023W WO2019119965A1 WO 2019119965 A1 WO2019119965 A1 WO 2019119965A1 CN 2018112023 W CN2018112023 W CN 2018112023W WO 2019119965 A1 WO2019119965 A1 WO 2019119965A1
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WO
WIPO (PCT)
Prior art keywords
power supply
supply unit
unit
voltage
series
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PCT/CN2018/112023
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English (en)
French (fr)
Inventor
邹桐
王利军
詹克团
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北京比特大陆科技有限公司
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Application filed by 北京比特大陆科技有限公司 filed Critical 北京比特大陆科技有限公司
Priority to CN201880002357.XA priority Critical patent/CN109874314B/zh
Publication of WO2019119965A1 publication Critical patent/WO2019119965A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters

Definitions

  • the present invention relates to power supply technology for integrated circuit chips, and more particularly to a series power supply circuit, system and method.
  • the computing equipment based on large-scale integrated circuits adopts the traditional parallel power supply architecture, which has significant shortcomings such as excessive current and low energy use efficiency, and increases the requirements of chip circuit design and the cost of production design.
  • the working voltage of the chip is getting lower and lower, and the working current is getting larger and larger.
  • the prior art starts to adopt the power supply mode of the chip in series on the printed circuit board (PCB). That is, multiple sets of chips are connected in series, and a multi-stage series voltage domain is formed between the power input end and the ground end.
  • the series power supply architecture can effectively reduce the overall supply current of the circuit, improve the power conversion efficiency, and reduce the cost of the circuit components of the power conversion portion.
  • the existing series supply architecture cannot simultaneously supply two power paths in series.
  • the prior art series power supply architecture also has problems such as low power conversion efficiency, high overall power supply current of the circuit, and complicated power supply circuit.
  • the present invention has been made in view of the above problems in the prior art, and an object thereof is to provide a voltage characteristic of two large current power sources under the CPU/GPU computing architecture, by using two high current main power sources.
  • the higher one serves as the serial power supply main path of the unit to be powered, and at each stage, another voltage is generated by DC voltage conversion on the input voltage on the main path, thereby achieving a power conversion efficiency that is significantly better than the current industry tradition.
  • Parallel and series power supply architecture and at the same time reduce the overall supply current of the circuit, simplifying the power supply circuit and saving the material cost of the device.
  • an aspect of the present invention provides a series power supply circuit, including: a first power supply unit, the first power supply unit is connected in parallel for providing a first power supply voltage; and the second power supply unit The second power supply unit is connected in series for providing a second power supply voltage; the power supply unit provides a power supply voltage for the first power supply unit and the second power supply unit; and the power supply unit, the power supply unit has a A power supply unit access terminal receives the power supply voltage provided by the first power supply unit.
  • the voltage of the first power supply unit is greater than the second power supply unit.
  • the power supply unit includes a first power supply unit and a second power supply unit, and the first power supply unit and the second power supply unit respectively include a power input end and a power output end.
  • the power input end is connected to an external power source; the first power supply unit is connected in series with the first power supply unit, and the second power supply unit is connected in series with the second power supply unit.
  • the to-be-powered unit is a group of to-be-powered objects including one or more objects to be powered connected in series.
  • the to-be-powered unit includes a group of the above-mentioned groups of objects to be powered, and the group of more than one group of objects to be powered are connected in parallel to be one or more units to be powered.
  • the power supply unit further includes a second power supply unit access end and a ground end, and the lowest level ground end of the multi-stage power supply unit is connected to the ground, and each of the other The grounding end of the power supply unit is connected to the second power supply unit access end of the next-stage power supply unit, so that the second power supply voltage is respectively provided for each power supply unit via the second power supply unit access terminal.
  • the highest-level first power supply unit access end of the multi-stage power supply unit is connected to the first power supply unit, and the first of each of the other power supply units is The power supply unit access terminals are respectively connected to the second power supply unit access terminals of the upper-level power supply unit, so that the first power supply voltage is respectively provided for each of the power supply units to be powered via the first power supply unit access terminal.
  • the series power supply circuit further comprising: a level conversion unit, wherein the level conversion unit is between a group of more to-be-powered object groups, and the power to be powered by each of the units to be powered The objects are connected in series for signal level conversion.
  • the power supply unit is a DC-DC module.
  • Another aspect of the present invention provides a series power supply system, characterized in that the series power supply system comprises a series power supply circuit as described in any of the preceding.
  • Another aspect of the present invention provides a series power supply method, the series power supply method using the series power supply circuit according to any one of the preceding claims, comprising: a first voltage conversion step, the first power supply unit being connected to An external power source is connected to the first power supply unit access terminal of the to-be-powered unit through the power input end, and the first power supply unit is provided with a first power supply voltage after the external power supply is converted, and the first power supply unit utilizes the a first power supply voltage is used to supply power to the power supply unit; and a second voltage conversion step, the second power supply unit is connected to an external power supply, and the power supply input end is connected to the second power supply unit access end of the to-be-powered unit, Providing a second supply voltage to the second power supply unit after the external power supply is switched, and the second power supply unit supplies power to the power supply unit by using the second power supply voltage;
  • the first voltage conversion step further includes: a first voltage dividing step, in the first voltage converting step, the highest level of the multi-stage power supply unit
  • the first power supply unit access end is connected to the first power supply unit
  • the other power supply unit access terminals of each of the other power supply units are respectively connected to the second power supply unit access end of the upper first power supply unit
  • the power supply units at each stage perform voltage division power supply, so that each stage of the power supply unit to be formed forms a balanced first power supply voltage.
  • the second voltage converting step further includes: a second voltage dividing step, in the second voltage converting step, the grounding end of the to-be-powered unit is respectively The second power supply unit access terminal of the next-stage power supply unit is connected, and the voltage-divided power supply is performed on the power supply units to be equalized, so that each of the power supply units to be formed forms a balanced second power supply voltage.
  • the second supply voltage supplies power only to the group of to-be-powered objects in series with the level conversion unit.
  • the grounding end of the lowest-level power supply unit is connected to the ground.
  • the invention provides a voltage characteristic of two large current power sources under the CPU/GPU computing architecture, by using the higher voltage among the two large current main power sources as the series power supply main path of the power supply unit, in each The stage generates another supply voltage by performing DC voltage conversion on the input voltage on the main path, thereby achieving the purpose of significantly lowering the power conversion efficiency than the conventional parallel and series power supply architectures in the industry, and reducing the overall supply current of the circuit. It further simplifies the power supply circuit and saves the material cost of the device.
  • FIG. 1 is a schematic structural view of a first embodiment of a series power supply circuit of the present invention
  • FIG. 2 is a schematic structural view of a second embodiment of the series power supply circuit of the present invention.
  • FIG. 3 is a schematic structural view of a third embodiment of the series power supply circuit of the present invention.
  • FIG. 4 is a view showing an example of the structure of a fourth embodiment of the series power supply circuit of the present invention.
  • Figure 5 is a view showing an example of the structure of a fifth embodiment of the series power supply circuit of the present invention.
  • Figure 6 is a flow chart showing the steps of the method of the series power supply circuit of the present invention.
  • a first power supply unit, a second power supply unit, a power supply unit, a power supply unit, and a level conversion unit are provided, wherein the number of each unit module may be one or more
  • a plurality of unit modules are referred to, and the first, second, etc. are distinguished.
  • Each unit module may have a connection end such as an input end and an output end to be connected to other unit modules.
  • the power supply unit can perform level shifting instead of the level shifting unit, and of course, the level shifting unit can be separately provided.
  • the power supply unit may be a DC-DC module, or may be another device that converts one voltage value of electrical energy into another voltage value in a direct current circuit.
  • the power supply unit includes a first power supply unit and a second power supply unit, and the input ends of the first power supply unit and the second power supply unit are connected to an external power supply (VCC), and the first power supply unit and the second power supply unit are respectively A power supply voltage VDDQ power supply terminal is connected in series with a second power supply voltage VDD power supply terminal.
  • VCC external power supply
  • the power supply unit may include a CPU chip, a GPU chip, an application specific integrated circuit ASIC chip, etc., and may also be a component having an integrated circuit module such as another storage device or a processor.
  • the unit to be powered may be a type of component, or a combination of a plurality of components of the same or different types. When it is a plurality of components, it is formed as a group of objects to be powered in series.
  • the to-be-powered unit may be one or more groups of objects to be powered.
  • each group of objects to be powered is connected in parallel, and more than one level of the unit to be powered is formed.
  • the first power supply unit and the second power supply unit will be described mainly by taking the main power supply first power supply voltage VDDQ power supply end and the second power supply voltage VDD power supply end of the two large currents in the CPU/GPU computing architecture as an example.
  • the first power supply unit and the second power supply unit of the present invention are not limited to VDDQ and VDD, and any voltage supply module or power supply capable of supplying power to the integrated circuit chip is within the protection scope of the present invention.
  • the first power supply voltage VDDQ power supply terminals are connected in parallel or in parallel connection, and the second power supply voltage VDD power supply terminals are connected in series or in series connection.
  • the series power supply circuit of the embodiment of the present invention includes N serially connected power supply units, each of which has a first power supply voltage (VDDQ) input end and a second power supply voltage (VDD) input end.
  • VDDQ first power supply voltage
  • VDD second power supply voltage
  • the second power voltage input end of the Nth stage power supply unit is connected to the second power supply end (VDDn)
  • the ground end of the first stage power supply unit is connected to the ground (VSS)
  • the ground of each stage to be powered The terminal is connected to the second power voltage input end of the next-stage power supply unit, so that a second power voltage (VDD1, VDD2, ..., VDDn) is respectively provided for each power supply unit via the second power voltage input terminal;
  • the first power voltage input end of the Nth stage power supply unit is connected to the first power supply end (VDDQn), and the first power supply voltage input end of the remaining N-1 stage power supply unit is respectively connected to the first power supply unit to be powered.
  • a second power supply voltage input terminal respectively, for providing a first power supply voltage (VDDQ1, VDDQ2, . . . , VDDQn) for each to-be-powered unit via the first power voltage input terminal, where N is an integer greater than one.
  • the first supply voltage VDDQ and the second supply voltage VDD are two high current mains in the CPU/GPU computing architecture, the VDDQ current can reach 12A, and the VDD current can reach 20A.
  • the first power voltage VDDQ is greater than the second power voltage VDD.
  • the first power voltage VDDQ may be 1.6V
  • the second power voltage VDD may be 0.8V.
  • the unit to be powered may include a CPU chip, a GPU chip, an application specific integrated circuit ASIC chip, and the like.
  • the VDDQ voltage is set to 1.6V by default, and VDD is used as the serial power supply main path of the unit to be powered, and the VDD voltage of the previous stage is borrowed step by step to generate the unit to be powered.
  • VDDQ supply voltage Compared with the conventional series power supply circuit, the series power supply circuit of the embodiment of the invention improves the power conversion efficiency by about 5-10%, and reduces the overall power supply current of the circuit, thereby saving more material costs.
  • the series power supply circuit of the embodiment of the present invention includes N first connected power supply object groups connected in series and N second connected power supply object groups connected in series, each of the first power supply target group and the second The group to be powered has a first power supply voltage (VDDQ) input terminal, a second power supply voltage (VDD) input terminal, and a ground terminal, and a second power supply voltage of the first power supply target group and the second power supply target group of the same level
  • VDDQ first power supply voltage
  • VDD second power supply voltage
  • ground terminals are connected in parallel.
  • the first power supply target group of the Nth stage and the second power voltage input end of the second power supply target group are connected to the second power supply terminal (VDDn), level 1
  • the grounding end of the first group to be powered and the ground of the second group to be powered are connected (VSS), and the ground of the first group to be powered and the group of the second group to be powered are respectively associated with the next level
  • the second power source is connected to the second power voltage input terminal of the second power supply target group, so that the second power source is respectively provided for each of the first power supply target group and the second power supply target group via the second power voltage input terminal.
  • the first power supply voltage input group of the Nth stage and the first power supply voltage input end of the second power supply target group are connected to the first power supply terminal (VDDQn), and the remaining N-1 level first power supply target group and the second standby
  • the first power voltage input end of the power supply object group is respectively connected to the second power voltage input end of the first first power supply target group and the second power supply target group, so that the first power supply voltage input terminal is first for each first
  • the to-be-powered object group and the second to-be-powered object group respectively provide a first power supply voltage (VDDQ1, VDDQ2, ..., VDDQn), where N is an integer greater than one.
  • the first supply voltage VDDQ and the second supply voltage VDD are two high current mains in the CPU/GPU computing architecture, the VDDQ current can reach 12A, and the VDD current can reach 20A.
  • the first power voltage VDDQ is greater than the second power voltage VDD.
  • the first power voltage VDDQ may be 1.6V
  • the second power voltage VDD may be 0.8V.
  • the first and second groups of objects to be powered may include a CPU chip, a GPU chip, an application specific integrated circuit ASIC chip, and the like.
  • the number of first and second groups of objects to be powered per stage can be expanded to a plurality of parallels.
  • the VDDQ voltage is set to 1.6V by default, and VDD is used as the serial power supply main path of the unit to be powered, and the VDD voltage of the previous stage is borrowed step by step to generate the unit to be powered.
  • VDDQ supply voltage Compared with the conventional series power supply circuit, the series power supply circuit of the embodiment of the invention improves the power conversion efficiency by about 5-10%, and reduces the overall power supply current of the circuit, thereby saving more material costs.
  • the series power supply circuit of the embodiment of the present invention includes N first groups of power to be supplied connected in series and N groups of second objects to be powered, each of the first group of power to be supplied has a first power supply voltage ( VDDQ) input terminal, second power supply voltage (VDD) input terminal and ground terminal, each second group of to-be-powered objects has a first power supply voltage (VDDQ) input end and a ground terminal, and the first group of power to be supplied in the same stage
  • VDDQ first power supply voltage
  • VDDQ first power supply voltage
  • the first power supply voltage input group of the Nth stage and the first power supply voltage input end of the second power supply target group are connected to the first power supply terminal (VDDQn), and the remaining N-1 level first power supply target group and the second standby
  • the first power voltage input end of the power supply target group is respectively connected to the second power voltage input end of the first first power supply target group, so that each first power supply target group and the second are provided via the first power voltage input end.
  • the group to be powered provides a first power supply voltage (VDDQ1, VDDQ2, ..., VDDQn), where N is an integer greater than one.
  • the first supply voltage VDDQ and the second supply voltage VDD are two high current mains in the CPU/GPU computing architecture, the VDDQ current can reach 12A, and the VDD current can reach 20A.
  • the first power voltage VDDQ is greater than the second power voltage VDD.
  • the first power voltage VDDQ may be 1.6V
  • the second power voltage VDD may be 0.8V.
  • the first group of objects to be powered may include a CPU chip, a GPU chip, an application specific integrated circuit ASIC chip, and the like
  • the second group of objects to be powered may include a DDR storage unit or the like.
  • the number of first and second groups of objects to be powered per stage can be expanded to a plurality of parallels.
  • the VDDQ voltage is set to 1.6V by default, and VDD is used as the serial power supply main path of the unit to be powered, and the VDD voltage of the previous stage is borrowed step by step to generate the unit to be powered.
  • VDDQ supply voltage Compared with the conventional series power supply circuit, the series power supply circuit of the embodiment of the invention improves the power conversion efficiency by about 5-10%, and reduces the overall power supply current of the circuit, thereby saving more material costs.
  • FIG. 4 is a view showing an application example of a fourth embodiment of the series power supply circuit of the present invention.
  • FIG. 4 is a diagram showing an application example of simultaneously supplying power to a plurality of first to-be-powered object groups and six second power-to-power groups to be connected in series according to an embodiment of the present invention, wherein the first group of power to be supplied is an ASIC chip.
  • the second group of objects to be powered is exemplified by a DDR storage unit.
  • the series power supply circuit of the present example includes six chips in series and six DDR memory cells connected in common with the same level chip, the ground of each stage of the chip and the DDR memory unit and the chip of the next stage.
  • the VDD input is connected, and the ground of the first-stage chip and the DDR memory cell is connected to ground (VSS).
  • the series power supply circuit of this example first converts the external DC voltage 12V into 4.8V through the DC-DC module, which is the supply voltage of the VDD6 input terminal of the chip of the sixth stage. Since each stage of the power supply object is the same, the 6 chips in series are connected.
  • the input voltages of 4.8V (VDD6), 4.0V (VDD5), 3.2V (VDD4), 2.4V (VDD3), 1.6V (VDD2), and 0.8V (VDD1) are provided in sequence, so that the ends of each chip are formed.
  • a balanced VDD voltage distribution of 0.8V is used.
  • the external 12V power supply voltage is converted to 5.6V through the DC-DC module, which is used as the VDDQ6 input voltage of the 6th stage chip and the DDR memory unit, and is borrowed step by step for the 5th to 1st stage chips and the DDR memory unit.
  • the VDD input voltage of the upper chip is used as the VDDQ input voltage of the current stage, so that 4.8V (VDDQ5), 4.0V (VDDQ4), and 3.2V are sequentially supplied to the fifth to the first stage by the VDD input voltage of the previous stage.
  • VDDQ3 The input voltages of VDDQ3), 2.4V (VDDQ2), and 1.6V (VDDQ1) form a balanced VDDQ voltage distribution of 1.6V across each chip and DDR memory cell, thus ensuring 6 chips and DDR memory cells in series. A stable operating voltage can be obtained.
  • the VDD current of a single chip is about 20A
  • the current of VDDQ1.6V is about 12.8A
  • the parallel power supply scheme has higher power conversion efficiency.
  • the VDDQ voltage is 0.1V higher than the VDDQ voltage in the previous embodiment, the higher portion of the voltage has a chance to run at a faster rate under the same DDR memory timing parameter tFAW, which is not wasted power.
  • FIG. 5 is a block diagram showing the structure of a fifth embodiment of the series power supply circuit of the present invention.
  • a level conversion unit is respectively connected in series between two adjacent power supply units, and the level conversion unit For signal level conversion between two connected units to be powered.
  • Fig. 5 only schematically shows an improvement based on the embodiment of Fig. 1, and for any of the other embodiments, the modification is the same.
  • the level shifting unit can be implemented, for example, by a capacitive coupling method, a differential signal transmission method, and a diode drop method.
  • Each of the to-be-powered units is connected to the to-be-powered unit in the upper-level voltage domain through a low-to-high signal level conversion module in the level conversion unit, respectively, through the high-to-low signal level conversion module in the signal level conversion unit Connect to the unit to be powered in the next voltage domain.
  • the voltage domain of the upper stage is higher than the voltage domain of the current stage, and the voltage domain of the current stage is higher than the voltage domain of the next stage, and the voltage of each stage is
  • the power supply unit of the domain is connected to the to-be-powered unit in the voltage domain of the upper stage through a low-to-high signal level conversion module, and the low-to-high signal level conversion module can convert the signal sent by the unit to be powered in the voltage domain of the current level into
  • the signal of the upper voltage domain is sent to the power supply unit in the upper voltage domain; the power supply unit of each voltage domain is connected to the power supply unit in the next voltage domain through the high to low signal level conversion module.
  • the high-to-low signal level conversion module can convert the signal sent by the power supply unit of the current stage into the signal of the next-level voltage domain and send it to the power supply unit in the next-level voltage domain, thereby being connected in series to be powered. Signal communication between different voltage domains is achieved between the units.
  • the series power supply system of the present invention relates to a computer server, and specifically includes a main board, a memory, a power supply, and an integrated circuit including a series power supply circuit.
  • the series power supply circuit is the series power supply circuit described in the above embodiments.
  • the series power supply system of the present invention also provides an apparatus for controlling powering up a series power supply circuit, including a memory and a processor, the memory including a computer program that executes a computer program to implement a power supply method of the series power supply circuit described below.
  • the series powering system of the present invention can be applied to computer systems/servers that can operate with numerous other general purpose or special purpose computing system environments or configurations.
  • Examples of well-known computing systems, environments, and/or configurations suitable for use with computer systems/servers include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, based on Microprocessor systems, set-top boxes, programmable consumer electronics, networked personal computers, small computer systems, mainframe computer systems, and distributed cloud computing technology environments including any of the above, and the like.
  • the computer system/server can be described in the general context of computer system executable instructions (such as program modules) being executed by a computer system.
  • program modules may include routines, programs, target programs, components, logic, data structures, and the like that perform particular tasks or implement particular abstract data types.
  • the computer system/server can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices that are linked through a communications network.
  • program modules may be located on a local or remote computing system storage medium including storage devices.
  • Figure 5 is a flow chart showing the steps of the method of the series power supply circuit of the present invention. As shown in FIG. 5, the method steps of the series power supply circuit of the present invention include:
  • the first power supply unit is connected to the external power supply, and is connected to the first power supply unit access terminal of the same-stage power supply unit through the power input end, and the first power supply unit is provided after the external power supply is converted.
  • the power supply voltage, the first power supply unit uses the first power supply voltage to supply power to the power supply unit;
  • the second supply voltage supplies power only to the group of objects to be powered connected in series with the level conversion unit
  • a first voltage dividing step S11 in the first voltage converting step S1, the access terminal of the highest level first power supply unit of the multi-stage power supply unit is connected to the first power supply unit, and the first power supply unit of each of the other power supply units to be powered The access end is respectively connected to the second power supply unit access end of the upper-level power supply unit, and the partial power supply units are divided and supplied with power, so that each stage of the power supply unit forms an equalized first power supply voltage;
  • the second power supply unit is connected to the external power supply, is connected to the second power supply unit access terminal of the to-be-powered unit through the power input end, and supplies the second power supply voltage to the second power supply unit after the external power supply is converted.
  • the second power supply unit supplies power to the power to be powered unit by using the second power supply voltage.
  • a second voltage dividing step S21 in the second voltage converting step S2, the grounding end of the power supply unit is respectively connected to the second power supply unit access end of the next-stage power supply unit, and the partial power supply unit is divided and supplied with power. So that each stage of the unit to be powered forms an equalized second supply voltage.
  • the grounding end of the lowest-level power supply unit is connected to the ground.

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Abstract

本发明实施例提供了一种串联供电电路，其特征在于，包括：第一供电单元，所述第一供电单元并联连接，用于提供第一供电电压；第二供电单元，所述第二供电单元串联连接，用于提供第二供电电压；电源单元，为所述第一供电单元和所述第二供电单元提供供电电压；待供电单元，所述待供电单元具有第一供电单元接入端接受所述第一供电单元提供的供电电压。达到了在电源转换效率上明显优于目前业界传统的并联和串联供电架构的目的，同时降低了电路整体供电电流，进一步简化了供电电路，节省了器件的物料成本。

Description

串联供电电路、系统和方法 技术领域
本发明涉及集成电路芯片的电源供电技术，特别是涉及一种串联供电电路、系统和方法。
背景技术
随着云计算和服务器级别的大规模计算持续快速发展，以及全球对环境保护和节能意识的提升，能源使用效率变成了在硬件计算体系里一个非常重要的指标。
目前基于大规模集成电路的计算设备采用传统并联电源架构存在电流过大、能源使用效率低等显著缺点，并且增加了芯片电路设计的要求和生产设计的成本。随着半导体工艺的发展，芯片的工作电源电压越来越低，工作电流越来越大，为了最大化电源的转换效率，现有技术在印刷电路板(PCB)上开始采取芯片串联的供电方式，即多组芯片采用相互串联的方式，在电源输入端和接地端之间形成多级串联的电压域。这种串联供电架构可以有效地减小电路整体供电电流，提高电源转换效率，并且可以降低电源转换部分电路器件的成本。
但是，在计算机、服务器、显卡或其他集成计算阵列中，在基于CPU/GPU的计算架构下使用这种串联供电架构还存在一些难点。现有的计算架构下，有两个不同电压的主电压源都存在较大的电流，例如VDD和VDDQ，现有的串联供电架构无论是以VDD还是VDDQ作为电源主路径，都无法同时对两个电源路径进行串联供电。这是因为VDD和VDDQ存在固定的电压差，如果两个电压在某一级上电压可以协同，那就意味着在这一级的上一级或下一级两者的电压肯定无法正好配合给芯片供电。
因此，有必要设计一种新的优化的串联供电方案，来进一步减少集成电路整体的供电电流，提升电源转换效率，降低电路器件成本。
发明内容
发明要解决的课题
因为VDD和VDDQ存在固定的电压差，因此现有的串联供电架构无法同时对两个电源路径进行串联供电。同时，现有技术的串联供电架构还存在电源转换效率低、电路整体供电电流高、供电电路复杂等问题。
本发明是鉴于现有技术存在的上述问题而做出的，其目的在于提供一种充分利用CPU/GPU计算架构下两个大电流电源的电压特点，通过将两个大电流的主电源中电压较高者作为待供电单元的串联供电主路径，在每一级通过对主路径上的输入电压进行直流电压转换来生成另一供电电压，从而达到在电源转换效率上明显优于目前业界传统的并联和串联供电架构，并且同时降低电路整体供电电流，简化了供电电路，节省了器件的物料成本。
用于解决课题的手段
为了解决上述问题，本发明的一方面提供了一种串联供电电路，其特征在于，包括：第一供电单元，所述第一供电单元并联连接，用于提供第一供电电压；第二供电单元，所述第二供电单元串联连接，用于提供第二供电电压；电源单元，为所述第一供电单元和所述第二供电单元提供供电电压；待供电单元，所述待供电单元具有第一供电单元接入端接受所述第一供电单元提供的供电电压。
优选地，根据前述的串联供电电路，其特征在于，所述第一供电单元的电压大于所述第二供电单元。
优选地，根据前述的串联供电电路，其特征在于，所述电源单元包括第一电源单元和第二电源单元，所述第一电源单元和第二电源单元分别包括电源输入端和电源输出端，所述电源输入端连接到外部电源；所述第一电源单元与所述第一供电单元串联连接，所述第二电源单元与所述第二供电单元串联连接。
优选地，根据前述的串联供电电路，其特征在于，所述待供电单元为包括一个以上串联连接的待供电对象的待供电对象组。
优选地，根据前述的串联供电电路，其特征在于，所述待供电单元包括一组以上所述待供电对象组，所述一组以上待供电对象组并联连接为一级以上待供电单元。
优选地，根据前述的串联供电电路，其特征在于，所述待供电单元还包 括第二供电单元接入端和接地端，所述多级待供电单元的最下级接地端连接地，其他每一级所述待供电单元的接地端与其下一级待供电单元的第二供电单元接入端相连，从而经由第二供电单元接入端为每个待供电单元分别提供第二供电电压。
优选地，根据前述的串联供电电路，其特征在于，所述多级待供电单元的最高级第一供电单元接入端连接至所述第一供电单元，其他每一级待供电单元的第一供电单元接入端分别连接到上一级待供电单元的第二供电单元接入端，从而经由第一供电单元接入端为每一级待供电单元分别提供第一供电电压。
优选地，根据前述的串联供电电路，其特征在于，还包括：电平转换单元，所述电平转换单元在一组以上待供电对象组之间，与所述每级待供电单元的待供电对象串联，用于进行信号电平转换。
优选地，根据前述的串联供电电路，其特征在于，所述电源单元为DC-DC模块。
本发明的另一方面提供了一种串联供电系统，其特征在于，所述串联供电系统包括如前任一所述的串联供电电路。
本发明的另一方面提供了一种串联供电方法，所述串联供电方法使用如前任一所述的串联供电电路，其特征在于，包括：第一电压转换步骤，所述第一电源单元连接至外部电源，通过所述电源输入端连接至待供电单元的第一供电单元接入端，将外部电源转换后对所述第一供电单元提供第一供电电压，所述第一供电单元利用所述第一供电电压为所述待供电单元供电；第二电压转换步骤，所述第二电源单元连接至外部电源，通过所述电源输入端连接至待供电单元的第二供电单元接入端，将外部电源转换后对所述第二供电单元提供第二供电电压，所述第二供电单元利用所述第二供电电压为所述待供电单元供电；
优选地，根据前述的串联供电方法，其特征在于，所述第一电压转换步骤还包括：第一分压步骤，在所述第一电压转换步骤中，所述多级待供电单 元的最高级第一供电单元接入端连接至所述第一供电单元，其他每一级待供电单元的第一供电单元接入端分别连接到上一级待供电单元的第二供电单元接入端，对所述各级待供电单元进行分压供电，使所述每级待供电单元形成均衡第一供电电压。
优选地，根据前述的串联供电方法，其特征在于，所述第二电压转换步骤还包括：第二分压步骤，在所述第二电压转换步骤中，所述待供电单元的接地端分别与下一级待供电单元的所述第二供电单元接入端连接，对所述各级待供电单元进行分压供电，使所述每级待供电单元形成均衡第二供电电压。
优选地，根据前述的串联供电方法，其特征在于，所述第一电压转换步骤中，所述第二供电电压仅对所述电平转换单元串联的所述待供电对象组供电。
优选地，根据前述任一所述的串联供电方法，其特征在于，还包括：
接地步骤，所述最下级待供电单元的接地端连接地。
本发明提供了一种充分利用CPU/GPU计算架构下两个大电流电源的电压特点，通过将两个大电流的主电源中电压较高者作为待供电单元的串联供电主路径，在每一级通过对主路径上的输入电压进行直流电压转换来生成另一供电电压，从而达到了在电源转换效率上明显优于目前业界传统的并联和串联供电架构的目的，同时降低了电路整体供电电流，进一步简化了供电电路，节省了器件的物料成本。
附图说明
图1是本发明串联供电电路的第一实施例的结构示意图；
图2是本发明串联供电电路的第二实施例的结构示意图；
图3是本发明串联供电电路的第三实施例的结构示意图；
图4是本发明串联供电电路的第四实施例的结构示例图；
图5是本发明串联供电电路的第五实施例的结构示例图；
图6是本发明串联供电电路的方法步骤流程图。
具体实施方式
下面将结合附图具体说明本发明的示例性实施方式，应当理解，给出这些实施方式仅仅是为了使本领域技术人员能够更好地理解进而实现本发明，而并非以任何方式限制本发明的范围。
[概述]
首先说明本发明的概述，在本发明中，提供第一供电单元、第二供电单元、电源单元、待供电单元和电平转换单元，其中各个单元模块的个数可以是一个也可以是多个，在以下描述中涉及多个单元模块的，以第一、第二等进行区别。各个单元模块可以具有输入端、输出端等连接端与其他单元模块进行连接导通。
在本发明中，电源单元可以进行电平转换，从而替代电平转换单元，当然也可以单独设置电平转换单元。
在本发明中，电源单元可以是DC-DC模块，也可以是其他在直流电路中将一个电压值的电能变为另一个电压值的电能的装置。
在本发明中，电源单元包括第一电源单元和第二电源单元，第一电源单元和第二电源单元的输入端连接到外部电源(VCC)，第一电源单元和第二电源单元分别与第一电源电压VDDQ供电端和第二电源电压VDD供电端串联。
在本发明中，待供电单元可以包括CPU芯片、GPU芯片、专用集成电路ASIC芯片等，也可以是其他储存器、处理器等具有集成电路模块的部件。
本发明中，待供电单元可以是一个类型的部件，也可以是多个相同或不同类型的部件的组合，当为多个部件时，形成为一组串联的待供电对象组。
本发明中，待供电单元可以是一个或多个待供电对象组，当为多个待供电对象组时，各个待供电对象组之间并联连接，并且形成一级以上的待供电单元。
在本发明中，第一供电单元、第二供电单元将主要以CPU/GPU计算架构中两个大电流的主电源第一电源电压VDDQ供电端和第二电源电压VDD供电端为例进行描述，当然本发明的第一供电单元、第二供电单元不限于VDDQ、VDD，凡是能够对集成电路芯片进行供电的电压提供模块或电源均在本发明保护范围内。
在本发明中，第一电源电压VDDQ供电端为并联连接或相当于并联连接的方式连接，第二电源电压VDD供电端为串联连接或相当于串联连接的方式连接。
下面将结合附图和具体实施例对本发明进行说明。
[串联供电电路]
图1为本发明串联供电电路的第一实施例的结构示意图。如图1所示，本发明实施例的串联供电电路包括N个串联连接的待供电单元，每个待供电单元分别具有第一电源电压(VDDQ)输入端、第二电源电压(VDD)输入端和接地端，第N级待供电单元的第二电源电压输入端连接第二电源供电端(VDDn)，第1级待供电单元的接地端连接地(VSS)，每一级待供电单元的接地端与下一级待供电单元的第二电源电压输入端相连，从而经由第二电源电压输入端为每个待供电单元分别提供第二电源电压(VDD1，VDD2，…，VDDn)；
第N级待供电单元的第一电源电压输入端连接至第一电源供电端(VDDQn)，其余N-1级待供电单元的第一电源电压输入端分别连接到上一级待供电单元的第二电源电压输入端，从而经由第一电源电压输入端为每个待供电单元分别提供第一电源电压(VDDQ1，VDDQ2，…，VDDQn)，其中N为大于1的整数。
在一些实施方式中，第一电源电压VDDQ和第二电源电压VDD为CPU/GPU计算架构中两个大电流的主电源，VDDQ的电流可以达到12A，VDD的电流可以达到20A。所述第一电源电压VDDQ大于第二电源电压VDD，例如，第一电源电压VDDQ可以为1.6V，第二电源电压VDD可以为0.8V。
在一些实施方式中，待供电单元可以包括CPU芯片、GPU芯片、专用集成电路ASIC芯片等。
本发明实施例利用VDD和VDDQ电压接近的特点，将VDDQ电压默认设置为1.6V，将VDD作为待供电单元的串联供电主路径，逐级借用上一级的VDD电压来生成本级待供电单元的VDDQ供电电压。与传统的串联供电电路相比，本发明实施例的串联供电电路在电源转换效率上提升了5-10％左右，并且减少了电路整体供电电流，节省了更多的物料成本。
图2为本发明串联供电电路的第二实施例的结构示意图。如图2所示，本发明实施例的串联供电电路包括N个串联连接的第一待供电对象组和N个串联连接的第二待供电对象组，每个第一待供电对象组和第二待供电对象组分别具有第一电源电压(VDDQ)输入端、第二电源电压(VDD)输入端和接地端，同一级的第一待供电对象组和第二待供电对象组的第二电源电压(VDD)输入端并联连接，接地端并联连接，第N级的第一待供电对象组和第二待供电对象组的第二电源电压输入端连接第二电源供电端(VDDn)，第1级的第一待供电对象组和第二待供电对象组的接地端连接地(VSS)，每一级的第一待供电对象组和第二待供电对象组的接地端分别与下一级的第一待供电对象组和第二待供电对象组的第二电源电压输入端相连，从而经由第二电源电压输入端为每个第一待供电对象组和第二待供电对象组分别提供第二电源电压(VDD1，VDD2，…，VDDn)；
第N级的第一待供电对象组和第二待供电对象组的第一电源电压输入端连接至第一电源供电端(VDDQn)，其余N-1级第一待供电对象组和第二待供电对象组的第一电源电压输入端分别连接到上一级第一待供电对象组和第二待供电对象组的第二电源电压输入端，从而经由第一电源电压输入端为每个第一待供电对象组和第二待供电对象组分别提供第一电源电压(VDDQ1，VDDQ2，…，VDDQn)，其中N为大于1的整数。
在一些实施方式中，第一电源电压VDDQ和第二电源电压VDD为CPU/GPU计算架构中两个大电流的主电源，VDDQ的电流可以达到12A，VDD的电流可以达到20A。所述第一电源电压VDDQ大于第二电源电压VDD，例如，第一电源电压VDDQ可以为1.6V，第二电源电压VDD可以为0.8V。
在一些实施方式中，第一和第二待供电对象组可以包括CPU芯片、GPU芯片、专用集成电路ASIC芯片等。在一些实施方式中，每一级第一和第二待供电对象组的数量可以扩展至并联的多个。
本发明实施例利用VDD和VDDQ电压接近的特点，将VDDQ电压默认设置为1.6V，将VDD作为待供电单元的串联供电主路径，逐级借用上一级的VDD电压来生成本级待供电单元的VDDQ供电电压。与传统的串联供电电路相比，本发明实施例的串联供电电路在电源转换效率上提升了5-10％左右，并且减少了电路整体供电电流，节省了更多的物料成本。
图3为本发明串联供电电路的第三实施例的结构示意图。如图3所示，本发明实施例的串联供电电路包括N个串联连接的第一待供电对象组和N个第二待供电对象组，每个第一待供电对象组具有第一电源电压(VDDQ)输入端、第二电源电压(VDD)输入端和接地端，每个第二待供电对象组具有第一电源电压(VDDQ)输入端和接地端，同一级的第一待供电对象组和第二待供电对象组的接地端相连接，第N级第一待供电对象组的第二电源电压输入端连接第二电源供电端(VDDn)，第1级第一待供电对象组的接地端连接地(VSS)，每一级的第一待供电对象组的接地端分别与下一级的第一待供电对象组的第二电源电压输入端相连，从而经由第二电源电压输入端为每个第一待供电对象组分别提供第二电源电压(VDD1，VDD2，…，VDDn)；
第N级的第一待供电对象组和第二待供电对象组的第一电源电压输入端连接至第一电源供电端(VDDQn)，其余N-1级第一待供电对象组和第二待供电对象组的第一电源电压输入端分别连接到上一级第一待供电对象组的第二电源电压输入端，从而经由第一电源电压输入端为每个第一待供电对象组和第二待供电对象组分别提供第一电源电压(VDDQ1，VDDQ2，…，VDDQn)，其中N为大于1的整数。
在一些实施方式中，第一电源电压VDDQ和第二电源电压VDD为CPU/GPU计算架构中两个大电流的主电源，VDDQ的电流可以达到12A，VDD的电流可以达到20A。所述第一电源电压VDDQ大于第二电源电压VDD，例如，第一电源电压VDDQ可以为1.6V，第二电源电压VDD可以为0.8V。
在一些实施方式中，第一待供电对象组可以包括CPU芯片、GPU芯片、专用集成电路ASIC芯片等，第二待供电对象组可以包括DDR存储单元等。在一些实施方式中，每一级第一和第二待供电对象组的数量可以扩展至并联的多个。
本发明实施例利用VDD和VDDQ电压接近的特点，将VDDQ电压默认设置为1.6V，将VDD作为待供电单元的串联供电主路径，逐级借用上一级的VDD电压来生成本级待供电单元的VDDQ供电电压。与传统的串联供电电路相比，本发明实施例的串联供电电路在电源转换效率上提升了5-10％左右，并且减少了电路整体供电电流，节省了更多的物料成本。
图4为本发明串联供电电路的第四实施例的应用示例图。图4展现了本发明实施例同时对6个串联的第一待供电对象组和6个第二待供电对象组进行供电的应用示例，其中，第一待供电对象组以专用集成电路ASIC芯片作为示例，第二待供电对象组以DDR存储单元为示例。如图所示，本示例的串联供电电路包括6个串联的芯片和6个与同级芯片共地连接的DDR存储单元，每一级的芯片和DDR存储单元的接地端与下一级的芯片的VDD输入端相连接，第1级芯片和DDR存储单元的接地端连接到地(VSS)。
本示例的串联供电电路首先通过DC-DC模块将外部直流电压12V转换为4.8V，作为第6级的芯片的VDD6输入端的供电电压，由于每一级供电对象相同，因此在串联的6个芯片上依次提供了4.8V(VDD6)、4.0V(VDD5)、3.2V(VDD4)、2.4V(VDD3)、1.6V(VDD2)、0.8V(VDD1)的输入电压，使得每级芯片两端形成了0.8V的均衡VDD电压分布。其次，通过DC-DC模块将外部12V的电源电压转换为5.6V，作为第6级芯片和DDR存储单元的VDDQ6输入电压，而对于第5级到第1级芯片和DDR存储单元，逐级借用上一级芯片的VDD输入电压作为本级的VDDQ输入电压，从而借助上一级的VDD输入电压为第5级到第1级依次提供4.8V(VDDQ5)、4.0V(VDDQ4)、3.2V(VDDQ3)、2.4V(VDDQ2)、1.6V(VDDQ1)的输入电压，使得每级芯片和DDR存储单元两端形成了1.6V的均衡VDDQ电压分布，从而保证了串联的6个芯片和DDR存储单元都能获得稳定的工作电压。
本示例中，单个芯片的VDD电流大约为20A，VDDQ1.6V的电流大约为12.8A，每一级芯片单元功耗大约为0.8*20+1.6*12.8＝36.5W左右，相比现有的串并联供电方案具有更高的电源转换效率。虽然VDDQ电压相比之前的实施例中VDDQ电压高出0.1V，高出的部分电压有机会在同样的DDR内存时序参数tFAW下运行更快的速率，并不是浪费的功耗。
图5是本发明串联供电电路的第五实施例的结构示意图。如图5所示，本发明实施例的串联供电电路在前述任一实施例的基础上，在相邻的两个待供电单元之间分别串联连接一个电平转换单元，所述电平转换单元用于在相连接的两个待供电单元之间进行信号电平转换。图5仅示意性地展现了在图1所述实施例基础上的改进，对于其他的任一实施例，改进方式相同。
具体而言，电平转换单元例如可以采用电容耦合法、差分信号传输法和\ 或二极管压降法实现。每个待供电单元分别通过电平转换单元中的低到高信号电平转换模块与上一级电压域中的待供电单元连接，通过信号电平转换单元中的高到低信号电平转换模块与下一级电压域中的待供电单元连接。本发明实施例中，由于串联的不同待供电单元上形成的电压域大小不同，上一级电压域要高于本级电压域，本级电压域又高于下一级电压域，每级电压域的待供电单元通过低到高信号电平转换模块与上一级电压域中的待供电单元连接，低到高信号电平转换模块可以将本级电压域的待供电单元发送的信号转换为上一级电压域的信号后发送给上一级电压域中的待供电单元；每级电压域的待供电单元通过高到低信号电平转换模块与下一级电压域中的待供电单元连接，高到低信号电平转换模块可以将本级电压域待供电单元发送的信号转换为下一级电压域的信号后发送给下一级电压域中的待供电单元，从而在串联的待供电单元之间实现不同电压域之间的信号通信。
[串联供电系统]
本发明的串联供电系统涉及一种计算机服务器，具体包括主板、存储器、电源以及包含串联供电电路集成电路。其中，串联供电电路为上述各实施例中介绍的串联供电电路。
本发明的串联供电系统还提供了一种控制串联供电电路上电的设备，包括存储器和处理器，存储器包括计算机程序，处理器执行计算机程序以实现下述串联供电电路的供电方法。
本发明串联供电系统可以应用于计算机系统/服务器，其可与众多其它通用或专用计算系统环境或配置一起操作。适于与计算机系统/服务器一起使用的众所周知的计算系统、环境和/或配置的例子包括但不限于：个人计算机系统、服务器计算机系统、瘦客户机、厚客户机、手持或膝上设备、基于微处理器的系统、机顶盒、可编程消费电子产品、网络个人电脑、小型计算机系统、大型计算机系统和包括上述任何系统的分布式云计算技术环境，等等。
计算机系统/服务器可以在由计算机系统执行的计算机系统可执行指令(诸如程序模块)的一般语境下描述。通常，程序模块可以包括例程、程序、目标程序、组件、逻辑、数据结构等等，它们执行特定的任务或者实现特定的抽象数据类型。计算机系统/服务器可以在分布式云计算环境中实施，分布式 云计算环境中，任务是由通过通信网络链接的远程处理设备执行的。在分布式云计算环境中，程序模块可以位于包括存储设备的本地或远程计算系统存储介质上。
[串联供电方法]
图5是本发明串联供电电路的方法步骤流程图。如图5所示，本发明串联供电电路的方法步骤包括：
第一电压转换步骤S1，第一电源单元连接至外部电源，通过电源输入端连接至同级的待供电单元的第一供电单元接入端，将外部电源转换后对第一供电单元提供第一供电电压，第一供电单元利用第一供电电压为待供电单元供电；
在第一电压转换步骤中，第二供电电压仅对所述电平转换单元串联的待供电对象组供电；
第一分压步骤S11，在第一电压转换步骤S1中，多级待供电单元的最高级第一供电单元接入端连接至第一供电单元，其他每一级待供电单元的第一供电单元接入端分别连接到上一级待供电单元的第二供电单元接入端，对各级待供电单元进行分压供电，使每级待供电单元形成均衡第一供电电压；
第二电压转换步骤S2，第二电源单元连接至外部电源，通过电源输入端连接至待供电单元的第二供电单元接入端，将外部电源转换后对第二供电单元提供第二供电电压，第二供电单元利用第二供电电压为待供电单元供电。
第二分压步骤S21，在第二电压转换步骤S2中，待供电单元的接地端分别与下一级待供电单元的第二供电单元接入端连接，对各级待供电单元进行分压供电，使每级待供电单元形成均衡第二供电电压。
接地步骤S3，最下级待供电单元的接地端连接地。
以上参考附图，基于实施方式的实施例和变形例说明了本发明，但本发明并非限定于上述的实施方式，根据实际需要等将各实施方式的部分构成适当组合或置换后的方案，也包含在本发明的范围内。另外，还可以基于本领域技术人员的知识适当重组各实施方式的组合和处理顺序，或者对各实施方式施加各种设计变更等变形，被施加了这样的变形的实施方式也可能包含在本发明的范围内。

Claims (15)

  1. 一种串联供电电路，其特征在于，包括：
    第一供电单元，所述第一供电单元并联连接(大电路电源)，用于提供第一供电电压；
    第二供电单元，所述第二供电单元串联连接(小电路电源)，用于提供第二供电电压；
    电源单元，为所述第一供电单元和所述第二供电单元提供供电电压；
    待供电单元，所述待供电单元具有第一供电单元接入端接受所述第一供电单元提供的供电电压。
  2. 根据权利要求1所述的串联供电电路，其特征在于，
    所述第一供电单元的电压大于所述第二供电单元。
  3. 根据权利要求2所述的串联供电电路，其特征在于，
    所述电源单元包括第一电源单元和第二电源单元，所述第一电源单元和第二电源单元分别包括电源输入端和电源输出端，所述电源输入端连接到外部电源；
    所述第一电源单元与所述第一供电单元串联连接，所述第二电源单元与所述第二供电单元串联连接。
  4. 根据权利要求2或3所述的串联供电电路，其特征在于，
    所述待供电单元为包括一个以上串联连接的待供电对象的待供电对象组。
  5. 根据权利要求4所述的串联供电电路，其特征在于，
    所述待供电单元包括一组以上所述待供电对象组，所述一组以上待供电对象组并联连接为一级以上待供电单元。
  6. 根据权利要求5所述的串联供电电路，其特征在于，
    所述待供电单元还包括第二供电单元接入端和接地端，所述多级待供电单元的最下级接地端连接地，其他每一级所述待供电单元的接地端与其下一 级待供电单元的第二供电单元接入端相连，从而经由第二供电单元接入端为每个待供电单元分别提供第二供电电压。
  7. 根据权利要求6所述的串联供电电路，其特征在于，
    所述多级待供电单元的最高级第一供电单元接入端连接至所述第一供电单元，其他每一级待供电单元的第一供电单元接入端分别连接到上一级待供电单元的第二供电单元接入端，从而经由第一供电单元接入端为每一级待供电单元分别提供第一供电电压。
  8. 根据权利要求7所述的串联供电电路，其特征在于，还包括：
    电平转换单元，所述电平转换单元在一组以上待供电对象组之间，与所述每级待供电单元的待供电对象串联，用于进行信号电平转换。
  9. 根据权利要求8所述的串联供电电路，其特征在于，
    所述电源单元为DC-DC模块。
  10. 一种串联供电系统，其特征在于，所述串联供电系统包括如权利要求1～9任一所述的串联供电电路。
  11. 一种串联供电方法，所述串联供电方法使用如权利要求1～9任一所述的串联供电电路，其特征在于，包括：
    第一电压转换步骤，所述第一电源单元连接至外部电源，通过所述电源输入端连接至待供电单元的第一供电单元接入端，将外部电源转换后对所述第一供电单元提供第一供电电压，所述第一供电单元利用所述第一供电电压为所述待供电单元供电；
    第二电压转换步骤，所述第二电源单元连接至外部电源，通过所述电源输入端连接至待供电单元的第二供电单元接入端，将外部电源转换后对所述第二供电单元提供第二供电电压，所述第二供电单元利用所述第二供电电压为所述待供电单元供电。
  12. 根据权利要求11所述的串联供电方法，其特征在于，所述第一电压转换步骤还包括：
    第一分压步骤，在所述第一电压转换步骤中，所述多级待供电单元的最高级第一供电单元接入端连接至所述第一供电单元，其他每一级待供电单元的第一供电单元接入端分别连接到上一级待供电单元的第二供电单元接入端，对所述各级待供电单元进行分压供电，使所述每级待供电单元形成均衡第一供电电压。
  13. 根据权利要求12所述的串联供电方法，其特征在于，所述第二电压转换步骤还包括：
    第二分压步骤，在所述第二电压转换步骤中，所述待供电单元的接地端分别与下一级待供电单元的所述第二供电单元接入端连接，对所述各级待供电单元进行分压供电，使所述每级待供电单元形成均衡第二供电电压。
  14. 根据权利要求13所述的串联供电方法，其特征在于，所述第一电压转换步骤中，所述第二供电电压仅对所述电平转换单元串联的所述待供电对象组供电。
  15. 根据权利要求11～14任一所述的串联供电方法，其特征在于，还包括：
    接地步骤，所述最下级待供电单元的接地端连接地。
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