WO2020057180A1 - 片内无源电源补偿电路及应用其的运算单元、芯片、算力板和计算设备 - Google Patents

片内无源电源补偿电路及应用其的运算单元、芯片、算力板和计算设备 Download PDF

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WO2020057180A1
WO2020057180A1 PCT/CN2019/090434 CN2019090434W WO2020057180A1 WO 2020057180 A1 WO2020057180 A1 WO 2020057180A1 CN 2019090434 W CN2019090434 W CN 2019090434W WO 2020057180 A1 WO2020057180 A1 WO 2020057180A1
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Prior art keywords
power supply
terminal
voltage
compensation circuit
chip
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PCT/CN2019/090434
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English (en)
French (fr)
Inventor
刘杰尧
张楠赓
吴敬杰
马晟厚
Original Assignee
北京嘉楠捷思信息技术有限公司
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Priority claimed from CN201811103945.0A external-priority patent/CN110928355A/zh
Priority claimed from CN201811206445.XA external-priority patent/CN111142641A/zh
Application filed by 北京嘉楠捷思信息技术有限公司 filed Critical 北京嘉楠捷思信息技术有限公司
Priority to US17/251,659 priority Critical patent/US11442517B2/en
Publication of WO2020057180A1 publication Critical patent/WO2020057180A1/zh

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Definitions

  • the invention relates to a multi-voltage domain power supply circuit, in particular to a circuit for compensating a power supply voltage based on a substrate reference, and a computing unit, a chip, a computing board and a computing device using the same.
  • Virtual currency (such as Bitcoin and Ethereum) is a digital currency in the form of P2P, which has received widespread attention since the introduction of the Bitcoin system in 2009.
  • the system builds a distributed shared ledger based on the blockchain, thereby ensuring the security, reliability, and decentralization of the system's operation.
  • Bitcoin In hashing operations and proof of work, Bitcoin is based on the only correct hash value calculated to prove the workload and thus get the right to book and package blocks, so it is rewarded. This is the proof of work (Pow). Except for brute force calculations, there are currently no effective algorithms for hashing. For the new generation of computing equipment used to mine virtual digital currencies, the mining process is a large number of repetitive logical calculation pipelines.
  • the core of this kind of computing device design is the performance-to-power ratio. Higher performance and lower power consumption indicate that mining is more efficient and mean that more computing power can be achieved with the same power consumption.
  • CN206039425U discloses a series power supply circuit. As shown in FIG. 1, multiple packaging units are connected in series between the power supply terminal VCC and ground. Each packaging unit includes one or more groups of components, and each group of components includes one The signal-to-be-powered chip and the auxiliary power supply unit are connected, and a signal level conversion unit is serially connected between the two groups of adjacent-to-be-powered chips.
  • this series power supply circuit can provide low power voltage to each chip to be powered, it is aimed at providing series power to different packaging units on the printed circuit board, and cannot achieve series power supply between different voltage domains inside the chip. .
  • Multi-supply voltage power supply technology is more and more widely used in System-on-chip (SoC) and multi-processor computing structures.
  • SoC System-on-chip
  • the chip In a chip using multi-voltage domain technology, the chip usually contains multiple independent voltage domains or voltage islands, and the modules in each voltage domain work at the appropriate power supply voltage according to their timing requirements.
  • VDDH high power voltage
  • VDDL low power voltage
  • each chip to be powered may include a chip core, or each chip to be powered may include multiple chips.
  • the chip core of each voltage domain includes a P-channel metal oxide semiconductor (PMOS) tube and an N-channel metal oxide semiconductor (NMOS) tube in its circuit. .
  • the core of the chip in each voltage domain, the substrate of its PMOS tube is connected to the power voltage or working voltage (VDD) of the voltage domain of this level, and the VDD of this voltage domain is connected to the ground of the upper voltage domain (VSS).
  • VDD working voltage
  • the series power supply chip also includes n deep wells used to achieve isolation between different voltage domains, these n deep wells are set independently of each other and are not connected to each other, each of the n power supply units to be powered They are respectively located in a deep well, so as to achieve isolation between different voltage domains on the same chip and effectively prevent short circuits between different voltage domains.
  • the chip's internal series power supply system achieves series power supply between different voltage domains inside the chip, in addition to the power supply VDD for each voltage domain, additional auxiliary voltage sources VDD_1, VDD_2, etc. are required. Not only auxiliary voltage sources It is difficult to design, and it also takes up a lot of chip area, resulting in large power consumption.
  • the present invention provides an on-chip passive power supply compensation circuit based on a substrate reference.
  • the above circuit not only reduces power consumption, but also reduces design difficulty, saves chip area, and reduces production costs.
  • an on-chip passive power supply compensation circuit including:
  • Two or more voltage domains to be powered which are connected in series between the power source and the ground;
  • Two or more isolation regions, the voltage domain to be supplied is formed in the isolation region, and the isolation region is used to isolate the voltage domain to be supplied;
  • the isolation region is connected in series between the power source and the ground;
  • a power supply compensation unit which is connected between the voltage domain to be supplied and the isolation area, and is configured to provide power compensation to the voltage domain to be supplied.
  • the power compensation unit provides power compensation to the voltage domain to be powered by operating in a saturated state.
  • a first power supply terminal and a first ground terminal are formed at both ends of each of the isolation areas, and the first power supply terminal and / or the first ground terminal are used for
  • the power supply compensation unit provides a reference voltage.
  • a second power supply terminal and a second ground terminal are formed at both ends of each of the voltage domains to be supplied, and the power supply compensation unit supplies the second power supply terminal and / or The second ground terminal provides power compensation.
  • the above-mentioned on-chip passive power supply compensation circuit wherein, based on the reference voltage, when the voltage change range of the second power supply terminal and / or the second ground terminal exceeds a threshold value of the power supply compensation unit, The power supply compensation unit operates in the saturated state.
  • the power compensation unit is a switching transistor.
  • the switching transistor is a PMOS switching transistor and / or an NMOS switching transistor.
  • the PMOS switching transistor there are one or more of the PMOS switching transistor and / or the NMOS switching transistor.
  • one or more semiconductor devices are formed in the voltage domain to be supplied, and the second power supply terminal and / or the second ground terminal provide a substrate for the semiconductor device. Bottom bias.
  • the semiconductor device includes a PMOS transistor and / or an NMOS transistor
  • the second power supply terminal provides a substrate bias voltage to the PMOS transistor
  • the second ground terminal faces the The NMOS transistor provides a substrate bias.
  • the above-mentioned on-chip passive power compensation circuit further includes a voltage stabilizing unit, and the voltage stabilizing unit is connected in parallel at both ends of each of the isolation regions.
  • a first power supply terminal and a first ground terminal are formed at both ends of each of the isolation areas, and the first power supply terminal and / or the first ground terminal are used for
  • the power supply compensation unit provides a reference voltage.
  • a second power supply terminal and a second ground terminal are formed at both ends of each of the voltage domains to be supplied, and the power supply compensation unit supplies the second power supply terminal and / or The second ground terminal provides power compensation.
  • the voltage stabilizing unit is configured to stabilize the voltage of the first power terminal and / or the first ground terminal.
  • the voltage stabilizing unit includes one or more of a resistor, a capacitor, or a diode.
  • the voltage stabilizing unit is directly connected between the first power terminal and the first ground terminal, or is connected to the first power terminal and the analog power switch respectively. Between the first ground ends.
  • an analog switch is provided between the first ground terminal and the second ground terminal.
  • the present invention further provides a data operation unit, wherein the data operation unit includes an interconnected control circuit, an operation circuit, a storage circuit, and one or more on-chip passive power supply compensation circuits.
  • the on-chip passive power compensation circuit is any of the on-chip passive power compensation circuits described above.
  • the present invention further provides a chip, wherein the chip includes any one of the data operation units described above.
  • the present invention further provides a computing board for use in a computing device, wherein the computing board includes any one of the chips described above.
  • the present invention further provides a computing device including a power board, a control board, a connection board, a radiator, and a plurality of computing boards.
  • the control board is connected to the computing board through the connection board.
  • the heat sink is provided around the computing power board, and the power board is used to provide power to the connection board, the control board, the heat sink, and the computing board, wherein the computing power
  • the board is any one of the computing boards described above.
  • a relatively stable working voltage can be provided to a voltage domain to be supplied without requiring an auxiliary power supply. Not only reduces power consumption, but also reduces design difficulty, saves chip area, and reduces production costs.
  • FIG. 1 is a schematic diagram of an existing series power supply circuit
  • FIG. 2 is a schematic diagram of a series internal power supply system of an existing chip
  • FIG. 3 is a schematic structural diagram of a series power supply circuit without an on-chip passive power supply compensation circuit according to the present invention
  • FIG. 4 is a schematic diagram of an on-chip passive power supply compensation circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an on-chip passive power supply compensation circuit according to another embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an on-chip passive power supply compensation circuit according to another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of an on-chip passive power supply compensation circuit including a voltage stabilization unit according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of an on-chip passive power supply compensation circuit including a voltage stabilization unit according to another embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a data operation unit of the present invention.
  • FIG. 11 is a schematic diagram of a chip of the present invention.
  • FIG. 12 is a schematic diagram of a computing board according to the present invention.
  • FIG. 13 is a schematic diagram of a computing device of the present invention.
  • VDD1, VDD2, ... VDDn power terminals of the voltage domain
  • VSS1, VSS2, ... VSSn Ground terminal of voltage domain
  • VPP1, VPP2, ... VPPn power supply terminal of deep N-well
  • VBB1, VBB2, ... VBBn Ground terminal of deep N-well
  • VDD system power supply
  • GND system ground
  • G gate terminal B: substrate terminal
  • connection board 1002 control board
  • FIG. 3 is a schematic structural diagram of a series power supply circuit without an on-chip passive power supply compensation circuit according to the present invention.
  • n voltage domains 101-1, 101-2, ... 101-n to be powered are formed in the series power supply circuit 10, where n is a positive integer greater than 1.
  • Each voltage domain 101-1, 101-2 ... 101-n respectively realizes between different voltage domains through a corresponding deep N-well 102-1, 102-2 ... 102-n Isolation to avoid short circuits between different voltage domains.
  • a certain number of P-wells 103-1, 103-2, 103-n, and N-well 104-1 are formed in the deep N-wells 102-1, 102-2, and 102-n, respectively. , 104-2 ... 104-n.
  • Each voltage domain 101-1, 101-2 ... 101-n is formed with a PMOS transistor and / or an NMOS transistor. If necessary, other types of devices such as resistors and capacitors may be formed. Among them, PMOS transistors are formed in the N-wells 104-1, 104-2 ... 104-n, and NMOS transistors are formed in the P-wells 103-1, 103-2 ... 103-n. PMOS transistors and NMOS transistors are used to implement various functions of the chip.
  • Each of the voltage domains 101-1, 101-2 ... 101-n to be powered is connected in series between the system power VDD and the system ground GND in series.
  • the power terminal VDD1 of the voltage domain 101-1 is connected to the system power VDD
  • the ground terminal VSS1 of the voltage domain 101-1 is connected to the power terminal VDD2 of the next-level voltage domain 101-2
  • the ground terminal VSS2 of the voltage domain 101-2 is connected to the lower side.
  • the power supply terminal VDD3 of the first-level voltage domain 101-3 is connected in series to the next stage
  • the ground terminal VSSn of the voltage domain 101-n is connected to the system ground GND. This creates n voltage domains that are powered in series.
  • the PMOS transistor or NMOS transistor has four ports of S / D / G / B, which are called source terminal, drain terminal, gate terminal, and substrate terminal, respectively.
  • the substrate terminals and source terminals of the PMOS transistors in each voltage domain 101-1, 101-2 ... 101-n are connected to the power supply terminals VDD1, VDD2 ... of the voltage domain together. .. VDDn
  • the substrate terminal of the NMOS transistor and the source terminal are connected to the ground terminals VSS1, VSS2, ... VSSn of the voltage domain.
  • auxiliary power source that is, adding an auxiliary power source to each voltage domain to supply power to the voltage domain.
  • the invention provides an on-chip passive power supply compensation circuit based on a substrate reference, which can reduce the voltage drift across the voltage domain without increasing the auxiliary power supply.
  • FIG. 4 is a schematic diagram of an on-chip passive power compensation circuit according to an embodiment of the present invention.
  • the n passive voltage compensation circuits 100 on the chip of the present invention are formed with n voltage domains 101-1, 101-2, etc .. .101-n, where n is a positive integer greater than 1.
  • Each voltage domain 101-1, 101-2 ... 101-n respectively realizes between different voltage domains through a corresponding deep N-well 102-1, 102-2 ... 102-n Isolation to avoid short circuits between different voltage domains.
  • a certain number of P-wells 103-1, 103-2, 103-n, and N-well 104-1 are formed in the deep N-wells 102-1, 102-2, and 102-n, respectively. , 104-2 ... 104-n.
  • Each voltage domain 101-1, 101-2 ... 101-n is formed with a PMOS transistor and / or an NMOS transistor. If necessary, other types of devices such as resistors and capacitors may be formed. Among them, PMOS transistors are formed in the N-wells 104-1, 104-2 ... 104-n, and NMOS transistors are formed in the P-wells 103-1, 103-2 ... 103-n. PMOS transistors and NMOS transistors are used to implement various functions of the chip.
  • Each of the voltage domains 101-1, 101-2 ... 101-n to be powered is connected in series between the system power VDD and the system ground GND in series.
  • the power terminal VDD1 of the voltage domain 101-1 is connected to the system power VDD
  • the ground terminal VSS1 of the voltage domain 101-1 is connected to the power terminal VDD2 of the next-level voltage domain 101-2
  • the ground terminal VSS2 of the voltage domain 101-2 is connected to the lower side.
  • the power supply terminal VDD3 of the first-level voltage domain 101-3 is connected in series to the next stage, and the ground terminal VSSn of the voltage domain 101-n is connected to the system ground GND.
  • n voltage domains of series power supply are formed, and the power terminals of each of the voltage domains 101-1, 101-2, and 101-n are VDD1, VDD2, and VDDn, respectively. They are VSS1, VSS2 ... VSSn.
  • Deep N-wells 102-1, 102-2 ... 102-n are used to achieve isolation between different voltage domains.
  • the present invention also uses the body resistance 106 of the P-well and / or N-well to divide the system power supply VDD, and in the deep N-wells 102-1, 102-2 ... A partial pressure is generated across 102-n.
  • the power terminal VPP1 of the deep N-well 102-1 is connected to the system power supply VDD
  • the ground terminal VBB1 of the deep N-well 102-1 is connected to the power terminal VPP2 of the deep N-well 102-2
  • the deep N-well 102-2 the deep N-well 102-2.
  • the ground terminal VBB2 is connected to the power supply terminal VPP3 of the deep N-well 102-3 of the next stage, which is connected in series to the next stage in sequence; the ground VBBn of the deep N-well 102-n is connected to the system ground GND.
  • a deep N-well is formed between the system power VDD and the ground GND in series and the potential at both ends is relatively stable.
  • the power terminals of the deep N-wells 102-1, 102-2, ... 102-n are VPP1, respectively.
  • VPP2 ... VPPn, the ground ends are VBB1, VBB2 ... VBBn.
  • 102-n power supply terminals VPP1, VPP2 ... VPPn have the same voltage, voltage domains 101-1, 101-2 ... 101-n ground terminals VSS1, VSS2.
  • the voltages of VSSn are the same as the voltages of the ground terminals VBB1, VBB2, ..., VBBn of the deep N-wells 102-1, 102-2, ..., 102-n, respectively.
  • the source terminals of the PMOS transistors in each of the voltage domains 101-1, 101-2 ... 101-n are connected to the power supply terminals VDD1, VDD2 ... VDDn of the voltage domain.
  • the substrate terminal of the PMOS transistor is connected to the power supply terminals VPP1, VPP2 ... VPPn of the deep N-wells 102-1, 102-2, ... 102-n; each voltage domain 101-1, 101
  • the source terminal of the NMOS transistor in -2 ... 101-n is connected to the ground terminals VSS1, VSS2 ... VSSn of the voltage domain, and the substrate terminal of the NMOS transistor is connected to the deep N-well 102- 1, 102-2 ... 102-n ground terminals VBB1, VBB2 ... VBBn.
  • the on-chip passive power supply compensation circuit of the present invention further includes a switching transistor 105, which is an NMOS transistor and is formed in the voltage domains 101-2, 101-3 ... 101- (n-1) .
  • a switching transistor 105 which is an NMOS transistor and is formed in the voltage domains 101-2, 101-3 ... 101- (n-1) .
  • the drain terminal D of the switching transistor 105 in the voltage domain 101-2 is connected to the power supply terminal VDD1 of the previous voltage domain 101-1, and the source terminal S of the switching transistor 105 is connected to the voltage domain of this stage.
  • the power supply terminal VDD2 of 101-2, the gate terminal G of the switching transistor 105 are connected to the power supply terminal VPP2 of the deep N-well 102-2, and the substrate terminal B of the switching transistor 105 is connected to the ground of the deep N-well 102-2. ⁇ VBB2.
  • the gate terminal G and the substrate terminal B of the switching transistor 105 are connected to VPP2 and VBB2, respectively. Due to the influence of the gate capacitance and the substrate bulk capacitance, no current flows between the gate and the substrate, so that the potential of VPP2 remains stable. In an ideal case, the voltage VPP2 at the gate terminal G of the switching transistor 105 is greater than the voltage VBB2 at the substrate terminal B, and a conductive channel is formed in the substrate.
  • the conductive channel formed in the substrate is pinched off, and no current flows between the source terminal S and the drain terminal D.
  • FIG. 5 is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention. As shown in FIG. 5, the difference between this embodiment and the first embodiment lies in the type and connection method of the switching transistor 105 '.
  • the on-chip passive power supply compensation circuit 100 also includes a switching transistor 105 ′, which is a PMOS transistor and is formed in the voltage domains 101-2, 101-3, etc. 101- (n -1).
  • a switching transistor 105 ′ which is a PMOS transistor and is formed in the voltage domains 101-2, 101-3, etc. 101- (n -1).
  • the drain terminal D of the switching transistor 105 'in the voltage domain 101-2 is connected to the ground terminal VSS3 of the next-level voltage domain 101-3, and the source terminal S of the switching transistor 105' is connected to this
  • the ground terminal VSS2 of the stage voltage domain 101-2, the gate terminal G of the switching transistor 105 ' is connected to the ground terminal VBB2 of the deep N well 102-2, and the substrate terminal B of the switching transistor 105' is connected to the deep N well of the current stage. 102-2 power supply terminal VPP2.
  • the gate terminal G and the substrate terminal B of the switching transistor 105 ' are connected to VBB2 and VPP2, respectively. Due to the influence of the gate capacitance and the substrate bulk capacitance, no current flows between the gate and the substrate, so the potentials of VBB2 and VPP2 keep it steady. In an ideal case, the voltage VBB2 at the gate terminal G of the switching transistor 105 'is smaller than the voltage VPP2 at the substrate terminal B, and a conductive channel is formed in the substrate.
  • VSS2 When the VSS2 in this level voltage domain forms an overcurrent, the potential of VSS2 rises, that is, the voltage of the source terminal S of the switching transistor 105 'rises. Since the voltage VBB2 of the gate terminal G remains unchanged, a state of Vgs ⁇ 0 will be formed. .
  • the drain terminal D of the switching transistor 105 when the drain terminal D of the switching transistor 105 'is connected to the power supply terminal VDD3 of the next-level voltage domain, and the source terminal S is connected to the power supply terminal VDD2 of the current-level voltage domain, the power supply terminal VDD2 of the current-level voltage domain can be connected.
  • the potential is clamped in the range (VDD2 + V th ).
  • the first embodiment and the second embodiment only show the case where the switching transistor formed in the same voltage domain is one type, or is a PMOS transistor, or an NMOS transistor. In different cases, each voltage domain may be simultaneously A PMOS transistor and an NMOS transistor are formed as a switching transistor.
  • FIG. 6 is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention.
  • a switching transistor 105 and a switching transistor 105 ' are formed in the voltage domain 101-m.
  • the switching transistor 105 is an NMOS transistor, and its connection method is the same as that of the switching transistor 105 in the first embodiment;
  • the switching transistor 105 ' is a PMOS transistor, and its connection method is the same as that of the switching transistor 105' in the second embodiment.
  • the third embodiment shows a case where a PMOS transistor and an NMOS transistor are simultaneously formed as switching transistors in the same voltage domain. If only one set of switching transistors 105, 105 'is provided, when a large current change occurs in a nearby circuit, it can quickly compensate. However, when a large current change occurs in a circuit at a long distance, it cannot be compensated in time. It may happen that the power supply voltage of the entire voltage domain changes with the working current, and the circuit of the entire voltage domain may not work normally. In actual design and production, the number of switching transistors can be set to a plurality.
  • FIG. 7 is a schematic diagram of an on-chip passive power compensation circuit according to another embodiment of the present invention. As shown in FIG. 7, a plurality of switching transistors 105 and 105 ′ are formed in each stage of the voltage domain 101 of the on-chip passive power compensation circuit 100.
  • Each level of the voltage domain 101 has a certain spare area in addition to the area where the necessary devices are formed.
  • As many switching transistors 105 and 105 'as possible can be formed in the vacant region in the voltage domain 101, and the specific number can be determined according to the size of the vacant region in the voltage domain 101.
  • the formed plurality of switching transistors 105 and 105 ' may be arranged uniformly or non-uniformly.
  • the body resistance of the P-well and / or N-well will change due to the on and / or off of the transistor, and then the deep N-wells 102-1, 102-2 ... 102-
  • the voltage will change accordingly.
  • a voltage stabilizing unit is connected in parallel to both ends of the well and / or N-well body resistor 106.
  • FIG. 8 is a schematic diagram of an on-chip passive power supply compensation circuit including a voltage stabilization unit according to an embodiment of the present invention.
  • a voltage stabilizing unit 107 is connected in parallel across the power supply terminal VPPm and the ground terminal VBBm of the deep N-well 102-m. That is, it is equivalent to connecting a voltage stabilizing unit 107 in parallel at both ends of the P well body resistance.
  • the voltage stabilizing unit 107 may be one or more of a resistor, a capacitor, and a diode. The voltage stabilizing unit 107 is not necessary, and can be selected at both ends through the analog switch 108 to select whether to connect.
  • the voltages of the power supply terminals VDD1, VDD2 ... VDDn and the ground terminals VSS1, VSS2 ... VSSn of each voltage domain will change, and the power supply terminal VPP1 of the deep N-well
  • the voltages of VPP2 ... VPPn and the ground terminals VBB1, VBB2 ... VBBn remain relatively stable.
  • the voltages at VDD1, VDD2 ..., VDDn are the same as VPP1, VPP2 ..., VPPn
  • the voltages at VSS1, VSS2 ..., VSSn are VBB1, VBB2 ... VBBn has the same voltage.
  • FIG. 9 is a schematic diagram of an on-chip passive power supply compensation circuit including a voltage stabilization unit according to another embodiment of the present invention.
  • the m-th voltage domain 101-m of the on-chip passive power compensation circuit 100 is also taken as an example.
  • the embodiment shown in FIG. 9 is different from the embodiment shown in FIG. 8 in that the voltage domain 101-m is different.
  • An analog switch 108 is connected between the ground terminal VSSm of m and the ground terminal VBBm of the deep N well. Whether the VSSm and VBBm are connected can be determined by turning on or off the analog switch 108.
  • FIG. 10 is a schematic diagram of the data operation unit of the present invention.
  • the data operation unit 700 includes a control circuit 701, an operation circuit 702, a storage circuit 703, and one or more on-chip passive power supply compensation circuits 100 interconnected.
  • FIG. 11 is a schematic diagram of a chip of the present invention.
  • the chip 800 includes a control unit 801 and one or more data operation units 700.
  • the control unit 801 inputs data to the data operation unit 700 and processes the data output by the data operation unit 700.
  • FIG. 12 is a schematic diagram of the computing board of the present invention. As shown in FIG. 12, each hash board 900 includes one or more chips 800 to perform a hash operation on the work data issued by the mining pool.
  • FIG. 13 is a schematic diagram of a computing device of the present invention.
  • each computing device 1000 includes a connection board 1001, a control board 1002, a radiator 1003, a power board 1004, and one or more computing boards 900.
  • the control board 1002 is connected to the computing board 900 through a connection board 1001, and the radiator 1003 is disposed around the computing board 900.
  • the power board 1004 is used to provide power to the connection board 1001, the control board 1002, the radiator 1003, and the computing board 900.
  • the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding Changes and modifications should fall within the protection scope of the claims attached to the present invention.
  • the on-chip passive power supply compensation circuit and the computing unit, chip, computing board and computing device using the same have the following beneficial effects:
  • a relatively stable working voltage can be provided to the voltage domain to be supplied without the need for an auxiliary power source. This not only reduces power consumption, but also reduces design difficulty, saves chip area, and reduces production costs.

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Abstract

本发明提供一种片内无源电源补偿电路及应用其的运算单元、芯片、算力板和计算设备。片内无源电源补偿电路包括两个或两个以上待供电电压域,所述待供电电压域串联连接在电源和地之间;两个或两个以上的隔离区域,所述待供电电压域形成在所述隔离区域内,所述隔离区域用于隔离所述待供电电压域;所述隔离区域串联连接在所述电源和所述地之间;其中,还包括电源补偿单元,连接在所述待供电电压域和所述隔离区域之间,用于向所述待供电电压域提供电源补偿。本发明的片内无源电源补偿电路能够有效减小功耗,降低设计难度,节约芯片面积,降低生产成本。

Description

片内无源电源补偿电路及应用其的运算单元、芯片、算力板和计算设备 技术领域
本发明涉及一种多电压域供电电路,特别涉及一种基于衬底基准对电源电压进行补偿的电路及应用其的运算单元、芯片、算力板和计算设备。
背景技术
虚拟货币(如比特币、以太币)是一种P2P形式的数字货币,自2009年比特币系统推出以来就受到了广泛关注。该系统是基于区块链构建分布式共享总账,从而保证系统运行的安全、可靠以及去中心化。
在哈希运算和工作量证明上,比特币是基于计算得到的唯一正确的哈希值,来证明工作量从而获得记账打包区块权,因此获得奖励,这就是工作量证明(Pow)。目前除了暴力计算外,还没有有效的算法进行哈希运算。对于新一代用于挖掘虚拟数字货币的计算设备而言,挖矿过程就是进行大量重复性的逻辑计算流水线。
此种计算设备设计的核心在于性能功耗比,更高的性能以及更低的功耗表示挖矿的效率更高,同时意味着在相同的电力消耗下能够实现更多的算力。
另外,大量重复性的逻辑计算需要向计算设备提供较大的电流,这将导致除逻辑计算所需的功耗之外,计算设备的额外功耗也较大。因此,需要降低计算设备的工作电流,从而降低其额外功耗。
CN206039425U公开了一种串联供电电路,如图1所示,在供电端VCC与地之间串行连接多个封装单元,每个封装单元中分别包括一组或多组元件,每组元件包括一个相连接的待供电芯片和辅助电源单元,两组相邻元件中的待供电芯片之间分别串行连接一个信号电平转换单元。虽然该串联供电电路可以实现向每一待供电芯片提供低的电源电压,但其针对的是向印刷电路板上不同的封装单元提供串联供电,无法实现向芯片内部不同电压域之间的串联供电。
多电压域(Multi-supply voltage domain)供电技术越来越广泛的应用于片上芯片系统(System-on-chip,SoC)及多处理器计算结构中。在应用了多电压域技术的芯片中,该芯片通常含有多个独立的电压域或电压岛,并且每个电压域下的模块根据其时序的要求工作在恰当的电源电压下。一般来说,对于时 序比较关键的模块,它通常工作在高的电源电压下(VDDH)下,以满足芯片对速度性能的要求;而对于非关键的电路模块,它则工作在低的电源电压(VDDL)甚至亚阈值电源电压下,以降低芯片的功耗消耗和能量消耗。
CN206523836U公开了一种芯片内部串联供电系统,如图2所示,串联供电芯片中,每个待供电单元中可以分别包括一个芯片内核(core),或者,每个待供电单元中可以分别包括多个并行连接的芯片内核。每级电压域的芯片内核,其电路中分别包括P沟道金属氧化物半导体(P-channel Metal Oxide Semiconductor,PMOS)管和N沟道金属氧化物半导体(N-channel metal oxide semiconductor,NMOS)管。每级电压域的芯片内核,其PMOS管的衬底都是和本级电压域的电源电压或工作电压(VDD)相连,而本级电压域的VDD又和上一级电压域的地(VSS)相连,串联供电芯片中,还包括n个用于实现不同电压域之间隔离的深阱,这n个深阱相互独立设置,互不相连,n个待供电单元中的每个待供电单元分别位于一个深阱中,从而实现在同一芯片上不同电压域之间的隔离,有效避免了不同电压域之间形成短路。该芯片内部串联供电系统虽然实现了芯片内部不同电压域之间的串联供电,但是,每一电压域除了电源VDD进行供电之外,还需要额外提供辅助电压源VDD_1、VDD_2等,不仅辅助电压源设计困难,而且也会占用大量的芯片面积,产生较大功耗。
发明公开
为了解决上述问题,本发明提供一种基于衬底基准的片内无源电源补偿电路,上述电路不仅减小了功耗,还降低了设计难度,节约芯片面积,降低生产成本。
为了实现上述目的,本发明提供了一种片内无源电源补偿电路,包括:
两个或两个以上待供电电压域,所述待供电电压域串联连接在电源和地之间;
两个或两个以上的隔离区域,所述待供电电压域形成在所述隔离区域内,所述隔离区域用于隔离所述待供电电压域;
所述隔离区域串联连接在所述电源和所述地之间;
其中,还包括电源补偿单元,连接在所述待供电电压域和所述隔离区域之间,用于向所述待供电电压域提供电源补偿。
上述的片内无源电源补偿电路,其中,所述电源补偿单元通过工作在饱和状态向所述待供电电压域提供电源补偿。
上述的片内无源电源补偿电路,其中,在每一所述隔离区域两端形成第一电源端和第一地端,所述第一电源端和/或所述第一地端用于向所述电源补偿单元提供参考电压。
上述的片内无源电源补偿电路,其中,在每一所述待供电电压域两端形成第二电源端和第二地端,所述电源补偿单元向所述第二电源端和/或所述第二地端提供电源补偿。
上述的片内无源电源补偿电路,其中,以所述参考电压为基准,当所述第二电源端和/或所述第二地端的电压变化范围超过所述电源补偿单元的阈值时,所述电源补偿单元工作在所述饱和状态。
上述的片内无源电源补偿电路,其中,所述电源补偿单元为开关晶体管。
上述的片内无源电源补偿电路,其中,所述开关晶体管为PMOS开关晶体管和/或NMOS开关晶体管。
上述的片内无源电源补偿电路,其中,所述PMOS开关晶体管和/或所述NMOS开关晶体管为一个或多个。
上述的片内无源电源补偿电路,其中,所述待供电电压域中形成有一个或多个半导体器件,所述第二电源端和/或所述第二地端向所述半导体器件提供衬底偏压。
上述的片内无源电源补偿电路,其中,所述半导体器件包括PMOS晶体管和/或NMOS晶体管,所述第二电源端向所述PMOS晶体管提供衬底偏压,所述第二地端向所述NMOS晶体管提供衬底偏压。
上述的片内无源电源补偿电路,其中,还包括稳压单元,所述稳压单元并联连接在每一所述隔离区域两端。
上述的片内无源电源补偿电路,其中,在每一所述隔离区域两端形成第一电源端和第一地端,所述第一电源端和/或所述第一地端用于向所述电源补偿单元提供参考电压。
上述的片内无源电源补偿电路,其中,在每一所述待供电电压域两端形成第二电源端和第二地端,所述电源补偿单元向所述第二电源端和/或所述第二地端提供电源补偿。
上述的片内无源电源补偿电路,其中,所述稳压单元用于稳压所述第一电源端和/或所述第一地端的电压。
上述的片内无源电源补偿电路,其中,所述稳压单元包括电阻、电容或二极管中的一种或多种。
上述的片内无源电源补偿电路,其中,所述稳压单元直接连接在所述第一电源端以及所述第一地端之间,或通过模拟开关分别连接在所述第一电源端以及所述第一地端之间。
上述的片内无源电源补偿电路,其中,在所述第一地端以及所述第二地端之间设置一模拟开关。
为了实现上述目的,本发明还提供一种数据运算单元,其中,所述数据运算单元包括互联连接的控制电路、运算电路、存储电路,以及一个或多个片内无源电源补偿电路,其中,所述片内无源电源补偿电路为上述的任意一种片内无源电源补偿电路。
为了实现上述目的,本发明还提供一种芯片,其中,所述芯片包括上述的任意一种数据运算单元。
为了实现上述目的,本发明还提供一种用于计算设备中的算力板,其中,所述算力板包括上述的任意一种芯片。
为了实现上述目的,本发明还提供一种计算设备,包括电源板、控制板、连接板、散热器以及多个算力板,所述控制板通过所述连接板与所述算力板连接,所述散热器设置在所述算力板的周围,所述电源板用于向所述连接板、所述控制板、所述散热器以及所述算力板提供电源,其中,所述算力板为上述的任意一种所述算力板。
采用本发明的片内无源电源补偿电路,可以实现在不需要辅助电源的前提下,也可以向待供电电压域提供较为稳定的工作电压。不仅减小了功耗,还降低了设计难度,节约芯片面积,降低生产成本。
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
附图简要说明
图1为现有串联供电电路示意图;
图2为现有芯片内部串联供电系统示意图;
图3为本发明不含片内无源电源补偿电路的串联供电电路结构示意图;
图4为本发明一实施例的片内无源电源补偿电路示意图;
图5为本发明另一实施例的片内无源电源补偿电路示意图;
图6为本发明又一实施例的片内无源电源补偿电路示意图;
图7为本发明再一实施例的片内无源电源补偿电路示意图;
图8为本发明一实施例的含稳压单元的片内无源电源补偿电路示意图;
图9为本发明另一实施例的含稳压单元的片内无源电源补偿电路示意图;
图10为本发明数据运算单元示意图;
图11为本发明芯片示意图;
图12为本发明算力板示意图;
图13为本发明计算设备示意图。
其中,附图标记:
10:串联供电电路
100:片内无源电源补偿电路
101-1、101-2、......101-n:电压域
102-1、102-2、......102-n:深N阱
103-1、103-2、......103-n:P阱
104-1、104-2、......104-n:N阱
105、105’:开关晶体管
106:体电阻                107:稳压单元
108:模拟开关
VDD1、VDD2、......VDDn:电压域的电源端
VSS1、VSS2、......VSSn:电压域的地端
VPP1、VPP2、......VPPn:深N阱的电源端
VBB1、VBB2、......VBBn:深N阱的地端
VDD:系统电源             GND:系统地
S:源极端                 D:漏极端
G:栅极端                 B:衬底端
700-数据运算单元          701-控制电路
702-运算电路        703-存储电路
800:芯片           801:控制单元
900:算力板         1000:计算设备
1001:连接板        1002:控制板
1003:散热器        1004:电源板
实现本发明的最佳方式
下面结合附图对本发明的结构原理和工作原理作具体的描述:
在说明书及后续的权利要求当中使用了某些词汇来指称特定组件。所属领域中具有通常知识者应可理解,制造商可能会用不同的名词来称呼同一个组件。本说明书及后续的权利要求并不以名称的差异来作为区分组件的方式,而是以组件在功能上的差异来作为区分的准则。在整个说明书中,相同的附图标记表示相同的元件。
在通篇说明书及后续的权利要求当中所提及的“包括”和“包含”为一开放式的用语,故应解释成“包含但不限定于”。以外,“连接”一词在此为包含任何直接及间接的电性连接手段。间接的电性连接手段包括通过其它装置进行连接。
图3是本发明不含片内无源电源补偿电路的串联供电电路结构示意图。如图3所示,以芯片衬底为P型衬底为例,串联供电电路10内形成有n个待供电的电压域101-1、101-2......101-n,其中n为大于1的正整数。每一电压域101-1、101-2......101-n分别通过一个对应的深N阱102-1、102-2......102-n实现不同电压域之间的隔离,以避免不同电压域之间的短路。深N阱102-1、102-2......102-n内分别形成有一定数量的P阱103-1、103-2......103-n以及N阱104-1、104-2......104-n。
每一电压域101-1、101-2......101-n中都形成有PMOS晶体管和/或NMOS晶体管,如有必要,还可以形成电阻、电容等其他类型的器件。其中,PMOS晶体管在N阱104-1、104-2......104-n内形成,NMOS晶体管在P阱103-1、103-2......103-n内形成。PMOS晶体管及NMOS晶体管用于实现芯片的各种功能。
各待供电的电压域101-1、101-2......101-n依次串联连接在系统电源VDD以及系统地GND之间。电压域101-1的电源端VDD1连接系统电源VDD,电压 域101-1的地端VSS1连接至下一级电压域101-2的电源端VDD2,电压域101-2的地端VSS2连接至下一级电压域101-3的电源端VDD3,依次向下一级串联,电压域101-n的地端VSSn连接至系统地GND。由此形成了串联供电的n个电压域。
PMOS晶体管或NMOS晶体管具有S/D/G/B四个端口,分别称为源极端、漏极端、栅极端以及衬底端。通常情况下,各电压域101-1、101-2......101-n内的PMOS晶体管的衬底端与源极端一起连接至该电压域的电源端VDD1、VDD2......VDDn,NMOS晶体管的衬底端与源极端一起连接至该电压域的地端VSS1、VSS2......VSSn。当栅极端与衬底端之间的电压超过阈值电压时,会在衬底内形成源极端到漏极端的导电通道,使得载流子可以在源极端和漏极端之间的衬底内流动,形成电流。
当串联供电的n个电压域正常工作时,每一电压域的电源端VDD1、VDD2......VDDn以及地端VSS1、VSS2......VSSn的电位基本上保持稳定状态。当串联供电的n个电压域中的其中一个电压域101-m(1≤m≤n)发生大电流的情况下,由于电压域101-m自身电阻的原因,电压域101-m的两端形成较大的电压差,会导致其他未产生大电流的电压域两端的电压受到影响从而产生电源电压的漂移,随着电流的变化不断产生漂移,漂移与电流大小成正相关关系,从而可能造成芯片的功能失效。
为了避免上述情况的发生,一般都会采用增加辅助电源的方式进行改进,即在每一电压域上增加一个辅助电源向该电压域进行供电。本发明提供一种基于衬底基准的片内无源电源补偿电路,可以在不增加辅助电源的情况下减小电压域两端的电压漂移。
实施例一
图4为本发明一实施例的片内无源电源补偿电路示意图。如图4所示,以芯片衬底为P型衬底为例,本发明片内无源电源补偿电路100内形成有n个待供电的电压域101-1、101-2......101-n,其中n为大于1的正整数。每一电压域101-1、101-2......101-n分别通过一个对应的深N阱102-1、102-2......102-n实现不同电压域之间的隔离,以避免不同电压域之间的短路。深N阱102-1、102-2......102-n内分别形成有一定数量的P阱103-1、103-2......103-n以及N阱104-1、104-2......104-n。
每一电压域101-1、101-2......101-n中都形成有PMOS晶体管和/或NMOS晶体管,如有必要,还可以形成电阻、电容等其他类型的器件。其中,PMOS晶体管形成在N阱104-1、104-2......104-n内,NMOS晶体管形成在P阱103-1、103-2......103-n内。PMOS晶体管及NMOS晶体管用于实现芯片的各种功能。
各待供电的电压域101-1、101-2......101-n依次串联连接在系统电源VDD以及系统地GND之间。电压域101-1的电源端VDD1连接系统电源VDD,电压域101-1的地端VSS1连接至下一级电压域101-2的电源端VDD2,电压域101-2的地端VSS2连接至下一级电压域101-3的电源端VDD3,依次向下一级串联,电压域101-n的地端VSSn连接至系统地GND。由此形成了串联供电的n个电压域,每个电压域101-1、101-2......101-n的电源端分别为VDD1、VDD2......VDDn,地端分别为VSS1、VSS2......VSSn。
深N阱102-1、102-2......102-n用于实现不同电压域之间的隔离。除了形成上述的串联供电通路之外,本发明还利用P阱和/或N阱的体电阻106对系统电源VDD进行分压,在深N阱102-1、102-2......102-n的两端产生分压。其中,深N阱102-1的电源端VPP1连接至系统电源VDD,深N阱102-1的地端VBB1连接至下一级深N阱102-2的电源端VPP2,深N阱102-2的地端VBB2连接至下一级深N阱102-3的电源端VPP3,依次向下一级串联;深N阱102-n的地端VBBn连接至系统地GND。在系统电源VDD和地GND之间形成依次串联连接且两端电位相对稳定的深N阱,深N阱102-1、102-2......102-n的电源端分别为VPP1、VPP2......VPPn,地端分别为VBB1、VBB2......VBBn。
理想情况下,电压域101-1、101-2......101-n的电源端VDD1、VDD2......VDDn的电压分别与深N阱102-1、102-2......102-n的电源端VPP1、VPP2......VPPn的电压相同,电压域101-1、101-2......101-n的地端VSS1、VSS2......VSSn的电压分别与深N阱102-1、102-2......102-n的地端VBB1、VBB2......VBBn的电压相同。
在本实施例中,各电压域101-1、101-2......101-n内的PMOS晶体管的源极端连接至该电压域的电源端VDD1、VDD2......VDDn,PMOS晶体管的衬底端连接至深N阱102-1、102-2......102-n的电源端VPP1、VPP2......VPPn;各电压域101-1、101-2......101-n内的NMOS晶体管的源极端连接至该电压域的地端VSS1、VSS2......VSSn,NMOS晶体管的衬底端连接至深N阱102-1、 102-2......102-n的地端VBB1、VBB2......VBBn。
另外,本发明的片内无源电源补偿电路还包括开关晶体管105,开关晶体管105为NMOS晶体管,形成在电压域101-2、101-3......101-(n-1)中。以电压域101-2为例,电压域101-2中的开关晶体管105的漏极端D连接至上一级电压域101-1的电源端VDD1,开关晶体管105的源极端S连接至本级电压域101-2的电源端VDD2,开关晶体管105的栅极端G连接至本级深N阱102-2的电源端VPP2,开关晶体管105的衬底端B连接至本级深N阱102-2的地端VBB2。
开关晶体管105的栅极端G以及衬底端B分别连接至VPP2、VBB2,由于栅电容以及衬底体电容的影响,在栅和衬底之间不会流过电流,从而VPP2的电位保持稳定。在理想情况下,开关晶体管105栅极端G的电压VPP2大于衬底端B的电压VBB2,进而在衬底中形成了导电沟道。但是,由于开关晶体管漏极端D的电压VDD1大于栅极端G的电压VPP2,栅极端G的电压VPP2与源极端S的电压VDD2相同,即V d>V g=V s,也就是V gs=0,形成在衬底中的导电沟道夹断,在源极端S和漏极端D之间没有电流流过。
当本级电压域的电源VDD2供电不足时,VDD2的电压下降,即开关晶体管105源极端S的电压下降,由于栅极端G的电压VPP2保持不变,则会形成V gs>0的状态。由于V ds>V gs,当V gs=V th时,开关晶体管105开启并工作在饱和区,此时,开关晶体管105源极端S和漏极端D之间的电流为:I DS=[K*(W/L)*(V gs-V th) 2]/2。此时,漏极端D的VDD1给予源极端S的VDD2以充分的电荷补充,VDD2的电位将被箝位在(VPP2-V th),并不会进一步降低。
基于同样的道理,当开关晶体管105的漏极端D接上一级电压域的地端VSS1,源极端S接本级电压域的地端VSS2时,就可以将本级电压域VSS2的电位箝位在(VSS2-V th)范围内。
实施例二
图5为本发明另一实施例的片内无源电源补偿电路示意图。如图5所示,本实施例与实施例一的区别在于开关晶体管105’的类型及连接方式不同。
在本实施例中,片内无源电源补偿电路100同样包括开关晶体管105’,开关晶体管105’为PMOS晶体管,形成在电压域101-2、101-3......101-(n-1)中。以电压域101-2为例,电压域101-2中的开关晶体管105’的漏极端D连 接至下一级电压域101-3的地端VSS3,开关晶体管105’的源极端S连接至本级电压域101-2的地端VSS2,开关晶体管105’的栅极端G连接至本级深N阱102-2的地端VBB2,开关晶体管105’的衬底端B连接至本级深N阱102-2的电源端VPP2。
开关晶体管105’的栅极端G以及衬底端B分别连接至VBB2、VPP2,由于栅电容以及衬底体电容的影响,在栅和衬底之间不会流过电流,从而VBB2、VPP2的电位保持稳定。在理想情况下,开关晶体管105’栅极端G的电压VBB2小于衬底端B的电压VPP2,进而在衬底中形成了导电沟道。但是,由于开关晶体管105’漏极端D的电压VSS3低于栅极端G的电压VBB2,栅极端G的电压VBB2与源极端S的电压VSS2相同,即V d>V g=V s,也就是V gs=0,形成在衬底中的导电沟道夹断,在源极端S和漏极端D之间没有电流流过。
当本级电压域的VSS2形成过电流时,VSS2的电位上升,即开关晶体管105’源极端S的电压升高,由于栅极端G的电压VBB2保持不变,则会形成V gs<0的状态。开关晶体管105’的阈值电压为V th,由于V ds>V gs,当V gs=V th时,开关晶体管105’开启并工作在饱和区,此时,开关晶体管105’源极端S和漏极端D之间的电流为:I DS=[K*(W/L)*(V gs-V th) 2]/2。此时,漏极端D的VSS3给予源极端S的VSS2以充分的电荷泄放,VSS2的电位将被箝位在(VSS2+V th)范围内,并不会进一步升高。
基于同样的道理,当开关晶体管105’的漏极端D接下一级电压域的电源端VDD3,源极端S接本级电压域的电源端VDD2时,就可以将本级电压域电源端VDD2的电位箝位在(VDD2+V th)范围内。
实施例三
实施例一以及实施例二仅仅示出了同一电压域中形成的开关晶体管为一种类型,或者为PMOS晶体管,或者为NMOS晶体管的情形,在不同的情况下,每一电压域中还可以同时形成PMOS晶体管以及NMOS晶体管作为开关晶体管。
图6为本发明又一实施例的片内无源电源补偿电路示意图。如图6所示,以片内无源电源补偿电路100的第m级电压域101-m为例,在电压域101-m中形成了开关晶体管105以及开关晶体管105’。其中,开关晶体管105为NMOS晶体管,其连接方式与实施例一中开关晶体管105的连接方式相同;开关晶体管105’为PMOS晶体管,其连接方式与实施例二中开关晶体管105’的连接方式 相同。
实施例四
实施例三示出了在同一电压域中同时形成一个PMOS晶体管以及一个NMOS晶体管作为开关晶体管的情形。如果仅设置一组开关晶体管105、105’时,当其临近的电路发生较大的电流变化时,其可以迅速进行补偿。但距离较远位置处的电路发生大电流变化时,其不能及时进行补偿,有可能发生整个电压域的电源电压随着工作电流产生变化,进而导致整个电压域的电路不能正常工作。在实际设计以及生产中,可以将开关晶体管的数量设置为多个。
图7为本发明再一实施例的片内无源电源补偿电路示意图。如图7所示,片内无源电源补偿电路100的每一级电压域101中均形成了多个开关晶体管105、105’。
每一级电压域101中除了形成必要器件的区域外,还具有一定的空余区域。为了快速对临近电路提供电源补偿并提高电源补偿能力,可以在电压域101中的空余区域尽可能多的形成开关晶体管105、105’,具体数量可以根据电压域101中空余区域的大小决定。其中,形成的多个开关晶体管105、105’既可以均匀排布,也可以非均匀排布。
实施例五
在电路实际工作中,由于晶体管的导通和/或关闭,会导致P阱和/或N阱的体电阻发生变化,进而深N阱102-1、102-2......102-n的电源端VPP1、VPP2......VPPn的电压以及深N阱102-1、102-2......102-n的地端VBB1、VBB2......VBBn的电压也会随之发生变化。为了保证VPP1、VPP2......VPPn的电压以及VBB1、VBB2......VBBn电压的稳定,需要保证P阱和/或N阱的体电阻保持相对恒定的状态,可以在P阱和/或N阱体电阻106的两端并联一稳压单元。
图8为本发明一实施例的含稳压单元的片内无源电源补偿电路示意图。如图8所示,以片内无源电源补偿电路100的第m级电压域101-m为例,在深N阱102-m的电源端VPPm以及地端VBBm两端并联一稳压单元107,即相当于在P阱体电阻两端并联一稳压单元107,稳压单元107可以是电阻、电容以及二极管中的一种或多种。稳压单元107并非必须的,可以在两端通过模拟开关108进行选择是否连接。
实施例六
在电路实际工作过程中,各电压域的电源端VDD1、VDD2......VDDn以及地端VSS1、VSS2......VSSn的电压会发生变化,而深N阱的电源端VPP1、VPP2......VPPn以及地端VBB1、VBB2......VBBn的电压保持相对稳定。理想状态下VDD1、VDD2......VDDn端的电压与VPP1、VPP2......VPPn相同,VSS1、VSS2......VSSn端的电压与VBB1、VBB2......VBBn的电压相同。
图9为本发明再一实施例的含稳压单元的片内无源电源补偿电路示意图。如图9所示,同样以片内无源电源补偿电路100的第m级电压域101-m为例,图9所示的实施例与图8所示实施例的区别在于,电压域101-m的地端VSSm与深N阱的地端VBBm之间连接有一模拟开关108,可以通过模拟开关108的开通或关闭决定VSSm与VBBm之间是否连通。
本发明还提供一种数据运算单元,图10为本发明数据运算单元示意图。如图10所示,数据运算单元700包括互联连接的控制电路701、运算电路702、存储电路703,以及一个或多个片内无源电源补偿电路100。
本发明还提供一种芯片,图11为本发明芯片示意图。如图11所示,芯片800包括控制单元801,以及一个或多个数据运算单元700。控制单元801向数据运算单元700输入数据并将数据运算单元700输出的数据进行处理。
本发明还提供一种算力板,图12为本发明算力板示意图。如图12所示,每一个算力板900上包括一个或多个芯片800,对矿池下发的工作数据进行哈希运算。
本发明还提供一种计算设备,所述计算设备优选用于挖掘虚拟数字货币的运算,当然所述计算设备也可以用于其他任何海量运算。图13为本发明计算设备示意图。如图13所示,每一个计算设备1000包括连接板1001、控制板1002、散热器1003、电源板1004,以及一个或多个算力板900。控制板1002通过连接板1001与算力板900连接,散热器1003设置在算力板900的周围。电源板1004用于向所述连接板1001、控制板1002、散热器1003以及算力板900提供电源。
需要说明的是,在本发明的描述中,术语“横向”、“纵向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,并不是指示或暗示所指的装置 或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。
尽管本发明的实施方案已公开如上,但其并不仅仅限于说明书和实施方式中所列运用,它完全可以被适用于各种适合本发明的领域,对于熟悉本领域的人员而言,可容易地实现另外的修改,因此在不背离权利要求及等同范围所限定的一般概念下,本发明并不限于特定的细节和这里示出与描述的图例。
换言之,本发明还可有其它多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
工业应用性
采用本发明的片内无源电源补偿电路及应用其的运算单元、芯片、算力板和计算设备,具有以下有益效果:
可以实现在不需要辅助电源的前提下,也可以向待供电电压域提供较为稳定的工作电压。这不仅减小了功耗,还降低了设计难度,节约芯片面积,减少生产成本。

Claims (21)

  1. 一种片内无源电源补偿电路,其特征在于,包括:
    两个或两个以上待供电电压域,所述待供电电压域串联连接在电源和地之间;
    两个或两个以上的隔离区域,所述待供电电压域形成在所述隔离区域内,所述隔离区域用于隔离所述待供电电压域;
    所述隔离区域串联连接在所述电源和所述地之间;
    其中,还包括电源补偿单元,连接在所述待供电电压域和所述隔离区域之间,用于向所述待供电电压域提供电源补偿。
  2. 如权利要求1所述的片内无源电源补偿电路,其特征在于:所述电源补偿单元通过工作在饱和状态向所述待供电电压域提供电源补偿。
  3. 如权利要求2所述的片内无源电源补偿电路,其特征在于:在每一所述隔离区域两端形成第一电源端和第一地端,所述第一电源端和/或所述第一地端用于向所述电源补偿单元提供参考电压。
  4. 如权利要求3所述的片内无源电源补偿电路,其特征在于:在每一所述待供电电压域两端形成第二电源端和第二地端,所述电源补偿单元向所述第二电源端和/或所述第二地端提供电源补偿。
  5. 如权利要求4所述的片内无源电源补偿电路,其特征在于:以所述参考电压为基准,当所述第二电源端和/或所述第二地端的电压变化范围超过所述电源补偿单元的阈值时,所述电源补偿单元工作在所述饱和状态。
  6. 如权利要求5所述的片内无源电源补偿电路,其特征在于:所述电源补偿单元为开关晶体管。
  7. 如权利要求6所述的片内无源电源补偿电路,其特征在于:所述开关晶体管为PMOS开关晶体管和/或NMOS开关晶体管。
  8. 如权利要求7所述的片内无源电源补偿电路,其特征在于:所述PMOS开关晶体管和/或所述NMOS开关晶体管为一个或多个。
  9. 如权利要求8所述的片内无源电源补偿电路,其特征在于:所述待供电电压域中形成有一个或多个半导体器件,所述第一电源端和/或所述第一地端向所述半导体器件提供衬底偏压。
  10. 如权利要求9所述的片内无源电源补偿电路,其特征在于:所述半导体器件包括PMOS晶体管和/或NMOS晶体管,所述第一电源端向所述PMOS晶体管提供衬底偏压,所述第一地端向所述NMOS晶体管提供衬底偏压。
  11. 如权利要求1所述的片内无源电源补偿电路,其特征在于:还包括稳压单元,所述稳压单元并联连接在每一所述隔离区域两端。
  12. 如权利要求11所述的片内无源电源补偿电路,其特征在于:在每一所述隔离区域两端形成第一电源端和第一地端,所述第一电源端和/或所述第一地端用于向所述电源补偿单元提供参考电压。
  13. 如权利要求12所述的片内无源电源补偿电路,其特征在于:在每一所述待供电电压域两端形成第二电源端和第二地端,所述电源补偿单元向所述第二电源端和/或所述第二地端提供电源补偿。
  14. 如权利要求13所述的片内无源电源补偿电路,其特征在于:所述稳压单元用于稳压所述第一电源端和/或所述第一地端的电压。
  15. 如权利要求14所述的片内无源电源补偿电路,其特征在于:所述稳压单元包括电阻、电容或二极管中的一种或多种。
  16. 如权利要求15所述的片内无源电源补偿电路,其特征在于:所述稳压单元直接连接在所述第一电源端以及所述第一地端之间,或通过模拟开关分别连接在所述第一电源端以及所述第一地端之间。
  17. 如权利要求16所述的片内无源电源补偿电路,其特征在于:在所述第一地端以及所述第二地端之间设置一模拟开关。
  18. 一种数据运算单元,包括互联连接的控制电路、运算电路、存储电路,以及一个或多个片内无源电源补偿电路,其特征在于:所述片内无源电源补偿电路为权利要求1-17中任意一种所述的片内无源电源补偿电路。
  19. 一种芯片,其特征在于,包括至少一个权利要求18中所述的任意一种数据运算单元。
  20. 一种用于计算设备中的算力板,其特征在于,包括多个权利要求19中所述的任意一种所述芯片。
  21. 一种计算设备,包括电源板、控制板、连接板、散热器以及多个算力板,所述控制板通过所述连接板与所述算力板连接,所述散热器设置在所述算力板的周围,所述电源板用于向所述连接板、所述控制板、所述散热器以及所 述算力板提供电源,其中,所述算力板为权利要求20所述的任意一种所述算力板。
PCT/CN2019/090434 2018-09-20 2019-06-06 片内无源电源补偿电路及应用其的运算单元、芯片、算力板和计算设备 WO2020057180A1 (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11442517B2 (en) * 2018-09-20 2022-09-13 Canaan Creative Co., Ltd. On-chip passive power supply compensation circuit and operation unit, chip, hash board and computing device using same
US20230100033A1 (en) * 2020-06-12 2023-03-30 Shenzhen Microbt Electronics Technology Co., Ltd. Control circuit of large data processing device system for virtual currency and large data processing device for virtual currency
EP4254132A4 (en) * 2020-11-25 2024-10-16 Bitmain Tech Inc CHIP POWER SUPPLY CIRCUIT AND ELECTRONIC DEVICE

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109086130B (zh) * 2018-06-06 2022-06-10 北京嘉楠捷思信息技术有限公司 计算设备的芯片调频方法、装置、算力板、计算设备及存储介质
CN108809068A (zh) * 2018-06-29 2018-11-13 北京嘉楠捷思信息技术有限公司 电压跟随串联供电电路
CN114201024A (zh) * 2020-09-17 2022-03-18 深圳比特微电子科技有限公司 串联供电电路和虚拟货币挖矿机设备
TWI843415B (zh) * 2023-01-18 2024-05-21 大陸商星宸科技股份有限公司 故障安全輸入輸出裝置與電壓切換方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105045364A (zh) * 2015-07-21 2015-11-11 北京比特大陆科技有限公司 串联供电电路、虚拟数字币挖矿机和计算机服务器
CN206039425U (zh) * 2016-07-29 2017-03-22 北京比特大陆科技有限公司 供电电路、虚拟数字币挖矿机和计算机服务器
CN106774767A (zh) * 2016-12-16 2017-05-31 算丰科技(北京)有限公司 串联供电芯片和系统、虚拟数字币挖矿机、及服务器
US20180089642A1 (en) * 2016-09-23 2018-03-29 Intel Corporation Bitcoin mining hardware accelerator with optimized message digest and message scheduler datapath
CN208861201U (zh) * 2018-09-20 2019-05-14 北京嘉楠捷思信息技术有限公司 片内无源电源补偿电路及应用其的运算单元、芯片、算力板和计算设备
CN209182771U (zh) * 2018-10-16 2019-07-30 北京嘉楠捷思信息技术有限公司 片内串联供电系统及应用其的运算单元、芯片、算力板和计算设备

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US7046568B2 (en) * 2002-09-24 2006-05-16 Sandisk Corporation Memory sensing circuit and method for low voltage operation
US6760248B2 (en) * 2002-10-09 2004-07-06 Infineon Technologies Ag Voltage regulator with distributed output transistor
US7358771B1 (en) * 2006-03-06 2008-04-15 Advanced Micro Devices, Inc. System including a single ended switching topology for high-speed bidirectional signaling
US9741417B1 (en) * 2016-10-14 2017-08-22 Nxp Usa, Inc. Sense amplifier circuit
CN206523836U (zh) 2016-12-16 2017-09-26 算丰科技(北京)有限公司 串联供电芯片和系统
US10230370B2 (en) * 2017-04-25 2019-03-12 Ati Technologies Ulc Data transmission with power supply noise compensation
KR102475892B1 (ko) * 2017-07-26 2022-12-08 삼성전자주식회사 집적 회로, 집적 회로에게 전력을 공급하는 방법 및 시스템
WO2020057180A1 (zh) * 2018-09-20 2020-03-26 北京嘉楠捷思信息技术有限公司 片内无源电源补偿电路及应用其的运算单元、芯片、算力板和计算设备
CN111142641A (zh) * 2018-10-16 2020-05-12 北京嘉楠捷思信息技术有限公司 片内串联供电系统及应用其的运算单元、芯片、算力板和计算设备
US10742116B2 (en) * 2018-11-29 2020-08-11 Nxp Usa, Inc. High voltage regulator using low voltage devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105045364A (zh) * 2015-07-21 2015-11-11 北京比特大陆科技有限公司 串联供电电路、虚拟数字币挖矿机和计算机服务器
CN206039425U (zh) * 2016-07-29 2017-03-22 北京比特大陆科技有限公司 供电电路、虚拟数字币挖矿机和计算机服务器
US20180089642A1 (en) * 2016-09-23 2018-03-29 Intel Corporation Bitcoin mining hardware accelerator with optimized message digest and message scheduler datapath
CN106774767A (zh) * 2016-12-16 2017-05-31 算丰科技(北京)有限公司 串联供电芯片和系统、虚拟数字币挖矿机、及服务器
CN208861201U (zh) * 2018-09-20 2019-05-14 北京嘉楠捷思信息技术有限公司 片内无源电源补偿电路及应用其的运算单元、芯片、算力板和计算设备
CN209182771U (zh) * 2018-10-16 2019-07-30 北京嘉楠捷思信息技术有限公司 片内串联供电系统及应用其的运算单元、芯片、算力板和计算设备

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11442517B2 (en) * 2018-09-20 2022-09-13 Canaan Creative Co., Ltd. On-chip passive power supply compensation circuit and operation unit, chip, hash board and computing device using same
US20230100033A1 (en) * 2020-06-12 2023-03-30 Shenzhen Microbt Electronics Technology Co., Ltd. Control circuit of large data processing device system for virtual currency and large data processing device for virtual currency
EP4254132A4 (en) * 2020-11-25 2024-10-16 Bitmain Tech Inc CHIP POWER SUPPLY CIRCUIT AND ELECTRONIC DEVICE

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