WO2022105322A1 - 测试方法及测试系统 - Google Patents

测试方法及测试系统 Download PDF

Info

Publication number
WO2022105322A1
WO2022105322A1 PCT/CN2021/112768 CN2021112768W WO2022105322A1 WO 2022105322 A1 WO2022105322 A1 WO 2022105322A1 CN 2021112768 W CN2021112768 W CN 2021112768W WO 2022105322 A1 WO2022105322 A1 WO 2022105322A1
Authority
WO
WIPO (PCT)
Prior art keywords
time
time node
calibration
node
maximum value
Prior art date
Application number
PCT/CN2021/112768
Other languages
English (en)
French (fr)
Inventor
徐景宏
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/453,001 priority Critical patent/US11810639B2/en
Publication of WO2022105322A1 publication Critical patent/WO2022105322A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current

Definitions

  • the present application relates to the field of memory performance testing, and in particular, to a testing method and a testing system.
  • the resistance value of the pull-up resistor and the pull-down resistor at the output end will affect the integrity of the output signal.
  • ZQ calibration is usually used to adjust the resistance value of the pull-up resistor and the resistance value of the pull-down resistor, so as to adjust the output pull-up and/or output pull-down capability. It can be seen that, for the performance test of the memory, the specific time when the memory performs ZQ calibration can also be used as an important indicator for evaluating the performance of the memory.
  • the embodiments of the present disclosure provide a test method and a test system, which can conveniently and accurately obtain the time when the memory performs ZQ calibration in a low-cost manner.
  • an embodiment of the present disclosure provides a test method for obtaining the ZQ calibration time of the memory to be tested.
  • the memory to be tested includes a ZQ calibration module, a terminating resistor and a DQ terminal, one end of the terminating resistor is connected to the working voltage terminal, and the other One end is connected to the DQ end, and the ZQ calibration module is used to control the resistance value of the termination resistor connected to the working voltage end to the DQ end, including: providing an initialization command to the ZQ calibration module, so that the resistance value of the termination resistor is the first maximum value; to the ZQ calibration The module provides a ZQ calibration command, so that the resistance value of the termination resistor increases or decreases from the first maximum value to the second maximum value, one of the first maximum value and the second maximum value is the maximum value, and the other is the minimum value; get The first time node, the first time node is the sending time of the ZQ calibration command; the second time node is obtained, and the second time node is the time when the
  • the termination resistance of the memory to be tested is changed to a maximum value by the initialization command, and then the termination resistance of the memory to be tested is changed to another maximum value by the ZQ calibration command, and the change of the termination resistance is the largest at this time.
  • the actual running time of the ZQ calibration can be accurately characterized. Then, according to the time node when the ZQ calibration command is sent and the time node when the resistance value change of the termination resistor is completed, the time when the memory to be tested performs ZQ calibration is read out.
  • An embodiment of the present disclosure further provides a testing system, which is applied to a testing machine, and the testing machine includes: a sending unit, configured to provide an initialization command and a ZQ calibration command to a memory to be tested; a first obtaining unit, configured to obtain a first time node, the first time node is the time when the sending unit sends the ZQ calibration command; the second acquisition unit is used to obtain the second time node, and the second time node is the time when the termination resistance of the memory to be tested changes to the second maximum value; processing The unit is configured to acquire the ZQ calibration time of the memory to be tested according to the second time node and the first time node.
  • the initializing command is provided to the memory to be tested by the testing machine to change the termination resistance of the memory to be tested to a maximum value
  • the ZQ calibration command is provided to the memory to be tested through the testing machine to change the termination resistance of the memory to be tested. It becomes another maximum value, and the change of the termination resistance is the largest at this time, which can accurately characterize the actual progress time of the ZQ calibration of the memory to be calibrated. Then, according to the time node when the ZQ calibration command is sent and the time node when the resistance value change of the termination resistor is completed, the time when the memory to be tested performs ZQ calibration is read out.
  • FIG. 1 and 2 are schematic flowcharts of the testing method provided by the first embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a memory to be tested provided by the first embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a testing system provided by a second embodiment of the present disclosure.
  • the first embodiment of the present disclosure provides a test method for obtaining the ZQ calibration time of the memory to be tested, the memory to be tested includes a ZQ calibration module, a termination resistor and a DQ terminal, and one end of the termination resistor is connected to the working voltage terminal.
  • the other end is connected to the DQ end
  • the ZQ calibration module is used to control the resistance value of the termination resistor connected to the working voltage end to the DQ end, including: providing an initialization command to the ZQ calibration module, so that the resistance value of the termination resistor is the first maximum value;
  • the ZQ calibration module provides the ZQ calibration command, so that the resistance value of the termination resistor increases or decreases from the first maximum value to the second maximum value, one of the first maximum value and the second maximum value is the maximum value, and the other is the minimum value
  • Obtain the second time node, the second time node is the time when the resistance value of the termination resistor changes to the second maximum value; Based on the second time node and At the first time node, obtain the ZQ calibration time.
  • FIGS. 4 to 8 are the first embodiment of the present disclosure.
  • a schematic diagram of the provided test method the following will describe the test method provided in this embodiment in detail with reference to the accompanying drawings.
  • the test method is used to obtain the ZQ calibration time of the memory to be tested 200.
  • the memory to be tested 200 includes a ZQ calibration module 201, a termination resistor 202, and a DQ terminal 204.
  • One end of the termination resistor 202 is connected to the working voltage terminal 203, and the other end is connected to the working voltage terminal 203.
  • the DQ terminal 204 and the ZQ calibration module 201 are used to control the resistance value of the termination resistor 202 connected to the working voltage terminal 203 to the DQ terminal 204 .
  • test method includes the following steps:
  • Step 101 providing an initialization command.
  • an initialization command is provided to the ZQ calibration module 201, so that the resistance value of the termination resistor 202 is the first maximum value.
  • Step 102 providing a ZQ calibration command.
  • a ZQ calibration command is provided to the ZQ calibration module, so that the resistance value of the termination resistor increases or decreases from the first maximum value to the second maximum value, one of the first maximum value and the second maximum value is the maximum value, and the other One is the minimum value.
  • the first maximum value is the minimum value and the second maximum value is the maximum value, which does not constitute a limitation on this embodiment. In other embodiments, the first maximum value may be used.
  • the value is the maximum value, and the second minimum value is the minimum value.
  • the ZQ calibration module 201 is designed for an existing unit of an existing semiconductor memory, and is used to respond to a ZQ calibration command and perform ZQ calibration on the semiconductor memory.
  • the ZQ pin of the semiconductor memory is connected to a reference resistor, and the reference resistance is usually a 240 ohm resistor.
  • the ZQ calibration module 201 compares the output pull-up resistance and output pull-down resistance inside the semiconductor memory with the reference resistance.
  • the termination resistor 202 in FIG. 3 does not refer to a single resistor, but represents a set of output resistors connected to the DQ terminal 204 by the output driver.
  • the initialization command is used to set the termination resistance 202 to the minimum value, and then through the ZQ calibration command, the memory starts to perform ZQ calibration, and the termination resistance 202 is increased to the maximum value.
  • the termination resistance 202 increases to the maximum value, the memory is completed.
  • the actual time when the memory executes the ZQ calibration command can be accurately represented by the time when the ZQ calibration command is issued and the time when the termination resistance 202 changes to the maximum value.
  • Step 103 acquiring a first time node.
  • the first time node is the sending time of the ZQ calibration command.
  • the current time is obtained as the first time node, and the time required for the ZQ calibration command to be transmitted from the external device to the memory under test is negligible.
  • the sending time of the ZQ calibration command is obtained as the first or time node t1.
  • step 104 acquiring a second time node.
  • the second time node is the time when the resistance value of the termination resistor 202 changes to the second maximum value.
  • the change of the resistance value of the termination resistor 202 is monitored in real time, and when the resistance value of the termination resistor 202 changes to the maximum value, the current time is obtained as the second time node.
  • the second time node is obtained by detecting the output voltage of the DQ terminal 204.
  • the second time node is the time node when the output voltage of the DQ terminal changes to the second maximum value.
  • One end of the terminating resistor R tt is connected to the working voltage terminal, and the other end is connected to the DQ terminal.
  • the terminating resistor divides the voltage V DD of the working voltage terminal, that is, the larger the resistance value loaded on the terminating resistor R tt , the more the terminating resistor R tt is loaded. The larger the voltage across tt , the smaller the output voltage V DQ (relative to ground voltage V SS ) at DQ.
  • the voltage loaded on both ends of the terminating resistor R tt also reaches the maximum value.
  • the output voltage V DQ of the DQ terminal is the minimum value, that is, the output voltage V through the DQ terminal
  • the second time node t2 is acquired.
  • the method for obtaining the second time node includes: dividing the output voltage of the DQ terminal into a first level and a second level, the first level satisfies the preset range of the second maximum value, and the second level If the level does not meet the preset range of the second maximum value, the transition time between the first level and the second level is obtained, and the transition time is used as the second time node t2.
  • the resistance value of the termination resistor R tt changes from the minimum value to the maximum value.
  • the output voltage V DQ of the DQ terminal changes from the maximum value to the minimum value.
  • the range is divided into the first level and the second level.
  • 0.95V DQ ⁇ V DQ actual voltage ⁇ 1.00V DQ the V DQ actual voltage is the second level; when the V DQ actual voltage ⁇ 0.95V DQ , the V DQ The actual voltage is the first level.
  • a jumping time point occurs, and the jumping time node is used as the second time node to simply and accurately obtain the time node at which V DQ changes to the minimum value.
  • Step 105 Obtain the ZQ calibration time based on the first time node and the second time node.
  • the time difference between the second time node and the first time node is used as the ZQ calibration time of the memory to be tested.
  • step 105 specifically includes:
  • Step 115 Obtain a third time node.
  • the third time node is the time when the resistance value of the termination resistor 202 starts to change.
  • the third time node is obtained by detecting the output voltage of the DQ terminal 204.
  • the third time node is the time node at which the output voltage of the DQ terminal begins to change. Refer to FIG. 4 for its principle. One end of tt is connected to the V DD end, and the other end is connected to the DQ end.
  • the termination resistor divides the voltage of V DD , that is, the greater the resistance value loaded on the termination resistor R tt , the greater the voltage loaded on both ends of the termination resistor R tt .
  • the output voltage V DQ of the DQ terminal is smaller.
  • the change of the resistance value of the terminating resistor 202 is monitored in real time, and when the resistance value of the terminating resistor 202 changes, the current time is obtained as the third time node.
  • Step 125 Obtain the calibration code generation time based on the third time node and the first time node.
  • the calibration code generation time is that the ZQ calibration module 201 compares the resistance value of the output pull-up resistor and the output pull-down resistor inside the semiconductor memory with the resistance value of the reference resistor, so that the resistance value of the output pull-up resistor and the output pull-down resistor is the same as the resistance value of the reference resistor. match and generate the corresponding calibration code at the time of this process.
  • Step 135 Obtain the calibration code transfer time based on the second time node and the third time node.
  • the calibration code transfer time is the process of sending the calibration code to the termination resistor 202 of the DQ terminal 204 , that is, the output driver is connected to the output resistor of the DQ terminal 204 , and adjusts the process time of the termination resistor 202 according to the calibration code.
  • the resistance change of the termination resistor 202 is obtained by detecting the change of the output voltage V DQ of the DQ terminal 204 , which does not constitute a limitation of this embodiment.
  • the resistance change of the termination resistor R tt can also be obtained according to the change of the voltage V Rtt loaded at both ends of the termination resistor R tt .
  • FIG. 7 for its schematic diagram.
  • the resistance value of the termination resistor R tt is the minimum value
  • the voltage V Rtt loaded across the termination resistor R tt is also the minimum value
  • the voltage V Rtt loaded across the termination resistor R tt increases accordingly
  • the termination resistor R tt increases
  • the voltage V Rtt applied to both ends of the termination resistor R tt is also the maximum value.
  • the resistance change of the terminating resistor R tt can also be obtained according to the change of the current I Rtt passing through the terminating resistor R tt .
  • FIG. 8 for the schematic diagram.
  • the resistance value of the terminating resistor R tt is the minimum value
  • the terminating resistor R tt The current I Rtt is the maximum value; with the increase of the resistance value of the termination resistor R tt , the current value I Rtt through the termination resistor R tt decreases; when the resistance value of the termination resistor R tt is the maximum value, through the termination resistor R tt
  • the current I Rtt of R tt is the minimum value.
  • the termination resistance of the memory to be tested is changed to a maximum value by the initialization command, and then the termination resistance of the memory to be tested is changed to another maximum value by the ZQ calibration command, and the change of the termination resistance is the largest at this time. , which can accurately characterize the actual progress time of ZQ calibration. Then, according to the time node when the ZQ calibration command is sent and the time node when the resistance value change of the termination resistor is completed, the time when the memory to be tested performs ZQ calibration is read out.
  • the second embodiment of the present disclosure relates to a test system, which is applied to a test machine, and the test machine includes: a sending unit for providing an initialization command and a ZQ calibration command to a memory to be tested; a first obtaining unit for obtaining a first Time node, the first time node is the time when the sending unit sends the ZQ calibration command; the second acquisition unit is used to obtain the second time node, and the second time node is the time when the termination resistance of the memory to be tested changes to the second maximum value;
  • the processing unit is configured to acquire the ZQ calibration time of the memory to be tested according to the second time node and the first time node.
  • FIG. 9 is a schematic structural diagram of the test system provided by the second embodiment of the present disclosure.
  • the test system provided by the present embodiment will be described in detail below with reference to the accompanying drawings. The parts that are the same as or corresponding to the first embodiment will not be described in detail below. .
  • the testing system includes a testing machine 300 and a memory to be tested 200 .
  • the memory to be tested 200 includes a ZQ calibration module 201, a termination resistor 202, and a DQ terminal 204.
  • One end of the termination resistor 202 is connected to the working voltage terminal 203, and the other end is connected to the DQ terminal 204.
  • the ZQ calibration module 201 is used to control the connection of the termination resistor 202.
  • Test machine 300 including:
  • the sending unit 301 is configured to provide an initialization command and a ZQ calibration command to the memory under test 200 .
  • the first obtaining unit 312 is configured to obtain a first time node, where the first time node is the time when the sending unit 301 sends the ZQ calibration command.
  • the second obtaining unit 322 is configured to obtain a second time node, where the second time node is the time when the termination resistance 202 of the memory under test 200 changes to the second maximum value.
  • the processing unit 303 is configured to acquire the ZQ calibration time of the memory under test 200 according to the second time node and the first time node.
  • the ZQ calibration time includes the calibration code generation time and the calibration code transfer time.
  • the testing system further includes: a third obtaining unit 332, configured to obtain a third time node, where the third time node is the time node at which the termination resistance 202 begins to change.
  • the processing unit 303 includes a first processing sub-unit 313 and a second processing sub-unit 323 .
  • the first processing subunit 313 is configured to acquire the calibration code generation time according to the third time node and the first time node.
  • the calibration code generation time is that the ZQ calibration module 201 compares the resistance value of the output pull-up resistor and the output pull-down resistor inside the semiconductor memory with the resistance value of the reference resistor, so that the resistance value of the output pull-up resistor and the output pull-down resistor is the same as the resistance value of the reference resistor. match and generate the corresponding calibration code at the time of this process.
  • the second processing subunit 323 is configured to acquire the calibration code transfer time according to the second time node and the third time node.
  • the calibration code transfer time is the process of sending the calibration code to the termination resistor 202 of the DQ terminal 204 , that is, the output driver is connected to the output resistor of the DQ terminal 204 , and adjusts the process time of the termination resistor 202 according to the calibration code.
  • the second obtaining unit 322 and the third obtaining unit 332 obtain the second time node and the third time node by obtaining the output voltage of the DQ terminal 204 of the memory under test 200 .
  • the second time node is the time node when the output voltage of the DQ terminal 204 changes to the second maximum value
  • the third time node is the time node when the output voltage of the DQ terminal 204 starts to change.
  • the second acquisition unit and the third acquisition unit acquire the second time node and the third time node by acquiring the voltage loaded across the termination resistor in the memory to be tested.
  • the second time node is the time node when the voltage loaded across the termination resistor changes to the second maximum value
  • the third time node is the time node when the voltage loaded across the termination resistor starts to change.
  • the second acquisition unit and the third acquisition unit acquire the second time node and the third time node by acquiring the current passing through the termination resistor in the memory to be tested.
  • the second time node is the time node when the current passing through the termination resistor changes to the second maximum value
  • the third time node is the time node when the current passing through the termination resistor starts to change.
  • the test system further includes: an adjustment sub-unit 302 for dividing the output voltage of the DQ port 204 into a first level and a second level, and the first level satisfies the preset of the second maximum value. range, the second level does not meet the preset range of the second maximum value; the second obtaining unit 322 is used to obtain the jump time of the first level and the second level, and the jump time is used as the second time node, and the jump time is used as the second time node.
  • the transition time point is used as the second time node, and the time node at which the output voltage of the DQ terminal 204 changes to the second maximum value is simply and accurately obtained.
  • the testing machine Provides the initialization command to the memory to be tested by the testing machine to change the termination resistance of the memory to be tested to a maximum value, and then provide the ZQ calibration command to the memory to be tested through the testing machine to change the termination resistance of the memory to be tested to another maximum value , at this time, the change degree of the termination resistance is the largest, which can accurately represent the actual progress time of the ZQ calibration of the memory to be calibrated. Then, according to the time node when the ZQ calibration command is sent and the time node when the resistance value change of the termination resistor is completed, the time when the memory to be tested performs ZQ calibration is read out.
  • each unit involved in this embodiment is a logical unit.
  • a logical unit may be a physical unit, a part of a physical unit, or multiple physical units.
  • a composite implementation of the unit in order to highlight the innovative part of the present disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems raised by the present disclosure, but this does not mean that there are no other units in this embodiment.
  • this embodiment can be implemented in cooperation with the first embodiment.
  • the relevant technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment. In order to reduce repetition, details are not repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Memory System (AREA)

Abstract

本公开实施例提供一种测试方法及测试系统，测试方法用于获取待测存储器的ZQ校准时间，包括：向ZQ校准模块提供初始化命令，以使终结电阻的电阻值为第一最值；向ZQ校准模块提供ZQ校准命令，以使终结电阻的电阻值由第一最值递增或递减至第二最值，第一最值和第二最值的其中一个为最大值，另一个为最小值；获取第一时间节点，第一时间节点为ZQ校准命令的发送时间；获取第二时间节点，第二时间节点为终结电阻的电阻值变化至第二最值的时间；基于第二时间节点和第一时间节点，获取ZQ校准时间；本公开实施例以一种低成本的方式，便捷且准确地获取存储器进行ZQ校准的时间。

Description

测试方法及测试系统
交叉引用
本申请基于申请号为202011297404.3、申请日为2020年11月18日、申请名称为“测试方法及测试系统”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及存储器性能测试领域，特别涉及一种测试方法及测试系统。
背景技术
对于半导体存储器而言，输出端的上拉电阻的电阻值和下拉电阻的电阻值会影响输出信号的完整性。
相关技术中，通常采用ZQ校准(ZQ calibration)来调整上拉电阻的电阻值和下拉电阻的电阻值，以调节输出上拉(pull-up)和/或输出下拉(pull-down)的能力。由此可见，对于存储器的性能测试而言，存储器进行ZQ校准的具体时间也可以作为对存储器性能评估的重要指标。
因此，如何获取存储器进行ZQ校准的具体时间，是当前亟待解决的技术问题。
发明内容
本公开实施例提供一种测试方法及测试系统，以一种低成本的方式，便捷且准确地获取存储器进行ZQ校准的时间。
为解决上述问题，本公开实施例提供一种测试方法，用于获取待测存储器的ZQ校准时间，待测存储器包括ZQ校准模块、终结电阻和DQ端，终结电阻的一端连接工作电压端，另一端连接DQ端，ZQ校准模块用于控制终结电阻接入工作电压端至DQ端的电阻值，包括：向ZQ校准模块提供初始化命令，以使终结电阻的电阻值为第一最值；向ZQ校准模块提供ZQ校准命令，以使终结电阻的电阻值由第一最值递增或递减至第二最值，第一最值和第二最值的其中一个为最大值，另一个为最小值；获取第一时间节点，第一时间节点为ZQ校准命令的发送时间；获取第二时间节点，第二时间节点为终结电阻的电阻值变化至第二最值的时间；基于第二时间节点和第一时间节点，获取ZQ校准时间。
与相关技术相比，通过初始化命令将待测存储器的终结电阻变为一最值，然后通过ZQ校准命令将待测存储器的终结电阻变为另一最值，此时终结电阻的变化程度最大，可以准确表征ZQ校准的实际进行时间。然后根据ZQ校准命令发送的时间节点和终结电阻的电阻值变化完成的时间节点，读出待测存储器进行ZQ校准的时间。
本公开实施例还提供一种测试系统，应用于测试机台，测试机台包括：发送单元，用于向待测存储器提供初始化命令和ZQ校准命令；第一获取单元，用于获取第一时间节点，第一时间节点为发送单元发 送ZQ校准命令的时间；第二获取单元，用于获取第二时间节点，第二时间节点为待测存储器的终结电阻变化至第二最值的时间；处理单元，用于根据第二时间节点和第一时间节点，获取待测存储器的ZQ校准时间。
与相关技术相比，通过测试机台向待测存储器提供初始化命令将待测存储器的终结电阻变为一最值，然后通过测试机台向待测存储器提供ZQ校准命令将待测存储器的终结电阻变为另一最值，此时终结电阻的变化程度最大，可以准确表征待存储器ZQ校准的实际进行时间。然后根据ZQ校准命令发送的时间节点和终结电阻的电阻值变化完成的时间节点，读出待测存储器进行ZQ校准的时间。
附图说明
图1和图2为本公开第一实施例提供的测试方法的流程示意图；
图3为本公开第一实施例提供的待测存储器的结构示意图；
图4至图8为本公开第一实施例提供的测试方法的原理图；
图9为本公开第二实施例提供的测试系统的结构示意图；
V DD—工作电压端电压，R tt—终结电阻，DQ—DQ端，V DQ—DQ端电压，V SS—接地电压，I out—DQ端输出电流，t1—第一时间节点，t2—第二时间节点，t3—第三时间节点。
具体实施方式
由背景技术可知，对于存储器的性能测试而言，存储器进行ZQ校准的具体时间也可以作为对存储器性能评估的重要指标，如何获取存储器进行ZQ校准的具体时间，是当前亟待解决的技术问题。
为解决上述问题，本公开第一实施例提供一种测试方法，用于获取待测存储器的ZQ校准时间，待测存储器包括ZQ校准模块、终结电阻和DQ端，终结电阻的一端连接工作电压端，另一端连接DQ端，ZQ校准模块用于控制终结电阻接入工作电压端至DQ端的电阻值，包括：向ZQ校准模块提供初始化命令，以使终结电阻的电阻值为第一最值；向ZQ校准模块提供ZQ校准命令，以使终结电阻的电阻值由第一最值递增或递减至第二最值，第一最值和第二最值的其中一个为最大值，另一个为最小值；获取第一时间节点，第一时间节点为ZQ校准命令的发送时间；获取第二时间节点，第二时间节点为终结电阻的电阻值变化至第二最值的时间；基于第二时间节点和第一时间节点，获取ZQ校准时间。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1和图2为本公开第一实施例提供的测试方法的流程示意图，图3为本公开第一实施例提供的待测存储器的结构示意图，图4至图8为本公开第一实施例提供的测试方法的原理图，以下将结合附图对 本实施例提供的测试方法进行详细说明。
参考图3，测试方法用于获取待测存储器200的ZQ校准时间，待测存储器200包括ZQ校准模块201、终结电阻202和DQ端204，终结电阻202的一端连接工作电压端203，另一端连接DQ端204，ZQ校准模块201用于控制终结电阻202接入工作电压端203至DQ端204的电阻值。
参考图1且结合图3，测试方法，包括以下步骤：
步骤101，提供初始化命令。
具体地，向ZQ校准模块201提供初始化命令，以使终结电阻202的电阻值为第一最值。
步骤102，提供ZQ校准命令。
具体地，向ZQ校准模块提供ZQ校准命令，以使终结电阻的电阻值由第一最值递增或递减至第二最值，第一最值和第二最值的其中一个为最大值，另一个为最小值。
在一可选实施例中，以DQ端的输出电压为例，以第一最值为最小值，第二最值为最大值为例进行具体描述仅仅是对本实施的举例说明，便于本领域技术人员了解本方案的实现，需要说明的是，本实施例以第一最值为最小值，第二最值为最大值并不构成对本实施例的限定，在其他实施例中，可以采用第一最值为最大值，第二最值为最小值。
ZQ校准模块201为现有半导体存储器的已有单元设计，用于响应ZQ校准命令并对半导体存储器进行ZQ校准。半导体存储器的ZQ 管脚外接一个参考电阻，参考电阻通常为240欧姆的电阻，当ZQ校准模块201进行ZQ校准时，ZQ校准模块201会对半导体存储器内部的输出上拉电阻和输出下拉电阻与参考电阻的电阻值做比较，使输出上拉电阻和输出下拉电阻的电阻值与参考电阻的电阻值匹配，并产生相应的校准代码，然后将校准代码发送至DQ端204的终结电阻202，即输出驱动连接DQ端204的输出电阻。需要说明的是，图3中的终结电阻202并不是指代单个的电阻，而是表征输出驱动连接DQ端204的输出电阻的集合。
本实施例以初始化命令，使得终结电阻202为最小值，然后通过ZQ校准命令，使存储器开始执行ZQ校准，且使终结电阻202递增变为最大值，当终结电阻202递增至最大值，存储器完成ZQ校准，通过ZQ校准命令的发出时间，和终结电阻202变化至最大值的时间，可以准确的表征存储器执行ZQ校准命令的实际时间。
步骤103，获取第一时间节点。第一时间节点为ZQ校准命令的发送时间。
具体地，当外部装置向待测存储器发送ZQ校准命令时，获取当前时间作为第一时间节点，ZQ校准命令有外部装置向待测存储器传输的过程时间可忽略不计。参考图5，通过获取ZQ校准命令的发送时间作为第一或时间节点t1。
继续参考图1，步骤104，获取第二时间节点。第二时间节点为终结电阻202的电阻值变化至第二最值的时间。
具体地，实时监控终结电阻202的电阻值变化，当终结电阻202 的电阻值变化至最大值，获取当前时间为第二时间节点。
在一可选实施例中，通过检测DQ端204的输出电压获取第二时间节点，具体地，第二时间节点为DQ端的输出电压变化至第二最值的时间节点，其原理参考图4，终结电阻R tt的一端连接至工作电压端，另一端连接至DQ端，终结电阻对工作电压端的电压V DD进行分压，即加载在终结电阻R tt的阻值越大，加载在终结电阻R tt两端的电压越大，DQ端的输出电压V DQ(相对于接地电压V SS而言)越小。参考图5，当终结电阻R tt的电阻值为最大值时，加载在终结电阻R tt两端的电压也达到最大值，此时DQ端的输出电压V DQ为最小值，即通过DQ端的输出电压V DQ变化至最小值时，获取第二时间节点t2。
继续参考图5，当终结电阻R tt的电阻值趋近于最大值时，终结电阻R tt的电阻值变化缓慢，在获取第二时间节点时，无法准确获取V DQ变化至最小值的时间节点。
在一可选实施例中，获取第二时间节点的方法包括：将DQ端的输出电压分为第一电平和第二电平，第一电平满足第二最值的预设范围，第二电平不满足第二最值的预设范围，获取第一电平和第二电平的跳变时间，以跳变时间作为第二时间节点t2。
在一个例子中，终结电阻R tt的电阻值由最小值向最大值变化，此时，DQ端的输出电压V DQ由最大值向最小值变化，以V DQ的最小值，5％的误差为预设范围划分第一电平和第二电平，当0.95V DQ＜V DQ实际电压＜1.00V DQ时，V DQ实际电压为第二电平；当V DQ实际电压＜0.95V DQ时，V DQ实际电压为第一电平。此时在V DQ的变化过程中，会出现一个 跳变的时间点，以该跳变的时间节点作为第二时间节点，简单且准确的获取V DQ变化至最小值的时间节点。
步骤105，基于第一时间节点和第二时间节点，获取ZQ校准时间。
具体地，将第二时间节点和第一时间节点之间的时间差值作为待测存储器的ZQ校准时间。
由前述内容可知，待测存储器的ZQ校准时间包括校准代码的生成阶段和校准代码的转移阶段，即ZQ校准时间包括校准代码生成时间和校准代码转移时间。具体地，参考图2，步骤105具体包括：
步骤115，获取第三时间节点。第三时间节点为终结电阻202的电阻值开始发生变化的时间。
在一可选实施例中，通过检测DQ端204的输出电压获取第三时间节点，具体地，第三时间节点为DQ端的输出电压开始发生变化的时间节点，其原理参考图4，终结电阻R tt的一端连接至V DD端，另一端连接至DQ端，终结电阻对V DD进行分压，即加载在终结电阻R tt的阻值越大，加载在终结电阻R tt两端的电压越大，DQ端的输出电压V DQ越小。参考图5，当终结电阻R tt的电阻值开始发生变化时，加载在终结电阻R tt两端的电压也开始发生变化，此时DQ端的输出电压V DQ也开始发生变化，即通过DQ端的输出电压V DQ开始发生变化时，获取第三时间节点t3。
具体地，实时监控终结电阻202的电阻值变化，当终结电阻202的电阻值发生变化时，获取当前时间为第三时间节点。
步骤125，基于第三时间节点和第一时间节点，获取校准代码生成时间。
具体地，将第三时间节点和第一时间节点之间的时间差值作为待测存储器的校准代码生成时间。校准代码生成时间即ZQ校准模块201会对半导体存储器内部的输出上拉电阻和输出下拉电阻与参考电阻的电阻值做比较，使输出上拉电阻和输出下拉电阻的电阻值与参考电阻的电阻值匹配，并产生相应的校准代码这一过程的时间。
步骤135，基于第二时间节点和第三时间节点，获取校准代码转移时间。
具体地，将第二时间节点和第三时间节点之间的时间差值作为待测存储器的校准代码转移时间。校准代码转移时间即将校准代码发送至DQ端204的终结电阻202，即输出驱动连接DQ端204的输出电阻，并根据校准代码调整终结电阻202这一过程的时间。
需要说明的是，在一可选实施例中，通过检测DQ端204的输出电压V DQ变化来获取终结电阻202的电阻变化，并不构成对本实施例的限定。
在其他实施例中，还可以根据加载在终结电阻R tt两端的电压V Rtt变化来获取终结电阻R tt的电阻变化，其原理图参考图7，当终结电阻R tt的电阻值为最小值时，加载在终结电阻R tt两端的电压V Rtt同样为最小值；随着终结电阻R tt的电阻值的增大，加载在终结电阻R tt两端的电压V Rtt随之增大；当终结电阻R tt为最大值时，加载在终结电阻R tt两端的电压V Rtt同样为最大值。通过获取ZQ校准命令的发送时间作为 第一或时间节点t1，通过获取加载在终结电阻R tt两端的电压V Rtt开始变化的时间作为第三时间节点t3，通过获取加载在终结电阻R tt两端的电压V Rtt变化至最大值的时间作为第二时间节点t2，从而获取待测存储器的ZQ校准时间。
另外，还可以根据通过终结电阻R tt的电流I Rtt变化来获取终结电阻R tt的电阻变化，其原理图参考图8，当终结电阻R tt的电阻值为最小值时，通过终结电阻R tt的电流I Rtt为最大值；随着终结电阻R tt的电阻值的增大，通过终结电阻R tt的电流值I Rtt减小；当终结电阻R tt的电阻值为最大值时，通过终结电阻R tt的电流I Rtt为最小值。通过获取ZQ校准命令的发送时间作为第一或时间节点t1，通过获取通过终结电阻R tt的电流I Rtt开始变化的时间作为第三时间节点t3，通过获取通过终结电阻R tt的电流I Rtt变化至最小值的时间作为第二时间节点t2，从而获取待测存储器的ZQ校准时间。
相对于相关技术而言，通过初始化命令将待测存储器的终结电阻变为一最值，然后通过ZQ校准命令将待测存储器的终结电阻变为另一最值，此时终结电阻的变化程度最大，可以准确表征ZQ校准的实际进行时间。然后根据ZQ校准命令发送的时间节点和终结电阻的电阻值变化完成的时间节点，读出待测存储器进行ZQ校准的时间。
值得一提的是，上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计 都在该专利的保护范围内。
本公开第二实施例涉及一种测试系统，应用于测试机台，测试机台包括：发送单元，用于向待测存储器提供初始化命令和ZQ校准命令；第一获取单元，用于获取第一时间节点，第一时间节点为发送单元发送ZQ校准命令的时间；第二获取单元，用于获取第二时间节点，第二时间节点为待测存储器的终结电阻变化至第二最值的时间；处理单元，用于根据第二时间节点和第一时间节点，获取待测存储器的ZQ校准时间。
图9为本公开第二实施例提供的测试系统的结构示意图，以下将结合附图对本实施例提供的测试系统进行详细说明，与第一实施例相同或相应的部分，以下将不做详细赘述。
参考图9，测试系统包括测试机台300和待测存储器200。
其中，待测存储器200包括ZQ校准模块201、终结电阻202和DQ端204，终结电阻202的一端连接工作电压端203，另一端连接DQ端204，ZQ校准模块201用于控制终结电阻202接入工作电压端203至DQ端204的电阻值。
测试机台300，包括：
发送单元301，用于向待测存储器200提供初始化命令和ZQ校准命令。
第一获取单元312，用于获取第一时间节点，第一时间节点为发送单元301发送ZQ校准命令的时间。
第二获取单元322，用于获取第二时间节点，第二时间节点为待 测存储器200的终结电阻202变化至第二最值的时间。
处理单元303，用于根据第二时间节点和第一时间节点，获取待测存储器200的ZQ校准时间。
具体地，ZQ校准时间包括校准代码生成时间和校准代码转移时间。
测试系统还包括：第三获取单元332，用于获取第三时间节点，第三时间节点为终结电阻202开始发生变化的时间节点。
处理单元303包括第一处理子单元313和第二处理子单元323。
第一处理子单元313，用于根据第三时间节点和第一时间节点，获取校准代码生成时间。校准代码生成时间即ZQ校准模块201会对半导体存储器内部的输出上拉电阻和输出下拉电阻与参考电阻的电阻值做比较，使输出上拉电阻和输出下拉电阻的电阻值与参考电阻的电阻值匹配，并产生相应的校准代码这一过程的时间。
第二处理子单元323，用于根据第二时间节点和第三时间节点，获取校准代码转移时间。校准代码转移时间即将校准代码发送至DQ端204的终结电阻202，即输出驱动连接DQ端204的输出电阻，并根据校准代码调整终结电阻202这一过程的时间。
在一可选实施例中，第二获取单元322和第三获取单元332通过获取待测存储器200的DQ端204的输出电压来获取第二时间节点和第三时间节点。具体地，第二时间节点为DQ端204的输出电压变化至第二最值的时间节点，第三时间节点为DQ端204的输出电压开始发生变化的时间节点。
在其他实施例中，第二获取单元和第三获取单元通过获取待测存储器中加载在终结电阻两端的电压来获取第二时间节点和第三时间节点。具体地，第二时间节点为加载在终结电阻两端的电压变化至第二最值的时间节点，第三时间节点为加载在终结电阻两端的电压开始发生变化的时间节点。另外，第二获取单元和第三获取单元通过获取待测存储器中通过终结电阻的电流来获取第二时间节点和第三时间节点。具体地，第二时间节点为通过终结电阻的电流变化至第二最值的时间节点，第三时间节点为通过终结电阻的电流开始发生变化的时间节点。
当终结电阻202的电阻值趋近于最大值时，终结电阻202的电阻值变化缓慢，在获取第二时间节点时，无法准确获取DQ端204的输出电压变化至最小值的时间节点。在一可选实施例中，测试系统还包括：调整子单元302，用于将DQ端口204的输出电压划分为第一电平和第二电平，第一电平满足第二最值的预设范围，第二电平不满足第二最值的预设范围；第二获取单元322用于获取第一电平和第二电平的跳变时间，以跳变时间作为第二时间节点，以该跳变的时间点作为第二时间节点，简单且准确的获取DQ端204的输出电压变化至第二最值的时间节点。
通过测试机台向待测存储器提供初始化命令将待测存储器的终结电阻变为一最值，然后通过测试机台向待测存储器提供ZQ校准命令将待测存储器的终结电阻变为另一最值，此时终结电阻的变化程度最大，可以准确表征待存储器ZQ校准的实际进行时间。然后根据ZQ 校准命令发送的时间节点和终结电阻的电阻值变化完成的时间节点，读出待测存储器进行ZQ校准的时间。
值得一提的是，本实施例中所涉及到的各单元均为逻辑单元，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本公开的创新部分，本实施例中并没有将与解决本公开所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
由于第一实施例与本实施例相互对应，因此本实施例可与第一实施例互相配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (10)

  1. 一种测试方法，用于获取待测存储器的ZQ校准时间，所述待测存储器包括ZQ校准模块、终结电阻和DQ端，所述终结电阻的一端连接工作电压端，另一端连接所述DQ端，所述ZQ校准模块用于控制所述终结电阻接入所述工作电压端至所述DQ端的电阻值，包括：
    向所述ZQ校准模块提供初始化命令，以使所述终结电阻的电阻值为第一最值；
    向所述ZQ校准模块提供ZQ校准命令，以使所述终结电阻的电阻值由所述第一最值递增或递减至第二最值，所述第一最值和所述第二最值的其中一个为最大值，另一个为最小值；
    获取第一时间节点，所述第一时间节点为所述ZQ校准命令的发送时间；
    获取第二时间节点，所述第二时间节点为所述终结电阻的电阻值变化至所述第二最值的时间；
    基于所述第二时间节点和所述第一时间节点，获取所述ZQ校准时间。
  2. 根据权利要求1所述的测试方法，其中，所述ZQ校准时间包括校准代码生成时间和校准代码转移时间，获取所述ZQ校准时间，包括：
    获取第三时间节点，所述第三时间节点为所述终结电阻的电阻值开始发生变化的时间；
    基于所述第三时间节点和所述第一时间节点，获取所述校准代码生成时间；
    基于所述第二时间节点和所述第三时间节点，获取所述校准代码转移时间。
  3. 根据权利要求2所述的测试方法，其中，通过检测所述DQ端的输出电压获取所述第二时间节点和所述第三时间节点；
    所述第三时间节点为所述DQ端的输出电压开始发生变化的时间 节点；
    所述第二时间节点为所述DQ端的输出电压变化至所述第二最值的时间节点。
  4. 根据权利要求3所述的测试方法，其中，获取所述第二时间节点的方法包括：
    将所述DQ端的输出电压分为第一电平和第二电平，所述第一电平满足所述第二最值的预设范围，所述第二电平不满足所述第二最值的预设范围；
    获取所述第一电平和所述第二电平的跳变时间，以所述跳变时间作为所述第二时间节点。
  5. 根据权利要求2所述的测试方法，其中，通过检测通过所述终结电阻的电流获取所述第二时间节点和所述第三时间节点；
    所述第三时间节点为通过所述终结电阻的电流开始发生变化的时间节点；
    所述第二时间节点为通过所述终结电阻的电流变化至所述第二最值的时间节点。
  6. 根据权利要求2所述的测试方法，其中，通过检测所述终结电阻两端的电压获取所述第二时间节点和所述第三时间节点；
    所述第三时间节点为所述终结电阻两端的电压开始发生变化的时间节点；
    所述第二时间节点为所述终结电阻两端的电压变化至所述第二最值的时间节点。
  7. 一种测试系统，应用于测试机台，所述测试机台包括：
    发送单元，用于向待测存储器提供初始化命令和ZQ校准命令；
    第一获取单元，用于获取第一时间节点，所述第一时间节点为所述发送单元发送所述ZQ校准命令的时间；
    第二获取单元，用于获取第二时间节点，所述第二时间节点为所述待测存储器的终结电阻变化至第二最值的时间；
    处理单元，用于根据所述第二时间节点和所述第一时间节点，获取所述待测存储器的ZQ校准时间。
  8. 根据权利要求7所述的测试系统，其中，包括：
    所述ZQ校准时间包括校准代码生成时间和校准代码转移时间；所述测试系统还包括：第三获取单元，用于获取第三时间节点，所述第三时间节点为所述终结电阻开始发生变化的时间节点；
    所述处理单元包括第一处理子单元和第二处理子单元；
    所述第一处理子单元用于，根据所述第三时间节点和所述第一时间节点，获取所述校准代码生成时间；
    所述第二处理子单元用于，根据所述第二时间节点和所述第三时间节点，获取所述校准代码转移时间。
  9. 根据权利要求8所述的测试系统，其中，所述第二获取单元和所述第三获取单元通过获取所述待测存储器的DQ端的输出电压来获取所述第二时间节点和所述第三时间节点；
    所述第二时间节点为所述DQ端的输出电压变化至所述第二最值的时间节点，所述第三时间节点为所述DQ端的输出电压开始发生变化的时间节点。
  10. 根据权利要求9所述的测试系统，其中，还包括：调整子单元，用于将所述DQ端的输出电压划分为第一电平和第二电平，所述第一电平满足所述第二最值的预设范围，所述第二电平不满足所述第二最值的预设范围；
    所述第二获取单元用于，获取所述第一电平和所述第二电平的跳变时间，以所述跳变时间作为所述第二时间节点。
PCT/CN2021/112768 2020-11-18 2021-08-16 测试方法及测试系统 WO2022105322A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/453,001 US11810639B2 (en) 2020-11-18 2021-10-31 Test method and test system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202011297404.3 2020-11-18
CN202011297404.3A CN114520018B (zh) 2020-11-18 2020-11-18 测试方法及测试系统

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/453,001 Continuation US11810639B2 (en) 2020-11-18 2021-10-31 Test method and test system

Publications (1)

Publication Number Publication Date
WO2022105322A1 true WO2022105322A1 (zh) 2022-05-27

Family

ID=81594167

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/112768 WO2022105322A1 (zh) 2020-11-18 2021-08-16 测试方法及测试系统

Country Status (2)

Country Link
CN (1) CN114520018B (zh)
WO (1) WO2022105322A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101136238A (zh) * 2006-08-29 2008-03-05 尔必达存储器株式会社 半导体器件的输出电路
CN101261874A (zh) * 2007-03-08 2008-09-10 海力士半导体有限公司 Zq校准控制器和用于zq校准的方法
CN107393577A (zh) * 2017-08-21 2017-11-24 睿力集成电路有限公司 应用于半导体存储器的zq校准控制
CN109817258A (zh) * 2019-01-02 2019-05-28 长江存储科技有限责任公司 一种zq校准电路和方法
US10747245B1 (en) * 2019-11-19 2020-08-18 Micron Technology, Inc. Apparatuses and methods for ZQ calibration
CN111933205A (zh) * 2020-08-04 2020-11-13 西安紫光国芯半导体有限公司 Zq校准器、zq校准方法以及多通道存储器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4916699B2 (ja) * 2005-10-25 2012-04-18 エルピーダメモリ株式会社 Ｚｑキャリブレーション回路及びこれを備えた半導体装置
KR20100027777A (ko) * 2008-09-03 2010-03-11 주식회사 하이닉스반도체 반도체 장치의 ｚｑ 캘리브레이션을 위한 구동 저항 측정 회로 및 방법
KR20170143127A (ko) * 2016-06-20 2017-12-29 삼성전자주식회사 터미네이션 저항을 보정하는 반도체 메모리 장치 및 그것의 터미네이션 저항 보정 방법
KR102651315B1 (ko) * 2018-08-16 2024-03-26 삼성전자주식회사 풀업 캘리브레이션 경로와 풀다운 캘리브레이션 경로에 의해 공유되는 공통 노드를 포함하는 캘리브레이션 회로 및 이를 포함하는 반도체 메모리 장치
US10504571B1 (en) * 2018-10-04 2019-12-10 Microa Technology, Inc. Apparatus with a calibration mechanism

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101136238A (zh) * 2006-08-29 2008-03-05 尔必达存储器株式会社 半导体器件的输出电路
CN101261874A (zh) * 2007-03-08 2008-09-10 海力士半导体有限公司 Zq校准控制器和用于zq校准的方法
CN107393577A (zh) * 2017-08-21 2017-11-24 睿力集成电路有限公司 应用于半导体存储器的zq校准控制
CN109817258A (zh) * 2019-01-02 2019-05-28 长江存储科技有限责任公司 一种zq校准电路和方法
US10747245B1 (en) * 2019-11-19 2020-08-18 Micron Technology, Inc. Apparatuses and methods for ZQ calibration
CN111933205A (zh) * 2020-08-04 2020-11-13 西安紫光国芯半导体有限公司 Zq校准器、zq校准方法以及多通道存储器

Also Published As

Publication number Publication date
CN114520018B (zh) 2024-06-07
CN114520018A (zh) 2022-05-20

Similar Documents

Publication Publication Date Title
US6525558B2 (en) Programmable impedance control circuit
US6734702B1 (en) Impedance calibration circuit
DE112012001972B4 (de) Vorrichtung, System und Verfahren zur Spannungshub- und Tastgradjustierung
US7034567B2 (en) Semiconductor devices with reference voltage generators and termination circuits configured to reduce termination mismatch
JP5171246B2 (ja) インピーダンスマッチング回路及びこれを備える半導体素子
US7848175B2 (en) Calibration of memory driver with offset in a memory controller and memory device interface in a communication bus
KR100618716B1 (ko) 라인 드라이버 장치 및 라인 드라이버에 독립적으로 제어가능한 출력 종단 저항, 출력 진폭 및 출력 공통 모드 전압을 제공하는 방법
US7269043B2 (en) Memory module and impedance calibration method of semiconductor memory device
KR100875673B1 (ko) 온 다이 터미네이션 장치 및 이의 캘리브래이션 방법
US7134101B2 (en) Active impedance compensation
DE102005048575A1 (de) Impedanzeinstellschaltung, integriertes Schaltungsbauelement und Impedanzsteuerverfahren
US20100164540A1 (en) Semiconductor Memory Device
CN109861795B (zh) Canfd总线系统采样点配置与测试方法及相应的数据传输方法
CN116959542A (zh) 校准电路、存储器及校准方法
WO2022105322A1 (zh) 测试方法及测试系统
KR20070088845A (ko) 메모리 모듈 및 메모리 모듈에 포함되는 반도체디바이스들의 임피던스 교정방법
US20050099219A1 (en) Setting multiple chip parameters using one IC terminal
US9945888B2 (en) On-die measurement technique for I/O DC parameters VOL and VOH
JP4179883B2 (ja) 終端抵抗装置、データ伝送装置及び終端抵抗回路の検査方法
US11810639B2 (en) Test method and test system
US20050046441A1 (en) Scalable termination
KR100980414B1 (ko) 캘리브레이션 회로 및 이를 이용하는 데이터 출력 회로
US11287455B2 (en) Sensor interface circuit
CN208954639U (zh) 片内终结电阻精度调整电路及存储器
US7248636B2 (en) Systems and methods for adjusting an output driver

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21893474

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21893474

Country of ref document: EP

Kind code of ref document: A1